GRM188R71E105KA12D [INFINEON]
12A Highly Integrated SupIRBuck Continuous 12A Load Capability; 12A高集成度的SupIRBuck 12A连续负载能力
| 型号： | GRM188R71E105KA12D |
| 厂家： | 
Infineon |
| 描述： | 12A Highly Integrated SupIRBuck Continuous 12A Load Capability |
| 文件： | 总21页 (文件大小：884K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12A Highly Integrated SupIRBuckTM
IR3476
FEATURES
DESCRIPTION
The IR3476 SupIRBuckTM is an easy‐to‐use, fully integrated
and highly efficient DC/DC voltage regulator. The onboard
constant on time hysteretic controller and MOSFETs make
IR3476 a space‐efficient solution that delivers up to 12A of
precisely controlled output voltage.
• Input Voltage Range: 3V to 27V
• Output Voltage Range: 0.5V to 12V
• Continuous 12A Load Capability
• Constant On‐Time Control
Programmable switching frequency, soft start, and
thermally compensated over current protection allows for
a very flexible solution suitable for many different
applications and an ideal choice for battery powered
applications.
• Compensation Loop not Required
• Excellent Efficiency at Very Low Output Currents
• Programmable Switching Frequency and Soft Start
• Thermally Compensated Over Current Protection
• Power Good Output
Additional features include pre‐bias startup, very precise
0.5V reference, under/over voltage shutdown, thermal
protection, power good output, and enable input with
voltage monitoring capability.
• Precision Voltage Reference (0.5V, +/‐1%)
• Enable Input with Voltage Monitoring Capability
• Pre‐bias Start Up
• Thermal Shut Down
APPLICATIONS
• Under/Over Voltage Fault Protection
• Forced Continuous Conduction Mode Option
• Small, Low Profile 5mm x 6mm QFN Package
• Notebook and Desktop Computers
• Consumer Electronics – STB, LCD, TV, Printers
• 12V and 24V Distributed Power Systems
• General Purpose POL DC‐DC Converters
• Game Consoles and Graphics Cards
EFFICIENCY
BASIC APPLICATION
95%
85%
75%
19VIN
12VIN
65%
8VIN
55%
45%
0.01
0.1
1
10
100
Load Current (A)
Figure 2: IR3476 Efficiency
Figure 1: IR3476 Basic Application Circuit
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
ORDERING INFORMATION
IR3476 ―
Package
Tape & Reel Qty
Part Number
IR3476MTR1PBF
IR3476MTRPBF
M
M
750
4000
PBF – Lead Free
TR – Tape and Reel
M – Package Type
MARKING INFORMATION
3476
?YWW?
xxxxx
Site/Date/Marking Code
Lot Code
Pin 1 Identifier
PIN DIAGRAM
θJA = 30o C /W
θJ-PCB = 2o C /W
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
FUNCTIONAL BLOCK DIAGRAM
Figure 3: IR3476 Functional Block Diagram
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
TYPICAL APPLICATION
+3.3V
VCC
+Vins
TP1
R1
VINS
10K
VIN
TP2
VIN
R2
10K
TP3
FCCM
+
C1
1uF
C2
22uF
C3
68uF
EN
TP4
EN
FCCM
+Vin1s
C4
TP20
+Vin1s
R3
200K
TP5
PGND
SW1
EN
/
FCCM
R4
10.5K
-Vins
0.22uF
TP6
PGNDS
TP23
+Vsws
VSW
ISET
L1
1.5uH
VSW
VOUT
U1
IR3476
TP7
VOUT
+3.3V
R5
C5
open
2
5
TP8
VOUTS
C6
open
C7
open
C8
open
C9
330uF
C10
47uF
C11
open
C12
0.1uF
1
2
3
4
5
6
7
FCCM
ISET
PGOOD
GND1
FB
R6
open
C13
open
10K
TP11
PGOOD
PGOOD
TP10
PGND
12
TP9
+Vout1s
PHASE
TP22
+Vsws
IR3476
TP24
+Vsws
FB
SS
2
5
TP13
SS
TP12
VSWS
SS
C20
0.1uF
C15
open
C16
open
C17
open
C18
open
C19
open
C26
open
C27
open
NC1
TP21
-Vsws
+3.3V
-Vout1s
TP14
TP15
+3.3V
-Vout1s
+Vdd2s
-Vdd2s
C21
1uF
TP25
-Vin1s
TP26
AGND
+Vdd1s
-Vdd1s
C22
open
C25
1uF
C24
open
C14
R7
VCC
TP16
VCC
open
2.80K
TP18
VOLTAGE SENSE
C23
open
TP17
PGND
R11
open
TP19
FB
R12
open
R8
2.55K
R13
open
R14
open
Figure 4: Demoboard Schematic for VOUT = 1.05V, FS = 300kHz
DEMOBOARD BILL OF MATERIALS
QTY
REFERENCE DESIGNATOR
VALUE
1.00uF
47uF
0.100uF
22.0uF
68uF
DESCRIPTION
capacitor, X7R, 1.00uF, 25V, 0.1, 0603
capacitor, 47uF, 6.3V, 805
MANUFACTURER
Murata
PART NUMBER
GRM188R71E105KA12D
C2012X5R0J476M
C1608X7R1H104K
EMK316BJ226ML‐T
EEV‐FK1E680P
3
1
2
1
1
1
1
C1, C21, C25
C10
C12, C20
C2
C3
C4
TDK
TDK
Taiyo Yuden
Panasonic
Murata
capacitor, X7R, 0.100uF, 50V, 0.1, 603
capacitor, X5R, 22.0uF, 16V, 20%, 1206
capacitor, electrolytic, 68uF, 25V, 0.2, SMD
capacitor, Y5V, 0.22uF, 50V, ‐20%, +80%, 0603
capacitor, 330uF, 2.5V, SMD
0.22uF
330uF
GRM188F51H224ZA01D
2R5TPE330M9
C9
Sanyo
inductor, ferrite, 1.5uH, 16.0A, 3.8mOhm,
SMT
1
L1
1.5uH
Cyntec
PIMB104T‐1R5MS‐39
3
1
1
1
1
1
1
R1, R2, R5
R3
10.0K
200K
resistor, thick film, 10.0K, 1/10W, 0.01, 0603
resistor, thick film, 200K, 1/10W, 0.01, 603
resistor, thick film, 10.5K, 1/10W, 0.01, 603
resistor, thick film, 2.80K, 1/10W, 0.01, 603
resistor, thick film, 2.55K, 1/10W, 0.01, 0603
switch, DIP, SPST, 2 position, SMT
KOA
KOA
KOA
KOA
KOA
RK73H1J1002F
RK73H1JLTD2003F
RK73H1JLTD1052F
RK73H1JLTD2801F
RK73H1J2551F
SD02H0SK
R4
R7
R8
SW1
U1
10.5K
2.80K
2.55K
Switch
IR3476
C&K Components
IRF
5mm x 6mm QFN
IR3476MTRPBF
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12A Highly Integrated SupIRBuckTM
IR3476
PIN DESCRIPTIONS
PIN #
PIN NAME
I/O LEVEL
PIN DESCRIPTION
Forced Continuous Conduction Mode (CCM). Ground this pin to enable diode
emulation mode or discontinuous conduction mode (DCM). Pull this pin to 3.3V
to operate in CCM under all load conditions.
1
FCCM
3.3V
2
3
ISET
PGOOD
GND
Connecting resistor to PHASE pin sets over current trip point.
Power good open drain output – pull up with a resistor to 3.3V
Bias return and signal reference.
5V
Reference
3.3V
4, 17
5
FB
Inverting input to PWM comparator, OVP / PGOOD sense.
Soft start/shutdown. This pin provides user programmable soft‐start function.
Connect an external capacitor from this pin to GND to set the startup time of the
output voltage. The converter can be shutdown by pulling this pin below 0.3V.
6
SS
3.3V
7
NC
3VCBP
NC
‐
3.3V
‐
‐
8
For internal LDO. Bypass with a 1.0µF capacitor to GND.
‐
9
10
11
12
13
14
15
VCC
5V
VCC input. Gate drive supply. A minimum of 1.0µF ceramic capacitor is required.
Power return.
PGND
PHASE
VIN
Reference
VIN
Phase node (or switching node) of MOSFET half bridge.
Input voltage for the system.
VIN
BOOT
FF
VIN + VCC
VIN
Bootstrapped gate drive supply – connect a capacitor to PHASE.
Input voltage feed forward – sets on‐time with a resistor to VIN.
Enable pin to turn on and off the device. Use two external resistors to set the
turn on threshold (see Electrical Specifications) for input voltage monitoring.
16
EN
5V
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications are not implied.
VIN, FF
‐0.3V to 30V
VCC, PGOOD, EN
BOOT
‐0.3V to 8V
‐0.3V to 38V
PHASE
‐0.3V to 30V (DC), ‐5V (100ns)
‐0.3V to 8V
BOOT to PHASE
ISET
‐0.3V to 30V, 30mA
‐0.3V to +0.3V
PGND to GND
All other pins
‐0.3V to 3.9V
Storage Temperature Range
Junction Temperature Range
ESD Classification
Moisture Sensitivity Level
‐65°C to 150°C
‐40°C to 150°C
JEDEC Class 1C
JEDEC Level 2 @ 260°C (Note 2)
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
UNITS
SYMBOL
VIN
MIN
3
MAX
27*
5.5
Recommended VIN Range
V
Recommended VCC Range
VCC
VOUT
IOUT
4.5
0.5
0
Recommended Output Voltage Range
Recommended Output Current Range
Recommended Switching Frequency
Recommended Operating Junction Temperature
* PHASE pin must not exceed 30V.
12
12
A
kHz
°C
FS
N/A
‐40
750
125
TJ
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, these specifications apply over VIN = 12V, 4.5V < VCC < 5.5V, 0°C ≤ TJ ≤ 125°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Control Loop
Reference Accuracy
On‐Time Accuracy
Min. Off Time
VREF
VFB = 0.5V
0.495
280
0.5
300
500
10
0.505
320
580
12
V
RFF = 180K, TJ = 65°C
ns
ns
Soft‐Start Current
DCM Comparator Offset
Feedback Input Current
Supply Current
EN = High
8
µA
mV
µA
Measure at VPHASE
VFB = 0.5V, TA = 25°C, Note 1
‐4.5
‐2.5
0.01
0
0.2
VCC Supply Current (standby)
VCC Supply Current (dynamic)
FF Shutdown Current
EN = Low, No Switching
EN = High, FS = 300kHz
EN = Low, RFF = 180K
23
8
µA
mA
µA
2
Forced Continuous Conduction Mode (FCCM)
FCCM Start Threshold
2
5
V
V
FCCM Stop Threshold
0.6
30
Gate Drive
Deadtime
Monitor body diode
conduction on PHASE pin,
Note 1
ns
Bootstrap PFET
Forward Voltage
I(BOOT) = 10mA
300
20
mV
mΩ
mΩ
Upper MOSFET
Static Drain‐to‐Source On‐Resistance
Lower MOSFET
VCC = 5V, ID = 12A, TJ = 25°C
VCC = 5V, ID = 12A, TJ = 25°C
25
Static Drain‐to‐Source On‐Resistance
10
12.5
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
PARAMETER
Fault Protection
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
ISET Pin Output Current
On the basis of 25°C
17
19
21
µA
ISET Pin Output Current
Temperature Coefficient
On the basis of 25°C, Note 1
4400
ppm/
°C
Under Voltage Threshold
Falling VFB & Monitor
PGOOD
0.37
0.4
0.43
V
Under Voltage Hysteresis
Over Voltage Threshold
Over Voltage Hysteresis
VCC Turn‐on Threshold
VCC Turn‐off Threshold
VCC Threshold Hysteresis
EN Rising Threshold
Rising VFB, Note 1
7.5
0.625
7.5
mV
V
Rising VFB & Monitor PGOOD
Falling VFB, Note 1
‐40°C to 125°C
0.586
0.655
mV
V
3.9
3.6
4.2
4.5
4.2
3.9
V
300
1.25
400
mV
V
‐40°C to 125°C
1.1
1.45
EN Hysteresis
mV
µA
Ω
EN Input Current
EN = 3.3V
15
50
PGOOD Pull Down Resistance
PGOOD Delay Threshold
Thermal Shutdown Threshold
25
1
VSS
V
Note 1
Note 1
125
140
20
°C
°C
Thermal Shutdown Threshold
Hysteresis
Note:
1. Guaranteed by design but not tested in production
2. Upgrade to industrial/MSL2 level applies from date codes 1227 (marking explained on application note AN1132 page 2).
Products with prior date code of 1227 are qualified with MSL3 for Consumer Market.
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 4, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no airflow,
unless otherwise specified.
100%
90%
80%
70%
60%
50%
95%
85%
75%
65%
55%
45%
19VIN
12VIN
8VIN
VOUT = 1.05V; L = 1.5µH, 3.8mΩ
VOUT = 1.5V; L = 2.2µH, 4.6mΩ
VOUT = 3.3V; L = 3.3µH, 7.7mΩ
0.01
0.1
1
10
100
0.01
0.1
1
10
100
Load Current (A)
Load Current (A)
Figure 5: Efficiency vs. Load Current for VOUT = 1.05V
Figure 6: Efficiency vs. Load Current for VIN = 12V
1400
1200
1000
800
600
400
200
0
400
350
300
250
200
150
100
50
5.0 Vout
4.0
3.0
2.0
1.0
4.5
3.5
2.5
1.5
0.5
0
0
3
6
9
12
200 250 300 350 400 450 500 550 600 650 700 750
Switching Frequency (kHz)
Load Current (A)
Figure 7: Switching Frequency vs. Load Current
Figure 8: RFF vs. Switching Frequency
1.060
1.060
19VIN
12VIN
8VIN
1.058
1.056
1.054
1.052
1.050
1.058
1.056
1.054
1.052
1.050
8
9
10 11 12 13 14 15 16 17 18 19
Input Voltage (V)
0
2
4
6
8
10
12
Load Current (A)
Figure 9: Load Regulation
Figure 10: Line Regulation at IOUT = 12A
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 4, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no airflow, unless
otherwise specified.
EN
EN
PGOOD
SS
PGOOD
SS
VOUT
VOUT
5V/div 5V/div 1V/div 500mV/div
500µs/div
5V/div 5V/div 1V/div 500mV/div
5ms/div
Figure 11: Startup
Figure 12: Shutdown
VOUT
PHASE
iL
VOUT
PHASE
iL
20mV/div 5V/div 5A/div
10µs/div
20mV/div 5V/div 10A/div
2µs/div
Figure 13: DCM (IOUT = 0.1A)
Figure 14: CCM (IOUT = 12A)
PGOOD
FB
PGOOD
SS
VOUT
iL
VOUT
iL
5V/div 1V/div 500mV/div 2A/div
50µs/div
5V/div 1V/div 1V/div 10A/div
2ms/div
Figure 15: Over Current Protection
(tested by shorting VOUT to PGND)
Figure 16: Over Voltage Protection
(tested by shorting FB to VOUT)
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 4, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no airflow, unless
otherwise specified.
VOUT
VOUT
PHASE
PHASE
iL
iL
50mV/div 10V/div 5A/div
20µs/div
50mV/div 10V/div 5A/div
20µs/div
Figure 17: Load Transient 0‐8A
Figure 18: Load Transient 4‐12A
FCCM
FCCM
PHASE
PHASE
VOUT
VOUT
iL
iL
5V/div 10V/div 500mV/div 5A/div
10µs/div
2V/div 10V/div 500mV/div 5A/div
5µs/div
Figure 19: DCM/FCCM Transition
Figure 20: FCCM/DCM Transition
Figure 21: Thermal Image at VIN = 12V, IOUT = 12A
(IR3476: 98oC, Inductor: 58oC, PCB: 47oC)
Figure 22: Thermal Image at VIN = 19V, IOUT = 12A
(IR3476: 104oC, Inductor: 61oC, PCB: 50oC)
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
reaches VSS (see Electrical Specification), SS_DELAY goes
HIGH. With EN_DELAY = LOW, the capacitor voltage and SS
pin is held to the FB pin voltage. A normal startup
sequence is shown in Figure 23.
THEORY OF OPERATION
PWM COMPARATOR
The PWM comparator initiates a SET signal (PWM pulse)
when the FB pin falls below the reference (VREF) or the
soft start (SS) voltage.
PGOOD
The PGOOD pin is open drain and it needs to be externally
pulled high. High state indicates that output is in
regulation. The PGOOD logic monitors EN_DELAY,
SS_DELAY, and under/over voltage fault signals. PGOOD is
released only when EN_DELAY and SS_DELAY = HIGH and
output voltage is within the OV and UV thresholds.
ON‐TIME GENERATOR
The PWM on‐time duration is programmed with an
external resistor (RFF) from the input supply (VIN) to the FF
pin. The simplified equation for RFF is shown in equation 1.
The FF pin is held to an internal reference after EN goes
HIGH. A copy of the current in RFF charges a timing
capacitor, which sets the on‐time duration, as shown in
equation 2.
PRE‐BIAS STARTUP
IR3476 is able to start up into pre‐charged output, which
prevents oscillation and disturbances of the output
voltage.
V
OUT
R
FF
=
=
(1)
(2)
With constant on‐time control, the output voltage is
compared with the soft start voltage (SS) or Vref,
depending on which one is lower, and will not start
switching unless the output voltage drops below the
reference. This scheme prevents discharge of a pre‐biased
output voltage.
1V ⋅20pF ⋅FSW
R
FF ⋅1V ⋅20pF
T
ON
V
IN
CONTROL LOGIC
SHUTDOWN
The control logic monitors input power sources, sequences
the converter through the soft‐start and protective modes,
and initiates an internal RUN signal when all conditions are
met.
The IR3476 will shutdown if VCC is below its UVLO limit.
The IR3476 can be shutdown by pulling the EN pin below
its lower threshold. Alternatively, the output can be
shutdown by pulling the soft start pin below 0.3V.
VCC and 3VCBP pins are continuously monitored, and the
IR3476 will be disabled if the voltage of either pin drops
below the falling thresholds. EN_DELAY will become HIGH
when VCC and 3VCBP are in the normal operating range
and the EN pin = HIGH.
SOFT START
With EN = HIGH, an internal 10µA current source charges
the external capacitor (CSS) on the SS pin to set the output
voltage slew rate during the soft start interval. The soft
start time (tSS) can be calculated from equation 3.
CSS ⋅0.5V
10μA
tSS
=
(3)
The feedback voltage tracks the SS pin until SS reaches the
0.5V reference voltage (Vref), then feedback is regulated
to Vref. CSS will continue to be charged, and when SS pin
Figure 23: Normal Startup
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
MOSFET, VPHASE, is monitored for over current and zero
crossing. The OCP circuit evaluates VPHASE for an over
current condition typically 270ns after the lower MOSFET
is gated on. This delay functions to filter out switching
noise. The minimum lower gate interval allows time to
sample VPHASE.
UNDER/OVER VOLTAGE MONITOR
The IR3476 monitors the voltage at the FB node through a
350ns filter. If the FB voltage is below the under voltage
threshold, UV# is set to LOW holding PGOOD to be LOW. If
the FB voltage is above the over voltage threshold, OV# is
set to LOW, the shutdown signal (SD) is set to HIGH,
MOSFET gates are turned off, and PGOOD signal is pulled
low. Toggling VCC or EN will allow the next start up. Figure
24 and 25 show PGOOD status change when UV/OV is
detected. The over voltage and under voltage thresholds
can be found in the Electrical Specification section.
The over current trip point is programmed with a resistor
from the ISET pin to PHASE pin, as shown in equation 4.
When over current is detected, the MOSFET gates are tri‐
state and SS voltage is pulled to 0V. This initiates a new
soft start cycle. If there is a total of four OC events, the
IR3476 will disable switching. Toggling VCC or EN will allow
the next start up.
R
DSON ⋅ OC
I
R
SET
=
(4)
19 μA
* typical filter delay
Figure 24: Under/Over Voltage Monitor
Figure 26: Over Current Protection
UNDER VOLTAGE LOCK‐OUT
The IR3476 has VCC and EN under voltage lock‐out (UVLO)
protection. When either VCC or EN is below their UVLO
threshold, IR3476 is disabled. IR3476 will restart when
both VCC and EN are above their UVLO thresholds.
* typical filter delay
Figure 25: Over Voltage Protection
OVER TEMPERATURE PROTECTION
When the IR3476 exceeds its over temperature threshold,
the MOSFET gates are tri‐state and PGOOD is pulled low.
Switching resumes once temperature drops below the over
temperature hysteresis level.
OVER CURRENT MONITOR
The over‐current circuitry monitors the output current
during each switching cycle. The voltage across the lower
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
capacitor, the magnitude of the AC voltage ripple is
determined by the total inductor ripple current flowing
through the total equivalent series resistance (ESR) of the
output capacitor bank.
GATE DRIVE LOGIC
The gate drive logic features adaptive dead time,
diode emulation, and a minimum lower gate interval.
An adaptive dead time prevents the simultaneous
conduction of the upper and lower MOSFETs. The lower
gate voltage must be below approximately 1V after PWM
goes HIGH before the upper MOSFET can be gated on.
Also, the differential voltage between the upper gate and
PHASE must be below approximately 1V after PWM goes
LOW before the lower MOSFET can be gated on.
One can use equation 5 to find the required inductance.
ΔI is defined as shown in Figure 27. The main advantage
of small inductance is increased inductor current slew rate
during a load transient, which leads to a smaller output
capacitance requirement as discussed in the Output
Capacitor Selection section. The drawback of using smaller
inductances is increased switching power loss in the upper
MOSFET, which reduces the system efficiency and
increases the thermal dissipation.
The upper MOSFET is gated on after the adaptive delay
for PWM = HIGH and the lower MOSFET is gated on after
the adaptive delay for PWM = LOW. When FCCM = LOW,
the lower MOSFET is driven ‘off’ when the ZCROSS signal
indicates that the inductor current is about to reverse
direction. The ZCROSS comparator monitors the PHASE
voltage to determine when to turn off the lower MOSFET.
The lower MOSFET stays ‘off’ until the next PWM falling
edge. When the lower peak of the inductor current is
above zero, IR3476 operates in continuous conduction
mode. The continuous conduction mode can also be
selected for all load current levels by pulling FCCM to
HIGH.
T
ON
⋅
V
IN −
VOUT
)
(5)
ΔI =
2⋅ L
Figure 27: Typical Input Current Waveform
Whenever the upper MOSFET is turned ‘off’, it stays
‘off’ for the Min Off Time denoted in the Electrical
Specifications. This minimum duration allows time to
recharge the bootstrap capacitor and allows the over
current monitor to sample the PHASE voltage.
Input Capacitor Selection
The main function of the input capacitor bank is to provide
the input ripple current and fast slew rate current during
the load current step up. The input capacitor bank must
have adequate ripple current carrying capability to handle
the total RMS current. Figure 27 shows a typical input
current. Equation 6 shows the RMS input current.
The RMS input current contains the DC load current and
the inductor ripple current. As shown in equation 5, the
inductor ripple current is unrelated to the load current.
The maximum RMS input current occurs at the maximum
output current. The maximum power dissipation in the
input capacitor equals the square of the maximum RMS
input current times the input capacitor’s total ESR.
COMPONENT SELECTION
Selection of components for the converter is an iterative
process which involves meeting the specifications and
tradeoffs between performance and cost. The following
sections will guide one through the process.
Ts
1
IIN_RMS
=
⋅ f 2
(
t
)
⋅dt
Inductor Selection
∫
Ts
0
Inductor selection involves meeting the steady state
output ripple requirement, minimizing the switching loss
of the upper MOSFET, meeting transient response
specifications and minimizing the output capacitance.
The output voltage includes a DC voltage and a small AC
ripple component due to the low pass filter which has
incomplete attenuation of the switching harmonics.
Neglecting the inductance in series with the output
2
1
ΔI
⎛
⎜
⎞
⎟
= IOUT ⋅ TON ⋅ Fs ⋅ 1+ ⋅
(6)
3
IOUT
⎝
⎠
The voltage rating of the input capacitor needs to be
greater than the maximum input voltage because of high
frequency ringing at the phase node. The typical
percentage is 25%.
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12A Highly Integrated SupIRBuckTM
IR3476
VESR is usually much greater than VESL. The IR3476
requires a total ESR such that the ripple voltage at the
FB pin is greater than 7mV.
Output Capacitor Selection
Selection of the output capacitor requires meeting
voltage overshoot requirements during load removal, and
meeting steady state output ripple voltage requirements.
The output capacitor is the most expensive converter
component and increases the overall system cost.
The output capacitor decoupling in the converter typically
includes the low frequency capacitor, such as Specialty
Polymer Aluminum, and mid frequency ceramic capacitors.
The second purpose of the output capacitor is to minimize
the overshoot of the output voltage when the load
decreases as shown in Figure 29. By using the law of
energy before and after the load removal, equation 8
shows the output capacitance requirement for a load
step down.
VOS
The first purpose of output capacitors is to provide current
when the load demand exceeds the inductor current,
as shown in Figure 28. Equation 7 shows the charge
requirement for a certain load step. The advantage
provided by the IR3476 at a load step is the reduced delay
compared to a fixed frequency control method. If the
load increases right after the PWM signal goes low, the
longest delay will be equal to the minimum lower gate
on‐time as shown in the Electrical Specifications section.
The IR3476 also reduces the inductor current slew time,
the time it takes for the inductor current to reach equality
with the output current, by increasing the switching
frequency up to 1/(TON + Min Off Time). This results in
reduced recovery time.
VOUT
VL
VDROP
VESR
ISTEP
IOUT
Figure 29: Typical Output Voltage Response Waveform
2
L ⋅ ISTEP
C
OUT
=
(8)
2
2
V
OS − VOUT
Boot Capacitor Selection
Load
Current
ISTEP
The boot capacitor starts the cycle fully charged to a
voltage of VB(0). Cg equals 0.58nF in IR3476. Choose a
sufficiently small ΔV such that VB(0)‐ΔV exceeds the
maximum gate threshold voltage to turn on the upper
MOSFET.
Output
Charge
Inductor
Slew
Rate
t
Δt
V (0)
⎛
⎜
⎞
B
CBOOT = C ⋅
−1 (9)
⎟
g
ΔV
⎝
⎠
Figure 28: Charge Requirement during Load Step
Choose a boot capacitor value larger than the calculated
BOOT in equation 9. Equation 9 is based on charge balance
C
Q = C⋅V = 0.5⋅ISTEP ⋅Δt (7a)
at CCM operation. Usually the boot capacitor will be
discharged to a much lower voltage when the circuit is
operating in DCM mode at light load, due to much longer
lower MOSFET off time and the bias current drawn by the
IC. Boot capacitance needs to be increased if insufficient
turn‐on of the upper MOSFET is observed at light load,
typically larger than 0.1µF is needed. The voltage rating of
this part needs to be larger than VB(0) plus the desired
derating voltage. It’s ESR and ESL needs to be low in order
to allow it to deliver the large current and di/dt’s which
drive MOSFETs most efficiently. In support of these
requirements a ceramic capacitor should be chosen.
2
⎡
⎤
1
1
2
L⋅ISTEP
C
OUT
=
⋅
(7b)
⎢
⎣
⎥
⎦
V
DROP
(
VIN −
V
OUT
)
The output voltage drop, VDROP, initially depends on the
characteristic of the output capacitor. VDROP is the sum of
the equivalent series inductance (ESL) of the output
capacitor times the rate of change of the output current
and the ESR times the change of the output current.
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12A Highly Integrated SupIRBuckTM
IR3476
loss as possible to increase the overall system efficiency.
For instance, choose a PIMB103E‐1R0MS‐39 manufactured by
CYNTEC. The inductance of this part is 1µH and has 2.7mΩ
DCR. Ripple current needs to be recalculated using the chosen
inductor.
DESIGN EXAMPLE
DESIGN CRITERIA
•
•
•
•
•
•
•
•
•
Input Voltage, VIN = 6V to 21V
Output Voltage, VOUT = 1.25V
1.25V ⋅
21V ⋅1μH ⋅ 400kHz
21V -1.25V
)
= 3A
2ΔI =
Switching Frequency, Fs = 400kHz
Inductor Ripple Current, 2ΔI = 3A
Maximum Output Current, IOUT = 12A
Over Current Trip, IOC = 18A
Choose an input capacitor:
2
1.25V
1 1.5A
⎛
3 12A
⎝
⎞
⎟
IIN_RMS =12A⋅
⋅ 1+ ⋅
= 2.9A
⎜
Current Transient Step Size = 5A
Overshoot Allowance, VOS = VOUT + 50mV
Undershoot Allowance, VDROP = 50mV
21V
⎠
A Panasonic 10µF (ECJ3YB1E106M) accommodates 6 Arms of
ripple current at 300kHz. Due to the chemistry of multilayer
ceramic capacitors, the capacitance varies over temperature
and operating voltage, both AC and DC. One 10µF capacitor is
recommended. In a practical solution, one 1µF capacitor is
required along with 10µF. The purpose of the 1µF capacitor is
to suppress the switching noise and deliver high frequency
current.
Find RFF:
1.25V
R
FF
=
=156 kΩ
1V ⋅ 20pF ⋅ 400kHz
Pick a standard value 158 kΩ, 1% resistor.
Find RSET:
Choose an output capacitor:
10mΩ
⋅
18A
To meet the undershoot and overshoot specification,
equations 7b and 8 will be used to calculate the minimum
output capacitance. As a result, 200μF will be needed for 5A
load removal. To meet the stability requirement, choose an
output capacitor with ESR larger than 6mΩ. Combine those
two requirements, one can choose a set of output capacitors
from manufactures such as SP‐Cap (Specialty Polymer
Capacitor) from Panasonic or POSCAP from Sanyo. A 220μF
(EEFSL0D221R) from Panasonic with 9mΩ ESR will meet both
requirements.
R
SET
=
= 9.5kΩ
19μA
Pick a 9.53kΩ, 1% standard resistor.
Find a resistive voltage divider for VOUT = 1.25V:
R
2
VFB
=
⋅ VOUT = 0.5V
1
R
2
+ R
R2 = 1.33kΩ, R1 = 1.96 kΩ, both 1% standard resistors.
If an all ceramic output capacitor solution is desired, the
external slope injection circuit composed of R6, C13, and C14
is required as explained in the Stability Considerations
section. In this design example, we can choose C14 = 1nF and
C13 = 100nF. To calculate the value of R6 with PIMB103E‐
1R0MS‐39 as our inductor:
Choose the soft start capacitor:
Once the soft start time has chosen, such as 1000us to
reach to the reference voltage, a 22nF for CSS is used to
meet 1000us.
Choose an inductor to meet the design specification:
L
R6 =
DCR ⋅C13
V
OUT
⋅
(
V
IN −
V
OUT
)
L =
1μH
2.7mΩ⋅100nF
= 3.7kΩ
V
IN ⋅ 2ΔI⋅ F
s
=
1.25V ⋅
21V ⋅3A⋅ 400kHz
(
21V -1.25V
)
=
=1.0μH
Pick a standard value for R6 = 3.74kΩ.
Choose the inductor with the lowest DCR and AC power
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
STABILITY CONSIDERATIONS
LAYOUT RECOMMENDATIONS
Bypass Capacitor:
Constant‐on‐time control is a fast, ripple based control
scheme. Unstable operation can occur if certain conditions
are not met. The system instability is usually caused by:
A 1µF high quality ceramic capacitor should be placed on
the same side as the IR3476 and connected to VCC and
PGND pins directly.
Switching noise coupled to FB input:
Boot Circuit:
This causes the PWM comparator to trigger prematurely
after the 500ns minimum on‐time for lower MOSFET.
It will result in double or multiple pulses every switching
cycle instead of the expected single pulse. Double pulsing
can causes higher output voltage ripple, but in most
application it will not affect operation. This can usually be
prevented by careful layout of the ground plane and the
FB sensing trace.
C
BOOT should be placed near the BOOT and PHASE pins to
reduce the impedance when the upper MOSFET turns on.
Power Stage:
Figure 30 shows the current paths and their directions
for the on and off periods. The on time path has low
average DC current and high AC current. Therefore, it is
recommended to place the input ceramic capacitor, upper,
and lower MOSFET in a tight loop as shown in Figure 30.
Steady state ripple on FB pin being too small:
The PWM comparator in IR3476 requires minimum
7mVp‐p ripple voltage to operate stably. Not enough ripple
will result in similar double pulsing issue described above.
Solving this may require using output capacitors with
higher ESR.
The purpose of the tight loop from the input ceramic
capacitor is to suppress the high frequency (10MHz range)
switching noise and reduce Electromagnetic Interference
(EMI). If this path has high inductance, the circuit will
cause voltage spikes and ringing, and increase the
switching loss. The off time path has low AC and high
average DC current. Therefore, it should be laid out with
a tight loop and wide trace at both ends of the inductor.
Lowering the loop resistance reduces the power loss. The
typical resistance value of 1‐ounce copper thickness is
0.5mΩ per square inch.
ESR loop instability:
The stability criteria of constant on‐time is:
ESR ⋅COUT > TON
2
If ESR is too small that this criteria is violated then sub‐
harmonic oscillation will occur. This is similar to the
instability problem of peak‐current‐mode control with
D>0.5. Increasing ESR is the most effective way to stabilize
the system, but the tradeoff is the larger output voltage
ripple.
Q1
Q2
System with all ceramic output capacitors:
For applications with all ceramic output capacitors, the ESR
is usually too small to meet the stability criteria. In these
applications, external slope compensation is necessary to
make the loop stable. The ramp injection circuit, composed
of R6, C13, and C14, shown in Figure 4 is required.
The inductor current ripple sensed by R6 and C13 is AC
coupled to the FB pin through C14. C14 is usually chosen
between 1 to 10nF, and C13 between 10 to 100nF. R6
should then be chosen such that L/DCR = C13*R6.
Figure 30: Current Path of Power Stage
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March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
PCB METAL AND COMPONENT PLACEMENT
•
Pad lands (the 4 big pads) length and width
should be equal to maximum part pad length and
width. However, the minimum metal to metal
spacing should be no less than; 0.17mm for 2 oz.
Copper or no less than 0.1mm for 1 oz. Copper or
no less than 0.23mm for 3 oz. Copper.
•
Lead lands (the 13 IC pins) width should be equal
to nominal part lead width. The minimum lead to
lead spacing should be ≥ 0.2mm to minimize
shorting.
•
Lead land length should be equal to maximum
part lead length + 0.3 mm outboard extension.
The outboard extension ensures a large toe fillet
that can be easily inspected.
Figure 31: Metal and Component Placement
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format
18
March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
SOLDER RESIST
•
Ensure that the solder resist in between the lead
lands and the pad land is ≥ 0.15mm due to the
high aspect ratio of the solder resist strip
•
It is recommended that the lead lands are Non
Solder Mask Defined (NSMD). The solder resist
should be pulled away from the metal lead lands
by a minimum of 0.025mm to ensure NSMD
pads.
separating the lead lands from the pad land.
•
The land pad should be Solder Mask Defined
(SMD), with a minimum overlap of the solder
resist onto the copper of 0.05mm to
accommodate solder resist misalignment.
Figure 32: Solder Resist
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format
19
March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
STENCIL DESIGN
•
The maximum length and width of the land pad
stencil aperture should be equal to the solder
resist opening minus an annular 0.2mm pull back
in order to decrease the risk of shorting the
center land to the lead lands when the part is
pushed into the solder paste.
•
The Stencil apertures for the lead lands should be
approximately 80% of the area of the lead lads.
Reducing the amount of solder deposited will
minimize the occurrences of lead shorts. If too
much solder is deposited on the center pad the
part will float and the lead lands will open.
Figure 33: Stencil Design
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format
20
March 27, 2013 | V2.2 | PD97603
12A Highly Integrated SupIRBuckTM
IR3476
PACKAGE INFORMATION
Figure 34: Package Dimensions
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial Market (Note2).
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
www.irf.com
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March 27, 2013 | V2.2 | PD97603
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