GRM31CR60J107ME39L_技术文档

Single-Input Voltage, Synchronous Buck Regulator

35A Highly Integrated SupIRBuck^®

IR3846

FEATURES

DESCRIPTION

The IR3846 SupIRBuck^®is an easy-to-use, fully

integrated and highly efficient DC/DC regulator. The

onboard PWM controller and MOSFETs make IR3846

a space-efficient solution, providing accurate power

delivery for low output voltage and high current

applications.

 Single 5V to 21V application

 Wide Input Voltage Range from 1.5V to 21V with

external Vcc

 Output Voltage Range: 0.6V to 0.86*PVin

 0.5% accurate Reference Voltage

 Enhanced line/load regulation with Feed-Forward

 Programmable Switching Frequency up to

IR3846 is

a

versatile regulator which offers

1.5MHz

programmability of switching frequency and current

limit while operating in wide input and output voltage

range.

 Internal Digital Soft-Start

 Enable input with Voltage Monitoring Capability

 Remote Sense Amplifier with True Differential

Voltage Sensing

The switching frequency is programmable from 300

kHz to 1.5MHz for an optimum solution.

 Thermally compensated current limit and Hiccup

Mode Over Current Protection

It also features important protection functions, such as

Over Voltage Protection (OVP), Pre-Bias startup,

hiccup current limit and thermal shutdown to give

required system level security in the event of fault

conditions.

 Smart LDO to enhance efficiency

 Vp for tracking applications and sequencing

 Vref is available externally to enable margining

 External synchronization with Smooth Clocking

 Dedicated output voltage sensing for power good

indication and overvoltage protection which

remains active even when Enable is low.

APPLICATIONS

 Enhanced Pre-Bias Start up

 Body Braking to improve transient

 Netcom Applications

 Integrated MOSFET drivers and Bootstrap diode

 Thermal Shut Down

 Embedded Telecom Systems

 Server Application

 Post Package trimmed rising edge dead-time

 Programmable Power Good Output with tracking

 Small Size 5mm x 7mm PQFN

 Distributed Point of Load Power Architectures

 Storage Applications

 Operating Junction Temp: -40^oC<Tj<125^oC

 Lead-free, Halogen-free and RoHS Compliant

ORDERING INFORMATION

Base Part

Standard Pack

Orderable Part

Number

Package Type

Number

Form

Quantity

750

IR3846

PQFN 5mm x 7mm

Tape and Reel

IR3846MTR1PBF

IR3846MTRPBF

4000

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August 01, 2013

IR3846

BASIC APPLICATION

Figure 1: IR3846 Basic Application Circuit

Figure 2: Efficiency [Vin=12V, Fsw=600kHz]

PIN DIAGRAM

5mm X 7mm POWER QFN

Top View

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August 01, 2013

IR3846

FUNCTIONAL BLOCK DIAGRAM

Figure 3: IR3846 Simplified Block Diagram

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August 01, 2013

IR3846

PIN DESCRIPTIONS

PIN #

PIN NAME

PIN DESCRIPTION

Input voltage for power stage. Bypass capacitors between PVin and

PGND should be connected very close to this pin and PGND; also forms

input to feedforward block

1

PVin

2, 3, 22, 23, 26

NC

Boot

No Connect

4

5

Supply voltage for high side driver

Enable pin to turning on and off the IC.

Enable

Use an external resistor from this pin to LGND to set the switching

frequency, very close to the pin. This pin can also be used for external

synchronization.

6

Rt/Sync

Current limit setpoint. This pin allows the trip point to be set to one of

three possible settings by either floating this pin, tying it to VCC or tying it

to PGnd.

7

8

OCset

Vsns

Sense pin for OVP and PGood

Inverting input to the error amplifier. This pin is connected directly to the

output of the regulator or to the output of the remote sense amplifier, via

resistor divider to set the output voltage and provide feedback to the

error amplifier.

9

FB

Output of error amplifier. An external resistor and capacitor network is

typically connected from this pin to FB to provide loop compensation.

10

11

COMP

RSo

Remote Sense Amplifier Output

Power ground. This pin should be connected to the system’s power

ground plane. Bypass capacitors between PVin and PGND should be

connected very close to PVIN pin (pin 1) and this pin.

12, 25

13

PGND

LGND

S_Ctrl

Signal ground for internal reference and control circuitry.

Soft start/stop control. A high logic input enables the device to go into the

internal soft start; a low logic input enables the output soft discharged.

Pull this pin high if this function is not used.

14

15

16

RS-

Remote Sense Amplifier input. Connect to ground at the load.

Remote Sense Amplifier input. Connect to output at the load.

RS+

External reference voltage can be used for margining operation. A

capacitor between 100pF and 180pF should be connected between this

pin and LGnd. Tie to LGnd for tracking function.

17

18

Vref

Vp

Used for voltage sequencing and tracking. Leave open if sequencing or

tracking is not needed, ensuring that there is no capacitor on the pin.

Power Good status pin. Output is open drain. Connect a pull up resistor

from this pin to VCC.

19

20

21

24

PGD

Vin

Input Voltage for LDO.

Bias Voltage for IC and driver section, output of LDO. Add a minimum of

4.7uF bypass cap from this pin to PGnd.

VCC/LDO_out

SW

Switch node. This pin is connected to the output inductor.

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August 01, 2013

IR3846

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only and functional operation of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications are not implied.

PVin

-0.3V to 25V

Vin

-0.3V to 25V

VCC

SW

BOOT

-0.3V to 8V (Note 1)

-0.3V to 25V (DC), -4V to 25V (AC, 100ns)

-0.3V to 33V

BOOT to SW

Input/Output pins

-0.3V to VCC + 0.3V (Note 2)

-0.3V to 3.9V

RS+, RS-, RSo, PGD, Enable, OCset, S_Ctrl

PGND to LGND, RS- to LGND

Junction Temperature Range

Storage Temperature Range

Machine Model

-0.3V to 8V (Note 1)

-0.3V to + 0.3V

-40°C to 150°C

-55°C to 150°C

Class A

ESD

Human Body Model

Class 1C

Charged Device Model

Class III

Moisture Sensitivity level

RoHS Compliant

JEDEC Level 3 @ 260°C

Yes

Note:

1. VCC must not exceed 7.5V for Junction Temperature between -10°C and -40°C.

2. Must not exceed 8V.

THERMAL INFORMATION

Thermal Resistance, Junction to Case (θ_{JC_TOP}

)

30 °C/W

Thermal Resistance, Junction to PCB (θ_JB)

2.71 °C/W

Thermal Resistance, Junction to Ambient (θ_JA) (Note 3) 14.3 °C/W

Note:

3. Thermal resistance (θ_JA) is measured with components mounted on a high effective thermal conductivity

test board in free air.

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August 01, 2013

IR3846

ELECTRICAL SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

SYMBOL

UNIT

DEFINITION

Input Bus Voltage *

Supply Voltage

Supply Voltage **

Supply Voltage

Output Voltage

MIN

1.5

5.0

4.5

0.6

0

MAX

21

7.5

PVin

Vin

VCC

V

Boot to SW

V_O

I_O

0.86 PVin

±35

Output Current

A

Fs

T_J

Switching Frequency

Junction Temperature

300

-40

1500

125

kHz

°C

*

**

SW node must not exceed 25V

When VCC is connected to an externally regulated supply, also connect Vin.

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, these specification apply over, 1.5V < PVin < 21V, 4.5V< VCC < 7.5V, 0^oC < T_J<

125^oC.

Typical values are specified at T_A= 25^oC.

PARAMETER

Power Loss

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

V_in= PV_in= 12V, V_O=

1.2V, I_O= 35A, Fs =

600kHz, L=0.250uH,

T_A= 25°C, Note 4

Power Loss

P_LOSS

5.3

W

MOSFET R_ds(on)

V_Boot– V_SW= 6.8V,

Top Switch

Rds(on)_Top

Rds(on)_Bot

3.1

4

I_D= 35A, Without Cu

Clip, Tj = 25°C

mΩ

VCC =6.8V, I_D= 35A,

With Cu Clip,

Bottom Switch

1.27

1.64

Tj = 25°C

Reference Voltage

Feedback Voltage

V_FB

0.6

V

Vref=0.6V,

-0.5

-1.0

+0.5

+1.0

0°C < Tj < 105°C

Accuracy

%

Vref=0.6V,

-40°C < Tj < 125°C

Sink Current

Isink_Vref

Isrc_Vref

Vref=0.7V

Vref=0.5V

12.7

16.0

19.3

µA

Source Current

Vref Pin connected

externally

Vref_disable

Vref_enable

0.15

V

Vref Comparator Threshold

0.4

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IR3846

PARAMETER

Supply Current

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

V_inSupply Current

(Standby)

Vin=21V, Enable low,

No Switching

I_in(Standby)

I_in(Dyn)

I_cc(Standby)

I_cc(Dyn)

300

425

40

µA

mA

µA

V_inSupply Current (Dyn)

Vin=21V, Enable high,

Fs = 600kHz

VCC Supply Current

(Standby)

Enable low, VCC=7V,

No Switching

300

425

40

VCC Supply Current (Dyn)

Enable high, VCC=7V,

Fs = 600kHz

mA

Under Voltage Lockout

VCC–Start–Threshold

VCC–Stop–Threshold

Enable–Start–Threshold

Enable–Stop–Threshold

Enable leakage current

Oscillator

VCC_UVLO_Start

VCC_UVLO_Stop

VCC Rising Trip Level

VCC Falling Trip Level

4.0

3.7

4.2

3.9

1.2

1.0

4.4

4.2

1.36

1.06

1

V

Enable_UVLO_Start Supply ramping up

Enable_UVLO_Stop Supply ramping down

1.14

0.9

V

Ien

Enable=3.3V

µA

Rt Voltage

1

V

Rt=80.6k

Rt=39.2k

Rt=15k

270

540

300

600

330

660

Frequency Range

F_S

kHz

1350

1500 1650

PVin=6.8V, PVin(max)

slew rate=1V/us,

1.02

Note 4

PVin=12V, PVin(max)

slew rate=1V/us,

Ramp Amplitude

Vramp

1.8

2.4

Vp-p

Note 4

PVin=16V, PVin(max)

slew rate=1V/us,

Note 4

Ramp Offset

Ramp (os)

Tmin (ctrl)

0.16

50

V

Min Pulse Width

Fixed Off Time

Max Duty Cycle

ns

200

230

Dmax

Fs=300kHz,

PVin=Vin=12V

86

%

Sync Frequency Range

Sync Pulse Duration

Note 4

270

100

3

1650

kHz

ns

200

High

Low

Sync Level Threshold

V

0.6

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August 01, 2013

IR3846

PARAMETER

Error Amplifier

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

%

VFb – Vref, Vref =

0.6V

Vos_Vref

-1.5

+1.5

Vref

Input Offset Voltage

Vos_Vp

IFb(E/A)

IVp(E/A)

Isink(E/A)

Isource(E/A)

SR

VFb – Vp, Vp = 0.6V

-1.5

-0.5

0

+1.5

+0.5

4

%Vp

µA

Input Bias Current

Sink Current

µA

0.4

4

0.85

7.5

12

1.2

11

mA

V/µs

MHz

dB

Source Current

Slew Rate

Note 4

7

20

Gain-Bandwidth Product

DC Gain

GBWP

20

100

30

40

Gain

110

120

Maximum Output

Voltage

Vmax(E/A)

1.7

2

2.3

V

Minimum Output Voltage

Common Mode Voltage

Margining Range

Vmin(E/A)

Vcm_Vp

100

1.2

mV

V

Note 4

0

Vmarg_Vref

0.4

V

Remote Sense Differential Amplifier

Unity Gain Bandwidth

DC Gain

BW_RS

Note 4

3

6.4

9

MHz

dB

Gain_RS

110

Vref=0.6V,

-1.5

-2

0

1.5

2

mV

0°C < Tj < 85°C

Offset Voltage

Offset_RS

Vref=0.6V,

-40°C < Tj < 125°C

Source Current

Sink Current

Isource_RS

Isink_RS

Slew_RS

Rin_RS+

Rin_RS-

3

0.4

2

13

1

20

2

mA

Slew Rate

Note 4, Cload = 100pF

4

8

V/µs

kohm

V

RS+ input impedance

RS- input impedance

Maximum Voltage

Minimum Voltage

Internal Digital Soft Start

Soft Start Clock

45

63

1

85

Note 4

Vmax_RS

Min_RS

V(VCC) – V(RSo)

0.5

1.5

50

mV

Clk_SS

Note 4

180

0.3

2.4

200

0.4

220

0.5

kHz

mV /

µs

Soft Start Ramp Rate

S_CTRL Threshold

Ramp(SS_Start)

High

Low

V

0.6

Bootstrap Diode

Forward Voltage

I(Boot) = 30mA

360

520

960

mV

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August 01, 2013

IR3846

PARAMETER

Switch Node

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

SW = 0V, Enable = 0V

SW Leakage Current

lsw

1

µA

SW = 0V, Enable =

HIGH, Vp=0 V

Internal Regulator (VCC/LDO)

Vin(min) = 7.2V, Io=0-

30mA, Cload = 2.2uF,

DCM=0

6.3

4

6.8

4.4

7.1

Output Voltage

VCC

V

Vin(min) = 7.2V, Io=0-

30mA, Cload = 2.2uF,

DCM=1

4.8

0.7

Vin = 7V, Io=70 mA,

Cload = 2.2uF

VCC dropout

VCC_drop

Ishort

V

mA

s

Short Circuit Current

Note 4

70

Zero-crossing

Comparator Delay

256 /

Fs

Tdly_zc

Zero-crossing

Comparator Offset

Vos_zc

0

mV

%

Body Braking

Fb > Vref, Sw duty

cycle, Note 3

BB Threshold

BB_threshold

0

FAULTS

Power Good

Vsns Rising,

115

1.5

120

2.5

95

125

3.5

% Vref

% Vp

µs

0.4V < Vref < 1.2V

Power Good Low Upper

Threshold

VPG_low(upper)

Vsns Rising,

Vref < 0.1V

Power Good Low Upper

Threshold Falling delay

Vsns >

VPG_low(upper)

VPG_low(upper)_Dly

VPG_high(lower)

Vsns Rising,

% Vref

% Vp

ms

0.4V < Vref < 1.2V

Power Good High Lower

Threshold

Vsns Rising,

Vref < 0.1V

95

Power Good High Lower

Threshold Rising Delay

VPG_high(lower)_Dly Vsns rising

Vsns falling,

1.28

90

% Vref

%Vp

0.4V < Vref < 1.2V

Power Good Low Lower

Threshold

VPG_low(lower)

Vsns falling,

0.1V < Vref

90

Power Good Low Lower

Threshold Falling delay

Vsns <

VPG_low(lower)

VPG_low(lower)_Dly

PG (voltage)

101

150

199

0.5

µs

V

PGood Voltage Low

I_PGood= -5mA

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August 01, 2013

IR3846

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Tracker Comparator

Upper Threshold

VPG(tracker_upper) Vp Rising, Vref < 0.1V

0.4

V

Tracker Comparator

Lower Threshold

VPG(tracker_lower)

Tdelay(tracker)

Vp Falling, Vref < 0.1V

Vp Rising, Vref < 0.1V

0.3

Tracker Comparator

Delay

1.28

ms

Over Voltage Protection (OVP)

Vsns Rising,

115

120

125

% Vref

0.45V < Vref < 1.2V

OVP Trip Threshold

OVP (trip)

Vsns Rising,

Vref < 0.1V

115

1.5

120

2.5

125

3.5

% Vp

µs

OVP Fault Prop Delay

OVP (delay)

Vsns rising

Over-Current Protection

OCSet=VCC, VCC =

6.8V, TJ = 25°C

41

32

24

44.4

35

48

38

30

A

OCSet=floating, VCC

= 6.8V, TJ = 25°C

OC Trip Current

I_TRIP

OCSet=PGnd, VCC

=6.8V, TJ = 25°C

26.88

20.48

A

Hiccup blanking time

Thermal Shutdown

Hysteresis

Tblk_Hiccup

Note 4

ms

Note 4

145

20

°C

Notes:

4. Guaranteed by design but not tested in production.

August 01, 2013

IR3846

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = Vin = 12V, VCC = Internal LDO, Io=0-35A, Fs= 600kHz, Room Temperature, LFM=200. Note that the

losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves.

The table below shows the indicator used for each of the output voltages in the efficiency measurement.

VOUT (V)

1.2

LOUT (uH)

0.25

P/N

DCR (mΩ)

0.165

744309025 (Wurth Electronik)

744309033 (Wurth Electronik)

1.8

3.3

5.0

0.33

0.165

August 01, 2013

IR3846

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = 12V, Vin = VCC = 5V, Io=0-35A, Fs= 600kHz, Room Temperature, LFM=200. Note that the losses of the

inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table

below shows the indicator used for each of the output voltages in the efficiency measurement.

VOUT (V)

1.2

LOUT (uH)

0.25

P/N

DCR (mΩ)

0.165

744309025 (Wurth Electronik)

744309033 (Wurth Electronik)

1.8

3.3

5.0

0.33

0.165

August 01, 2013

IR3846

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = Vin = VCC = 5V, Io=0-25A, Fs= 600kHz, Room Temperature, LFM=200. Note that the losses of the

inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table

below shows the indicator used for each of the output voltages in the efficiency measurement.

VOUT (V)

1.0

LOUT (uH)

0.19

P/N

DCR (mΩ)

0.200

SL40307A-R19KHF (ITG)

1.2

0.19

0.200

August 01, 2013

IR3846

MOSFET RDSON VARIATION OVER TEMPERATURE

August 01, 2013

IR3846

TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C)

August 01, 2013

IR3846

TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C)

April 29, 2013

IR3846

TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C)

OCset=VCC

OCset=Float

OCset=GND

OCset=Float

OCset=GND

OCset=VCC

OCset=Float

OCset=GND

August 01, 2013

IR3846

THEORY OF OPERATION

set thresholds. Normal operation resumes once VCC

and Enable rise above their thresholds.

DESCRIPTION

The IR3846 uses a PWM voltage mode control

scheme with external compensation to provide good

noise immunity and maximum flexibility in selecting

inductor values and capacitor types.

The POR (Power On Ready) signal is generated when

all these signals reach the valid logic level (see

system block diagram). When the POR is asserted the

soft start sequence starts (see soft start section).

The switching frequency is programmable from

300kHz to 1.5MHz and provides the capability of

optimizing the design in terms of size and

performance.

ENABLE

The Enable features another level of flexibility for

startup. The Enable has precise threshold which is

internally monitored by Under-Voltage Lockout

(UVLO) circuit. Therefore, the IR3846 will turn on only

when the voltage at the Enable pin exceeds this

threshold, typically, 1.2V.

IR3846 provides precisely regulated output voltage

programmed via two external resistors from 0.6V to

0.86*PVin.

The IR3846 operates with an internal bias supply

(LDO) which is connected to the VCC pin. This allows

operation with single supply. The bias voltage is

variable according to load condition. If the output load

current is less than half of the peak-to-peak inductor

current, a lower bias voltage, 4.4V, is used as the

internal gate drive voltage; otherwise, a higher

voltage, 6.8V, is used.

If the input to the Enable pin is derived from the bus

voltage by a suitably programmed resistive divider, it

can be ensured that the IR3846 does not turn on until

the bus voltage reaches the desired level as shown in

Figure 4. Only after the bus voltage reaches or

exceeds this level and voltage at the Enable pin

exceeds its threshold, IR3846 will be enabled.

Therefore, in addition to being a logic input pin to

enable the IR3846, the Enable feature, with its precise

threshold, also allows the user to implement an

Under-Voltage Lockout for the bus voltage (PVin). It

can help prevent the IR3846 from regulating at low

PVin voltages that can cause excessive input current.

This feature helps the converter to reduce power

losses. The device can also be operated with an

external bias from 4.5V to 7.5V, allowing an extended

operating input voltage (PVin) range from 1.5V to 21V.

For using the internal LDO supply, the Vin pin should

be connected to PVin pin. If an external bias is used, it

should be connected to VCC pin and the Vin pin

should be shorted to VCC pin.

The device utilizes the on-resistance of the low side

MOSFET (synchronous Mosfet) as current sense

element. This method enhances the converter’s

efficiency and reduces cost by eliminating the need for

external current sense resistor.

IR3846 includes two low R_ds(on)MOSFETs using IR’s

HEXFET technology. These are specifically designed

for high efficiency applications.

UNDER-VOLTAGE LOCKOUT AND POR

Figure 4: Normal Start up, device turns on when the

bus voltage reaches 10.2V

The under-voltage lockout circuit monitors the voltage

of VCC pin and the Enable input. It assures that the

MOSFET driver outputs remain in the off state

whenever either of these two signals drops below the

A resistor divider is used at EN pin from PVin to turn

on the device at 10.2V.

August 01, 2013

IR3846

input. In this operating mode Vref is left floating.

Figure 6 shows the recommended startup sequence

for sequenced operation of IR3846 with Enable used

as logic input. Figure 7 shows the recommended

startup sequence for tracking operation of IR3846 with

Enable used as logic input. For this mode of

operation, Vref should be connected to LGND.

PVin=Vin

Vcc

Vp

> 1.0V

> 1.2V

EN

PRE-BIAS STARTUP

Intl_SS

Vo

IR3846 is able to start up into pre-charged output,

which prevents oscillation and disturbances of the

output voltage.

Figure 5: Recommended startup for Normal operation

The output starts in asynchronous fashion and keeps

the synchronous MOSFET (Sync FET) off until the

first gate signal for control MOSFET (Ctrl FET) is

PVin=Vin

Vcc

generated. Figure

8 shows a typical Pre-Bias

condition at start up. The sync FET always starts with

a narrow pulse width (12.5% of a switching period)

and gradually increases its duty cycle with a step of

12.5% until it reaches the steady state value. The

number of these startup pulses for each step is 16

and it’s internally programmed. Figure 9 shows the

series of 16x8 startup pulses.

Vp

> 1.2V

EN

Intl_SS

Vo

[V]

Vo

Figure 6: Recommended startup for sequencing

operation (ratiometric or simultaneous)

Pre-Bias

Voltage

PVin=Vin

Vcc

[Time]

Figure 8: Pre-Bias startup

VDDQ

...

VDDQ/2

Vp

HDRv

...

87.5%

12.5%

16

25%

> 1.2V

0V

EN

Vref

Vo

...

LDRv

...

End of

PB

16

VTT Tracking

Figure 9: Pre-Bias startup pulses

SOFT-START

Figure 7: Recommended startup for memory tracking

operation (Vtt-DDR)

IR3846 has an internal digital soft-start to control the

output voltage rise and to limit the current surge at the

start-up. To ensure correct start-up, the soft-start

sequence initiates when the Enable and VCC rise

Figure 5 shows the recommended startup sequence

for the normal (non-tracking, non-sequencing)

operation of IR3846, when Enable is used as a logic

August 01, 2013

IR3846

Table 1: Switching Frequency(Fs) vs. External

above their UVLO thresholds and generate the Power

On Ready (POR) signal. The internal soft-start

(Intl_SS) signal linearly rises with the rate of 0.4mV/µs

from 0V to 1.5V. Figure 10 shows the waveforms

during soft start. The normal Vout startup time is fixed,

and is equal to:

Resistor(Rt)

Freq

Rt (Kꢀ)

(KHz)

80.6

60.4

48.7

39.2

34

300

400

500

600

700



0.75V  0.15V

0.4mV / S



1.5mS

Tstart 

(1)

29.4

26.1

23.2

21

19.1

17.4

16.2

15

800

900

During the soft start the over-current protection (OCP)

and over-voltage protection (OVP) is enabled to

protect the device for any short circuit or over voltage

condition.

1000

1100

1200

1300

1400

1500

POR

3.0V

1.5V

0.75V

SHUTDOWN

0.15V

IR3846 can be shutdown by pulling the Enable pin

below its 1.0V threshold. During shutdown the high

side and the low side drivers are turned off.

Intl_SS

Vout

OVER CURRENT PROTECTION

t

2

t

3

1

The Over Current (OC) protection is performed by

sensing the inductor current through the R_DS(on)of the

Synchronous MOSFET. This method enhances the

converter’s efficiency, reduces cost by eliminating a

current sense resistor and any layout related noise

issues. The Over Current (OC) limit can be set to one

of three possible settings by floating the OCset pin, by

pulling up the OCset pin to VCC, or pulling down the

OCset pin to PGnd. The current limit scheme in the

IR3846 uses an internal temperature compensated

current source to achieve an almost constant OC limit

over temperature.

Figure 10: Theoretical operation waveforms during

soft-start (non tracking / non sequencing)

OPERATING FREQUENCY

The switching frequency can be programmed between

300kHz – 1500kHz by connecting an external resistor

from R_tpin to LGnd. Table 1 tabulates the oscillator

frequency versus R_t.

Over Current Protection circuit senses the inductor

current flowing through the Synchronous MOSFET.

To help minimize false tripping due to noise and

transients, inductor current is sampled for about 30 nS

on the downward inductor current slope approximately

12.5% of the switching period before the inductor

current valley. However, if the Synchronous MOSFET

is on for less than 12.5% of the switching period, the

current is sampled approximately 40nS after the start

of the downward slope of the inductor current. When

August 01, 2013

IR3846

the sampled current is higher than the OC Limit, an

OC event is detected.

Automatic restart is initiated when the sensed

temperature drops within the operating range. There

is a 20^oC hysteresis in the thermal shutdown

threshold.

When an Over Current event is detected, the

converter enters hiccup mode. Hiccup mode is

performed by latching the OC signal and pulling the

Intl_SS signal to ground for 20.48 mS (typ.). OC

signal clears after the completion of hiccup mode and

the converter attempts to return to the nominal output

voltage using a soft start sequence. The converter will

repeat hiccup mode and attempt to recover until the

overload or short circuit condition is removed.

REMOTE VOLTAGE SENSING

True differential remote sensing in the feedback loop

is critical to high current applications where the output

voltage across the load may differ from the output

voltage measured locally across an output capacitor

at the output inductor, and to applications that require

die voltage sensing.

Because the IR3846 uses valley current sensing, the

actual DC output current limit will be greater than OC

limit. The DC output current is approximately half of

peak to peak inductor ripple current above selected

OC limit. OC Limit, inductor value, input voltage,

output voltage and switching frequency are used to

calculate the DC output current limit for the converter.

Equation (2) to determine the approximate DC output

current limit.

The RS+ and RS- pins of the IR3846 form the inputs

to a remote sense differential amplifier (RSA) with

high speed, low input offset and low input bias current

which ensure accurate voltage sensing and fast

transient response in such applications.

The input range for the differential amplifier is limited

to 1.5V below the VCC rail. Note that IR3846

incorporates a smart LDO which switches the VCC rail

voltage depending on the loading. When determining

the input range assume the part is in light load and

using the lower VCC rail voltage.

i

I_OCP I_LIMIT



(2)

2

I_OCP

I_LIMIT

∆i

= DC current limit hiccup point

= Current Limit Valley Point

= Inductor ripple current

There are two remote sense configurations that are

usually implemented. Figure 12 shows a general

remote sense (RS) configuration. This configuration

allows the RSA to monitor output voltages above

VCC. A resistor divider is placed in between the

output and the RSA to provide a lower input voltage to

the RSA inputs. Typically, the resistor divider is

calculated to provide VREF (0.6V) across the RSA

inputs which is then outputted to RSo. The input

impedance of the RSA is 63 KOhms typically and

should be accounted for when determining values for

the resistor divider. To account for the input

impedance, assume a 63 KOhm resistor in parallel to

the lower resistor in the divider network.

The

compensation is then designed for 0.6V to match the

RSo value.

Figure 11: Timing Diagram for Current Limit Hiccup

Low voltage applications can use the second remote

sense configuration. When the output voltage range

is within the RSA input specifications, no resistor

divider is needed in between the converter output and

RSA. The second configuration is shown in Figure

13. The RSA is used as a unity gain buffer and

compensation is determined normally.

THERMAL SHUTDOWN

Temperature sensing is provided inside IR3846. The

trip threshold is typically 145^oC. When trip threshold is

exceeded, thermal shutdown turns off both MOSFETs

and resets the internal soft start.

August 01, 2013

IR3846

transitions to output voltage, a diode is recommended

to add between the external clock and Rt/Sync pin.

Figure 14 shows the timing diagram of these

transitions.

Resistor Divider

RS+ RSo

+

FB

-

Vout

(< VCC-1.5V)

RSA

RS-

An internal circuit is used to change the PWM ramp

slope according to the clock frequency applied on

Rt/Sync pin. Even though the frequency of the

external synchronization clock can vary in a wide

range, the PLL circuit keeps the ramp amplitude

constant, requiring no adjustment of the loop

compensation. PVin variation also affects the ramp

amplitude, which will be discussed separately in Feed-

Forward section.

-

Figure 12: General Remote Sense Configuration

Synchronize to the

external clock

Free Running

Frequency

Returntofree-

running freq

...

SW

Figure 13: Remote Sense Configuration for Vout less

than VCC-1.5V

Gradually change

Fs1

SYNC

Fs1

...

EXTERNAL SYNCHRONIZATION

Fs2

IR3846 incorporates an internal phase lock loop (PLL)

circuit which enables synchronization of the internal

oscillator to an external clock. This function is

important to avoid sub-harmonic oscillations due to

beat frequency for embedded systems when multiple

point-of-load (POL) regulators are used. A multi-

function pin, Rt/Sync, is used to connect the external

clock. If the external clock is present before the

converter turns on, Rt/Sync pin can be connected to

the external clock signal solely and no other resistor is

needed. If the external clock is applied after the

converter turns on, or the converter switching

frequency needs to toggle between the external clock

frequency and the internal free-running frequency, an

external resistor from Rt/Sync pin to LGnd is required

to set the free-running frequency.

Figure 14: Timing Diagram for Synchronization

to the external clock (Fs1>Fs2 or Fs1<Fs2)

FEED-FORWARD

Feed-Forward (F.F.) is an important feature, because

it can keep the converter stable and preserve its load

transient performance when PVin varies. The PWM

ramp amplitude (Vramp) is proportionally changed

with PVin to maintain PVin/Vramp almost constant

throughout PVin variation range (as shown in Figure

15). The PWM ramp amplitude is adjusted to 0.15 of

PVin. Thus, the control loop bandwidth and phase

margin can be maintained constant. Feed-forward

function can also minimize impact on output voltage

from fast PVin change. F.F. is disabled when

PVin<6.2V and the PWM ramp is typically 0.9V. For

PVin<6.2V, PVin voltage should be accounted for

when calculating control loop parameters.

When an external clock is applied to Rt/Sync pin after

the converter runs in steady state with its free-running

frequency,

a

transition from the free-running

frequency to the external clock frequency will happen.

This transition is to gradually make the actual

switching frequency equal to the external clock

frequency, no matter which one is higher. When the

external clock signal is removed from Rt/Sync pin, the

switching frequency is also changed to free-running

gradually. In order to minimize the impact from these

August 01, 2013

IR3846

Users can configure the IR3846 to use a single supply

or dual supplies. Depending on the configuration used

the PVin, Vin and VCC pins are connected differently.

Below several configurations are shown.

In an

internally biased configuration, the LDO draws from

the Vin pin and provides a gate drive voltage, as

shown in Figure 17. By connecting Vin and PVin

together as shown in the Figure 18, IR3846 is an

internally biased single supply configuration that runs

off a single supply.

Figure 15: Timing Diagram for Feed-Forward (F.F.)

Function

IR3846 can also use an external bias to provide gate

drive voltage for the drivers instead of the internal

LDO. To use an external bias, connected Vin and

VCC to the external bias. PVin can use a separate rail

as shown in Figure 19 or run off the same rail as Vin

and VCC.

SMART LOW DROPOUT REGULATOR (LDO)

IR3846 has an integrated low dropout (LDO) regulator

which can provide gate drive voltage for both drivers.

In order to improve overall efficiency over the whole

load range, LDO voltage is set to 6.8V (typ.) at mid- or

heavy load condition to reduce Rds(on) and thus

MOSFET conduction loss; and it is reduced to 4.4V

(typ.) at light load condition to reduce gate drive loss.

The smart LDO selects its output voltage according to

the load condition by sensing the inductor current (I_L).

At light load condition, the inductor current can fall

below zero as shown in Figure 16. A zero crossing

comparator is used to detect when the inductor

current falls below zero at the LDrv Falling Edge. If the

comparator detects zero crossing events for 256

consecutive switching cycles, the smart LDO reduces

its output to 4.4V. The LDO voltage will remain low

until a zero crossing is not detected. Once a zero

crossing is not detected, the counter is reset and LDO

voltage returns to 6.8V. Figure 16 shows the timing

diagram. Whenever the device turns on, LDO always

starts with 6.8V, then goes to 4.4V / 6.8V depending

upon the load condition. However, if only Vin is

applied with Enable low, the LDO output is 4.4V.

Figure 17: Internally Biased Configuration

Figure 18: Internally Biased Single Supply

Configuration

Figure 16: Time Diagram for Smart LDO

August 01, 2013

IR3846

For normal operation, Vp and Vref is left floating (Vref

should have a bypass capacitor).

Therefore, in normal operating condition, after Enable

goes high, the internal soft-start (Intl_SS) ramps up

the output voltage until Vfb (voltage of feedback/Fb

pin) reaches about 0.6V. Then Vref takes over and the

output voltage is regulated.

Tracking-mode operation is achieved by connecting

Vref to LGND. Then, while Vp = 0V, Enable is taken

above its threshold so that the soft-start circuit

generates Intl_SS signal. After the Intl_SS signal

reaches the final value (refer to Figure 7), ramping up

the Vp input will ramp up the output voltage. In

tracking mode, Vfb always follows Vp which means

Vout is always proportional to Vp voltage (typical for

DDR/Vtt rail applications). The effective Vp range is

0V~1.2V.

Figure 19: Externally Biased Configuration

When the Vin voltage is below 6.8V, the internal LDO

enters the dropout mode at medium and heavy load.

The dropout voltage increases with the switching

frequency. Figure 20 shows the LDO voltage for

600kHz

and

1000kHz

switching

frequency

respectively.

In sequencing mode of operation (simultaneous or

ratiometric), Vref is left floating and Vp is kept to

ground level until Intl_SS signal reaches the final

value. Then Vp is ramped up and Vfb follows Vp.

When Vp>0.6V the error-amplifier switches to Vref

and the output voltage is regulated with Vref. The

final Vp voltage after sequencing startup should

between 0.8V ~ 3.0V.

Figure 20: LDO_Out Voltage in dropout mode

OUTPUT VOLTAGE TRACKING AND

SEQUENCING

IR3846 can accommodate user programmable

tracking and/or sequencing options using Vp, Vref,

Enable, and Power Good pins. In the block diagram

presented on page 3, the error-amplifier (E/A) has

been depicted with three positive inputs. Ideally, the

input with the lowest voltage is used for regulating the

output voltage and the other two inputs are ignored. In

practice the voltage of the other two inputs should be

at least 200mV greater than the low-voltage input so

that their effects can completely be ignored. Vp is

pulled up to an internal rail via a high impedance path.

Figure 21: Typical waveforms for sequencing mode of

operation: (a) simultaneous, (b) ratiometric

August 01, 2013

IR3846

Tracking and sequencing operations can be

implemented to be simultaneous or ratiometric (refer

to Figure 21 and Figure 22). Figure 23 shows typical

circuit configuration for sequencing operation. With

this power-up configuration, the voltage at the Vp pin

of the slave reaches 0.6V before the Fb pin of the

master. If R_E/R_F=R_C/R_D, simultaneous startup is

achieved. That is, the output voltage of the slave

follows that of the master until the voltage at the Vp

pin of the slave reaches 0.6 V. After the voltage at the

Vp pin of the slave exceeds 0.6V, the internal 0.6V

reference of the slave dictates its output voltage. In

reality the regulation gradually shifts from Vp to

internal Vref. The circuit shown in Figure 23 can also

be used for simultaneous or ratiometric tracking

operation if Vref of the slave is connected to LGND.

Table 2 summarizes the required conditions to

achieve

simultaneous/ratiometric

tracking

or

sequencing operations.

Figure 22: Typical waveforms in tracking mode of

operation: (a) simultaneous, (b) ratiometric

Table 2: Required Conditions for Simultaneous /

Ratiometric Tracking and Sequencing (Figure 23)

Operating

Mode

Vref

(Slave)

Required

Condition

Vp

Normal

(Non-

0.6

(Floating)

Floating

―

sequencing,

Non-tracking)

Simultaneous

Sequencing

Ramp

up from

0V

R_A/R_B>

R_E/R_F=

R_C/R_D

R_A/R_B>

R_E/R_F>

R_C/R_D

0.6V

0V

Ratiometric

Sequencing

Ramp

up from

0V

Simultaneous

Tracking

Ramp

up from

0V

R_E/R_F=

R_C/R_D

Ratiometric

Tracking

Ramp

up from

0V

R_E/R_F>

R_C/R_D

0V

VREF

This pin reflects the internal reference voltage which is

used by the error amplifier to set the output voltage. In

most operating conditions this pin is only connected to

an external bypass capacitor and it is left floating. A

minimum 100pF ceramic capacitor is required from

stability point of view. In tracking mode this pin should

be pulled to LGND. For margining applications, an

external voltage source is connected to Vref pin and

Figure 23: Application Circuit for Simultaneous and

Ratiometric Sequencing

August 01, 2013

IR3846

overrides the internal reference voltage. The external

voltage source should have a low internal resistance

(<100ꢀ) and be able to source and sink more than

25µA.

POWER GOOD OUTPUT (TRACKING,

SEQUENCING, VREF MARGINING)

IR3846 continually monitors the output voltage via the

sense pin (Vsns) voltage. The Vsns voltage is an input

to the window comparator with upper and lower

threshold of 1.2*VREF and 0.95*VREF respectively.

PGood signal is high whenever Vsns voltage is within

the PGood comparator window thresholds. Hysteresis

has been applied to the lower threshold, PGood signal

goes low when Vsns drops below 0.9*VREF instead

of 0.95*VREF. The PGood pin is open drain and it

needs to be externally pulled high. High state

indicates that output is in regulation.

Figure 25: Vp Tracking (Vref = 0V)

The threshold is set differently in different operating

modes and the results of the comparison sets the

PGood signal. Figure 24, Figure 25 and Figure 26

show the timing diagram of the PGood signal at

different operating modes. Vsns signal is also used by

OVP comparator for detecting output over voltage

condition. PGood signal is low when Enable is low.

Vref

0.6V

0

1.2*VREF

0.90*VREF

Figure 26: Vp Sequence and Vref Margin

Vsns

0.95*VREF

0

OVER-VOLTAGE PROTECTION (OVP)

Over-voltage protection in IR3846 is achieved by

comparing sense pin voltage Vsns to a pre-set

threshold. In non-tracking mode, OVP threshold can

be set at 1.2*Vref; in tracking mode, it can be at

1.2*Vp. When Vsns exceeds the over voltage

threshold, an over voltage trip signal asserts after 2.5

uS (typ.) delay. The high side drive signal HDrv is

latched off immediately and PGood flags are set low.

The low side drive signal is kept on until the Vsns

voltage drops below the threshold. HDrv remains

latched off until a reset is performed by cycling VCC.

OVP is active when enable is high or low.

OVP

Latch

PGD

0

1.28 mS 150 uS 1.28 mS

2.5 uS

Figure 24: Non-sequence, Non-tracking Startup

and Vref Margin (Vp pin floating)

August 01, 2013

IR3846

Figure 29 shows the timing diagram of Enable

controlled soft-start and soft-stop.

Vsns voltage is set by the voltage divider connected to

the output and it can be programmed externally.

Figure 27 shows the timing diagram for OVP in non-

tracking mode.

Enable

0

S_Ctrl

0

0.65V

0.15V

0.65V

0.15V

Intl

_SS

0

Vout

0

Figure 28: Timing Diagram for S_Ctrl controlled Soft-

Start / Soft-Stop

S_Ctrl

0

Enable

1.2V

1.0V

Figure 27: Timing Diagram for OVP in non-tracking

mode

0

0.65V

0.15V

Intl

_SS

SOFT-START / SOFT-STOP (S_CTRL)

S_Ctrl allows for the gradual charging and discharging

of Vout to its final value by controlling the Soft-Start

and Soft-Stop functions. Soft-Start and Soft-Stop is

the gradual charging and discharging of Vout,

respectfully. Both functions use the internal Intl_SS

ramp to regulate the rate Vout charges and

discharges. Soft-Start feature is enabled when S_Ctrl

and EN are asserted high. S_Ctrl is internally pulled

high, so that EN typically controls the rise of Vout. To

delay the charging of Vout, keep S_Ctrl low while

setting EN. Then assert S_Ctrl high to initiate the

Intl_SS ramp (Soft-Start). Vout follows Intl_SS and

ramps up until it reaches its steady state. For Soft-

Stop, S_Ctrl needs to be pulled low before EN goes

low. When S_Ctrl falls below its lower threshold,

Intl_SS becomes a decreasing ramp with the same

rate as the Soft-Start ramp. Vout follows this ramp and

discharges softly until completely shut down. Figure

28 shows the timing diagram of S_Ctrl controlled soft-

start and soft-stop.

Vout

0

Figure 29: Timing Diagram for Enable controlled Soft-

Start / Shutdown

BODY BRAKING^TM

The Body Braking feature of the IR3846 allows

improved transient response for step-down load

transients. A severe step-down load transient would

cause an overshoot in the output voltage and drive the

Comp pin voltage down until control saturation occurs

demanding 0% duty cycle and the PWM input to the

Control FET driver is kept OFF. When the first such

skipped pulse occurs, the IR3846 enters Body Braking

mode, wherein the Sync FET also turned OFF. The

inductor current then decays by freewheeling through

the body diode of the Sync FET. Thus, with Body

Braking, the forward voltage drop of the body diode

provides and additional voltage to discharge the

inductor current faster to the light load value as shown

in equation (3) and equation (4) below:

If the Enable pin goes low before S_Ctrl, the converter

shuts down without Soft-Stop. Both gate drivers are

turned off immediately and Vout discharges to zero.

August 01, 2013

IR3846

The minimum output voltage is limited by the

di_L

V_oV_D

 

, with body braking

(3)

(4)

reference voltage and hence V_out(min)

Therefore, for V_out(min)= 0.6V,

=

0.6V.

dt

di_L

L

V_o

, without body braking

V_out

PV_in F_s

t_on(min)

dt

I_L

V_D

L

(9)

= Inductor current

= Forward voltage drop of the body diode of

the Sync FET.

= output voltage

0.6V

PV_in F_s

12V / S

V_o

L

50nS

= Inductor value

Therefore, at the maximum recommended input

voltage 21V and minimum output voltage, the

The Body Braking mechanism is kept OFF during pre-

bias operation. Also, in the event of an extremely

severe load step-down transient causing OVP, the

Body Brake is overridden by the OVP latch, which

turns on the Sync FET.

converter should be designed at

a

switching

frequency that does not exceed 571 kHz. Conversely,

for operation at the maximum recommended

operating frequency (1.5 MHz) and minimum output

voltage (0.6V). The input voltage (PVin) should not

exceed 8V, otherwise pulse skipping may happen.

MINIMUM ON TIME CONSIDERATIONS

The minimum ON time is the shortest amount of time

for Ctrl FET to be reliably turned on. This is very

critical parameter for low duty cycle, high frequency

applications. Conventional approach limits the pulse

width to prevent noise, jitter and pulse skipping. This

results to lower closed loop bandwidth.

MAXIMUM DUTY RATIO

A certain off-time is specified for IR3846. This

provides an upper limit on the operating duty ratio at

any given switching frequency. The off-time remains

at a relatively fixed ratio to switching period in low and

mid frequency range, while in high frequency range

this ratio increases, thus the lower the maximum duty

ratio at which IR3846 can operate. Figure 30 shows a

plot of the maximum duty ratio vs. the switching

frequency with built in input voltage feed forward

mechanism.

IR has developed a proprietary scheme to improve

and enhance minimum pulse width which utilizes the

benefits of voltage mode control scheme with higher

switching frequency, wider conversion ratio and higher

closed loop bandwidth, the latter results in reduction

of output capacitors. Any design or application using

IR3846 must ensure operation with a pulse width that

is higher than the minimum on-time. This is necessary

for the circuit to operate without jitter and pulse-

skipping, which can cause high inductor current ripple

and high output voltage ripple.

V_out

F_sPV_in F_s

D

t_on



(5)

In any application that uses IR3846, the following

condition must be satisfied:

t_on(min) t_on

(6)

(7)

V_out

t_on(min)



PV_in F_s

V_out

PV_in F_s

(8)

Figure 30: Maximum duty cycle vs. switching

frequency

t_on(min)

August 01, 2013

IR3846

TYPICAL OPERATING WAVEFORM

DESIGN EXAMPLE

Output Voltage Programming

Output voltage is programmed by reference voltage

and external voltage divider. The FB pin is the

inverting input of the error amplifier, which is internally

referenced to VREF. The divider ratio is set to equal

VREF at the FB pin when the output is at its desired

value. When an external resistor divider is connected

to the output as shown in Figure 32, the output

voltage is defined by using the following equation:

The following example is a typical application for

IR3846. The application circuit is shown in Figure 37.

V_in= PV_in= 12V

F_s= 600kHz

V_o= 1.2V

I_o= 35A

Ripple Voltage = ± 1% * V_o

∆V_o= ± 4% * Vo (for 30% load transient)





R



⁵

V_oV_ref 1

(12)

(13)







R₆



Enabling the IR3846

As explained earlier, the precise threshold of the

Enable lends itself well to implementation of a UVLO

for the Bus Voltage as shown in Figure 31.













V_ref

V_oV_ref

R₆ R₅

For the calculated values of R5 and R6, see feedback

compensation section.

Figure 31: Using Enable pin for UVLO implementation

For a typical Enable threshold of V_EN= 1.2 V

Figure 32: Typical application of the IR3846 for

programming the output voltage

R₂

PV_in(min)



V_EN1.2

(10)

(11)

R₁ R₂

Bootstrap Capacitor Selection

To drive the Control FET, it is necessary to supply a

gate voltage at least 4V greater than the voltage at the

SW pin, which is connected to the source of the

Control FET. This is achieved by using a bootstrap

configuration, which comprises the internal bootstrap

diode and an external bootstrap capacitor (C1). The

operation of the circuit is as follows: When the sync

FET is turned on, the capacitor node connected to SW

is pulled down to ground. The capacitor charges

towards V_ccthrough the internal bootstrap diode

(Figure 33), which has a forward voltage drop V_D. The

voltage V_cacross the bootstrap capacitor C1 is

approximately given as:

V_EN

R₂ R₁

PV_in(min)V_EN

For PV_{in (min)}=9.2V, R₁=49.9K and R₂=7.5K ohm is a

good choice.

Programming the frequency

For F_s= 600 kHz, select R_t= 39.2 Kꢀ, using Table 1.

V_cV_ccV_D

(14)

April 29, 2013 | V1.0

IR3846

When the control FET turns on in the next cycle, the

capacitor node connected to SW rises to the bus

voltage V_in. However, if the value of C1 is

appropriately chosen, the voltage V_cacross C1

remains approximately unchanged and the voltage at

the Boot pin becomes:

efficiency. For this application, it is advisable to have

7x22uF,

25V

ceramic

capacitors,

GRM31CR61E226KE15L from Murata. In addition to

these, although not mandatory, a 1x330uF, 25V SMD

capacitor EEV-FK1E331P from Panasonic may also

be used as a bulk capacitor and is recommended if

the input power supply is not located close to the

converter.

V_Boot PV_inV_ccV_D

(15)

Inductor Selection

Inductors are selected based on output power,

operating frequency and efficiency requirements. A

low inductor value causes large ripple current,

resulting in the smaller size, faster response to a load

transient but may also result in reduced efficiency and

high output noise. Generally, the selection of the

inductor value can be reduced to the desired

maximum ripple current in the inductor (∆i). The

optimum point is usually found between 20% and 50%

ripple of the output current. For the buck converter,

the inductor value for the desired operating ripple

current can be determined using the following relation:

Figure 33: Bootstrap circuit to generate Vc voltage

i

t

1

V_inV_o L  ;t  D 

F_s

A bootstrap capacitor of value 0.1uF is suitable for

most applications.

V_o

L 



V_inV_o





(18)

V_in i  F_s

Input Capacitor Selection

The ripple currents generated during the on time of

the control FETs should be provided by the input

capacitor. The RMS value of this ripple for each

channel is expressed by:

Where:

V_in= Maximum input voltage

V₀= Output Voltage

∆i = Inductor Ripple Current

F_s= Switching Frequency

I_RMS I_o D



1 D



(16)

(17)

∆

D

= On time for Control FET

= Duty Cycle

t

V_o

D 

V_in

If ∆i ≈ 30%*I_o, then the inductor is calculated to be

0.24μH. Select L=0.25μH, 744309025, from Wurth

Electronik which provides an inductor suitable for this

application.

Where:

D

= Duty Cycle

I_RMS= RMS value of the input capacitor current

I_o= output current.

V_in= Power Stage input voltage

Output Capacitor Selection

The voltage ripple and transient requirements

determine the output capacitors type and values. The

criterion is normally based on the value of the

Effective Series Resistance (ESR). However the

actual capacitance value and the Equivalent Series

Inductance (ESL) are other contributing components.

These components can be described as:

I_o=35A and D = 0.1, the I_RMS= 10.5A.

Ceramic capacitors are recommended due to their

peak current capabilities. They also feature low ESR

and ESL at higher frequency which enables better

August 01, 2013

IR3846

1

V_o V_{o } V_{o } V_o(C)



ESR



ESL

F_LC

2  L_oC_o

V_0(ESR) I_L ESR

(20)

V V

L

I_L





_o



in

V_0(ESL)

V_0(C)



 ESL

Figure 34 shows gain and phase of the LC filter. Since

we already have 180^ophase shift from the output filter

alone, the system runs the risk of being unstable.







(19)

8C_o F_s

Phase

Gain

0⁰

0dB

Where:

∆V₀= Output Voltage Ripple

∆I_L= Inductor Ripple Current

-40dB/Decade

-90⁰

Since the output capacitor has a major role in the

overall performance of the converter and determines

the result of transient response, selection of the

capacitor is critical. The IR3846 can perform well with

all types of capacitors.

-180⁰

Frequency

F_LC

Figure 34: Gain and Phase of LC filter

The IR3846 uses a voltage-type error amplifier with

high-gain and high-bandwidth. The output of the

amplifier is available for DC gain control and AC

phase compensation.

As a rule, the capacitor must have low enough ESR to

meet output ripple and load transient requirements.

The goal for this design is to meet the voltage ripple

requirement in the smallest possible capacitor size.

Therefore it is advisable to select ceramic capacitors

due to their low ESR and ESL and small size. Six of

Murata GRM31CR60J107ME39L (100uF/1206/X5R/

6.3V) capacitors is a good choice.

The error amplifier can be compensated either in type

II or type III compensation. Local feedback with Type

II compensation is shown in Figure 35.

This method requires that the output capacitor have

enough ESR to satisfy stability requirements. If the

output capacitor’s ESR generates a zero at 5kHz to

50kHz, the zero generates acceptable phase margin

and the Type II compensator can be used.

It is also recommended to use a 0.1µF ceramic

capacitor at the output for high frequency filtering.

Feedback Compensation

The IR3846 is a voltage mode controller. The control

loop is a single voltage feedback path including error

amplifier and error comparator. To achieve fast

transient response and accurate output regulation, a

compensation circuit is necessary. The goal of the

compensation network is to provide a closed-loop

transfer function with the highest 0 dB crossing

frequency and adequate phase margin (greater than

45^o).

The ESR zero of the output capacitor is expressed as

follows:

1

F_ESR



(21)

2  ESRC_o

The output LC filter introduces a double pole, -

40dB/decade gain slope above its corner resonant

frequency, and a total phase lag of 180^o. The resonant

frequency of the LC filter is expressed as follows:

August 01, 2013

IR3846

V^OUT

Use the following equation to calculate R3:

Z _IN

C_POLE

C3

V_ramp F_o F_ESR R₅

V_in   F_L²_C

R3

R₃

(26)

R5

Z f

Where:

Fb

E/A

Ve

V_ramp= Amplitude of the oscillator Ramp Voltage

F_o= Crossover Frequency

R6

Comp

VREF

F_ESR= Zero Frequency of the Output Capacitor

Gain(dB)

R₅= Feedback Resistor

H(s) dB

V_in= Maximum Input Voltage

β

= (RS+ - RS-) / Vo

F_LC= Resonant Frequency of the Output Filter

Frequency

F_POLE

F_Z

To cancel one of the LC filter poles, place the zero

before the LC filter resonant frequency pole:

Figure 35: Type II compensation network and its

asymptotic gain plot

F_Z 75% F_LC

The transfer function (V_e/V_out) is given by:

1

F_Z 0.75

(27)

Z _f

V_e

1 sR₃C₃

sR₅C₃

2 L_oC_o

 H(s)  

 

(22)

V_out

Z_IN

Use equation (24), (25) and (26) to calculate C3.

The (s) indicates that the transfer function varies as a

function of frequency. This configuration introduces a

gain and zero, expressed by:

One more capacitor is sometimes added in parallel

with C3 and R3. This introduces one more pole which

is mainly used to suppress the switching noise.

R₃

The additional pole is given by:

H(s) 

(23)

(24)

R₅

1

F_p

(28)

1

C₃C_POLE

C₃ C_POLE

F_z

2 

2  R₃C₃

First select the desired zero-crossover frequency (F_o):

(25)

The pole sets to one half of the switching frequency

which results in the capacitor C_POLE

:

F_o F_ESRand F_o (1/5 ~1/10) F_s

1

C_POLE





(29)

1

  R₃ F_S

  R₃ F_S

C₃

For a general unconditional stable solution for any

type of output capacitors with a wide range of ESR

values, we use a local feedback with a type III

compensation

network.

The

typically

used

compensation network for voltage-mode controller is

shown in Figure 36.

August 01, 2013

IR3846

V_OUT

R5

1

Z_IN

F_Z1

F_{Z 2}

(34)

(35)

C2

C3

2  R₃C₃

C4

R4

R3

1



2 C₄



R₃ R₅



2 C₄ R₅

Z_f

Cross over frequency is expressed as:

Fb

Ve

E A

/

R6

Comp

V_in

1

F_o R₃C₄  



V

REF

V_ramp2  L_oC_o

(36)

Gain (dB)

Based on the frequency of the zero generated by the

output capacitor and its ESR, relative to the crossover

frequency, the compensation type can be different.

Table 3 shows the compensation types for relative

locations of the crossover frequency.

|H(s)| dB

Frequency

F

P₃

P₂

Z₁

Z₂

Table 3: Different types of compensators

Figure 36: Type III Compensation network and its

asymptotic gain plot

Compensator

Type

Typical Output

Capacitor

F_ESRvs F_O

Again, the transfer function is given by:

F_LC< F_ESR< F_O<

F_S/2

Type II

Type III

Electrolytic

Z _f

V_e

 H(s)  

SP Cap,

Ceramic

F_LC< F_O< F_ESR

V_out

Z_IN

By replacing Z_inand Z_f, according to Figure 36, the

transfer function can be expressed as:

The higher the crossover frequency is, the potentially

faster the load transient response will be. However,

the crossover frequency should be low enough to

allow attenuation of switching noise. Typically, the

control loop bandwidth or crossover frequency (F_o) is

selected such that:



1 sR₃C₃





1 sC₄



R₄ R₅





H(s)  













C₂C₃

C₂ C₃





sR₅



C₂ C₃



1 sR



1 sR C₄



3

4







F 



1/5 ~1/10 *F



o

s

(30)

The DC gain should be large enough to provide high

DC-regulation accuracy. The phase margin should be

greater than 45^ofor overall stability.

The compensation network has three poles and two

zeros and they are expressed as follows:

The specifications for designing channel 1:

V_in= 12V

F_P1 0

F_P2

(31)

1

V_o= 1.2V

(32)

(33)

2  R₄C₄

V_ramp= 1.8V (This is a function of Vin, pls. see

Feed-Forward section)

V_ref= 0.6V

1

F_P3







2  R₃C₂

C₂C₃

C₂ C₃

β

= (RS+ - RS-) / Vo (This assumes the resistor

divider placed between Vout and the RSA

scales down the output voltage to Vref. If the

RSA is not used or Vout is connected directly





2  R₃





August 01, 2013

IR3846

to the RSA, β = 1. Please refer to the Remote

Sensing Amplifier section)

L_o= 0.250 µH

2  F_o L_oC_oV_osc

C₄V_in 

R₃

; R₃= 3.60 kꢀ,

C_o= 6 x 100µF, ESR≈3mꢀ each

Select: R₃= 2.7 kꢀ

It must be noted here that the value of the

capacitance used in the compensator design must be

the small signal value. For instance, the small signal

capacitance of the 100µF capacitor used in this

design is 56µF at 1.2 V DC bias and 600 kHz

frequency. It is this value that must be used for all

computations related to the compensation. The small

signal value may be obtained from the manufacturer’s

datasheets, design tools or SPICE models.

Alternatively, they may also be inferred from

measuring the power stage transfer function of the

converter and measuring the double pole frequency

F_LCand using equation (20) to compute the small

signal C_o.

1

C₃

; C₃= 8.49 nF,

2  F_Z1 R₃

Select: C₃= 8.2 nF

1

C₂

; C₂= 196 pF,

2  F_P3 R₃

Select: C₂= 160 pF

Calculate R₄, R₅and R₆:

1

R₄

; R₄= 127.6 ꢀ,

These result to:

2 C₄ F_P2

F_LC= 17.4 kHz

F

_ESR= 947 kHz

Select R₄= 127 ꢀ

F_s/2 = 300 kHz

Select crossover frequency F₀=100 kHz

1

R₅

; R₅= 5.13 kꢀ,

Since F_LC<F₀<Fs/2<F_ESR, Type III is selected to place

the pole and zeros.

2 C₄ F_{Z 2}

Select R₅= 4.02 kꢀ

Detailed calculation of compensation Type III:

V_ref

Desired Phase Margin Θ = 70°

R₆

 R₅; R₆= 4.02 kꢀ,



 V_oV_ref



1 sin

1 sin

F_{Z 2} F_o

 14.1 kHz

567.1 kHz

Select R₆= 4.02 kꢀ

If (β x V_o) equals Vref, R6 is not used.

1 sin 

1 sin 

F_P2 F

o

Setting the Power Good Threshold

In this design IR3846, the PGood outer limits are set

at 95% and 120% of VREF. PGood signal is asserted

1.3ms after Vsns voltage reaches 0.95*0.6V=0.57V

(Figure 37). As long as the Vsns voltage is between

the threshold ranges, Enable is high, and no fault

happens, the PGood remains high.

Select:

F_Z1 0.5 F_{Z 2} 7.05 kHz and

F_P3 0.5 F  300 kHz

s

The following formula can be used to set the PGood

Select C₄= 2.2nF.

threshold. V_{out (PGood}_TH can be taken as 95% of Vout.

)

Choose Rsns1=4.02 Kꢀ.

Calculate R₃, C₃and C₂:

August 01, 2013

IR3846

Vout__OVP= 1.44 V

V





out(PGood _ TH )





Rsns2 

1  Rsns1

(37)





0.95VREF



Selecting Power Good Pull-Up Resistor

The PGood is an open drain output and require pull

up resistors to VCC. The value of the pull-up resistors

should limit the current flowing into the PGood pin to

less than 5mA. A typical value used is 10kꢀ.

Rsns2 = 4.02 kꢀ, Select 4.02 kꢀ.

OVP comparator also uses Vsns signal for Over-

Voltage detection. With above values for Rsns2 and

Rsns1, OVP trip point (Vout_{_OVP}) is



Rsns1 Rsns2

Rsns1



Vout_{_ OVP}VREF 1.2 

(38)

August 01, 2013

IR3846

TYPICAL APPLICATION

INTERNALLY BIASED SINGLE SUPPLY

Vin

Ren2

49.9 K

Cpvin1

330uF

Cpvin2

7 x 22uF

Cpvin3

0.1uF

Ren1

7.5 K

Cboot

0.1uF

En

PVin

Boot

S_Ctrl

Vo

SW

Vin

Vp

Lo

0.250uH

Rsns2

4.02 K

Rsns1

4.02 K

Cvin

1uF

Cout

Co1

VSNS

6 x 100uF 0.1 uF

Vcc

RS+

RS-

Cvcc

10uF

IR3846

Rpg

10 K

OCselect

PGood

Vref

PGood

RSo

Rbode

20

Comp

FB

Cc3

Cc2

8.2nF

Rc2

Cc1

160pF

2200pF

Rc1

Rt/Sync

Rfb2

Cref

100pF

4.02 K

AGND

PGND

2.7 K

127

Rt

39.2 K

Rfb1

4.02 K

Figure 37: Application circuit for a 12V to 1.2V, 21A Point of Load Converter Using the Internal LDO

Suggested Bill of Material for application circuit 12V to 1.2V

Part Reference

Cpvin1

Qty

1

7

Value

330uF

22uF

Description

SMD, electrolytic, 25V, 20%

Manufacturer

Panasonic

Murata

Part Number

EEV-FK1E331P

GRM31CR61E226KE15L

Cpvin2

1206, 25V, X5R, 10%

Cref

Cvin

1

3

1

6

100pF

1.0uF

10uF

0.1uF

2200pF

8.2nF

160pF

100uF

0603, 50V, C0G, 5%

0603, 25V, X5R, 20%

0603, 10V, X5R, 20%

0603, 25V, X7R, 10%

0603, 50V, X7R, 10%

0603, 50V, NPO, 5%

Murata

TDK

Murata

GRM1885C1H101JA01D

GRM188R61E105KA12D

C1608X5R1A106M

GRM188R71E104KA01D

GRM188R71H222KA01D

GRM188R71H822KA01D

GRM1885C1H161JA01D

GRM31CR60J107ME39L

Cvcc

Cpvin3 Cboot Co1

Cc1

Cc2

Cc3

Cout1

1206, 6.3V, X5R, 20%

250nH,14x13x9mm

DCR=0.165ohm

Wurth

L0

1

0.250uH

744309025

Electronik Inc.

Panasonic

Rbd

Rc1

Rc2

Ren1

Ren2

1

20

127

2.7K

7.5K

49.9K

Thick Film, 0603, 1/10W, 1%

ERJ-3EKF20R0V

ERJ-3EKF1270V

ERJ-3EKF2701V

ERJ-3EKF7501V

ERJ-3EKF4992V

Rfb1 Rfb2

Rsns1Rsns1

4

4.02K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF4021V

Rt

Rpg

1

39.2K

10K

Thick Film, 0603, 1/10W, 1%

Panasonic

International

Rectifier

ERJ-3EKF3922V

ERJ-3EKF1002V

U1

1

IR3846

PQFN 5x7mm

IR3846MPBF

August 01, 2013

IR3846

EXTERNALLY BIASED DUAL SUPPLIES

Figure 38: Application circuit for a 12V to 1.2V, 21A Point of Load Converter using external 5V VCC

Suggested Bill of Material for application circuit 12V to 1.2V using external 5V VCC

Part Reference

Qty

Value

Description

Manufacturer

Part Number

Cpvin1

1

330uF

SMD, electrolytic, 25V, 20%

Panasonic

EEV-FK1E331P

Cpvin2

Cref

Cvin

Cvcc

7

1

3

1

6

22uF

100pF

1.0uF

10uF

0.1uF

2200pF

8.2nF

160pF

100uF

1206, 25V, X5R, 10%

0603, 50V, C0G, 5%

0603, 25V, X5R, 20%

0603, 10V, X5R, 20%

0603, 25V, X7R, 10%

0603, 50V, X7R, 10%

0603, 50V, NPO, 5%

1206, 6.3V, X5R, 20%

Murata

TDK

Murata

GRM31CR61E226KE15L

GRM1885C1H101JA01D

GRM188R61E105KA12D

C1608X5R1A106M

GRM188R71E104KA01D

GRM188R71H222KA01D

GRM188R71H822KA01D

GRM1885C1H161JA01D

GRM31CR60J107ME39L

Cpvin3 Cboot Co1

Cc1

Cc2

Cc3

Cout1

250nH,14x13x9mm

DCR=0.165ohm

Wurth

Electronik Inc.

L0

1

0.250uH

744309025

Rbd

Rc1

Rc2

Ren1

Ren2

1

20

127

2.7K

7.5K

49.9K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF20R0V

ERJ-3EKF1270V

ERJ-3EKF2701V

ERJ-3EKF7501V

ERJ-3EKF4992V

Rfb1 Rfb2

Rsns1Rsns1

Rt

4

4.02K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF4021V

1

39.2K

10K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF3922V

ERJ-3EKF1002V

Rpg

International

Rectifier

U1

1

IR3846

PQFN 5x7mm

IR3846MPBF

August 01, 2013

IR3846

EXTERNALLY BIASED SINGLE SUPPLY

Vin

Ren2

41.2 K

Cpvin1

330uF

Cpvin2

7 x 22uF

Cpvin3

0.1uF

Ren1

21 K

Cboot

0.1uF

En

PVin

Boot

Vo

SW

VSNS

RS+

Vin

Lo

0.190uH

Rsns2

4.53 K

Rsns1

4.53 K

Cvin

1uF

Cout

Co1

Vp

6 x 100 uF 0.1 uF

Vcc

Cvcc

10uF

Rpg

10 K

IR3846

RS-

OCselect

PGood

Vref

PGood

RSo

Rbode

20

Comp

FB

Cc3

Cc2

Cc1

100pF

8.2nF

Rc2

3.9 K

2200pF

Rc1

78.7

Rt/Sync

Rfb2

4.53 K

Cref

100pF

AGND

PGND

Rt

Rfb1

4.53 K

39.2 K

Figure 39: Application circuit for a 5V to 1.2V, 21A Point of Load Converter

Suggested bill of material for application circuit 5V to 1.2V

Part Reference

Qty

Value

Description

Manufacturer

Part Number

Cpvin1

1

330uF

SMD, electrolytic, 25V, 20%

Panasonic

EEV-FK1E331P

Cpvin2

Cref

Cvin

Cvcc

7

1

3

1

6

22uF

100pF

1.0uF

10uF

0.1uF

2200pF

8.2nF

100pF

100uF

1206, 25V, X5R, 10%

0603, 50V, C0G, 5%

0603, 25V, X5R, 20%

0603, 10V, X5R, 20%

0603, 25V, X7R, 10%

0603, 50V, X7R, 10%

0603, 50V, NPO, 5%

1206, 6.3V, X5R, 20%

Murata

TDK

Murata

GRM31CR61E226KE15L

GRM1885C1H101JA01D

GRM188R61E105KA12D

C1608X5R1A106M

GRM188R71E104KA01D

GRM188R71H222KA01D

GRM188R71H822KA01D

GRM1885C1H101JA01D

GRM31CR60J107ME39L

Cpvin3 Cboot Co1

Cc1

Cc2

Cc3

Cout1

Inter-

L0

1

0.190uH 10x6.8x7.3mm, DCR=0.20mꢀ

SL40307A-R19KHF

Technical,LLC

Panasonic

Rbd

Rc1

Rc2

Ren1

Ren2

1

20

78.7

3.9K

21K

Thick Film, 0603, 1/10W, 1%

ERJ-3EKF20R0V

ERJ-3EKF78R7V

ERJ-3EKF3901V

ERJ-3EKF2102V

ERJ-3EKF4122V

41.2K

Rfb1 Rfb2

Rsns1Rsns1

Rt

4

4.53K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF4531V

1

39.2K

10K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF3922V

ERJ-3EKF1002V

Rpg

International

Rectifier

U1

1

IR3846

PQFN 5x7mm

IR3846MPBF

August 01, 2013

IR3846

TYPICAL OPERATING WAVEFORMS

Vin=PVin=12V, Vout=1.2V, Iout=0-35A, Fs=600kHz, Room Temperature, No Air Flow

Figure 40: Startup with full load, Enable Signal

Figure 41: Startup with full load, VCC signal

CH1:Vin, CH2:Vout, CH3:PGood, CH4:Enable

CH1:Vin, CH2:Vout, CH3:PGood, CH4:VCC

Figure 42: Vout Startup with Pre-Bias, 1.08V

Figure 43: Recovery from Hiccup

Ch2:Vout, CH3:PGood

CH2:Vout, CH3:PGood, CH4:Iout

Figure 44: Inductor Switch Node at full load

Figure 45: Output Voltage Ripple at full load

CH2:SW

CH2:Vout

August 01, 2013

IR3846

TYPICAL OPERATING WAVEFORMS

Vin=PVin=12V, Vout=1.2V, Iout=3.5-14A, Fs=600kHz, Room Temperature, No air flow

Figure 46: Vout Transient Response, 3.5A to 14.0A step at 2.5A/uSec

CH2:Vout, CH4:Iout

August 01, 2013

IR3846

TYPICAL OPERATING WAVEFORMS

Vin=PVin=12V, Vout=1.2V, Iout=24.5-35A, Fs=600kHz, Room Temperature, No air flow

Figure 47: Vout Transient Response, 24.5A to 35A step at 2.5A/uSec

CH2:Vout, CH4:Iout

August 01, 2013

IR3846

TYPICAL OPERATING WAVEFORMS

Vin=PVin=12V, Vout=1.2V, Iout=35A, Fs=600kHz, Room Temperature, No air flow

Figure 48: Bode Plot with 35A load: Fo = 100.6 kHz, Phase Margin = 52.5 Degrees

August 01, 2013

IR3846

TYPICAL OPERATING WAVEFORMS

Vin=PVin=12V, Vout=1.2V, Iout=0-35A, Fs=600kHz, Room Temperature, No air flow

Figure 49: Efficiency versus load current

Figure 50: Power Loss versus load current

August 01, 2013

IR3846

LAYOUT RECOMMENDATIONS

The layout is very important when designing high

frequency switching converters. Layout will affect

noise pickup and can cause a good design to perform

with less than expected results.

pins. It is important to place the feedback components

including feedback resistors and compensation

components close to Fb and Comp pins.

In a multilayer PCB use at least one layer as a power

ground plane and have a control circuit ground

(analog ground), to which all signals are referenced.

The goal is to localize the high current path to a

separate loop that does not interfere with the more

sensitive analog control function. These two grounds

must be connected together on the PC board layout at

a single point. It is recommended to place all the

compensation parts over the analog ground plane in

top layer.

Make the connections for the power components in

the top layer with wide, copper filled areas or

polygons. In general, it is desirable to make proper

use of power planes and polygons for power

distribution and heat dissipation.

The inductor, input capacitors, output capacitors and

the IR3846 should be as close to each other as

possible. This helps to reduce the EMI radiated by the

power traces due to the high switching currents

through them. Place the input capacitor directly at the

PVin pin of IR3846.

The Power QFN is a thermally enhanced package.

Based on thermal performance it is recommended to

use at least a 6-layers PCB. To effectively remove

heat from the device the exposed pad should be

connected to the ground plane using vias. Figure

51a-f illustrates the implementation of the layout

guidelines outlined above, on the IRDC3846 6-layer

demo board.

The feedback part of the system should be kept away

from the inductor and other noise sources.

The critical bypass components such as capacitors for

PVin, Vin and VCC should be close to their respective

Vout

- Ground path between

VIN- and VOUT- should

be minimized with

maximum copper

-

PGND

- Bypass caps should be

placed as close as

possible to their

PVin

- Filled vias placed

under PGND and

PVin pads to help

thermal performance.

connecting pins

- Compensation parts

should be placed

as close as possible

to the Comp pins

- SW node copper is

kept only at the top

layer to minimize the

- Single point connection

between AGND &

PGND, should be placed

near the part and kept

away from noise sources

AGND

switching noise

PGND

Figure 51a: IRDC3846 Demo board Layout Considerations – Top Layer

August 01, 2013

IR3846

Vout

PVin

PGND

Figure 51b: IRDC3846 Demo board Layout Considerations – Bottom Layer

PGND

Figure 51c: IRDC3846 Demo board Layout Considerations – Mid Layer 1

PGND

Figure 51d: IRDC3846 Demo board Layout Considerations – Mid Layer 2

August 01, 2013

IR3846

Vout

PVin

PGND

Figure 51e: IRDC3846 Demo board Layout Considerations – Mid Layer 3

-Feedback and Vsns traces

routing should be kept away from

noise sources

PGND

Remote Sense Traces

- tap output where voltage value is

critical.

- Avoid noisy areas and noise coupling.

- RS+ and RS- lines near each other.

- Minimize trace resistance.

Figure 51f: IRDC3846 Demo board Layout Considerations – Mid Layer 4

August 01, 2013

IR3846

PCB METAL AND COMPONENT PLACEMENT

Evaluations have shown that the best overall

performance is achieved using the substrate/PCB

layout as shown in following figures. PQFN devices

should be placed to an accuracy of 0.050mm on both

X and Y axes. Self-centering behavior is highly

dependent on solders and processes, and

experiments should be run to confirm the limits of self-

centering on specific processes. For further

information, please refer to “SupIRBuck^®Multi-Chip

Module (MCM) Power Quad Flat No-Lead (PQFN)

Board Mounting Application Note.” (AN1132)

PAD SIZES

PCB SPACING

August 01, 2013

IR3846

SOLDER RESIST



IR recommends that the larger Power or Land

Area pads are Solder Mask Defined (SMD).

This allows the underlying Copper traces to be

as large as possible, which helps in terms of

current carrying capability and device cooling

capability.



However, for the smaller Signal type leads

around the edge of the device, IR recommends

that these are Non Solder Mask Defined or

Copper Defined.

When using NSMD pads, the Solder Resist

Window should be larger than the Copper Pad

by at least 0.025mm on each edge, (i.e.

0.05mm in X & Y), in order to accommodate any

layer to layer misalignment.



When using SMD pads, the underlying copper

traces should be at least 0.05mm larger (on

each edge) than the Solder Mask window, in

order to accommodate any layer to layer

misalignment. (i.e. 0.1mm in X & Y).



Ensure that the solder resist in-between the

smaller signal lead areas are at least 0.15mm

wide, due to the high x/y aspect ratio of the

solder mask strip.

PAD SIZES

PAD SPACING

August 01, 2013

IR3846

STENCIL DESIGN



Stencils for PQFN can be used with thicknesses of



Evaluations have shown that the best overall

performance is achieved using the stencil design

shown in following figure. This design is for a

stencil thickness of 0.127mm (0.005"). The

reduction should be adjusted for stencils of other

thicknesses.

0.100-0.250mm (0.004-0.010"). Stencils thinner

than 0.100mm are unsuitable because they

deposit insufficient solder paste to make good

solder joints with the ground pad; high

reductions sometimes create similar problems.

Stencils in the range of 0.125mm-0.200mm

(0.005-0.008"), with suitable reductions, give the

best results.

SOLDER PASTE STENCIL PAD SIZES

August 01, 2013

IR3846

SOLDER PASTE STENCIL PAD SPACING

(DETAIL 1)

SOLDER PASTE STENCIL PAD SPACING

(DETAIL 2)

August 01, 2013

IR3846

MARKING INFORMATION

Figure 52: Marking Information

PACKAGING INFORMATION

August 01, 2013

IR3846

August 01, 2013

IR3846

ENVIRONMENTAL QUALIFICATIONS

Industrial

Qualification Level

Moisture Sensitivity Level

5mm x 7mm PQFN

MSL3

Class A

<200V

Machine Model

(JESD22-A115A)

Class 1C

Human Body Model

(JESD22-A114F)

ESD

1000V to <2000V

Class III

Charged Device Model

(JESD22-C101D)

500V to ≤1000V

Yes

RoHS Compliant

Data and specifications subject to change without notice.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.

www.irf.com

August 01, 2013


型号：	GRM31CR60J107ME39L
厂家：	Infineon
描述：	Single-Input Voltage, Synchronous Buck Regulator 单输入电压，同步降压型稳压器稳压器
文件：	总53页 (文件大小：3243K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GRM31CR60J107ME39L [INFINEON]

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