HYB18T256321F-22 [INFINEON]
DDR DRAM, 8MX32, 0.45ns, CMOS, PBGA144, 11 X 11 MM, ROHS COMPLIANT, PLASTIC, MO-216, TFBGA-144;
| 型号： | HYB18T256321F-22 |
| 厂家： | 
Infineon |
| 描述： | DDR DRAM, 8MX32, 0.45ns, CMOS, PBGA144, 11 X 11 MM, ROHS COMPLIANT, PLASTIC, MO-216, TFBGA-144 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总83页 (文件大小：2114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.52, June 2004
HYB18T256321F–20
HYB18T256321F–22
HYB18T256321F–25
256-Mbit GDDR3 DRAM
RoHS compliant
Memory Products
N e v e r s t o p t h i n k i n g .
The information in this document is subject to change without notice.
Edition 06-2004
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, Rev. 1.52, June 2004
HYB18T256321F–20
HYB18T256321F–22
HYB18T256321F–25
256-Mbit GDDR3 DRAM
RoHS compliant
Memory Products
N e v e r s t o p t h i n k i n g .
HYB18T256321F–20 HYB18T256321F–22 HYB18T256321F–25
Revision History:
Rev. 1.52
06-2004
Previous Revision:
Rev. 1.5
2004-05
Page
11
Subjects (major changes since last revision)
table 1: added CL7
22
added to note 2 and 3: exept for READ, READ/A. WRITE, WRITE/A ends tWTR after the first pos.
edge of CLK following the last falling WDQS edge.
37, 78
50
Changed tRCmin-2.0 to 37.2ns
table 25: deleted tDQSQ min
changed TA <85 °C to TC<85 °C
table 34: VIH low changed
69-76
70
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Any information within this document that you feel is wrong, unclear or missing at all?
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Please send your proposal (including a reference to this document) to:
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Template: mp_a4_v2.3_2004-01-14.fm
HYB18T256321F–[20/22/25]
DDR SGRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
2.1
2.2
2.3
2.3.1
2.3.2
2.4
2.4.1
2.4.2
2.4.3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ball Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
State Diagram and Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
State Diagram for One Activated Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Function Truth Table for more than one Activated Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Function Truth Table for CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3
3.1
3.2
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clocks, CKE, Commands and Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Programmable impedance output drivers and active terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
GDDR3 IO Driver and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Self Calibration for Driver and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Dynamic Switching of DQ terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Output impedance and Termination DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 29
Extended Mode Register Set Command (EMRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DLL enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Termination Rtt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Output Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Vendor Code and Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Mode Register Set Command (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DLL Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Bank / Row Activation (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Writes (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Write Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Write - Basic Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Write - Consecutive Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Gapless Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Write with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Write followed by Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Write followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Write with Autoprecharge followed by Read / Read with Autoprecharge . . . . . . . . . . . . . . . . . . . . 47
Write followed by Precharge on same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Reads (RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Read - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Read - Basic Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Consecutive Read Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Gapless Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3.1
3.3.2
3.3.3
3.3.4
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.6
3.7
3.7.1
3.7.2
3.7.3
3.7.3.1
3.7.3.2
3.7.4
3.7.5
3.7.6
3.7.7
3.7.8
3.8
3.8.1
3.8.2
3.8.3
3.8.3.1
Data Sheet
5
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
3.8.5
3.8.6
3.9
3.9.1
3.9.2
3.10
3.11
3.12
3.12.1
3.12.2
3.13
Read followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Read followed by Precharge on the same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data Termination Disable (DTERDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DTERDIS followed by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DTERDIS followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Precharge (PRE/PREALL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Auto Refresh Command (AREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Self-Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Self-Refresh Entry (SREFEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Self-Refresh Exit (SREFEX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.7.1
4.8
4.9
4.10
4.11
4.11.1
4.12
4.13
4.14
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Recommended Power & DC Operation Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DC & AC Logic Input Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Differential Clock DC and AC Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Output Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Driver current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Driver IV characteristics at 40 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Termination IV Characteristic at 60 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Termination IV Characteristic at 120 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Termination IV Characteristic at 240 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Operating Current Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Summary of timing parameters for –2.0 ns, –2.2 ns and –2.5 ns speed sorts in DLL on mode . . . . . 78
AC Characteristics and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.1
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Data Sheet
6
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Key Timing and Power Supply Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Command Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Minimum delay from RD/A and WR/A to any other command (to another bank) with concurrent
Autoprecharge 20
Table 7
Table 8
Table 9
Function Truth Table I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Function Truth Table II (CKE Table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
General Timing Parameters for -2.0 ns, -2.2 ns and -2.5 ns speed sorts. . . . . . . . . . . . . . . . . . . . 24
Reset Timing Parameters for -2.0, -2.2 and -2.5 speed sorts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Range of external resistance ZQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Termination types and activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Termination update Keep Out time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Number of Legs used for Terminator and Driver Self Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
EMRS Timing Parameters for –2.0, –2.2 and –2.5 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision ID and Vendor Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Vendor Code and Revision ID Timing Parameters for -2.0, -2.2 and -2.5 speed sorts . . . . . . . . . 32
MRS Timing Parameters for –2.0, –2.2 and –2.5 speed sorts. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ACT Timing Parameters for –2.0, –2.2 and –2.5 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Mapping of WDQS and DM signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
WR Timing Parameters for –2.0, –2.2 and –2.5 speed sorts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
WL / CL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
READ Timing Parameters for -2.0 ns, -2.2 ns and -2.5 ns speed sorts . . . . . . . . . . . . . . . . . . . . . 50
BA1, BA0 precharge bank selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Precharge Timing Parameters for –2.0, –2.2 and –2.5 speed sorts . . . . . . . . . . . . . . . . . . . . . . . 63
Autorefresh Timing Parameters for –2.0, –2.2 and –2.5 speed sorts . . . . . . . . . . . . . . . . . . . . . . 64
Self Refresh Exit Timing Parameter for –2.0, –2.2 and –2.5 speed sorts . . . . . . . . . . . . . . . . . . . 66
Power Down Exit Timing Parameter for –2.0, –2.2 and –2.5 speed sorts. . . . . . . . . . . . . . . . . . . 67
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Power & DC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Differential Clock DC and AC Input conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Programmed Driver IV Characteristics at 40 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Programmed Terminator Characterisitc at 60 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Programmed Terminator Characterisitics at 120 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Programmed Terminator Characterisitc at 240 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Operating Current Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Timing Parameters for –2.0, –2.2 and –2.5 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
HYB18T256321F–20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
HYB18T256321F–22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
HYB18T256321F–25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
P-FBGA 144 Package Thermal Resitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Data Sheet
7
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Data Sheet
8
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Standard Ballout 256 Mbit GDDR3 Graphics RAM [500MHz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
State diagram for one bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock, CKE and Command/Address Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Driver simplified schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Termination update keep out time after Autorefresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Self Calibration of PMOS and NMOS Legs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ODT Disable Timing during a READ command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 10 Extended Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11 Extended Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12 Extended Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 13 Timing of Vendor Code and Revision ID generation on DQ[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 14 Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 15 Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 16 Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17 Activating a specific row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18 Bank Activation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20 Basic Write Burst / DM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 21 Write Burst Basic Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22 Gapless Write Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 23 Consecutive Write Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 24 Write with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 25 Write followed by Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 26 Write Command followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 27 Write with Autoprecharge followed by Read or Read with Autoprecharge on another bank . . . . . 47
Figure 28 Write followed by Precharge on same Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 29 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 30 Basic Read Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 31 Read Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 32 Gapless Consecutive Read Bursts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 33 Consecutive Read Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 34 Read Command followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 35 Read with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 36 Read followed by Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 37 Read followed by Precharge on the same Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 38 Data Termination Disable Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 39 DTERNIS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 40 DTERNIS followed by DTERNIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 41 DTERDIS Command followed by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 42 DTERDIS Command followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 43 Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 44 Precharge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 45 Auto Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 46 Auto Refresh Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 47 Self Refresh Entry Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 48 Self Refresh Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 49 Self Refresh Exit Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 50 Self Refresh Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 51 Power Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 52 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 53 Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 54 40 Ohm Driver Pull-Down and Pull-Up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 55 60 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Data Sheet
9
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Figure 56 120 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 57 240 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 58 Package Outline FBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Data Sheet
10
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
256-Mbit GDDR3 DRAM
HYB18T256321F–20
HYB18T256321F–22
HYB18T256321F–25
1
Overview
1.1
Features
•
•
•
Maximum clock frequency of 500 MHz
Organization: 2048K x 32 x 4 banks
4096 rows and 512 columns (128 burst start
locations) per bank
Differential clock inputs (CLK and CLK)
CAS latencies of 5, 6 and 7
Write latencies of 2, 3, 4
Fixed burst sequence with length of 4.
4n prefetch
•
Single ended WRITE strobe (WDQS) per byte.
WDQS center-aligned with WRITE data
DLL aligns RDQS and DQ transitions with Clock
Programmable IO interface including on chip
termination (ODT)
Autoprecharge option with concurrent
autoprecharge support
4k Refresh (32ms)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Autorefresh and Self Refresh
Short RAS to CAS timing for Writes
P-TFBGA 144 package (11mmx11mm)
VDD / VDDQ Voltage (according to Table 1)
Calibrated output drive. Active termination support.
RoHS compliant1)
t
t
RAS Lockout support
WR programmable for Writes with Auto-Precharge
Data mask for write commands
Single ended READ strobe (RDQS) per byte.
RDQS edge-aligned with READ data
Table 1
Key Timing and Power Supply Parameters
Speed Sort
Power Supply
CAS latency = 7
- 2.0
- 2.2
2.0 ± 100 mV
2.2
- 2.5
2.0 ± 100 mV
2.5
Units
V
V
DD / VDDQ
2.0 ± 100 mV
tCK7 min
fCK7 max
tCK6 min
fCK6 max
tCK5 min
fCK5 max
tACmin
2.0
ns
500
2.0
455
400
MHz
ns
CAS latency = 6
CAS latency = 5
Access Time
2.2
2.5
500
—
455
400
MHz
ns
2.7
3.0
—
370
333
MHz
ns
–0.4
0.4
–0.45
0.45
0.25
–0.5
0.5
tACmax
ns
RDQS-DQ Skew
tDQSQ
0.225
0.28
ns
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and
electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council
of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated
biphenyls and polybrominated biphenyl ethers.
Data Sheet
11
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Overview
Table 2
Ordering Information
Part Number1)
Organisation
V
DD / VDDQ (V)
Clock (MHz) Package
HYB18T256321F–20
HYB18T256321F–22
HYB18T256321F–25
×32
2.0
2.0
2.0
500
455
400
P-TBGA 144
1) HYB: designator for memory components
256: 256-Mbit density
F: lead free
1.2
General Description
The Infineon 256 Mbit GDDR3 Graphics RAM Read and write accesses to the HYB18T256321F are
[500MHz] is a high speed memory device, designed for burst oriented. The burst length is fixed to 4 and the two
high bandwidth intensive applications like PC graphics least significant bits of the burst address are ’Don’t
systems. The chip’s quad bank architecture is Care’ and internally set to LOW. Accesses begin with
optimized for high speed and achieves a peak the registration of an ACTIVATE command, which is
bandwidth of 4 Gbyte/s using a 32 bit interface and a then followed by a READ or WRITE command. The
maximum system clock of 500 MHz.
address bits registered coincident with the ACTIVATE
command are used to select the bank and the row to be
accessed. The address bits registered coincident with
the READ or WRITE command are used to select the
bank and the column location for the burst access.
Each of the 4 banks consists of 4096 row locations and
512 column locations. An AUTO PRECHARGE
function can be combined with READ and WRITE to
provide a self-timed row precharge that is initiated at
the end of the burst access. The pipelined, multibank
architecture of the HYB18T256321F allows for
concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
HYB18T256321F uses a double data rate interface and
a 4n-prefetch architecture. The GDDR3 interface
transfers two 32 bit wide data words per clock cycle
to/from the I/O pins. Corresponding to the 4n-prefetch
a single write or read access consists of a 128 bit wide,
one-clock-cycle data transfer at the internal memory
core and four corresponding 32 bit wide, one-half-
clock-cycle data transfers at the I/O pins.
Single-ended unidirectional Read and Write Data
strobes are transmitted simultaneously with Read and
Write data respectively in order to capture data properly
at the receivers of both the Graphics SDRAM and the
controller. Data strobes are organized per byte of the
32 bit wide interface. For read commands the RDQS
The device is supplied with 2.0 V for output drivers and
core. (VDD / VDDQ voltages see Table 1)
are edge-aligned with data, and the WDQS are center- The “On Die Termination” interface (ODT) is optimized
aligned with data for write commands.
for high frequency digital data transfers and is internally
controlled. The termination resistor value can be set
using an external ZQ resistor or disabled through the
Extended Mode Register.
The HYB18T256321F operates from a differential clock
(CLK and CLK). Commands (addresses and control
signals) are registered at every positive edge of CLK.
Input data is registered on both edges of WDQS, and The output driver impedance can be set using the
output data is referenced to both edges of RDQS.
Extended Mode Register. It can either be set to ZQ / 6
(autocalibration) or to 35, 40 or 45 Ohms.
In this document references to ’the positive edge of
CLK’ imply the crossing of the positive edge of CLK and Auto Refresh and Power Down with Self Refresh
the negative edge of CLK. Similarly, the ’negative edge operations are supported.
of CLK’ refers to the crossing of the negative edge of
A standard JEDEC P-TFBGA 144 package is used
CLK and the positive edge of CLK. References to
which enables ultra high speed data transfer rates and
RDQS are to be interpreted as any or all RDQS<3:0>.
a simple upgrade path from former DDR Graphics
WDQS, DM and DQ should be interpreted in a similar
SDRAM products.
fashion.
Data Sheet
12
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Pin Configuration
2
Pin Configuration
11
1
2
3
4
5
6
7
8
9
10
12
DQ3
VDDQ
VSSQ
VSS
DQ2
DQ1
VSSQ
VSSQ
DQ0
DQ31
DQ28 VSSQ
VDDQ VDDQ
WDQS0 RDQS0
VSSQ
VDDQ
VSSQ
VDD
DQ29
RDQS3 WDQS3
A
B
C
D
E
F
DQ4
DQ6
DQ7
DM0
DQ5
RFU
DM3 DQ27
VDDQ VDDQ DQ30
VDD
VSS
VDD
VSS
VSSQ
VSSQ
VSSQ
VSS
VSSQ DQ26 DQ25
VDD RFU DQ24
VSS
VSS
VSS
VSS
DQ17 DQ16
DQ19 DQ18
WDQS2 RDQS2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSSQ VDDQ DQ15 DQ14
VSSQ VDDQ DQ13 DQ12
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
therm
therm
therm
therm
VSS
VSS
VSS
VSS
therm
therm
therm
therm
VSS
VSS
VSS
VSS
VSSQ
VDDQ
VSSQ VDDQ
VSSQ VDDQ
RDQS1 WDQS1
G
H
J
therm
therm
therm
therm
VSS
VSS
VSS
VSS
DQ20
DM2
DM1 DQ11
therm
therm
therm
therm
DQ21 DQ22
VSS
VSS
VDD
DQ9
A4
VSS
VDD
VSS
RFU
ZQ
DQ10
DQ8
VREF
A7
DQ23
VREF
A0
A3
A2
A1
VSS
VDD
A9
RFU
K
L
A10
A5
RESET
RAS#
BA0
CKE
RFU
CS#
BA1
A11
CLK CLK#
A6
CAS#
WE#
A8/AP
M
144 BALL P-TFBGA: TOP VIEW
Figure 1
Standard Ballout 256 Mbit GDDR3 Graphics RAM [500MHz]
Note: Figure shows top view
Data Sheet
13
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Pin Configuration
2.1
Ball Definition and Description
Table 3
Ball
Ball description
Type
Detailed Function
CLK, CLK
Input
Clock: CLK and CLK are differential clock inputs. Address and command inputs are
latched on the positive edge of CLK. Graphics SDRAM outputs (RDQS, DQs) are
referenced to CLK. CLK and CLK are not internally terminated.
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock and
input buffers. Taking CKE LOW provides Power Down. If all banks are precharged, this
mode is called Precharge Power Down and Self Refresh mode is entered if a Autorefresh
command is issued. If at least one bank is open, Active Power Down mode is entered and
no Self Refresh allowed. All input receivers except CLK, CLK and CKE are disabled
during Power Down. In Self Refresh mode the clock receivers are disabled too. Self
Refresh Exit is performed by setting CKE asynchronously HIGH. Exit of Power Down
without Self Refresh is accomplished by setting CKE HIGH with a positive edge of CLK.
The value of CKE is latched asynchronously by Reset during Power On to determine the
value of the termination resistor of the address and command inputs.
CKE is not allowed to go LOW during a RD, a RW or a snoop BURST.
CS
Input
Chip Select: CS enables the command decoder when low and disables it when high.
When the command decoder is disabled, new commands with the exeption of DETERNIS
are ignored, but internal operations continue. CS is one of the four command balls.
RAS, CAS,
WE
Input
I/O
Command Inputs: Sampled at the positive edge of CLK, CAS, RAS, and WE define
(together with CS) the command to be executed.
DQ<0:31>
Data Input/Output: The DQ signals form the 32 bit data bus. During READs the balls are
outputs and during WRITEs they are inputs. Data is transferred at both edges of RDQS.
DM<0:3>
Input
Input Data Mask: The DM signals are input mask signals for WRITE data. Data is
masked when DM is sampled HIGH with the WRITE data. DM is sampled on both edges
of WDQS. DM0 is for DQ<0:7>, DM1 is for DQ<8:15>, DM2 is for DQ<16:23> and DM3
is for DQ<24:31>. Although DM balls are input-only, their loading is designed to match
the DQ and WDQS balls.
RDQS<0:3> Output Read Data Strobes: RDQSx are unidirectional strobe signals. During READs the RDQSx
are transmitted by the Graphics SDRAM and edge-aligned with data. RDQS have
preamble and postamble requirements. RDQS0 is for DQ<0:7>, RDQS1 for DQ<8:15>,
RDQS2 for DQ<16:23> and RDQS3 for DQ<24:31>.
WDQS<0:3> Input
Write Data Strobes: WDQS are unidirectional strobe signals. During WRITEs the WDQS
are generated by the controller and center aligned with data. WDQS have preamble and
postamble requirements. WDQS0 is for DQ<0:7>, WDQS1 for DQ<8:15>, WDQS2 for
DQ<16:23> and WDQS3 for DQ<24:31>.
BA<0:1>
A<0:11>
Input
Input
Bank Address Inputs: BA select to which internal bank an ACTIVATE, READ, WRITE
or PRECHARGE command is being applied. BA are also used to distinguish between the
MODE REGISTER SET and EXTENDED MODE REGISTER SET commands.
Address Inputs: During ACTIVATE, A0-A11 defines the row address. For
READ/WRITE, A2-A7 and A9 defines the column address, and A8 defines the auto
precharge bit. If A8 is HIGH, the accessed bank is precharged after execution of the
column access. If A8 is LOW, AUTO PRECHARGE is disabled and the bank remains
active. Sampled with PRECHARGE, A8 determines whether one bank is precharged
(selected by BA<0:1>, A8 LOW) or all 4 banks are precharged (A8 HIGH). During
(EXTENDED) MODE REGISTER SET the address inputs define the register settings.
A<0:11> are sampled with the positive edge of CLK.
ZQ
-
ODT Impedance Reference: The ZQ ball is used to control the ODT impedance.
Data Sheet
14
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
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DDR SGRAM
Pin Configuration
Table 3
Ball
Ball description
Type
Detailed Function
RES
Input
Reset pin: The RES pin is a VDDQ CMOS input. RES is not internally terminated. The
LOW to HIGH transition of the Reset signal is used to latch the CKE value during Power
On in order to set the value of the termination resistors of the address and command
inputs. When RES is LOW, all terminations are switched off. The LOW to HIGH transition
of the RES signal must occur at the beginning of the power up sequence in order to insure
functionnality.
Vref
Supply Voltage Reference: Vref is the reference voltage input.
Supply Power Supply: Power and Ground for the internal logic.
VDD, VSS
V
DDQ, VSSQ
Supply I/O Power Supply: Isolated Power and Ground for the output buffers to provide improved
noise immunity.
NC, RFU
-
Please do not connect No Connect and Reserved for Future Use balls.
Data Sheet
15
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
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DDR SGRAM
Pin Configuration
2.2
Functional Block Diagram
A0-A7,A9, A8/AP, A10-A11
BA0, BA1
Address buffer
A8/AP
Row Addresses A0-A11, BA0-BA1
Row Address Buffer
Column Addresses A2-A7,A9
Refresh
Counter
Column Address Buffer
CS#
RAS#
CAS#
WE#
Row Decoder
Row Decoder
Row Decoder
Row Decoder
Memory
Array
Memory
Array
Memory
Array
Memory
Array
RES
Bank 0
Bank 1
Bank 2
Bank 3
4096 x 512
x 32 bit
4096 x 512
x 32 bit
4096 x 512
x 32 bit
4096 x 512
x 32 bit
ZQ
CKE
CLK
DLL
Output Buffers
DQ8-DQ15
Input Buffers
CLK#
DQ0-DQ7
DQ16-DQ23
DQ24-DQ31
Figure 2
Functional Block Diagram
Data Sheet
16
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
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DDR SGRAM
Pin Configuration
2.3
Commands
2.3.1
Command Table
In the following table CKEn refers to the positive edge of CLK corresponding to the clock cycle when the command
is given to the Graphics SDRAM. CKEn-1 refers to the previous positive edge of CLK. For all command and
address inputs CKEn is implied.
All input states or sequences not shown are illegal or reserved.
Table 4
Command Overview
Code
Operation
CKE CKE CS RAS CAS WE BA0 BA1 A8
A2-7 Note
A9-11
n-1
n
Device Deselect
DESEL
H
H
H
L
X
H
X
X
H
X
L
H
X
X
X
X
1
Data Terminator Disable DTERDIS H
H
H
H
H
H
L
L
L
H
H
L
L
H
L
L
H
H
L
X
X
0
1
X
X
0
0
X
X
X
X
1,9
No Operation
NOP
MRS
H
H
H
Mode Register Set
OPCODE
OPCODE
Extended Mode Register EMRS
Set
L
L
Bank Activate
ACT
H
H
L
L
H
H
BA BA Row
Address
Col.
1,2
Read
RD
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
H
H
L
H
H
L
BA BA
BA BA
BA BA
BA BA
BA BA
L
1,3
1,3
1,3
1,3
1
Read w/ Autoprecharge
Write
RD/A
WR
H
L
Col.
Col.
Col.
X
Write w/ Autoprecharge
Precharge
WR/A
PRE
L
H
L
L
Precharge All
Auto Refresh
PREALL
AREF
L
L
X
X
X
X
X
X
H
X
X
X
1
L
H
X
1,4
1,5
Power Down Mode Entry PWDNEN H
H
L
X
H
X
H
X
H
X
Power Down Mode Exit
Self Refresh Entry
Self Refresh Exit
PWDNEX L
H
L
X
L
X
L
X
L
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
1,6
1,7
1,8
SREFEN
SREFEX
H
L
H
X
X
X
1. X represents “Don’t Care”.
2. BA0 and BA1 provide bank address, A0 - A11
provide the row address.
7. Self Refresh is selected by issuing AREF at the first
positive CLK edge following the HIGH to LOW
transition of CKE.
3. BA0 and BA1 provide bank address, A2- A7, A9 8. First possible valid command after tXSC. During tXSC
provide the column address, A8/AP controls Auto
Precharge.
only NOP or DESEL commands are allowed.
9. This command is invoked when a Read is issued on
another DRAM rank placed on the same command
bus. Cannot be in power-down or self-refresh state.
The Read command will cause the data termination
to be disabled. Refer to for timing.
4. Auto Refresh and Self Refresh Entry differ only by
the state of CKE
5. PWDNEN is selected by issuing a DESEL or NOP
at the first positive CLK edge following the HIGH to
LOW transition of CKE.
6. First possible valid command after tXPN. During tXPN
only NOP or DESEL commands are allowed.
Abbreviations:
BA:Bank Address
Col.:Column Address
Data Sheet
17
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Pin Configuration
2.3.2
Description of Commands
Table 5
Description of Commands
Command Description
DESEL
The DESEL function prevents new commands from being executed by the Graphics SDRAM. The
Graphics SDRAM is effectively deselected. Operations in progress are not affected.
NOP
The NOP command is used to perform a no operation to the Graphics SDRAM, which is selected
(CS is LOW). This prevents unwanted commands from being registered during idle or wait states.
Operations already in progress are not affected.
MRS
EMRS
ACT
The Mode Register is loaded via address inputs A0 - A11. For more details see sections
Chapter 3.5. The MRS command can only be issued when all banks are idle and no bursts are in
progress. A subsequent executable command cannot be issued until tMRD is met.
The Extended Mode Register is loaded via address inputs A0 - A11. For more details see section
Chapter 3.4. The EMRS command can only be issued when all banks are idle and no bursts are in
progress. A subsequent executable command cannot be issued until tMRD is met.
The ACT command is used to open (or activate) a row in a particular bank for a subsequent access.
The value on the BA0 and BA1 inputs selects the bank, and the address provided in inputs A0 - A11
selects the row. This row remains active (or open) for accesses until a precharge (PRE, RD/A, or
WR/A command) is issued to that bank. A precharge must be issued before opening a different row
in the same bank.
RD
The RD command is used to initiate a burst read access to an active row. The value on the BA0 and
BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column
location. The row will remain open for subsequent accesses. For RD commands the value on A8 is
set LOW.
RD/A
The RD/A command is used to initiate a burst read access to an active row. The value on the BA0
and BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column
location. The value on input A8 is set HIGH. The row being accessed will be precharged at the end
of the read burst. The same individual-bank precharge function is performed like it is described for
the PRE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage
within the burst. The user must not issue a new ACT command to the same bank until the precharge
time (tRP) is completed. This time is determined as if an explicit PRE command was issued at the
earliest possible time as described in section Chapter 3.10.
WR
The WR command is used to initiate a burst write access to an active row. The value on the BA0
and BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column
location. The row will remain open for subsequent accesses. For WR commands the value on A8 is
set LOW.
Input data appearing on the DQs is written to the memory array depending on the value on the DM
input appearing coincident with the data. If a given DM signal is registered LOW, the corresponding
data will be written to the memory; if the DM signal is registered HIGH, the corresponding data inputs
will be ignored, and a write will not be executed for that byte / column location.
WR/A
The WR/A command is used to initiate a burst write access to an active row. The value on the BA0
and BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column
location. The value on input A8 is set HIGH. The row being accessed will be precharged at the end
of the write burst. The same individual-bank precharge function is performed which is described for
the PRE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage
within the burst. The user is not allowed to issue a new ACT to the same bank until the precharge
time (tRP) is completed. This time is determined as if an explicit PRE command was issued at the
earliest possible time as described in section Chapter 3.7.
Input data appearing on the DQs is written to the memory array depending on the DM input logic
level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding
data will be written to the memory; if the DM signal is registered HIGH, the corresponding data inputs
will be ignored, and a write will not be executed to that byte / column location.
Data Sheet
18
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Pin Configuration
Table 5
Description of Commands
Command Description
PRE
The PRE command is used to deactivate the open row in a particular bank. The bank will be
available for a subsequent row access a specified time (tRP) after the PRE command is issued.
Inputs BA0 and BA1 select the bank to be precharged. A8/AP is set to LOW. Once a bank has been
precharged, it is in the idle state and must be activated again prior to any RD or WR commands
being issued to that bank. A PRE command will be treated as a NOP if there is no open row in that
bank, or if the previously open row is already in the process of precharging.
PREALL
AREF
The PREALL command is used to deactivate all open rows in the memory device. The banks will
be available for a subsequent row access a specified time (tRP) after the PREALL command is
issued. Once the banks have been precharged, they are in the idle state and must be activated prior
to any read or write commands being issued. The PREALL command will be treated as a NOP for
those banks where there is no open row, or if a previously open row is already in the process of
precharging. PREALL is issued by a PRE command with A8/AP set to HIGH.
The AREF is used during normal operation of the GDDR3 Graphics RAM to refresh the memory
content. The refresh addressing is generated by the internal refresh controller. This makes the
address bits “Don’t Care” during an AREF command. The HYB18T256321F requires AREF cycles
at an average periodic interval of tREFI(max)=7.8µs. To improve efficiency a maximum number of
eight AREF commands can be posted to one memory device (with tRFC from AREF to AREF) as
described in section Chapter 3.11. This means that the maximum absolute interval between any
AREF command is 8 x 7.8µs (62.4µs). This maximum absolute interval is to allow the GDDR3
Graphics RAM output drivers and internal terminators to recalibrate, compensating for voltage and
temperature changes. All banks must be in the idle state before issuing the AREF command. They
will be simultaneously refreshed and return to the idle state after AREF is completed. tRFC is the
minimum required time between an AREF command and a following ACT/AREF command.
SREFEN
The Self Refresh function can be used to retain data in the GDDR3 Graphics RAM even if the rest
of the system is powered down. When entering the self refresh mode by issuing the SREFEN
command, the GDDR3 Graphics RAM retains data without external clocking. The SREFEN
command is initiated like an AREF command except CKE is disabled (LOW). The DLL is
automatically disabled upon entering Self Refresh mode and automatically enabled and reset upon
exiting Self Refresh. (200 cycles must then occur before a RD command can be issued) The adress,
command and data terminators remain on input signals except CKE are “Don’t Care”. If two GDDR3
Graphics RAMs share the same cimmand and address bus, Self Refresh max be entered only for
the two devices at the sme time.
SREFEX
The SREFEX command is used to exit the self refresh mode. The DLL is automatically enabled and
resetted upon exiting. The procedure for exiting self refresh requires a sequence of commands. First
CLK and CLK must be stable prior to CKE going from LOW to HIGH. Once CKE is HIGH, the
GDDR3 Graphics RAM must receive only NOP/DESEL commands until tXSNR is satisfied. This time
is required for the completion of any internal refresh in progress. A simple algorithm for meeting both
refresh, DLL requirements and output calibration is to apply NOPs for 200 cycles before applying
any other command to allow the DLL to lock and the output drivers to recalibrate.
PWDNEN The PWDNEN command enables the power down mode. It is entered when CKE is set low together
with a NOP/DESEL. The CKE signal is sampled at the rising edge of the clock. Once the power
down mode is initiated, all of the receiver circuits except CLK and CKE are gated off to reduce power
consumption. The DLL remains active (unless disabled before with EMRS). All banks can be set to
idle state or stay active. During Power Down Mode, refresh operations cannot be performed;
therefore the refresh conditions of the chip have to be considered and if necessary Power Down
state has to be left to perform an Autorefresh cycle.
Data Sheet
19
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Pin Configuration
Table 5
Description of Commands
Command Description
PWDNEX
DTERDIS
A CKE HIGH value sampled at a low to high transition of CLK is required to exit power down mode.
Once CKE is HIGH, the GDDR3 Graphics RAM must receive only NOP/DESEL commands until tXPN
is satisfied. After tXPN any command can be issued, but it has to comply with the state in which the
power down mode was entered.
Data Termination Disable (Bus snooping for RD commands) : The Data Termination Disable
Command is detected by the device by snooping the bus for RD commands excluding CS. The
GDDR3 Graphics RAM will disable its Data terminators when a RD command is detected. The
terminators are disabled starting at CL - 1 clocks after the RD command is detected and the duration
is 4 clocks. In a two rank system, both DRAM devices will snoop the bus for RD commands to either
device and both will disable their terminators if a RD command is detected. The command and
address terminators are always enabled. See Figure 9 for an example of when the data terminators
are disabled during a RD command.
Table 6
Minimum delay from RD/A and WR/A to any other command (to another bank) with concurrent
Autoprecharge
From Command
To Command
Minimum delay to another bank
(with concurrent autoprecharge)
Note
WR/A
RD or RD/A
WR or WR/A
PRE
(WL + 2) . tCK + tWTR
2 . tCK
tCK
ACT
tCK
RD/A
RD or RD/A
WR or WR/A
PRE
2 . tCK
(CL + 4 - WL) . tCK
tCK
tCK
ACT
Data Sheet
20
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
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DDR SGRAM
Pin Configuration
2.4
State Diagram and Truth Tables
2.4.1
State Diagram for One Activated Bank
The following diagram shows all possible states and transitions for one activated bank. The other three banks of
the Graphics SDRAM are assumed to be in idle state.
single bank
WR
RD
ACTIVE
ACT
PRE
WR/A
RD/A
PDEN
PDEX
MRS
EMRS
PDEN
PDEX
active
IDLE
AUTO
POWER DOWN
REFRESH
precharge
SREX
SREN
SELF
REFRESH
all banks
Figure 3
State diagram for one bank
Note: MRS, EMRS, AUTO REFRESH, SELF REFRESH and precharge POWER DOWN are only allowed if all four
banks are idle.
Data Sheet
21
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
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DDR SGRAM
Pin Configuration
2.4.2
Function Truth Table for more than one Activated Bank
If there is more than one bank activated in the Graphics submitted command. This table is based on the
SDRAM, some commands can be performed in parallel assumption that there are no other actions ongoing on
due to the chip’s multibank architecture. The following bank n or bank m. If there are any actions ongoing on a
table defines for which commands such a scheme is third bank tRRD, tRTW and tWTR have to be taken always
possible. All other transitions are illegal. Notes 1-11 into account.
define the start and end of the actions belonging to a
Table 7
Function Truth Table I
ongoing action on bank n
Current
State
possible action in parallel on bank m
ACTIVE
ACTIVATE 1
ACT, PRE, WRITE, WRITE/A, READ, READ/A 12
WRITE 2
ACT, PRE, WRITE, WRITE/A, READ, READ/A13
WRITE/A 3
ACT, PRE, WRITE, WRITE/A, READ 14
READ 4
ACT, PRE, WRITE, WRITE/A, READ, READ/A15
READ/A 5
ACT, PRE, WRITE, WRITE/A, READ, READ/A 15
PRECHARGE 6
ACT, PRE, WRITE, WRITE/A, READ, READ/A 12
PRECHARGE ALL 6
POWER DOWN ENTRY 7
ACTIVATE 1
-
-
IDLE
ACT
POWER DOWN ENTRY 7
AUTO REFRESH 8
SELF REFRESH ENTRY 7
MODE REGISTER SET (MRS)9
EXTENDED MRS 9
POWER DOWN EXIT 10
SELF REFRESH EXIT 11
-
-
-
-
-
-
-
POWER DOWN
SELF REFRESH
1. Action ACTIVATE starts with issuing the command 7. During POWER DOWN and SELF REFRESH only
and ends after tRCD the EXIT commands are allowed
2. Action WRITE starts with issuing the command and 8. Action AUTO REFRESH starts with issuing the
ends tWR after the first pos. edge of CLK following command and ends after tRFC
the last falling WDQS edge; exept for READ, 9. Actions MODE REGISTER SET and EXTENDED
READ/A. WRITE, WRITE/A ends tWTR after the first
pos. edge of CLK following the last falling WDQS
edge.
MODE REGISTER SET start with issuing the
command and ends after tMRD
10. Action POWER DOWN EXIT starts with issuing the
command and ends after tXPN
3. Action WRITE/A starts with issuing the command
and ends tWR after the first positive edge of CLK 11. Action SELF REFRESH EXIT starts with issuing the
following the last falling WDQS edge; exept for command and ends after tXSC
READ, READ/A. WRITE, WRITE/A ends tWTR after 12. During action ACTIVATE an ACT command on
the first pos. edge of CLK following the last falling
WDQS edge.
4. Action READ starts with issuing the command and
another bank is allowed considering tRRD, a PRE
command on another bank is allowed any time.
WR, WR/A, RD and RD/A are always allowed.
ends with the first positive edge of CLK following the 13. During action WRITE an ACT or a PRE command
last falling edge of RDQS
on another bank is allowed any time. A new WR or
WR/A command on another bank must be
separated by at least one NOP from the ongoing
WRITE. RD or RD/A are not allowed before tWTR is
met.
5. Action READ/A starts with issuing the command
and ends with the first positive edge of CLK
following the last falling edge of RDQS
6. Action PRECHARGE and PRECHARGE ALL start
with issuing the command and ends after tRP
Data Sheet
22
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
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DDR SGRAM
Pin Configuration
14. During action WRITE/A an ACT or a PRE command 15. During action READ and READ/A an ACT or a PRE
on another bank is allowed any time. A new WR or
WR/A command on another bank has to be
separated by at least one NOP from the ongoing
command. RD is not allowed before tWTR is met.
RD/A is not allowed during an ongoing WRITE/A
action.
command on another bank is allowed any time. A
new RD or RD/A command on another bank has to
be separated by at least one NOP from the ongoing
command. A WR or WR/A command on another
bank has to meet tRTW
.
2.4.3
Function Truth Table for CKE
Table 8
Function Truth Table II (CKE Table)
CKE
n-1
CKE
n
CURRENT STATE
COMMAND
ACTION
L
L
H
L
H
L
Power Down
Self Refresh
Power Down
Self Refresh
All Banks Idle
Bank(s) Active
All Banks Idle
X
stay in Power Down
stay in Self Refresh
Exit Power Down
X
DESEL or NOP
DESEL or NOP
DESEL or NOP
DESEL or NOP
Auto Refresh
Exit Self Refresh 5
Entry Precharge Power Down
Entry Active Power Down
Entry Self Refresh
1. CKEn is the logic step at clock edge n; CKEn-1 was 4. All states and sequences not shown are illegal or
the state of CKE at the previous clock edge. reserved.
2. Current state is the state of the GDDR3 Graphics 5. DESEL or NOP commands should be issued on
RAM immediatly prior to clock edge n.
3. COMMAND is the command registered at clock
edge n, and ACTION is a result of COMMAND.
any clock edges occuring during the tXSR period. A
minimum of 200 clock cycles is required before
applying any other valid command.
Data Sheet
23
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3
Functional Description
3.1
Clocks, CKE, Commands and Addresses
tCK
tCH
tCL
CLK#
CLK
tIPW
CMD,
ADDR,
CKE
Don't Care
tIS
tIH
Figure 4
Clock, CKE and Command/Address Timings
Setup and Hold Timing for CKE is equal to CMD and ADDR Setup and Hold Timing. The DLL ensures the
alignment of DQs and CLK. Therefore the preferred operation mode for high frequencies is DLL on. The DLL
frequency range is from 500 MHz down to 250 MHz.
Table 9
General Timing Parameters for -2.0 ns, -2.2 ns and -2.5 ns speed sorts
Parameter
CAS
latency
Symbol Limit Values
- 2.0
Unit
- 2.2
min
- 2.5
min
min
max
max
max
Clock
Clock Cycle Time
7
6
5
7
6
5
tCK7
tCK6
tCK5
fCK7
fCK6
fCK5
tCH
2.0
2.0
—
4.0
4.0
—
2.2
4.0
2.5
4.0
ns
2.2
4.0
2.5
4.0
ns
2.7
4.0
3.0
4.0
ns
System frequency
250
250
—
500
500
—
250
250
250
0.45
0.45
455
455
370
0.55
0.55
250
250
250
0.45
0.45
400
400
333
0.55
0.55
MHz
MHz
MHz
tCK
Clock high level width
Clock low-level width
0.45
0.45
0.55
0.55
tCL
tCK
Command, CKE and Address Setup and Hold Times
Address/Command/CKE input setup
time
tIS
0.75
—
0.75
—
0.85
—
ns
Address/Command/CKE input hold time tIH
0.75
0.85
—
—
0.75
0.85
—
—
0.85
0.85
—
—
ns
Address/Command/CKE input pulse
width
tIPW
tCK
Data Sheet
24
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.2
Initialization
The HYB18T256321F must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation or permanent damage to the device.
The following sequence is highly recommended for Power-Up:
1. Apply power (VDD, VDDQ, VREF). Apply VDD before or at the same time as VDDQ, apply VDDQ before or at the
same time as VREF. Maintain RES=L and CS=H to ensure that all the DQ ouputs will be in HiZ state, all active
terminations off and the DLL off. All other pins may be undefined.
2. Maintain stable conditions for 200 µs minimum for the GDDR3 Graphics RAM to power up.
3. After clock is stable, set CKE to L. After tATS minimum set RES to high. On the rising edge of RES, the CKE
value is latched to determine the address and command bus termination value. If CKE is sampled LOW the
address termination value is set to ZQ / 2. If CKE is sampled HIGH, the address and command bus termination
is set to ZQ.
4. After tATH minimum, set CKE to high.
5. Wait a minimum of 350 cycles to calibrate and update the address and command termination impedances.
Issue DESELECT on the command bus during these 350 cycles.
6. Apply a PRECHARGE ALL command, followed by an Extended Mode Register command after tRP is met and
activate the DLL.
7. Issue an Mode Register Set command after tMRD is met to reset the DLL and define the operating parameters.
8. Wait 200 cycles of clock input to lock the DLL. No Read command can be applied during this time. Since the
impedance calibration is already completed, the DLL mimic circuitry can use the actual programmed driver
impedance value.
9. Issue a PRECHARGE ALL command or issue 4 single bank PRECHARGE commands, one to each of the 4
banks to place the chip in an idle state.
10. Issue two or more AUTO REFRESH commands to update the driver impedance.
VDD
VDDQ
VREF
tATS tATH
RES
CKE
CLK#
CLK
EM
DES
PA
MRS
PA
ARF
ARF
A.C.
Com.
DES
R
R
P
R
P
tRFC
tRFC
t
tMRD
tMRD
t
min. 350 cycles
min. 200 µs
min. 200 cycles
VDD and
CLK stable
MRS: MRS command
with DLL Reset
EMR: EMRS command
DES : Deselect
PA: PREALL command
ARF: AUTO REFRESH command
A.C.: Any command
Don't Care
Figure 5
Power Up Sequence
Table 10
Reset Timing Parameters for -2.0, -2.2 and -2.5 speed sorts
Symbol Limit Values
Parameter
Unit Notes
- 2.0
- 2.2
- 2.5
min max min max min max
RES to CKE setup time
RES to CKE hold time
tATS
tATH
10
10
—
—
10
10
—
—
10
10
—
—
ns
ns
Data Sheet
25
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.3
Programmable impedance output drivers and active terminations
GDDR3 IO Driver and Termination
3.3.1
The GDDR3 SGRAM is equipped with programmable DM<0:3>. The two termination values that are
impedance output buffers and active terminations. This selectable using EMRS[3:2] are ZQ / 4 and ZQ / 2.
allows the user to match the driver impedance to the
system impedance.
The value of ZQ is also used to calibrate the internal
address command termination resistors. The inputs
To adjust the impedance of DQ<0:31> and terminated in this manner are A<0:11>, CKE, CS, RAS,
RDQS<0:3> , an external precision resistor (ZQ) is CAS, WE. The two termination values that are
connected between the ZQ pin and VSS. The value of selectable upon power up (CKE latched a the LOW to
the resitor must be six times the value of the desired HIGH transition of RES) are ZQ/2 and ZQ.
impedance. For example, a 240Ω resistor is required
for an output impedance of 40Ω. The range of ZQ is
The signals RES and CLK/CLK are not internally
terminated.
210Ω to 270Ω, giving an output impedance range of
If no resistance is connected to ZQ, an internal default
35Ω to 45Ω (one sixth the value of ZQ within 10%).
value of 240Ω will be used. In this case, no calibration
RES, CLK and CLK are not internally terminated.
will be performed.
The value of ZQ is used to calibrate the internal DQ
termination resistors of DQ<0:31>, WDQS<0:3> and
VDDQ
ZQ/4 or ZQ/2
Terminator when
Read to
receiving
other Rank
Output Data
Read Data
Enable
DQ
ZQ/6 Driver
when transmitting
VSSQ
Figure 6
Output Driver simplified schematic
Table 11
Range of external resistance ZQ
Symbol
Parameter
min
nom
max
Unit
Notes
External resistance value
ZQ
210
240
270
Ω
Table 12
Ball
Termination types and activation
Termination type
No termination
Add / CMDs
DQ
Termination activation
CLK, CLK, RDQS<0:3>, ZQ, RES
CKE, CS, RAS, CAS, WE, BA<0:1>, A<0:11>
DM<0:3>, WDQS<0:3>,
Always ON
Always ON
DQ<0:31>
DQ
CMD bus snooping
Data Sheet
26
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.3.2
Self Calibration for Driver and Termination
CLK#
CLK
Com.
Add.
DQ
ARF
ARF: Autorefresh
Don't Care
tKO
Keep Out time
Figure 7
Table 13
Parameter
Termination update keep out time after Autorefresh command
Termination update Keep Out time
Symbol Limit Values
Unit Notes
- 2.0
min max min max min max
10 10 10
- 2.2
- 2.5
Termination update Keep Out time
tKO
—
—
—
ns
To guarantee optimum driver impedance after power-up, the GDDR3 SGRAM needs 350 cycles after the clock is
applied and stable to calibrate the impedance upon power-up. The user can operate the part with fewer than 350
cycles, but optimal output impedance will not be guaranteed.
The GDDR3 Graphics RAM proceeds in the following manner for Self Calibration :
The PMOS device is calibrated against the external ZQ resistor value (Figure 8). First one PMOS leg is calibrated
against ZQ. The number of legs used for the terminators ( DQ and ADD/CMD) and the PMOS driver is represented
in Table 14. Next, one NMOS leg is calibrated against the already calibrated PMOS leg. The NMOS driver uses
6 NMOS legs.
Table 14
Number of Legs used for Terminator and Driver Self Calibration
Termination
CKE (at RES)
Number of Legs Notes
Terminator
ADD / CMD
DQ
0
ZQ/2
ZQ
2
1
1
EMRS[3:2]
00
10
11
Disabled
ZQ/4
0
4
2
6
6
1
ZQ/2
Driver
PMOS
NMOS
ZQ/6
ZQ/6
Note: EMRS[3:2] = 00 disables the ADD and CMD terminations as well.
Figure 8 represents a simplified schematic of the calibration circuits. First, the strength control bits are adjusted
in such a way that the VDDQ voltage is divided equaly between the PMOS device and the ZQ resistor. The best bit
Data Sheet
27
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
pattern will cause the comparator to switch the PMOS Match signal output value. In a second step, the NFET is
calibrated against the already calibrated PFET. In the same manner, the best control bit combination will cause
the comparator to switch the NMOS Match signal output value.
VDDQ
VDDQ
NMOS
Calibration
Strength
VSSQ
Control [2:0]
PMOS
Calibration
Match
VDDQ / 2
Strength
Control [2:0]
ZQ
Match
VDDQ / 2
VSSQ
VSSQ
Figure 8
Self Calibration of PMOS and NMOS Legs
3.3.3
Dynamic Switching of DQ terminations
The GDDR3 Graphics RAM will disable its data terminators when a READ or DTERDIS command is detected. The
terminators are disabled starting at CL - 1 Clocks after the READ / DTERDIS command is detected and the
duration is 4 clocks. In a two rank system, both devices will snoop the bus for a READ / DTERDIS command to
either device and both will disable their terminators if a READ / DTERDIS command is detected. The address and
command terminators are always enabled.
0
1
2
3
4
5
6
7
8
9
CLK#
CLK
Com
.
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B / C
CAS latency = 5
RDQS
DQ
D0
D1
D2
D3
DQ
Termination
Data Terminations are disabled
Dx:
Data from B / C
B / C: Bank / Column address
RD: READ
N/D: NOP or Deselect
Com.: Command
Addr.: Address B / C
Don't Care
Figure 9
ODT Disable Timing during a READ command
Data Sheet
28
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.3.4
Output impedance and Termination DC Electrical Characteristics
The Driver and Termination impedances are determined by applying VDDQ/2 nominal (1.0 V) at the corresponding
input / output and by measuring the current flowing into or out of the device. VDDQ is set to the nominal value of
2.0 V. (see Table 1)
I
OH is the current flowing out of DQ when the Pull-Up transistor is activated and the DQ termination disabled.
IOLis the current flowing into DQ when the Pull-Down transistor is activated and the DQ termination disabled.
TCAH(ZQ) is the current flowing out of the Termination of Commands and Addresses for a ZQ termination value.
I
Table 15
DC Electrical Characteristics
Parameter
Nom.
240
Unit
Notes
Ω
ZQ Value
min
max
25.0
25.0
4.2
IOH
ZQ/6
ZQ/6
ZQ
20.5
20.5
3.4
mA
mA
mA
1
1
1
IOL
ITCAH(ZQ)
Note: 1: Measurement performed with VDDQ =2.0 V (nominal see Table 1) and by applying VDDQ/2 (1.0 V) at the
corresponding Input / Output.
0°C ≤ TC ≤ 85°C.
Data Sheet
29
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.4
Extended Mode Register Set Command (EMRS)
The Extended Mode Register is used to set the output
driver impedance value, the termination impedance
value, the Write Recovery time value for Write with
Autoprecharge. It is used as well to enable/disable the
DLL, to issue the Vendor ID and to enable/disable the
Low Power mode. There is no default value for the
Extended Mode Register. Therefore it must be written
after power up to operate the GDDR3 Graphics RAM.
The Extended Mode Register can be programmed by
performing a normal Mode Register Set operation and
setting the BA0 bit to HIGH. All other bits of the EMR
register are reserved and should be set to LOW.
CLK#
CLK
CKE
CS#
RAS#
CAS#
The Extended Mode Register must be loaded when all
banks are idle and no burst are in progress. The
controller must wait the specified time tMRD before
initiating any subsequent operation).
WE#
A0-A11
BA0
The timing of the EMRS command operation is
equivalent to the timing of the MRS command
operation.
COD
COD: Code to be loaded into
the register
1
0
Don't Care
BA1
Figure 10 Extended Mode Register Bitmap
A7
A6
A5
A4
A3
A2
A1
A0
BA1
0
BA0
1
A11
LP
A10
V
A9
A8
RFU
DLL
WR
Rtt
Data Z
Output Driver
DLL
A11
Low Power
A1
A0
A6
A5
A4
WR
Impedance
Enable
0
1
Disable
Enable
0
0
1
1
0
1
0
1
Autocal
35 Ω 1)
40 Ω 1)
45 Ω 1)
0
1
Enable
Disable
0
0
1
1
0
1
0
1
3
4
5
6
A10 Vendor ID
0
1
Off
On
A3
A2
Termination
0
0
1
0
1
0
ODT disabled
RFU
ZQ / 4
ZQ / 2
1
1
(Default) 2)
Figure 11 Extended Mode Register Bitmap
1. These settings are for debugging purposes only.
2. Default termination values at Power Up.
3. The ODT disable function disables all terminators on th device.
4. If the user activates bits in an extended mode register in an optional field, either the optional field is activated
(if option implemented on the device) or no action is taken by the device (if ioption not implemented).
5. WR (write recovery time for write with autoprecharge) in clock cycles is calculated by dividing tWR (in ns) and
rounding up to the next integer (WR[cycles]=tWR[ns]/tCK[ns]). The mode register must be programmed to this
value.
Data Sheet
30
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
CLK#
CLK
EMRS
Command
PA
NOP
NOP
NOP
A.C.
tRP
tMRD
EMRS: Extended MRS command
PA: PREALL command
A.C.: Any command
Don't Care
Figure 12 Extended Mode Register Set Timing
Table 16
EMRS Timing Parameters for –2.0, –2.2 and –2.5 speed sorts
Symbol Limit Values
Parameter
Unit Notes
- 2.0
- 2.2
- 2.5
min max min max min max
Mode Register Set cycle time
tMRD
4
—
4
—
4
—
tCK
3.4.1
DLL enable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon
returning to normal operation after having disabled the DLL. (When the device exits self-refresh mode, the DLL is
enabled automatically). Anytime the DLL is enabled, 200 cycles must occur before a READ command can be
issued.
3.4.2
WR
The WR parameter is programmed using the register bits A4 and A5. This integer parameter defines as a number
of clock cycles the Write Recovery time in a Write with Autoprecharge operation.
The following inequality has to be complied with : WR * tCK ≥ tWR, where tCK is the clock cycle time as defined in
Table 8 and tWR the Write Recovery time as defined in Table 23.
Note: Refer to Figure 3.7.4 for more details.
3.4.3
Termination Rtt
The data termination, Rtt , is used to set the value of the internal terminaton resistors. The GDDR III DRAM
supports ZQ / 4 and ZQ / 2 termination values. The termination may also be disabled for testing and other
purposes.
3.4.4
Output Driver Impedance
The Output Driver Impedance extended mode register is used to set the value of the data output driver impedance.
When the autocalibration is used, the output driver impedance is set nominally to ZQ / 6.
3.4.5
Low Power
When the Low Power extended mode register is set, the device enters a low power mode of operation. This mode
is not enabled for the HYB18T256321F. Setting this bit to HIGH will have no effect on the behavior of the GDDR3
DRAM.
Data Sheet
31
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.4.6
Vendor Code and Revision Identification
The Manufacturer Vendor Code is selected by issuing an Extended Mode Register Set command with bit A10 set
to 1 and bits A0-A9 and A11 set to the desired value. When the Vendor Code function is enabled the GDDR3
DRAM will provide the Infineon vendor code on DQ[3:0] and the revision identification on DQ[7:4]. The code will
be driven onto the DQ bus after tRIDon following the EMRS command that sets A10 to 1. The Vendor Code and
Revision ID will be driven on DQ[7:0] until a new EMRS command is issued with A10 set back to 0. After tRDoff
following the second EMRS command, the data bus is driven back to HIGH. This second EMRS command must
be issued before initiating any subsequent operation. Violating this requirement will result in unspecified operation.
Table 17
Revision ID and Vendor Code
Revision Identification
Infineon
Vendor Code
DQ[7:4]
xxxx
DQ[3:0]
0010
Note: Please refer to Revision Release Note for Revision ID value
0
1
2
3
4
5
6
7
8
9
10
CLK#
CLK
EMRS
Add
EMRS
Add
Com.
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
A[9:0],
A11
A10
t
t
RIDon
RIDoff
RDQS
DQ[7:0]
Vendor Code and Revision ID
EMRS: Extended Mode Register Set Command
Add:
N/D:
Address
NOP or Deselect
Don't Care
Figure 13 Timing of Vendor Code and Revision ID generation on DQ[7:0]
Table 18
Vendor Code and Revision ID Timing Parameters for -2.0, -2.2 and -2.5 speed sorts
Parameter
Symbol Limit Values
- 2.0
Unit Notes
- 2.2
- 2.5
min max min max min max
EMRS to DQ on time
EMRS to DQ off time
tRIDon
tRIDoff
—
—
20
20
—
—
20
20
—
—
20
20
ns
ns
Data Sheet
32
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.5
Mode Register Set Command (MRS)
The mode register stores the data for controlling the
operating modes of the memory. It programs read
latency, test mode, DLL Reset and the value of the
write latency. There is no default value for the mode
register; therefore it must be written after power up to
operate the GDDR3 Graphics RAM. During a Mode
Register Set command the address inputs are sampled
and stored in the mode register.
CLK#
CLK
CKE
CS#
t
MRD must be met before any command can be issued
to the Graphics SDRAM. The Mode Register contents
can only be set or changed when the Graphics SDRAM
is in idle state.
RAS#
CAS#
WE#
A0-A11
BA0
COD
0
0
BA1
COD: Code to be loaded into
the register
Don't Care
Figure 14 Mode Register Set Command
A7
A6
A5
A4
A3
BT
A2
A1
BL
A0
BA1
0
BA0
0
A11
A10
WL
A9
A8
DLL
TM
CAS Latency
Burst Length
B
L
A1
A0
Write Latency
A11 A10 A9
A2
Testmode
mode
WL
A7
0
1
0
4
0
0
1
1
0
1
0
2
3
RFU
all others
0
1
Normal
1
0
Testmode
4
CAS Latency
all others
RFU
Burst Type
BT
A6
A5
A4
Latency
DLL Reset
A3
A8
DLL Reset
1
1
1
1
0
0
1
1
0
1
0
1
RFU
0
1
sequential
RFU
5
6
0
1
No
Yes
7
all others
RFU
Note: 1) The DLL Reset command is self-clearing
Figure 15 Mode Register Bitmap
Note: The DLL Reset command is self-clearing
Data Sheet
33
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
CLK#
CLK
Command
PA
NOP
MRS
NOP
NOP
A.C.
NOP
RD
tMRD
tRP
tMRDR
MRS: MRS command
PA: PREALL command
A.C.: Any other command as READ
RD: READ command
Don't Care
Figure 16 Mode Register Set Timing
Table 19
MRS Timing Parameters for –2.0, –2.2 and –2.5 speed sorts
Symbol Limit Values
Parameter
Unit Notes
- 2.0
- 2.2
- 2.5
min max min max min max
Mode Register Set cycle time
tMRD
4
—
—
4
—
—
4
—
—
tCK
tCK
1, 2
1
Mode Register Set to READ timing
tMRDR
12
12
12
1. This value of tMRD applies only to the case where the
“DLL reset” bit is not activated.
2. tMRD is defined from MRS to any other command as READ.
3.5.1
Burst length
Read and Write accesses to the GDDR3 Graphics RAM are burst oriented with burst length 4. This value must be
programmed using the Mode Register Set command (A0 .. A2). The burst length determines the number of column
locations that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block if a boundary is reached. The block is uniquely selected by
A2-Ai where Ai is the most significant bit for a given configuration. The starting location within this block is
determined by the two least significant bits A0 and A1 which are set internally to the fixed value of zero each.
Reserved states should not be used, as unknow operation or incompatibility with future versions may result.
3.5.2
Burst type
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set
command (A3) . This device does not support the burst interleave mode.
Table 20
Burst Type
Burst Length
Starting Column address
Order of accesses within the burst
Type = Sequential
4
A1 A0
x x
0-1-2-3
The value applied at the balls A0 and A1 for the column address is “Don’t care”.
Data Sheet
34
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.5.3
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability
of the first bit of output data as shown on Figure 31. The latency can be set to 5 to 7 clocks as shown in Figure 15.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally
concident with clock edge n+m. Refer to Appendix, Figure 42, for values of operating frequencies at which each
CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
3.5.4
Write Latency
The WRITE latency, WL, is the delay, in clock cycles, between the registration of a WRITE command and the
availability of the first bit of input data as shown in Figure 21. WL can be set from 2 to 4 clocks depending on the
operating frequency. Setting the WRITE latency to 2 or 3 clocks will cause the device to enable the data input
receivers on all ACT commands.
3.5.5
Test mode
The normal operating mode is selected by issuing a Mode Register Set command with bit A7 set to zero and bits
A0-A6 and A8-A11 set to the desired value.
3.5.6
DLL Reset
The normal operating mode is selected by issuing a Mode Register Set command with bit A8 set to zero and bits
A0-A7 and A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command
with bit A8 set to one and bits A0-A7 and A9-A11 set to the desired values. The GDDR3 SGRAM returns
automatically in the normal mode of operations once the DLL reset is completed.
Data Sheet
35
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.6
Bank / Row Activation (ACT)
Before a READ or WRITE command can be issued to
a bank, a row in that bank must be opened. This is
accomplished via the ACT command, which selects
both the bank and the row to be activated.
CLK#
CLK
CKE
CS#
After opening a row by issuing an ACT command, a
READ or WRITE command may be issued after tRCD to
that row.
A subsequent ACT command to a different row in the
same bank can only be issued after the previous active
row has been closed (precharged). The minimum time
interval between successive ACT commands to the
RAS#
CAS#
WE#
same bank is defined by tRC
.
A subsequent ACT command to another bank can be
issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACT
commands to different banks is defined by tRRD
.
There is a minimum time tRAS between opening and
closing a row.
A0-A11
RA
BA
BA0-BA1
RA: Row Address
BA: Bank Address
Don't Care
Figure 17 Activating a specific row
CLK#
CLK
Com.
ACT
Row
B.Y
R/W
Col
PRE
A8
ACT
Row
B.Y
ACT
Row
B.X
Row: Row Address
Col: Column Address
B.X: Bank X
A0-A11
BA0, BA1
B.Y
B.Y
B.Y: Bank Y
R/W: READ or WRITE command
PRE: PRECHARGE command
ACT: ACTIVATE command
tRCD
tRAS
tRC
tRRD
Don't Care
Figure 18 Bank Activation timing
Data Sheet
36
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
Table 21
ACT Timing Parameters for –2.0, –2.2 and –2.5 speed sorts
Symbol Limit Values
Parameter
Unit Notes
- 2.0
- 2.2
- 2.5
min max
min max
min max
Row Cycle Time
Row Active Time
tRC
37.2
—
39.6
—
45.0
—
ns
tRAS
tRRD
24.0 8 x tREFI 26.2 8 x tREFI 30.0 8 x tREFI ns
ACT(a) to ACT(b) Command
period
8.0
—
—
8.8
—
—
10.0
17.5
—
—
ns
ns
ns
Row to Column Delay Time for
Reads
tRCDRD
tRCDWR
16.0
17.5
Row to Column Delay Time for
Writes
tRCDWR(min) = tRCDRD(min) - (WL + 1) x tCK(min)
3.7
Writes (WR)
Write Basic Information
3.7.1
Write bursts are initiated with a WR command, as
shown in Figure 19. The column and bank addresses
are provided with the WR command, and Auto
Precharge is either enabled or disabled for that access.
The length of the burst initiated with a WR command is
always four. There is no interruption of WR bursts. The
two least significant address bits A0 and A1 are ’Don’t
Care’.
CLK#
CLK
CKE
CS#
RAS#
For WR commands with Autoprecharge the row being
accessed is precharged tWR/A after the completion of
the burst. If tRAS(min) is violated the begin of the internal
Autoprecharge will be performed one cycle after
t
RAS(min) is met. tWR/A can be programmed in the Mode
CAS#
Register. Choosing high values for tWR/A will prevent the
chip to delay the internal Autoprecharge in order to
meet tRAS(min).
WE#
During WR bursts data will be registered with the edges
of WDQS. The write latency can be programmed during
Extended Mode Register Set. The first valid data is
registered with the first valid rising edge of WDQS
following the WR command. The externally provided
WDQS must switch from HIGH to LOW at the beginning
of the preamble. There is also a postamble requirement
before the WDQS returns to HIGH. The WDQS signal
can only transition when data is applied at the chip input
and during pre- and postambles.
A2-A7, A9
CA
A0, A1
A10-A11
A8
AP
BA
t
DQSS is the time between WR command and first valid
BA0-BA1
rising edge of WDQS. Nominal case is when WDQS
edges are aligned with edges of external CLK.
Minimum and maximum values of tDQSS define early
and late WDQS operation. Any input data will be
ignored before the first valid rising WDQS transition.
AP: AutoPrecharge
CA: Column Address
BA: Bank Address
Don't Care
Figure 19 Write Command
t
DQSL and tDQSH define the width of low and high phase
of WDQS. The sum of tDQSL and tDQSH has to be tCK.
Data Sheet
37
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
Back to back WR commands are possible and produce Setup and hold time for incoming DQs and DMs relative
a continuous flow of input data. There must be one to the WDQS edges are specified as tDS and tDH. DQ
NOP cycle between two back to back WR commands.
and DM input pulse width for each input is defined as
DIPW. The input data is masked if the corresponding DM
signal is high.
t
Any WR burst may be followed by a subsequent RD
command. Figure 3.7.5 shows the timing requirements
for a WR followed by a RD. A WR may also be followed All timing parameters are defined with graphics DRAM
by a PRE command to the same bank. tWR has to be terminations on.
met as shown in Figure 3.7.8.
Table 22
WDQS
Mapping of WDQS and DM signals
Data mask signal
Controlled DQs
DQ0 - DQ7
WDQS0
WDQS1
WDQS2
WDQS3
DM0
DM1
DM2
DM3
DQ8 - DQ15
DQ16 - DQ23
DQ24 - DQ31
CLK#
CLK
tDQSS
tWPRE
nominal WDQS
tDQSH
tDQSL
tDQSH
tWPST
tDS tDH
tDS tDH
Preamble
Postamble
WDQS
DQ
tDIPW
D0
D1
D2
D3
tDS
tDH
DMx
tDIPW
Data masked
Data masked
min(tDQSS
)
early WDQS
WDQS
max(tDQSS
)
late WDQS
WDQS
Don't Care
DMx: Represents one DM line
Figure 20 Basic Write Burst / DM Timing
Note: : WDQS can only transition when data is applied at the chip input and during pre- and postambles
Data Sheet
38
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
Table 23
WR Timing Parameters for –2.0, –2.2 and –2.5 speed sorts
Symbol Limit Values
Parameter
Unit Notes
- 2.5
- 2.0
- 2.2
min max min max min max
1)
CAS(a) to CAS(b) Command period
tCCD
2
—
2
—
2
—
tCK
Write Cycle Timing Parameters for Data and Data Strobe
Write command to first WDQS latching tDQSS
transition
WL - WL
0.25 +0.25 0.25 +0.25 0.25 +0.25
WL - WL
WL - WL
tCK
ns
ns
tCK
2)
2)
Data-in and Data Mask to WDQS Setup tDS
Time
0.375 —
0.375 —
0.375 —
0.375 —
0.425 —
0.425 —
Data-in and Data Mask to WDQS Hold tDH
Time
Data-in and DM input pulse width (each tDIPW
0.45
—
0.45
—
0.45
—
input)
3)
3)
WDQS input low pulse width
WDQS input high pulse width
WDQS Write Preamble Time
WDQS Write Postamble Time
Write to Read Command Delay
Write Recovery Time
tDQSL
tDQSH
tWPRE
tWPST
tWTR
0.45
0.45
—
—
0.45
0.45
—
—
0.45
0.45
—
—
tCK
tCK
0.75 1.25 0.75 1.25 0.75 1.25 tCK
0.75 1.25 0.75 1.25 0.75 1.25 tCK
2)4)
2)4)
6.0
—
—
6.6
—
—
7.5
—
—
ns
ns
tWR
11.0
11.0
12.5
1) tCCD is either for gapless consecutive writes or gapless consecutive reads
2) Timing parameters defined with Graphics DRAM terminations on.
3) tDQSL. and tDQSH apply for the Write preamble and postamble as well.
4) tWTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQSx
signal
Data Sheet
39
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.7.2
Write - Basic Sequence
0
1
2
3
4
5
6
7
8
CLK#
CLK
Com
.
WR
B/C
N/D
DES
DES
DES
DES
DES
DES
DES
Addr.
WL = 2
WDQS
DQ
D0
D1
D2
D3
WL = 4
WDQS
DQ
D0
D1
D2
D3
Com
.
WR
B/C
N/D
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Addr.
WL = 2
DQ
D0
D1
D2
D3
WL = 4
WDQS
DQ
D0
D1
D2
D3
B / C: Bank / Column address
WR: WRITE
NOP: No Operation
DES: Deselect
Com.: Command
Addr.: Address B / C
D#:
WL:
Data to B / C
Write Latency
N/P: NOP or DES
Don't Care
Figure 21 Write Burst Basic Sequence
1. Shown with nominal value of tDQSS.
2. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
3. When NOPs are applied on the command bus, the WDQS and the DQ busses remain stable High.
4. When DESs are applied on the command bus, the status of the WDQS and DQ busses is unknown.
Data Sheet
40
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.7.3
Write - Consecutive Bursts
Gapless Bursts
3.7.3.1
0
1
2
3
4
5
6
7
8
9
CLK#
CLK
Com.
WR
N/D
WR
N/D
DES
DES
DES
DES
DES
DES
Addr.
B/Cx
B/Cy
WL = 2
WDQS
DQ
Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3
WL = 3
WDQS
DQ
Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3
WL = 4
WDQS
DQ
Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3
Dx#:
Dy#:
Com.: Command
Data to B / Cx
Data to B / Cy
WR:
DES: Deselect
N/D:
WRITE
B / Cx: Bank / Column address x
B / Cy: Bank / Column address y
NOP / Deselect
WL:
Write Latency
Addr.: Address B / C
Don't Care
Figure 22 Gapless Write Bursts
1. Shown with nominal value of tDQSS
2. The second WR command may be either for the same bank or another bank
3. WDQS can only transition when data is applied at the chip input and during pre- and postambles
Data Sheet
41
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.7.3.2
Bursts with Gaps
0
1
2
3
4
5
6
7
8
9
10
CLK#
CLK
Com
.
WR
N/D
N/D
WR
DES
DES
DES
DES
DES
DES
DES
Addr.
B/Cx
B/Cy
WL = 2
WDQS
DQ
Dx0 Dx1 Dx2 Dx3
Dy0 Dy1 Dy2 Dy3
WL = 3
WDQS
DQ
Dx0 Dx1 Dx2 Dx3
Dy0 Dy1 Dy2 Dy3
WL = 4
WDQS
DQ
Dx0 Dx1 Dx2 Dx3
Dy0 Dy1 Dy2 Dy3
Com.: Command
Addr.: Address B / C
B / Cx: Bank / Column address x
B / Cy: Bank / Column address y
WL:
Write Latency
WR:
Dx#:
Dy#:
WRITE
Data to B / Cx
Data to B / Cy
DES: Deselect
N/D: NOP / Deselect
Don't Care
Figure 23 Consecutive Write Bursts with Gaps
1. Shown with nominal value of tDQSS.
2. The second WR command may be either for the same bank or another bank.
3. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
42
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.7.4
Write with Autoprecharge
0
1
2
3
4
5
6
7
8
9
10
CLK#
CLK
Com.
WR/A
B/C
N/D
DES
DES
DES
DES
DES
DES
DES
DES
DES
A9,
A7-A2
A8
tWR/A=3
WL = 2
WDQS
tRP
DQ
D0
D1 D2
D3
D1
Begin of
tRASMIN
satisfied
Autoprecharge
WL = 3
t
WR/A=3
WDQS
DQ
tRP
D0
D2
D0
D3
D1
Begin of
tRASMIN
Autoprecharge
satisfied
WL = 4
t
WR/A=3
WDQS
DQ
tRP
D2
D3
Begin of
tRASMIN
satisfied
Autoprecharge
Com.: Command
Addr.: Address B / C
B / C: Bank / Column address
WR/A: WRITE with auto-precharge
WL:
Write Latency
Don't Care
D#:
Data to B / C
DES: Deselect
N/D: NOP or Deselect
Figure 24 Write with Autoprecharge
1. Shown with nominal value of tDQSS
2. tWR/A starts at the first rising edge of CLK after the last valid edge of WDQS.
3. tRP starts after tWR/A has been expired.
4. when issuing a WR/A command please consider that the tRAS requirement also must be met at the beginning
of tRP
5. tWR/A * tCYC ≥ tWR
6. WDQS can only transition when data is applied at the chip input and during pre- and postambles
Data Sheet
43
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.7.5
Write followed by Read
0
1
2
3
4
5
6
7
8
9
CLK#
CLK
Com.
Addr.
WR
B/C
N/D
DES
DES
DES
DES
DES
RD
DES
DES
B/C
WL = 2
tWTR
WDQS
DQ
D0
D1
D2
D3
WR
B/C
N/D
DES
DES
DES
DES
DES
DES
RD
N/D
B/C
WL = 3
tWTR
WDQS
DQ
D0
D1
D2
D3
WR
B/C
N/D
DES
DES
DES
DES
DES
DES
DES
RD
B/C
WL = 4
tWTR
WDQS
DQ
D0
D1
D2
D3
B / C: Bank / Column address
D#:
Data to B / Cx
WR:
RD:
WRITE
READ
Com.: Command
Addr.: Address B / C
WL:
DES: Deselect
N/D: NOP / Deselect
Write Latency
Don't Care
Figure 25 Write followed by Read
1. Shown with nominal value of tDQSS.
2. The RD command may be either for the same bank or another bank.
3. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
44
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.7.6
Write followed by DTERDIS
0
1
2
3
4
5
6
7
8
9
CLK#
CLK
Com.
Addr.
WR
B/C
DTD
DES
DES
DES
DES
DES
DES
DES
DES
CL = 5
WL = 2
WDQS
DQ
D0
D1
D2
D3
WR
B/C
DTD
DES
DES
DES
DES
DES
DES
DES
DES
CL = 6
WL = 3
WDQS
DQ
D0
D1
D2
D3
WR
B/C
N/D
DTD
DES
DES
DES
DES
DES
DES
DES
CL = 6
WL = 4
WDQS
DQ
D0
D1
D2
D3
B / C: Bank / Column address
WR: WRITE
DTD: DTERDIS
WL:
CL:
DES:
N/D:
Write Latency
CAS Latency
Deselect
D#:
Data to B / Cx
NOP or Deselect
Com.: Command
Addr.: Address B / C
Don't Care
Data Termination Off
Figure 26 Write Command followed by DTERDIS
1. Write shown with nominal value of tDQSS.
2. WDQS can only transition when data is applied at the chip input and during pre- and postambles
3. A margin of one clock has been introduced in order to make sure that the data termination are still on when
the last Write data reaches the memory.
4. The minimum distance between Write and DTERDIS is (WL -CL + 4) clocks and always bigger than or equal
to 1. For (CL=6 / WL=2) and (CL=7 / WL=3) as well as for (CL=7 / WL=2) the minimum distance between Write
and DTERDIS is set to 1 clock. Please refer to table below :
Data Sheet
45
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
Table 24
WL / CL
WL \ CL
5
1
2
3
6
1
1
2
7
1
1
1
2
3
4
Data Sheet
46
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.7.7
Write with Autoprecharge followed by Read / Read with Autoprecharge
0
1
2
3
4
5
6
7
8
9
CLK#
CLK
RD
Com.
WR/A
B/C
N/D
DES
DES
DES
DES
DES
DES
DES
RD/A
A9,
A2-A7
B/C
A8
tWTR
tWR/A
tRP
WL = 2
WDQS
DQ
Begin of Autoprecharge
DES
D0
D1
D2
D3
RD
RD/A
WR/A
B/C
Com.
N/D
DES
DES
DES
DES
DES
DES
A9,
A2-A7
B/C
A8
tWTR
tWR/A
tRP
WL = 3
WDQS
DQ
Begin of Autoprecharge
D0
D1
D2
D3
RD
DES
WR/A
B/C
Com.
N/D
DES
DES
DES
DES
DES
DES
RD/A
A9,
A2-A7
B/C
A8
tWTR
tRP
tWR/A
WL = 4
WDQS
DQ
Begin of Autoprecharge
D0
D1
D2
D3
Com.: Command
Addr.: Address B / C
WL: Write Latency
Don't Care
B / C: Bank / Column address
WR/A: WRITE with Autoprecharge
RD RD/A: READ or
READ with Autoprecharge
Data to B / Cx
D#:
DES: Deselect
N/D: NOP or Deselect
0: RD, 1: RD/A
Figure 27 Write with Autoprecharge followed by Read or Read with Autoprecharge on another bank
1. Shown with nominal value of tDQSS.
2. The RD command is only allowed for another activated bank
3. tWR/A is set to 3 in this example
4. WDQS can only transition when data is applied at the chip input and during pre- and postambles
Data Sheet
47
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.7.8
Write followed by Precharge on same Bank
0
1
2
3
4
5
6
7
8
9
10
CLK#
CLK
Com.
WR
B/C
N/D
DES
DES
DES
DES
DES
DES
PRE
B
DES
DES
Addr.
tRP
WL = 2
tWR
WDQS
DQ
D0
D1
D2
D3
WR
B/C
N/D
DES
DES
DES
DES
DES
DES
DES
PRE
B
DES
tRP
WL = 3
tWR
WDQS
DQ
D0
D1
D2
D3
WR
B/C
N/D
DES
DES
DES
DES
DES
DES
DES
DES
PRE
B
tRP
WL = 4
tWR
WDQS
DQ
D0
D1
D2
D3
N/D: NOP or Deselect
DES: Deselect
B / C: Bank / Column address
WR:
PRE:
Dx#:
Dy#:
WRITE
Com.: Command
PRECHARGE
Data to B / Cx
Data to B / Cy
Addr.: Address B / C
WL:
Write Latency
Don't Care
Figure 28 Write followed by Precharge on same Bank
1. Shown with nominal value of tDQSS.
2. WR and PRE commands are to same bank
3. tRAS requirement must also be met before issuing PRE command
4. WDQS can only transition when data is applied at the chip input and during pre- and postambles
Data Sheet
48
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.8
Reads (RD)
3.8.1
Read - Basic Information
During RD bursts the memory device drives the read
data edge aligned with the RDQS signal which is also
driven by the memory. After a programmable CAS
latency of 5, 6 or 7 the data is driven to the controller.
RDQS leaves HIGH state one cycle before its first rising
edge (RD preamble tRPRE). After the last falling edge of
RDQS a postamble of tRPST is performed.
CLK#
CLK
CKE
CS#
t
AC is the time between the positive edge of CLK and the
appearance of the corresponding driven read data. The
skew between RDQS and the crossing point of
CLK/CLK is specified as tDQSCK. tAC and tDQSCK are
defined relatively to the positive edge of CLK. tDQSQ is
the skew between a RDQS edge and the last valid data
edge belonging to the RDQS edge. tDQSQ is derived at
each RDQS edge and begins with RDQS transition and
ends with the last valid transition of DQs. tQHS is the
data hold skew factor and tQH is the time from the first
valid rising edge of RDQS to the first conforming DQ
going non-valid and it depends on tHP and tQHS. tHP is
the minimum of tCL and tCH. tQHS is effectively the time
from the first data transition (before RDQS) to the
RDQS transition. The data valid window is derived for
each RDQS transition and is defined as tQH minus
RAS#
CAS#
WE#
A2-A7, A9
CA
A0, A1
A10-A11
tDQSQ
.
A8
AP
BA
After completion of a burst, assuming no other
commands have been initiated, data will go High-Z and
RDQS will go HIGH. Back to back RD commands are
possible producing a continuous flow of output data.
There has to be one NOP cycle between back to back
RD commands.
BA0-BA1
AP: AutoPrecharge
CA: Column Address
BA: Bank Address
Any RD burst may be followed by a subsequent WR
command. The minimum required number of NOP
commands between the RD command and the WR
command (tRTW) depends on the programmed Read
latency and the programmed Write latency
Don't Care
Figure 29 Read Command
Read bursts are initiated with a RD command, as
shown in Figure 29. The column and bank addresses
are provided with the RD command and Autoprecharge
is either enabled or disabled for that access. The length
of the burst initiated with a RD command is always four.
There is no interruption of RD bursts. The two least
significant start address bits are ’Don’t Care’.
t
RTW(min)= (CL+4-WL)
Chapter 3.8.5 shows the timing requirements for RD
followed by a WR with some combinations of CL and
WL.
A RD may also be followed by a PRE command. Since
no interruption of bursts is allowed the minimum time
between a RD command and a PRE is two clock cycles
as shown in Chapter 3.8.6.
If Autoprecharge is enabled, the row being accessed
will start precharge at the completion of the burst. The
begin of the internal Autoprecharge will always be one
cycle after tRAS(min) is met.
All timing parameters are defined with controller
terminations on.
Data Sheet
49
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
tCH
tCL
tCK
tHP
CLK#
CLK
tDQSCK
RDQS
Preamble
tRPRE
Postamble
tRPST
DQ (first data valid)
DQ (last data valid)
D0
D1
D2
D3
D0
D1
D2
D3
tAC
All DQs collectively
D0
tDQSQ
tQH
D1
D2
tDQSQ
D3
data
valid
window
Don't Care
Hi-Z : Not driven
by DDRIII SGRAM
tQHS
tLZ
tHZ
Figure 30 Basic Read Burst Timing
1. The GDDR3 SGRAM switches off the DQ terminations one cycle before data appears on the busand drives
the data bus HIGH.
2. The GDDR3 SGRAM drives the data bus HIGH one cycle after the last data driven on the bus before switching
the termination on again.
Table 25
READ Timing Parameters for -2.0 ns, -2.2 ns and -2.5 ns speed sorts
Symbol Limit Values
Parameter
Unit Note
- 2.0
min
2
- 2.2
- 2.5
max min
max min
max
CAS (a) to CAS (b) Command period tCCD
—
2
—
2
—
tCK
tCK
1
Read to Write command delay
tRTW
tRTW(min)= (CL+4-WL)
2
Read Cycle Timing Parameters for Data and Data Strobe
Data Access Time from Clock
Read Preamble
tAC
–0.4
0.75
0.75
0.4
–0.45 0.45 –0.5
0.5
ns
4
tRPRE
tRPST
tHZ
1.25 0.75
1.25 0.75
1.25 0.75
1.25 0.75
1.25 tCK
1.25 tCK
Read Postamble
Data-out high impedance time from
CLK
tACmin tACmax tACmin tACmax tACmin tACmax ns
4
4
Data-out low impedance time from
CLK
tLZ
tACmin tACmax tACmin tACmax tACmin tACmax ns
RDQS edge to Clock edge skew
tDQSCK
-0.4
—
+0.4 -0.45 +0.45 -0.5
+0.5 ns
0.28 ns
0.280 ns
ns
4
4
4
4
3
RDQS edge to output data edge skew tDQSQ
0.225 —
0.225 0
0.25
0.250 0
tHP–tQHS
0.45
—
Data hold skew factor
tQHS
tQH
tHP
0
Data output hold time from RDQS
Minimum clock half period
tHP–tQHS
0.45
tHP–tQHS
0.45
—
—
—
tCK
1. tCCD is either for gapless consecutive reads or gapless consecutive writes.
Data Sheet
50
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
2. Please round up tRTW to the next integer of tCK.
3. tHP is the minimum of tCL and tCH
4. Timing parameters defined with controller terminations on.
3.8.2
Read - Basic Sequence
0
1
2
3
4
5
6
7
8
9
CLK#
CLK
Com
.
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B / C
CAS latency = 5
RDQS
DQ
D0
D1
D2
D3
CAS latency = 6
RDQS
DQ
D0
D1
D2
D3
RD:
READ
B / C: Bank / Column address
Dx: Data from B / C
N/D: Nop or Deselect
Com.: Command
Don't Care
Addr.: Address B / C
DQs : Terminations off
RDQS : Not driven
Figure 31 Read Burst
1. Shown with nominal tAC and tDQSQ
2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS
3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data
Data Sheet
51
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.8.3
Consecutive Read Bursts
Gapless Bursts
3.8.3.1
0
1
2
3
4
5
6
7
8
9
10
11
CLK#
CLK
Com.
Addr.
RD
N/D
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
B/Cx
B/Cy
CAS latency = 5
RDQS
DQ
Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3
CAS latency = 6
RDQS
DQ
Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3
B / Cx: Bank / Column address x
B / Cy: Bank / Column address y
RD:
READ
N/D: NOP or Deselect
Dx#:
Dy#:
Com.: Command
Data from B / Cx
Data from B / Cy
Don't Care
DQs : Terminations off
RDQS : Not driven
Addr.: Address B / C
Figure 32 Gapless Consecutive Read Bursts
1. the second RD command may be either for the same bank or another bank
2. Shown with nominal tAC and tDQSQ
3. Example applies only when READ commands are issued to same device
4. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS
5. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data
Data Sheet
52
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.8.3.2 Bursts with Gaps
0
1
2
3
4
5
6
7
8
9
10
CLK#
CLK
Com.
Addr.
RD
N/D
N/D
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
B/Cx
B/Cy
CAS latency = 5
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
Dy0 Dy1 Dy2 Dy3
CAS latency = 6
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
Dy0 Dy1 Dy2
B / Cx: Bank / Column address x
B / Cy: Bank / Column address y
Don't Care
DQs : Terminations off
RDQS : Not driven
RD:
READ
Data from B / Cx
Data from B / Cy
Dx#:
Dy#:
Com.: Command
Addr.: Address B / C
Figure 33 Consecutive Read Bursts with Gaps
1. the second RD command may be either for the same bank or another bank
2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS.
3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data
Data Sheet
53
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.8.3.3 Read followed by DTERDIS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK#
CLK
Com.
Addr.
RD
N/D
N/D
N/D
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
B/Cx
CAS latency = 5
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
Com.
Addr.
RD
N/D
N/D
N/D
N/D
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
B/Cx
CAS latency = 5
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
B / Cx: Bank / Column address x
Dx#: Data from B / Cx
Com.: Command
RD:
READ
Don't Care
DTD: DTERDIS
DES: Deselect
N/D: NOP or Deselect
DQs : Terminations off
RDQS : Not driven
Addr.: Address B / C
Figure 34 Read Command followed by DTERDIS
1. At least 3 NOPs are required between a READ command and a DTERDIS command in order to avoid
contention on the RDQS bus in a 2 rank system.
2. CAS Latency 5 is used as an example.
3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of (BL/2
+ 2 ) clocks.
4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command
corresponds to a Read command applied to the second Graphics DRAM in a 2 rank system. In this case,
RDQS would be driven by the second Graphics DRAM.
Data Sheet
54
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.8.4 Read with Autoprecharge
0
1
2
3
4
5
6
7
8
CLK#
CLK
Com.
RD/A
B / C
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
A9,
A7-A2
A8
CAS latency = 5
RDQS
DQ
D0
D1
D2
D3
CAS latency = 6
RDQS
DQ
D0
D1
D2
D3
BL / 2
t
RP
B / C: Bank / Column address
RD/A: READ with auto-precharge
N/D: NOP or Deselect
Don't Care
Begin of
Dx:
Data from B / C
DQs : Terminations off
RDQS : Not driven
Autoprecharge
Com.: Command
Addr.: Address B / C
Figure 35 Read with Autoprecharge
1. When issuing a RD/A command , the tRAS requirement must be met at the beginning of Autoprecharge
2. Shown with nominal tAC and tDQSQ
3. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS
4. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data
5. tRAS Lockout support
Data Sheet
55
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.8.5
Read followed by Write
0
1
2
3
4
5
6
7
8
9
10
11
CLK#
CLK
Com.
RD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
Addr.
B/Cr
B/Cw
CAS latency = 5
Write latency = 3
tRTW
RDQS
WDQS
DQ
D0r D1r D2r D3r
D0w D1w D2w D3w
RD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
B/Cr
B/Cw
CAS latency = 6
Write latency = 4
tRTW
RDQS
WDQS
DQ
D0r D1r D2r D3r
D0w D1w D2w
Dxr:
READ Data from B / C
B / Cr: Bank / Column address for READ
B / Cw: Bank / Column address for WRITE
Don't Care
Dxw: WRITE Data from B / C
Com.: Command
Addr.: Address B / C
DQs : Terminations off
RDQS : Not driven
RD:
READ
WRITE
WR:
DES: Deselect
Figure 36 Read followed by Write
1. Shown with nominal tAC, tDQSQ and tDQSS
2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS
3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data
4. WDQS can only transition when data is applied at the chip input and during pre- and postambles
5. The Write command may be either on the same bank or on another bank
Data Sheet
56
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.8.6
Read followed by Precharge on the same Bank
0
1
2
3
4
5
6
7
8
CLK#
CLK
Com.
RD
N/D
PRE
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B / C
CAS latency = 5
RDQS
DQ
D0
D1
D2
D3
CAS latency = 6
RDQS
DQ
D0
D1
D2
D3
tRP
B / C: Bank / Column address
Don't Care
RD:
PRE:
Dx:
READ
PRECHARGE
Data from B / C
Com.: Command
Addr.: Address B / C
DQs : Terminations off
RDQS : Not driven
N/D: NOP or Deselect
Figure 37 Read followed by Precharge on the same Bank
1. tRAS requirement must also be met before issuing PRE command
2. RD and PRE commands are applied to the same bank.
3. Shown with nominal tAC and tDQSQ
4. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS
Data Sheet
57
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.9
Data Termination Disable (DTERDIS)
The Data Termination Disable command is detected by
the device by snooping the bus for Read commands
when CS is high. The terminators are disabled starting
at CL - 1 clocks after the DTERDIS command is
detected and the duration is 4 clocks. The command
and address terminators are always enabled.
CLK#
CLK
CKE
CS#
DTERDIS may only be applied to the GDDR3 Graphics
memory if it is not in the Power Down or in the Self
Refresh state.
The timing relationship between DTERDIS and other
commands is defined by the constraint to avoid
contention on the RDQS bus (i.e Read to DTERDIS
transistion) or the necessity to have a defined
termination on the data bus during Write (i.e. Write to
DTERDIS transition). ACT and PRE/PREALL may be
applied at any time before or after a DTERDIS
command.
RAS#
CAS#
WE#
A2-A7, A9
A0, A1
A10-A11
A8
BA0-BA1
AP: AutoPrecharge
Don't Care
Figure 38 Data Termination Disable Command
0
1
2
3
4
5
6
7
8
9
CLK#
CLK
Com
.
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
CAS latency = 5
DQ
Termination
Data Terminations are disabled
DTD:
DTERDIS
Don't Care
N/D : NOP or Deselect
Com.: Command
Addr.: Address B / C
Figure 39 DTERNIS Timing
Data Sheet
58
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK#
CLK
Com.
Addr.
DTD
N/D
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
CAS latency = 5
RDQS
DQ
Com.
Addr.
DTD
N/D
N/D
N/D
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
CAS latency = 5
RDQS
DQ
Com.
Addr.
DTD
N/D
N/D
N/D
N/D
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
CAS latency = 5
RDQS
DQ
Com.: Command
Addr.: Address B / C
B / Cx: Bank / Column address x
RD: READ
DTD: DTERDIS
Don't Care
DQs : Terminations off
RDQS : Not driven
N/D :
NOP or Deselect
Dx#:
Data from B / Cx
Figure 40 DTERNIS followed by DTERNIS
1. At least 1NOP is required between 2 DTERDIS commands. This correspond to a Read to Read transistion on
the other memory in a 2 rank system.
2. CAS Latency 5 is used as an example.
3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of (BL/2
+ 2 ) clocks
4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command
corresponds to a Read command applied to the second Graphics DRAM in a 2 rank system. In this case,
RDQS would be driven by the second Graphics DRAM.
Data Sheet
59
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.9.1
DTERDIS followed by READ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK#
CLK
Com.
Addr.
DTD
N/D
N/D
N/D
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
B/Cx
CAS latency = 5
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
Com.
Addr.
DTD
N/D
N/D
N/D
N/D
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
B/Cx
CAS latency = 5
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
Com.: Command
Addr.: Address B / C
B / Cx: Bank / Column address x
RD: READ
DTD: DTERDIS
Don't Care
DQs : Terminations off
RDQS : Not driven
N/D:
Dx#:
NOP or Deselect
Data from B / Cx
Figure 41 DTERDIS Command followed by READ
1. At least 3 NOPs are required between a DTERDIS command and a READ command in order to avoid
contention on the RDQS bus in a 2 rank system.
2. CAS Latency 5 is used as an example.
3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of 4
clocks.
Data Sheet
60
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.9.2
DTERDIS followed by Write
0
1
2
3
4
5
6
7
8
9
10
11
CLK#
CLK
Com.
Addr.
DTD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
B/Cw
CAS latency = 5
Write latency = 3
WDQS
DQ
D0w D1w D2w D3w
DTD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
B/Cw
Write latency = 4
CAS latency = 6
WDQS
DQ
D0w D1w D2w
B / Cw: Bank / Column address for WRITE
WR: WRITE
DTD: DTERDIS
Dxw: WRITE Data from B / C
Com.: Command
Addr.: Address B / C
Don't Care
DQs : Terminations off
DES: Deselect
Figure 42 DTERDIS Command followed by Write
1. Write shown with nominal value of tDQSS
2. WDQS can only transition when data is applied at the chip input and during pre- and postambles
3. The minimum distance between DTERDIS and Write is (CL -WL + 4) clocks.
Data Sheet
61
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.10
Precharge (PRE/PREALL)
The Precharge command is used to deactivate the
open row in a particular bank (PRE) or the open rows in
all banks (PREALL). The bank(s) will enter the idle
state and be available again for a new row access after
the time tRP. A8/AP sampled with the PRE command
determines whether one or all banks are to be
precharged. For PRE commands BA0 and BA1 select
the bank. For PREALL inputs BA0 and BA1 are “Don’t
Care”. The PRE/PREALL command may not be given
unless the tRAS requirement is met for the selected bank
(PRE), or for all banks (PREALL).
CLK#
CLK
CKE
CS#
RAS#
CAS#
WE#
A0-7,9-11
A8
ALL
BA
BA0-BA1
ALL: High selects all banks
Low selects Bank BA
BA: Bank Address
/
Don't Care
Figure 43 Precharge Command
Table 26
BA1, BA0 precharge bank selection
A8 / AP
BA1
BA0
precharged bank(s)
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
All banks
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Data Sheet
62
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
CLK#
CLK
Command
ACT
Row
B.X
NOP
PRE
B.X
NOP
NOP
ACT
Row
B.X
A0 - A11
BA0, BA1
tRAS
tRC
tRP
PRE: Precharge
ACT: Activate
Row: Row Address
B.X: Bank X
Don't Care
Figure 44 Precharge Timing
Table 27
Precharge Timing Parameters for –2.0, –2.2 and –2.5 speed sorts
Symbol Limit Values
Parameter
Unit Notes
- 2.0
min max min max min max
13.2 13.2 15.0
- 2.2
- 2.5
Row Precharge Time
tRP
–
–
–
ns
Data Sheet
63
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.11
Auto Refresh Command (AREF)
AREF is used to do a refresh cycle on one row in each
bank. The addresses are generated by an internal
refresh controller; external address pins are “DON’T
CARE”. All banks must be idle before the AREF
command can be applied. The delay between the
AREF command and the next ACT or subsequent
AREF must be at least tRFC(min). The refresh period
starts when the AREF command is entered and ends
CLK#
CLK
CKE
CS#
t
RFC later at which time all banks will be in the idle state.
Within a period of tREF=32ms the whole memory has to
be refreshed. The average periodic interval time from
AREF to AREF is then tREFI(max)=7.8µs.
RAS#
To improve efficiency bursts of AREF commands can
be used. Such bursts may consist of maximum 8 AREF
commands. tRFC(min) is the minimum required time
between two AREF commands inside one AREF burst.
According to the number of AREF commands in one
burst the average required time from one AREF burst
to the next can be increased. Example: If the AREF
bursts consists of 4 AREF commands, the average
time from one AREF burst to the next is 4 * 7.8µs =
31.2µs.
CAS#
WE#
A0-A11
BA0-BA1
The AREF command generates an update of the OCD
output impedance and of the addresses, commands
and DQ terminations. The timing parameter tKO ( see
section 2.3.2 ) must be complied with.
BA: Bank Address
Don't Care
Figure 45 Auto Refresh Command
CLK#
CLK
Command
CKE
PRE
ARF
NOP
A.C.
NOP
ARF
NOP
tRP
tRFC
A.C.: AREF or ACT Command
ARF: Auto Refresh
tREFI
Don't Care
Figure 46 Auto Refresh Cycle
Table 28
Autorefresh Timing Parameters for –2.0, –2.2 and –2.5 speed sorts
Symbol Limit Values
Parameter
Unit Notes
- 2.0
- 2.2
- 2.5
min max min max min max
Refresh Period (4096 cycles)
tREF
—
32
—
—
32
—
—
32
—
ms
µs
ns
Average periodic Auto Refresh interval
Delay from AREF to next ACT/ AREF
7.8
54
7.8
54
7.8
54
tREFI
tRFC
Data Sheet
64
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.12
Self-Refresh
3.12.1
Self-Refresh Entry (SREFEN)
The Self-Refresh mode can be used to retain data in
the GDDR3 Graphics RAM even if the rest of the
system is powered down. When in the Self-Refresh
mode, the GDDR3 Graphics RAM retains data without
external clocking. The Self-Refresh command is
initiated like an Auto-Refresh command except CKE is
disabled (LOW). Self Refresh Entry is only possible if all
banks are precharged and tRP is met.
CLK#
CLK
CKE
CS#
RAS#
CAS#
WE#
The GDDR3 Graphics RAM has a build-in timer to
accomodate Self-Refresh operation. The Self-Refresh
command is defined by having CS, RAS, CAS and CKE
held low with WE high at the rising edge of the clock.
Once the command is registered, CKE must be held
LOW to keep the device in Self-Refresh mode. When
the GDDR3 Graphics RAM has entered the Self-
Refresh mode, all external control signals, except CKE
are disabled. The address, command and data
terminators remain on. The DLL and the clock are
internally disabled to save power. The user may halt the
external clock while the device is in Self-Refresh mode
the next clock after Self-Refresh entry, however the
clock must be restarted before the device can exit Self-
Refresh operation.
A0-A7
A9-A11
A8
BA0-BA1
Don't Care
Figure 47 Self Refresh Entry Command
CLK#
CLK
Command
CKE
PA
SRF
1 Clock
tRP
CLK/CLK#
may be halted
PA.: Precharge ALL Command
(or last of PREs to each bank)
SRF: Self Refresh Command
Don't Care
Figure 48 Self Refresh Entry
Data Sheet
65
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.12.2
Self-Refresh Exit (SREFEX)
To exit the Self Refresh Mode, a stable external clock
is needed before setting CKE high asynchronously.
Once the Self-Refresh Exit command is registered, a
delay equal or longer than tXSC (minimum 200 Clock
Cycles) must be satisfied before any command can be
applied. During this time, the DLL is automatically
enabled, reset and calibrated.
CLK#
CLK
CKE
CS#
RAS#
CKE must remain HIGH for the entire Self-Refresh exit
period and commands must be gated off with CS held
HIGH. Alternately, NOP commands may be registered
on each positive clock edge during the Self Refresh exit
interval.
CAS#
WE#
A0-A11
A9-A11
Don't Care
Figure 49 Self Refresh Exit Command
CLK#
CLK
Command
CKE
N / D
N / D
N / D
A.C.
tXSC
CLK, CLK# must
be stable
A.C.: Any Command
N / D: NOP or DESEL Command
Don't Care
Figure 50 Self Refresh Exit
Table 29
Self Refresh Exit Timing Parameter for –2.0, –2.2 and –2.5 speed sorts
Symbol Limit Values
Parameter
Units Notes
- 2.0
min max min max min max
200 200 200
- 2.2
- 2.5
Self Refresh Exit time
Data Sheet
tXSC
–
–
–
tCK
66
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Functional Description
3.13
Power-Down
burst completion is defined after the rising edge of the
Read Postamble. For Writes, a burst completion is
defined one clock after the rising edge of the Write
Postamble.
CLK#
CLK
CKE
For Read with Autoprecharge and Write with
Autoprecharge, the internal Autoprecharge must be
completed before entering Power-Down.
1
2
CS#
RAS#
Power-Down is entered when CKE is registered LOW
(no access can be in progress). If Power-Down occurs
when all banks are idle, this mode is referred to as
Precharge Power-Down; if Power-Down occurs when
there is a row active in any bank, this mode is referred
to as Active Power-Down. Entering power-down
deactivates the input and output buffers, excluding
CLK, CLK and CKE. For maximum power saving, the
user has the option of disabling the DLL prior to
entering power-down. In that case the DLL must be
enabled and reset after exiting power-down, and 200
cycles must occur before a READ command can be
issued.
CAS#
WE#
A0-A11
BA0-BA1
In Power-Down mode, CKE low and a stable clock
signal must be maintained at the inputs of the GDDR3
Graphics RAM, all the other input signals are “Don’t
Care”. Power down duration is limited by the refresh
requirements of the device.
1: DESEL, 2: NOP
Don't Care
Figure 51 Power Down Command
The Power-Down state is synchronously exited when
CKE is registered HIGH (along with a NOP or DESEL
command). A valid executable command may be
applied tXPN later.
Unlike SDR SDRAMs, the GDDR3 Graphics RAM
requires CKE to be active at all times an access is in
progress : From the issuing of a READ or WRITE
command until completion of the burst. For READs, a
CLK#
CLK
N / D
N / D
N / D
N / D
A.C.
A.C.
Comm.
CKE
tIS
tXPN (Precharge)
tXARD (Active)
N / D: NOP or DESELECT
Command
Power-Down
Mode Entry
Power-Down
Mode Exit
A.C.:
Any Command
Don't Care
Figure 52 Power-Down Mode
Table 30
Power Down Exit Timing Parameter for –2.0, –2.2 and –2.5 speed sorts
Symbol Limit Values
Parameter
Unit Notes
- 2.0
- 2.2
- 2.5
min max min max min max
Precharge power-down exit timing
Data Sheet
tXPN
4
—
4
—
4
—
tCK
67
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
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DDR SGRAM
Electrical Characteristics
4
Electrical Characteristics
4.1
Absolute Maximum Ratings
Table 31
Absolute Maximum Ratings
Parameter
Symbol
Rating
min.
-0.5
-0.5
-0.5
-0.5
-55
Unit
max.
Power Supply Voltage
Power Supply Voltage for Output Buffer
Input Voltage
VDD
2.5
2.5
V
VDDQ
VIN
V
V
V
DDQ+0.5
DDQ+0.5
V
Output Voltage
VOUT
TSTG
IOUT
V
Storage Temperature
Short Circuit Output Current
+150
50
°C
mA
—
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage of the
device. This is a stress rating only, and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Table 32
Operation Conditions
Parameter
Symbol
Range
Unit
min.
0
max.
+90
+85
3.2
Operation Temperature (Junction)
Operation Temperature (Case)
Power Dissipation
TJ
°C
°C
W
TC
PD
0
—
Data Sheet
68
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Electrical Characteristics
4.2
Recommended Power & DC Operation Conditions.
All values are recommended operating conditions unless otherwise noted. Tc = 0 to 85 °C.
(0°C ≤ TC ≤ +85°C, VDD = +2.0 V ± 0.10 V, VDDQ = +2.0 V ± 0.10 V, see Table 1)
Table 33
Power & DC Operation Conditions
Symbol Speed Limit Values
Parameter
Unit Notes
sort
min.
1.9
1.9
1.9
1.9
1.9
1.9
typ.
2.0
2.0
2.0
2.0
2.0
2.0
max.
2.1
2.1
2.1
2.1
2.1
2.1
1)
Power Supply Voltage
VDD
–2.0
–2.2
–2.5
–2.0
–2.2
–2.5
–2.0
–2.2
–2.5
V
1)
V
1)
V
1)
Power Supply Voltage for I/O Buffer
Reference Voltage
VDDQ
V
1)
V
1)
V
2)
VREF
0.72*VDDQ 0.73*VDDQ 0.74*VDDQ
0.72*VDDQ 0.73*VDDQ 0.74*VDDQ
0.72*VDDQ 0.73*VDDQ 0.74*VDDQ
0.4*VDDQ
V
2)3)
2)3)
Output Low Voltage
VOL(DC)
IIL
V
4)
Input leakage current
CLK Input leakage current
Output leakage current
–5
–5
–5
+5
+5
+5
µA
IILC
µA
4)
IOL
µA
1) VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
2) VREF is allowed ± 19mV for DC error and an additionnal ± 28mV for AC noise.
3) VREF is expected to equal 73% of VDDQ for the transmitting device and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed ±2% VREF (DC). Thus, from 73% of VDDQ.
4) IIL and IOL are measured with ODT disabled.
Data Sheet
69
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Electrical Characteristics
4.3
DC & AC Logic Input Levels.
(0°C ≤ TC ≤ +85°C, VDD = +2.0 V ± 0.10 V, VDDQ = +2.0 V ± 0.10 V, see Table 1)
Table 34
DC & AC Logic Input Levels
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
Input logic high voltage, DC
Input logic low voltage, DC
Input logic high voltage, AC
Input logic low voltage, AC
Input logic high, DC, RESET pin
Input logoc low, DC, RESET pin
VIH(DC)
VIL(DC)
VIH (AC)
VIL(AC)
0.7 *VDDQ + 0.15
—
V
V
V
V
V
V
1
—
0.7 *VDDQ -0.15
—
1
0.7 *VDDQ +0.4
—
2,3
2,3
0.7 *VDDQ - 0.4
VIHR(DC)
VILR(DC)
0.8 *VDDQ
-0.3
V
DDQ + 0.3
0.2 *VDDQ
1. The DC values define where the input slew rate requirements are imposed, and the input signal must not
violate these levels in order to maintain a valid level.
2. Input slew rate = 2 V/ns. If the input slew rate is less than 2 V/ns, input timing may be compromised. All slew
rates are measured between VIL(DC) and VIH(DC)
.
3. VIH overshoot : VIH(MAX) = VDDQ+0.5 V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3
of the cycle rate. VIL undershoot: VIL(MIN) = 0 V for a pulse width ≤ 500ps and the pulse width cannot be greater
than 1/3 of the cycle rate.
4.4
Differential Clock DC and AC Levels
(0°C ≤ TC ≤ +85°C, VDD = +2.0 V ± 0.10 V, VDDQ = +2.0 V ± 0.10 V, see Table 1)
Table 35
Differential Clock DC and AC Input conditions
Symbol Limit Values
min.
Parameter
Unit Note
s
max.
Clock Input Mid-Point Voltage, CLK and CLK VMP(DC)
V
REF - 0.1
V
V
REF + 0.1
DDQ + 0.3
V
V
V
1
1
1
Clock Input Voltage Level, CLK and CLK
VIN(DC)
0.42
0.3
Clock DC Input Differential Voltage, CLK and VID(DC)
VDDQ
CLK
Clock AC Input Differential Voltage, CLK and VID(AC)
CLK
0.5
V
V
DDQ + 0.5
REF + 0.15
V
V
1, 2
1, 3
AC Differential Crossing Point Input Voltage VIX(AC)
VREF - 0.15
1. All voltages referenced to VSS
2. VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
3. The value of VIX is expected to equal 0.7 x VDDQ of the transmitting device and must track variations in the DC
level of the same.
Data Sheet
70
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Electrical Characteristics
4.5
Output Test Conditions
VDDQ
60 Ohm
Test point
DQ
DQS
Figure 53 Output Test Circuit
Note: VDDQ=2.0 ±0.1 V, Tc=0 °C to 85 °C, see Table 1
4.6
Pin Capacitances
Table 36
Capacitances
Parameter
Symbol
Min
Max
Unit
Notes
Input capacitance:
CLK, CLK
CCK
CDCK
CI
2.0
4.0
pF
Input capacitance delta:
CLK, CLK
0.1
4.0
0.6
4.5
pF
pF
pF
pF
1
Input capacitance:
A0-A11, BA0-1,CKE, CS, CAS, RAS, WE, CKE, RES
2.0
2.5
Input capacitance delta:
A0-A11, BA0-1,CKE, CS, CAS, RAS, WE, CKE, RES
DCI
CIO
1
2
Input capacitance:
DQ0-DQ31, RDQS0-RDQS3, WDQS0-WDQS3, DM0-
DM3
Input capacitance delta:
DCIO
0.6
pF
DQ0-DQ31, RDQS0-RDQS3, WDQS0-WDQS3, DM0-
DM3
1. The input capcitance per pin group will not differ by more than this maximum amount for any given device.
2. The IO capacitance per RDQS and DQ byte / group will not differ by more than this maximum amount for any
given device.
Data Sheet
71
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Electrical Characteristics
4.7
Driver current characteristics
4.7.1
Driver IV characteristics at 40 Ohms
Figure 54 represents the driver Pull-Down and Pull-Up IV characteristics under process, voltage and temperature
best and worst case conditions. The actual Driver Pull-Down and Pull-Up current must lie between these two
bounding curves. The value of the external ZQ resistor is 240Ω, setting the nominal driver output impedance to
40Ω.
Pull-Down Characterstics
Pull-Up Characterstics
50
45
40
35
30
25
20
15
10
5
0.0
0.5
1.0
1.5
2.0
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
0
0.0
0.5
1.0
1.5
2.0
Vout (V)
VDDQ - Vout (V)
Figure 54 40 Ohm Driver Pull-Down and Pull-Up characteristics
Table 37 lists the numerical values of the minimum and maximum allowed values of the output driver Pull-Down
and Pull-Up IV characteristics.
Table 37
Programmed Driver IV Characteristics at 40 Ohm
Pull-Down Current (mA)
Voltage (V)
Pull-Up Current (mA)
Minimum
-2.44
Minimum
2.32
Maximum
3.04
Maximum
-3.27
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
4.56
5.98
-4.79
-6.42
6.69
8.82
-7.03
-9.45
8.74
11.56
14.19
16.72
19.14
21.44
23.61
26.10
28.45
30.45
32.73
34.95
37.10
39.15
41.01
42.53
43.71
-9.18
-12.37
-15.17
-17.83
-20.37
-22.78
-25.04
-27.17
-29.17
-31.25
-33.00
-35.00
-37.00
-39.14
-41.25
-43.29
-45.23
10.70
12.56
14.34
16.01
17.61
19.11
20.53
21.92
23.29
24.65
26.00
27.35
28.70
-
-11.23
-13.17
-15.01
-16.74
-18.37
-19.90
.21.34
-22.72
-24.07
-25.40
-26.73
-28.06
-29.37
-
-
-
Data Sheet
72
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Electrical Characteristics
4.8
Termination IV Characteristic at 60 Ohms
Figure 55 represents the DQ termination Pull-Up IV characteristic under process, voltage and temperature best
and worst case conditions. The actual DQ termination Pull-Up current must lie between these two bounding
curves. The value of the external ZQ resistor is 240Ω, setting the nominal DQ termination impedance to 60Ω.
(Extended Mode Register programmed to ZQ/4).
60 Ohm Termination Characterstics
0.0
0.5
1.0
1.5
2.0
0
-5
-10
-15
-20
-25
-30
-35
VDDQ - Vout (V)
Figure 55 60 Ohm Active Termination Characteristic
Table 38 lists the numerical values of the minimum and maximum allowed values of the output driver termination
IV characteristic.
Table 38
Programmed Terminator Characterisitc at 60 Ohm
Voltage (V)
Terminator Pull-Up Current
(mA)
Voltage (V)
Terminator Pull-Up Current
(mA)
Minimum
Maximum
Minimum
-13.27
-14.23
-15.14
-16.04
-16.94
-17.82
-18.70
-19.58
-
Maximum
-18.11
-19.45
-20.83
-22.00
-23.33
-24.67
-26.09
-27.50
-28.86
-30.15
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
-1.63
-3.19
-4.69
-6.12
-7.49
-8.78
-10.01
-11.16
-12.25
-2.18
-4.28
-6.30
-8.25
-10.11
-11.89
-13.58
-15.19
-16.69
-
Data Sheet
73
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Electrical Characteristics
4.9
Termination IV Characteristic at 120 Ohms
Figure 56 represents the DQ or ADD/CMD termination Pull-Up IV characteristic under process, voltage and
temperature best and worst case conditions. The actual termination Pull-Up current must lie between these two
bounding curves. The value of the external ZQ resistor is 240Ω, setting the nominal termination impedance to
120Ω. (Extended Mode Register programmed to ZQ/2 for DQ terminations or CKE = 0 at the RES transition during
Power-Up for ADD/CMD terminations).
120 Ohm Termination Characterstics
0.0
0.5
1.0
1.5
2.0
0
-2
-4
-6
-8
-10
-12
-14
-16
VDDQ - Vout (V)
Figure 56 120 Ohm Active Termination Characteristic
Table 39 lists the numerical values of the minimum and maximum allowed values of the termination IV
characteristic.
Table 39
Programmed Terminator Characterisitics at 120 Ohm
Voltage(V)
Terminator Pull-Up Current
(mA)
Voltage (V)
Terminator Pull-Up Current
(mA)
Minimum
Maximum
Minimum
-6.63
-7.11
-7.57
-8.02
-8.47
-8.91
-9.35
-9.79
-
Maximum
-9.06
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
-0.81
-1.60
-2.34
-3.06
-3.74
-4.39
-5.00
-5.58
-6.12
-1.09
-2.14
-3.15
-4.12
-5.06
-5.94
-6.79
-7.59
-8.35
-9.72
-10.42
-11.00
-11.67
-12.33
-13.05
-13.75
-14.43
-15.08
-
Data Sheet
74
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Electrical Characteristics
4.10
Termination IV Characteristic at 240 Ohms
Figure 57 represents the ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature
best and worst case conditions. The actual ADD/CMD termination Pull-Up current must lie between these two
bounding curves. The value of the external ZQ resistor is 240Ω, setting the nominal termination impedance to
240Ω. (CKE = 1at the RES transition during Power-Up for ADD/CMD terminations).
240 Ohm Termination Characterstics
0.0
0.5
1.0
1.5
2.0
0.0
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0
-8.0
VDDQ - Vout (V)
Figure 57 240 Ohm Active Termination Characteristic
Table 40 lists the numerical values of the minimum and maximum allowed values of the ADD/CMD termination IV
characteristic.
Table 40
Programmed Terminator Characterisitc at 240 Ohm
Voltage (V)
Terminator Pull-Up Current
(mA)
Voltage (V)
Terminator Pull-Up Current
(mA)
Minimum
Maximum
Minimum
-3.32
-3.56
-3.79
-4.01
-4.23
-4.46
-4.68
-4.90
-
Maximum
-4.53
-4.86
-5.21
-5.50
-5.83
-6.17
-6.52
-6.88
-7.21
-7.54
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
-0.41
-0.80
-1.17
-1.53
-1.87
-2.20
-2.50
-2.79
-3.06
-0.55
-1.07
-1.58
-2.06
-2.53
-2.97
-3.40
-3.80
-4.17
-
Data Sheet
75
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Electrical Characteristics
4.11
Operating Currents
4.11.1
Operating Current Ratings
(0°C ≤ TC ≤ +85°C, VDD = +2.0 V ± 0.10 V, VDDQ = +2.0 V ± 0.10 V, see Table 1)
Table 41
Operating Current Ratings
Parameter
Symbol Limit Values
Unit
Notes
- 2.0
typ.
238
258
86
- 2.2
- 2.5
typ.
204
222
75
typ.
222
241
81
1)2)3)
1)2)3)
1)2)3)
1)2)3)
1)2)3)
1)2)3)
1)2)3)
1)2)3)
1)2)3)
1)2)3)
1)2)3)
1)2)3)4)
1)2)3)
Operating Current
IDD0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Operating Current
IDD1
Precharge Power-Down Standby Current
Precharge Floating Standby Current
Precharge Quiet Standby Current
Active Power-Down Standy Current
Active Standby Current
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
136
98
127
92
118
86
86
81
75
158
412
278
374
88
148
385
265
348
83
138
355
245
312
77
Operating Current Burst Read
Operating Current Burst Write
Auto-Refresh Current (tRC=min(tRFC))
Auto-Refresh Current at tREFI
Self Refresh Current
5
5
5
Operating Current
IDD7
548
509
460
1) IDD specifications are tested after the device is properly initialized.
2) Input slew rate = 2 V/ns.
3) Mesured with Output open and On Die termination off.
4) Enables on-chip refresh and address counter.
4.12
Operating Current Measurement Conditions
(0°C ≤ TC ≤ +85°C, VDD = +2.0V ± 0.10 V, VDDQ = +2.0 V ± 0.10 V, see Table 1)
Table 42
Symbol Parameter/Condition
IDD0 Operating Current - One bank, Activate - Precharge
tCK=min(tCK), tRC=min(tRC)
Operating Current Measurement Conditions
Databus inputs are SWITCHING; Address and control inputs are SWITCHING, CS = HIGH between
valid commands.
IDD1
Operating Current - One bank, Activate - Read - Precharge
One bank is accessed with tCK=min(tCK), tRC=min(tRC), CL = CL(min), Address and control inputs are
SWITCHING;
CS = HIGH between valid commands. Iout=0mA
IDD2P
IDD2F
Precharge Power-Down Standby Current
All banks idle, power-down mode, CKE is LOW, tCK=min(tCK), Data bus inputs are STABLE.
Precharge Floating Standby Current
All banks idle; CS is LOW, CKE is HIGH, tCK=min(tCK); Address and control inputs are SWITCHING;
Data bus input are STABLE.
Data Sheet
76
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Electrical Characteristics
Table 42
Symbol Parameter/Condition
Precharge Quiet Standby Current
Operating Current Measurement Conditions
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
CS is HIGH, all banks idle, CKE is HIGH, tCK=min(tCK), Address and other control inputs STABLE, Data
bus inputs are STABLE.
Active Power-Down Standby Current
All banks active, CKE is LOW, Address and control inputs are STABLE; Data bus inputs are STABLE;
standard active power-down mode.
Active Standby Current
All banks active, CS is HIGH, CKE is HIGH, tRC=max(tRAS), tCK=min(tCK); Address and control inputs
are SWITCHING; Data bus inputs are SWITCHING; Iout = 0 mA.
Operating Current - Burst Read
All banks active; Continuous read bursts, CL = CL(min); tCK=min(tCK); Address and control inputs are
SWITCHING; Data bus inputs are SWITCHING.
Operating Current - Burst Write
All banks active; Continuous write bursts; tCK=min(tCK); Address and control inputs are SWITCHING;
Data bus inputs are SWITCHING.
Burst Auto Refresh Current
Refresh command at tRC=min(tRFC); tCK=min(tCK); CKE is HIGH, CS is HIGH between all valid
commands; Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING.
Distributed Auto Refresh Current
tCK=tCKmin; Refresh command every tREFI; CKE is HIGH, CS is HIGH between valid commands;
Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING.
Self Refresh Current
CKE ≤ max(VIL), external clock off, CK and CK LOW; Address and control inputs are STABLE; Data
Bus inputs are STABLE.
IDD7
Operating Bank Interleave Read Current
1. All banks interleaving with CL = CL(min); tRCD = tRCDRD(min); tRRD = tRRD(min); Iout=0mA;
Address and control inputs are STABLE during DESELECT; Data bus inputs are SWITCHING.
2: Timing pattern:
-2.5 (400 MHz, CL=6) : tCK = 2.5ns, tRCDRD = 7. tCK; tRRD = 4. tCK; tRC = 18. tCK
Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D
-2.2 (455 MHz, CL6) : tCK = 2.2ns, tRCDRD = 7. tCK; tRRD = 4. tCK; tRC = 18. tCK
Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D
-2.0 (500 MHz, CL6) : tCK = 2.0ns, tRCDRD = 7. tCK; tRRD = 4. tCK; tRC = 18. tCK
Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D
1. Data Bus consists of DQ, DM, WDQS
2. Definitions for IDD : LOW is defined as VIN = 0.4 x VDDQ; HIGH is defined as VIN = VDDQ
STABLE is defined as inputs are stable at a HIGH level.
;
SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and
control signals, and inputs changing 50% of each data transfer for DQ signals.
3. Legend : A=Activate, RA=Read with Autoprecharge, D=DESELECT
Data Sheet
77
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Electrical Characteristics
4.13
Summary of timing parameters for –2.0 ns, –2.2 ns and –2.5 ns speed sorts in
DLL on mode
Table 43
Timing Parameters for –2.0, –2.2 and –2.5 speed sorts
Parameter
read
Sym- Limit Values
Unit Notes
latency bol
- 2.0
min
- 2.2
min
- 2.5
min
max
max
max
Clock and Clock Enable
Clock Cycle Time
7
tCK7
tCK6
tCK5
fCK7
fCK6
fCK5
tCH
2.0
4.0
4.0
—
2.2
4.0
2.5
4.0
ns
6
5
7
6
5
2.0
2.2
4.0
2.5
4.0
ns
—
2.7
4.0
3.0
4.0
ns
System frequency
250
250
—
500
500
—
250
250
250
0.45
0.45
0.45
455
455
370
0.55
0.55
—
250
250
250
0.45
0.45
0.45
400
400
333
0.55
0.55
—
MHz
MHz
MHz
tCK
Clock high level width
Clock low-level width
Minimum clock half period
0.45
0.45
0.45
0.55
0.55
—
tCL
tCK
tHP
tCK
1
Command and Address Setup and Hold Timing
Address/Command input setup time tIS
Address/Command input hold time tIH
0.75
—
—
—
0.75
0.75
0.85
—
—
—
0.85
0.85
0.85
—
—
—
ns
ns
tCK
0.75
0.85
Address/Command input pulse
width
tIPW
Mode Register Set Timing
Mode Register Set cycle time
tMRD
4
—
—
4
—
—
4
—
—
tCK
tCK
Mode Register Set to READ timing tMRDR 12
12
12
Row Timing
Row Cycle Time
Row Active Time
tRC
37.2
24.0
8.0
—
39.6
—
45.0
—
ns
tRAS
8 x tREFI 26.2
8 x tREFI 30.0
8 x tREFI ns
ACT(a) to ACT(b) Command period tRRD
—
–
8.8
—
–
10.0
15.0
17.5
—
—
—
ns
ns
ns
Row Precharge Time
tRP
13.2
13.2
17.5
Row to Column Delay Time for
Reads
tRCDRD 16.0
–
–
Row to Column Delay Time for
Writes
tRCDWR
tRCDWR(min) = tRCDRD(min) - (WL + 1) x tCK(min)
ns
Column Timing
CAS(a) to CAS(b) Command period tCCD
2
—
—
2
—
—
2
—
—
tCK
ns
2
3
4
Write to Read Command Delay
Read to Write command delay
tWTR
tRTW
6.0
6.6
7.5
tRTW(min)= (CL+4-WL)
tCK
Write Cycle Timing Parameters for Data and Data Strobe
Write command to first WDQS
latching transition
tDQSS WL - WL
WL - WL
WL - WL
tCK
0.25
+0.25
0.25
+0.25
0.25
+0.25
Data-in and Data Mask to WDQS
Setup Time
tDS
0.375
—
0.375
—
0.425
—
ns
Data Sheet
78
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Electrical Characteristics
Table 43
Timing Parameters for –2.0, –2.2 and –2.5 speed sorts
read Sym- Limit Values
latency bol
Parameter
Unit Notes
- 2.0
min
- 2.2
min
- 2.5
max
max
min
max
Data-in and Data Mask to WDQS
Hold Time
tDH
0.375
—
0.375
—
0.425
—
ns
Data-in and DM input pulse width
(each input)
tDIPW 0.45
—
0.45
—
0.45
—
tCK
DQS input low pulse width
DQS input high pulse width
DQS Write Preamble Time
DQS Write Postamble Time
Write Recovery Time
tDQSL 0.45
tDQSH 0.45
tWPRE 0.75
tWPST 0.75
—
0.45
0.45
0.75
0.75
11.0
—
0.45
0.45
0.75
0.75
12.5
—
tCK
tCK
tCK
tCK
ns
—
—
—
1.25
1.25
—
1.25
1.25
—
1.25
1.25
—
tWR
11.0
3
Read Cycle Timing Parameters for Data and Data Strobe
Data Access Time from Clock
Read Preamble
tAC
–0.4
0.4
–0.45 0.45
–0.5
0.75
0.75
0.5
ns
tCK
tCK
ns
tRPRE 0.75
tRPST 0.75
1.25
1.25
0.75
0.75
1.25
1.25
1.25
1.25
Read Postamble
Data-out high impedance time from tHZ
tAC
tAC
tAC
tAC
tAC
tAC
CLK
min
max
min
max
min
max
Data-out low impedance time from tLZ
CLK
tAC
min
tAC
max
tAC
min
tAC
max
tAC
min
tAC
max
ns
DQS edge to Clock edge skew
tDQSCK -0.4
+0.4
-0.45 +0.45
-0.5
+0.5
0.28
0.280
ns
ns
ns
ns
DQS edge to output data edge skew tDQSQ
—
0.225
0.225
—
0.25
—
Data hold skew factor
tQHS
tQH
0
0
0.250
0
Data output hold time from DQS
Refresh/Power Down Timing
Refresh Period (4096 cycles)
tHP–tQHS
tHP–tQHS
tHP–tQHS
tREF
—
32
—
—
32
—
—
32
—
ms
µs
Average periodic Auto Refresh
interval
tREFI 7.8
7.8
7.8
Delay from AREF to next ACT/
AREF
tRFC
54
54
54
ns
Self Refresh Exit time
tXSC
200
4
—
—
—
200
4
—
—
—
200
4
—
—
—
tCK
tCK
tCK
Precharge Power Down Exit time
Active Power Down Exit time
Other Timing Parameters
RES to CKE setup timing
RES to CKE hold timing
tXPN
t XARD
6
6
6
tATS
tATH
tKO
10
10
10
—
—
—
10
10
10
—
—
—
10
10
10
—
—
—
ns
ns
ns
Termination update Keep Out
timing
Rev. ID EMRS to DQ on timing
Rev. ID EMRS to DQ off timing
tRIDon
tRIDoff
—
—
20
20
—
—
20
20
—
—
20
20
ns
ns
1. tHP is the lesser of tCL minimum and tCH minimum actually applied to the device CLK, CLK inputs
2. tCCD is either for gapless consecutive reads or gapless consecutive writes.
3.
tWTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal
.
4. Please round up tRTW to the next integer of tCK.
Data Sheet
79
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Electrical Characteristics
4.14
AC Characteristics and Settings
The following tables are meant as a guideline to correctly set the most important timing parameters depending on
speed sort and clock frequency.
Table 44
HYB18T256321F–20
Frequency / tCK
CAS
Latency
tRC
tRFC
tRAS
tRP
tWR
tRRD
tRCDRD tRCDWR Unit
500 MHz / 2.0ns
455 MHz / 2.2ns
400 MHz / 2.5ns
370 MHz / 2.7ns
300 MHz / 3.0ns
266 MHz / 3.8ns
250MHZ / 4.0ns
7,6
7,6
5
19
17
16
14
13
11
10
27
25
22
20
18
15
14
12
11
10
9
7
6
6
5
5
4
4
6
5
5
5
4
3
3
4
4
4
3
3
3
2
8
8
7
6
6
5
4
5
5
4
4
4
3
3
tCK
tCK
tCK
tCK
tCK
tCK
tCK
5
5
8
5
7
5
6
Table 45
HYB18T256321F–22
Frequency / tCK
CAS
Latency
tRC
tRFC
tRAS
tRP
tWR
tRRD
tRCDRD tRCDWR Unit
455 MHz / 2.2ns
400 MHz / 2.5ns
370 MHz / 2.7ns
300 MHz / 3.0ns
266 MHz / 3.8ns
250MHZ / 4.0ns
7,6
7,6
5
18
17
15
14
11
11
25
22
20
18
15
14
12
11
10
9
6
6
5
5
4
4
5
5
5
4
3
3
4
4
4
3
3
3
8
7
7
6
5
5
5
5
5
4
3
3
tCK
tCK
tCK
tCK
tCK
tCK
5
5
7
5
7
Table 46
HYB18T256321F–25
Frequency / tCK
CAS
Latency
tRC
tRFC
tRAS
tRP
tWR
tRRD
tRCDRD tRCDWR Unit
400 MHz / 2.5ns
370 MHz / 2.7ns
300 MHz / 3.0ns
266 MHz / 3.8ns
250MHZ / 4.0ns
7,6
7,6
5
18
18
15
12
12
22
20
18
15
14
12
12
10
8
6
6
5
4
4
5
5
5
4
4
4
4
4
3
3
7
7
6
5
5
5
5
4
3
3
tCK
tCK
tCK
tCK
tCK
5
5
8
Data Sheet
80
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Package Outlines
5
Package Outlines
11.00 ± 0.10
BALL A1
INDICATOR
1.20 MAX
TOP VIEW
C
1
2
3
4
5
6
7
8
9 10 11 12
M
L
K
J
H
G
F
0.12
C
E
D
C
B
A
0.40
0.80 (11X)
BALLS VIEW
All dimensions in mm.
Figure 58 Package Outline FBGA
1. The package is conforming with JEDEC MO216
2. The inner matrix of 4x4 balls is reserved for thermal contacts
Data Sheet
81
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
HYB18T256321F–[20/22/25]
DDR SGRAM
Package Outlines
5.1
Package Thermal Characteristics
Table 47
P-FBGA 144 Package Thermal Resitances
Theta_jA
Theta_jB Theta_jC
JEDEC Board
Air Flow
K/W
1s0p
1 m/s
40.2
2s0p
1 m/s
23.5
0 m/s
48.8
3 m/s
35.1
0 m/s
27.0
3 m/s
22.0
-
-
6.0
3.9
1. Theta_jA : Junction to Ambient thermal resistance. The values have been obtained by simulation using the
conditions stated in the JEDEC JESD-51 standard.
2. Theta_jB : Junction to Board thermal resistance. The value has been obtained by simulation.
3. Theta_jC : Junction to Case thermal resistance. The value has been obtainned by simulation.
Data Sheet
82
Rev. 1.52, 06-2004
05142004-ZTTV-E1OQ
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
相关型号：
HYB18T256321F-25
DDR DRAM, 8MX32, 0.5ns, CMOS, PBGA144, 11 X 11 MM, ROHS COMPLIANT, PLASTIC, MO-216, TFBGA-144
INFINEON
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