HYB18T256400AF-25F [INFINEON]
DDR DRAM, 64MX4, 0.4ns, CMOS, PBGA60, GREEN, PLASTIC, TFBGA-60;
| 型号： | HYB18T256400AF-25F |
| 厂家： | 
Infineon |
| 描述： | DDR DRAM, 64MX4, 0.4ns, CMOS, PBGA60, GREEN, PLASTIC, TFBGA-60 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总120页 (文件大小：5164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.4, Aug. 2005
HYB18T256400AF(L)
HYB18T256800AF(L)
HYB18T256160AF(L)
256-Mbit DDR2 SDRAM
DDR2 SDRAM
RoHS Compliant Products
Memory Products
N e v e r s t o p t h i n k i n g .
Edition 2005-08
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
HYB18T256400AF(L) HYB18T256800AF(L) HYB18T256160AF(L)
Revision History: 2005-08, Rev. 1.4
Page
Subjects (major changes since last revision)
Added low-power components HYB18T256[40/80/16]0AFL-3.7
Added DDR2-800 5-5-5 components
92
Updated IDD Currents (IDD2P, IDD3P1, IDD6)
chapter 2 Updated Pin Configuration - various editorial changes on notes
Previous Version: 2005-07 Rev. 1.3
Added DDR2-800 components
Added DDR2-800 to speed grade dependant table-values
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Template: mp_a4_s_rev314 / 3 / 2005-05-02
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1
1.2
1.3
2
Pin Configuration and Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TFBGA Ball Out Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
256 Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1
2.2
2.3
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Programming the Mode Register and Extended Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DDR2 SDRAM Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DDR2 SDRAM Extended Mode Register Set EMR(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Output Disable (Qoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Single-ended and Differential Data Strobe Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Extended Mode Register EMR(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Extended Mode Register EMR(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Off-Chip Driver (OCD) Impedance Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Bank Activate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Read and Write Commands and Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Posted CAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Write Data Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Burst Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Read Followed by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Write followed by Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Auto-Precharge Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Read with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Write with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Read or Write to Precharge Command Spacing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Concurrent Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Auto-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Self-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
No Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Deselect Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Input Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Asynchronous CKE LOW Reset Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.22.1
3.22.2
3.23
3.23.1
3.23.2
3.23.3
3.23.4
3.24
3.24.1
3.24.2
3.25
3.26
3.26.1
3.26.2
3.27
3.28
4
Truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5
AC & DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1
5.2
Data Sheet
4
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Table of Contents
5.3
5.4
5.5
5.5.1
5.6
5.7
5.8
5.9
DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Full Strength Output V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Calibrated Output Driver V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Reduced Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Power & Ground Clamp V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6
IDD Measurement Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.1
6.1.1
I
DD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Speed Grade Defenitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.1
7.2
7.3
8
AC Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Reference Load for Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Slew Rate Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Input Slew Rate - Differential signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Input and Data Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Definition for Input Setup (tIS) and Hold Time (tIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Definition for Data Setup (tDS) and Hold Time (tDH), differential Data Strobes . . . . . . . . . . . . . . . 109
Definition Data Setup (tDS1) and Hold Time (tDH1), Single-Ended Data Strobes . . . . . . . . . . . . . . 110
Slew Rate Definition for Input and Data Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Setup (tIS) and Hold (tIH) Time Derating Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
9
10
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Product Namenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Data Sheet
5
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
List of Tables
Table 1
Performance for DDR2–800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Performance for DDR2–667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Performance for DDR2–400B and DDR2–533C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Configuration of DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
256-Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Mode Register Definition (BA[2:0] = 000B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Extended Mode Register Definition (BA[2:0] = 001B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Single-ended and Differential Data Strobe Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . . 33
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . . 34
Off Chip Driver Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Off-Chip-Driver Adjust Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
ODT Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Bank Selection for Precharge by Address Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Minimum Command Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Command Delay Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Differential DC and AC Input and Output Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SSTL_18 Output DC Current Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SSTL_18 Output AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
OCD Default Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Full Strength Default Pull-up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Full Strength Default Pull–down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Full Strength Calibrated Pull-down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Full Strength Calibrated Pull-up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Reduced Strength Default Pull-up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Reduced Strength Default Pull–down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Power & Ground Clamp V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . 89
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . 89
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
I
DD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
I
I
I
DD Specification for HYB18T256xxxAF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
DD Measurement Test Condition for DDR2–800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
DD Measurement Test Conditions for DDR2–667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
IDD Measurement Test Condition for DDR2–533C and DDR2–400B . . . . . . . . . . . . . . . . . . . . . . 94
ODT current per terminated input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Speed Grade Definition Speed Bins DDR2-800. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Speed Grade Definition Speed Bins for DDR2–667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Data Sheet
6
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
List of Tables
Table 54
Table 55
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Speed Grade Definition Speed Bins for DDR2-533C and DDR2-400B . . . . . . . . . . . . . . . . . . . . . 97
Timing Parameter by Speed Grade - DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Timing Parameter by Speed Grade - DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Timing Parameter by Speed Grade - DDR2-533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Timing Parameter by Speed Grade - DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
ODT AC Electrical Characteristics and Operating Conditions for DDR2-667 and DDR2-800 . . . 107
ODT AC Electrical Characteristics and Operating Conditions for DDR2-533 and DDR2-400 . . . 107
Derating Values for Input Setup and Hold Time (DDR2-667 & DDR2-800) . . . . . . . . . . . . . . . . 113
Derating Values for Input Setup and Hold Time (DDR2-400 & DDR2-533) . . . . . . . . . . . . . . . . 114
Derating Values for Data Setup and Hold Time of Differential DQS (DDR2-667 & DDR2-800) . 115
Derating Values for Data Setup and Hold Time of Differential DQS (DDR2-400 & -533) . . . . . . 116
Derating Values for Data Setup and Hold Time of Single-ended DQS (DDR2-400 & -533) . . . . 116
Nomenclature Fields and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
DDR2 Memory Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Data Sheet
7
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Pin Configuration for ×4 components, P-TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin Configuration for ×8 components, P-TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin Configuration for ×16 components, P-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Block Diagram 16 Mbit ×4 I/O ×4 Internal Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block Diagram 8 Mbit ×8 I/O ×4 Internal Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block Diagram 4 Mbit ×16 I/O ×4 Internal Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Initialization Sequence after Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
OCD Impedance Adjustment Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10 Timing Diagram Adjust Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11 Timing Diagram Drive Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12 Functional Representation of ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13 ODT Timing for Active and Standby (Idle) Modes (Synchronous ODT timings). . . . . . . . . . . . . . . 40
Figure 14 ODT Timing for Precharge Power-Down and Active Power-Down Mode. . . . . . . . . . . . . . . . . . . . 40
Figure 15 ODT Mode Entry Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 16 ODT Mode Exit Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 17 Bank Activate Command Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 18 Read Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 19 Activate to Read Timing Example: Read followed by a write to the same bank. . . . . . . . . . . . . . . 45
Figure 20 Read to Write Timing Example: Read followed by a write to the same bank . . . . . . . . . . . . . . . . . 45
Figure 21 Read to Write Timing Example: Read followed by a write to the same bank . . . . . . . . . . . . . . . . . 46
Figure 22 Read to Write Timing Example: Read followed by a write to the same bank . . . . . . . . . . . . . . . . . 46
Figure 23 Write to Read Timing Example: Write followed by a read to the same bank . . . . . . . . . . . . . . . . . 46
Figure 24 Basic Read Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 25 Read Operation Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 26 Read Operation Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 27 Read followed by Write Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 28 Seamless Read Operation Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 29 Seamless Read Operation Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 30 Basic Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 31 Write Operation Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 32 Write Operation Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 33 Write followed by Read Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 34 Seamless Write Operation Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 35 Seamless Write Operation Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 36 Write Data Mask Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 37 Write Operation with Data Mask Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 38 Read Interrupt Timing Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 39 Write Interrupt Timing Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 40 Read Operation Followed by Precharge Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 41 Read Operation Followed by Precharge Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 42 Read Operation Followed by Precharge Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 43 Read Operation Followed by Precharge Example 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 44 Read Operation Followed by Precharge Example 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 45 Write followed by Precharge Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 46 Write followed by Precharge Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 47 Read with Auto-Precharge Example 1, followed by an Activation to the Same Bank (tRC Limit) . . 61
Figure 48 Read with Auto-Precharge Example 2, followed by an Activation to the Same Bank (tRAS Limit) . 61
Figure 49 Read with Auto-Precharge Example 3, followed by an Activation to the Same Bank . . . . . . . . . . 62
Figure 50 Read with Auto-Precharge Example 4, followed by an Activation to the Same Bank, . . . . . . . . . . 62
Figure 51 Write with Auto-Precharge Example 1 (tRC Limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 52 Write with Auto-Precharge Example 2 (WR + tRP Limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 53 Auto Refresh Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Data Sheet
8
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
List of Figures
Figure 54 Self Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 55 Active Power-Down Mode Entry and Exit after an Activate Command . . . . . . . . . . . . . . . . . . . . . 68
Figure 56 Active Power-Down Mode Entry and Exit Example after a Read Command . . . . . . . . . . . . . . . . . 69
Figure 57 Active Power-Down Mode Entry and Exit Example after a Write Command . . . . . . . . . . . . . . . . . 69
Figure 58 Active Power-Down Mode Entry and Exit Example after a Write Command with AP. . . . . . . . . . . 70
Figure 59 Precharge Power Down Mode Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 60 Auto-Refresh command to Power-Down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 61 MRS, EMRS command to Power-Down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 62 Input Frequency Change Example during Precharge Power-Down mode. . . . . . . . . . . . . . . . . . . 72
Figure 63 Asynchronous Low Reset Event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 64 Single-ended AC Input Test Conditions Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 65 Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 66 Full Strength Default Pull-up Driver Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 67 Full Strength Default Pull–down Driver Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 68 Reduced Strength Default Pull-up Driver Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 69 Reduced Strength Default Pull–down Driver Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 70 AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 71 AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins. . . . . . . . . . . . . . . . 89
Figure 72 Reference Load for Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 73 Input Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 74 Data Setup and Hold Time (Differential Data Strobes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 75 Data Setup and Hold Time (Single Ended Data Strobes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 76 Slew Rate Definition Nominal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 77 Slew Rate Definition Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 78 Package Pinout PG-TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 79 Package Pinout PG-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Data Sheet
9
Rev. 1.4, 2005-08
09112003-LZPT-I17F
256-Mbit DDR2 SDRAM
DDR2 SDRAM
HYB18T256400AF(L)
HYB18T256800AF(L)
HYB18T256160AF(L)
1
Overview
This chapter gives an overview of the 256-Mbit DDR2 SDRAM product family and describes its main
characteristics.
1.1
Features
The 256-Mbit DDR2 SDRAM offers the following key features:
•
•
•
1.8 V ± 0.1 V Power Supply
•
Commands entered on each positive clock edge,
data and data mask are referenced to both edges of
DQS
1.8 V ± 0.1 V (SSTL_18) compatible I/O
DRAM organisations with 4, 8 and 16 data
in/outputs
•
•
Data masks (DM) for write data
Double Data Rate architecture: two data transfers
per clock cycle, four internal banks for concurrent
operation
CAS Latency: (2), 3, 4, 5 and 6
Burst Length: 4 and 8
All speed grades faster than DDR2–400 comply
with DDR2–400 timing specifications
Differential clock inputs (CK and CK)
Bi-directional, differential data strobes (DQS and
DQS) are transmitted / received with data. Edge
aligned with read data and center-aligned with write
data.
DLL aligns DQ and DQS transitions with clock
DQS can be disabled for single-ended data strobe
operation
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver impedance adjustment (OCD) and
On-Die-Termination (ODT) for better signal quality.
Auto-Precharge operation for read and write bursts
Auto-Refresh, Self-Refresh and power saving
Power-Down modes
•
•
•
•
•
•
•
•
•
•
•
Average Refresh Period 7.8 µs
Full and reduced Strength Data-Output Drivers
1KByte Page Size for ×4 & ×8, 2KByte Page Size
for ×16
•
•
Packages: P-TFBGA-60 for ×4 & ×8 components,
P-TFBGA-84 for ×16 components
•
•
RoHS Compliant Products1)
Table 1
Performance for DDR2–800
Product Type Speed Code
Speed Grade
–25F
DDR2–800 5–5–5
–2.5
Unit
—
DDR2–800 6–6–6
max. Clock Frequency @CL6 fCK6 400
@CL5 fCK5 400
400
333
266
200
15
15
45
60
MHz
MHz
MHz
MHz
ns
ns
ns
ns
@CL4 fCK4 266
@CL3 fCK3 200
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
tRCD 12.5
tRP 12.5
tRAS 45
tRC 57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and
polybrominated biphenyl ethers.
Data Sheet
10
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Overview
Table 2
Performance for DDR2–667
Product Type Speed Code
Speed Grade
–3
–3S
Unit
—
DDR2–667 4–4–4
DDR2–667 5–5–5
max. Clock Frequency @CL5 fCK5 333
@CL4 fCK4 333
333
266
200
15
15
45
MHz
MHz
MHz
ns
ns
ns
@CL3 fCK3 200
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
tRCD 12
tRP 12
tRAS 45
tRC 57
60
ns
Table 3
Performance for DDR2–400B and DDR2–533C
Product Type Speed Code
Speed Grade
–3.7
–5
Unit
—
DDR2–533 4–4–4
DDR2–400 3–3–3
max. Clock Frequency @CL5 fCK5 266
@CL4 fCK4 266
200
200
200
15
15
40
MHz
MHz
MHz
ns
ns
ns
@CL3 fCK3 200
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
tRCD 15
tRP 15
tRAS 45
tRC 60
55
ns
1.2
Description
The 256-Mbit DDR2 DRAM is a high-speed Double- All of the control and address inputs are synchronized
Data-Rate-Two CMOS Synchronous DRAM device with a pair of externally supplied differential clocks.
containing 268,435,456 bits and internally configured Inputs are latched at the cross point of differential
as a quad-bank DRAM. The 256-Mbit device is clocks (CK rising and CK falling). All I/Os are
organized as either 16 Mbit × 4 I/O × 4 banks, 8 Mbit × 8 synchronized with a single ended DQS or differential
I/O × 4 banks or 4 Mbit × 16 I/O × 4 banks chip. These DQS-DQS pair in a source synchronous fashion.
synchronous devices achieve high speed transfer rates
starting at 400 Mbit/sec/pin for general applications.
See Table 1, Table 2 and Table 3 for performance
figures.
The device is designed to comply with all DDR2 DRAM
key features:
A 15 bit address bus is used to convey row, column and
bank address information in a RAS-CAS multiplexing
style.
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is
provided along with various power-saving power-down
modes.
1. posted CAS with additive latency,
The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
The DDR2 SDRAM is available in P-TFBGA-60 and P-
TFBGA-84 package.
2. write latency = read latency - 1,
3. normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
Data Sheet
11
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Overview
1.3
Ordering Information
Table 4
Part Number
Ordering Information for RoHS compliant products
Org Speed
CAS1)RCD2)RP3) Clock CAS1)RCD2)RP3) Clock Package
.
Latencies
(MHz) Latencies
(MHz)
HYB18T256400AF–2.5 ×4 DDR2–800 6–6–6
HYB18T256800AF–2.5 ×8
HYB18T256160AF–2.5 ×16
400
400
333
333
266
266
200
5–5–5
4–4–4
3–3–3
4–4–4
3–3–3
3–3–3
—
333
P-TFBGA-60
P-TFBGA-84
P-TFBGA-60
HYB18T256400AF–25F ×4
HYB18T256800AF–25F ×8
HYB18T256160AF–25F ×16
5–5–5
333
200
266
200
200
—
P-TFBGA-84
P-TFBGA-60
HYB18T256400AF–3
HYB18T256800AF–3
HYB18T256160AF–3
×4 DDR2–667 4–4–4
×8
×16
P-TFBGA-84
P-TFBGA-60
HYB18T256400AF–3S ×4
HYB18T256800AF–3S ×8
HYB18T256160AF–3S ×16
5–5–5
P-TFBGA-84
P-TFBGA-60
HYB18T256400AF–3.7 ×4 DDR2–533 4–4–4
HYB18T256800AF–3.7 ×8
HYB18T256160AF–3.7 ×16
P-TFBGA-84
P-TFBGA-60
HYB18T256400AFL–3.7 ×4
HYB18T256800AFL–3.7 ×8
HYB18T256160AFL–3.7 ×16
4–4–4
P-TFBGA-84
P-TFBGA-60
HYB18T256400AF–5
HYB18T256800AF–5
HYB18T256160AF–5
×4 DDR2–400 3–3–3
×8
×16
P-TFBGA-84
1) CAS: Column Adress Strobe
2) RCD: Row Column Delay
3) RP: Row Precharge
Note:For product nomenclature see Chapter 10 of this data sheet
Data Sheet
12
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
2
Pin Configuration and Block Diagrams
The pin configuration of a DDR2 SDRAM is listed by function in Table 5. The abbreviations used in the Pin# and
Buffer Type columns are explained in Table 6 and Table 7 respectively. The pin numbering for the FBGA package
is depicted in Figure 1 for ×4, Figure 2 for ×8 and Figure 3 for ×16.
Table 5
Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals ×4/×8 organizations
E8
CK
I
SSTL
Clock Signal CK, Complementary Clock Signal CK
F8
CK
I
SSTL
Note: CK and CK are differential system clock inputs. All address
and control inputs are sampled on the crossing of the
positive edge of CK and negative edge of CK. Output (read)
data is referenced to the crossing of CK and CK (both
direction of crossing)
F2
CKE
I
SSTL
Clock Enable
Note: CKE HIGH activates and CKE LOW deactivates internal
clock signals and device input buffers and output drivers.
Taking CKE LOW provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-
Down (row Active in any bank). CKE is synchronous for
power down entry and exit and for self-refresh entry. Input
buffers excluding CKE are disabled during self-refresh.
CKE is used asynchronously to detect self-refresh exit
condition. Self-refresh termination itself is synchronous.
After VREF has become stable during power-on and
initialisation sequence, it must be maintained for proper
operation of the CKE receiver. For proper self-refresh entry
and exit, VREF must be maintained to this input. CKE must
be maintained HIGH throughout read and write accesses.
Input buffers, excluding CK, CK, ODT and CKE are disabled
during power-down
Clock Signals ×16 organization
J8
K8
K2
CK
CK
CKE
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Note: See functional description in x4/x8 organization
Clock Enable
Note: See functional description in x4/x8 organization
Control Signals ×4/×8 organizations
F7
G7
F3
RAS
CAS
WE
I
I
I
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Note: RAS, CAS and WE (along with CS) define the command
being entered.
Data Sheet
13
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Table 5
Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
G8
CS
I
SSTL
Chip Select
Note: All command are masked when CS is registered HIGH. CS
provides for external rank selection on systems with
multiple memory ranks. CS is considered part of the
command.
Control Signals ×16 organization
K7
L7
K3
L8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
CS
Chip Select
Address Signals ×4/×8 organizations
G2
BA0
I
SSTL
Bank Address Bus 1:0
G3
BA1
I
SSTL
Note: BA[1:0] define to which bank an Activate, Read, Write or
Precharge command is being applied. BA[1:0] also
determines which (extended) mode register is to be
accessed during a (E)MRS cycle
H8
H3
H7
J2
J8
J3
A0
A1
A2
A3
A4
A5
A6
A7
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Signal 12:0, Address Signal 10/Autoprecharge
Note: Address Signal 10/Autoprecharge provides the row address
for Activate commands and the column address and Auto-
Precharge bit A10 (=AP) for Read/Write commands to
select one location out of the memory array in the respective
bank. A10 (=AP) is sampled during a Precharge command
to determine whether the Precharge applies to one bank
(A10=LOW) or all banks (A10=HIGH). If only one bank is to
be precharged, the bank is selected by BA[1:0]. The
address inputs also provide the register value during Mode
Register Set commands.
J7
K2
K8
K3
H2
A8
A9
A10
AP
A11
A12
A13
K7
L2
L8
Address Signal 13
Note: x4/x8 512 Mbit components
NC
–
–
Note: 256 Mbit components and x16 512 Mbit components
Address Signals ×16 organization
L2
L3
L1
BA0
BA1
NC
I
I
–
SSTL
SSTL
–
Bank Address Bus 1:0
Data Sheet
14
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Table 5
Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Signal 12:0, Address Signal 10/Autoprecharge
P7
R2
Data Signals ×4/×8 organizations
C8
C2
D7
D3
DQ0
DQ1
DQ2
DQ3
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Signal 3:0
Note: Bi-directional data bus. DQ[3:0] for ×4 components, DQ[7:0]
for ×8 components
Data Signals ×8 organization
D1
D9
B1
B9
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Signal 7:4
Data Signals ×16 organization
Data Sheet
15
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Table 5
Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal 15:0
Note: Bi-directional data bus. DQ[15:0] for ×16 components
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Data Strobe ×4/×8 organisations
B7
A8
DQS
DQS
I/O
I/O
SSTL
SSTL
Data Strobe
Note: Output with read data, input with write data. Edge aligned
with read data, centered with write data. LDQS corresponds
to the data on DQ[7:0]; UDQS corresponds to the data on
DQ[15:8]. The datastrobes DQS, LDQS, UDQS may be
used in single ended mode or paired with the optional
complementary signals DQS, LDQS, UDQS to provide
differential pair signaling to the system during both reads
and writes. An EMRS(1) control bit enables or disables the
complementary data strobe signals. For x8 components to
switch from bidirectional to unidirectional is supported and
selected by EMRS(1) control bit.
Data Strobe ×8 organisations
B3
A2
RDQS
RDQS
O
O
SSTL
SSTL
Read Data Strobe
Note: RDQS and RDQS are optional to be enabled by EMRS(1)
control bits. see functional description of DM and DQS pins.
Although RDQS/RDQS pins are output only the loading
matches the DQ and DQS loading.
Data Strobe ×16 organization
B7
A8
F7
E8
UDQS
UDQS
LDQS
LDQS
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Strobe Upper Byte
Note: UDQS corresponds to the data on DQ[15:8]
Data Strobe Lower Byte
Note: LDQS corresponds to the data on DQ[7:0]
Data Mask ×4/×8 organizations
Data Sheet
16
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Table 5
Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
B3
DM
I
SSTL
Data Mask
Note: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH coincident with that
input data during a write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading. For ×8
components the data mask function is disabled, if
RDQS/RDQS are enabled by EMRS(1) command.
Data Mask ×16 organization
B3
F3
UDM
LDM
I
I
SSTL
SSTL
Data Mask Upper/Lower Byte
Note: LDM and UDM are the input mask signals for ×16
components and control the lower or upper bytes.
Power Supplies ×4/×8/×16 organizations
A9,C1,C3,C7, VDDQ
C9
PWR
–
I/O Driver Power Supply
A1
VDD
PWR
PWR
–
–
Power Supply
I/O Driver Power Supply
A7,B2,B8,D2, VSSQ
D8
A3,E3
VSS
PWR
–
Power Supply
Power Supplies ×4/×8 organizations
E2
E1
E9,H9,L1
E7
J1,K9
VREF
VDDL
VDD
VSSDL
VSS
AI
–
–
–
–
–
I/O Reference Voltage
Power Supply
Power Supply
Power Supply
Power Supply
PWR
PWR
PWR
PWR
Power Supplies ×16 organization
J2
VREF
VDDQ
AI
PWR
–
–
I/O Reference Voltage
I/O Driver Power Supply
E9, G1, G3,
G7, G9
J1
VDDL
PWR
PWR
PWR
–
–
–
Power Supply
Power Supply
I/O Driver Power Supply
E1, J9, M9, R1 VDD
E7, F2, F8, H2, VSSQ
H8
J7
J3,N1,P9
VSSDL
VSS
PWR
PWR
–
–
Power Supply
Power Supply
Not Connected ×4/×8 organizations
G1, L3,L7, L8 NC
NC
–
Not Connected
Note: No internal electrical connection is present
Not Connected ×4 organization
A2, B1, B9,
D1, D9
NC
NC
–
Not Connected
Not Connected ×16 organization
Data Sheet
17
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Table 5
Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
A2, E2, L1, R3, NC
R7, R8
NC
–
Not Connected
Other Pins ×4/×8 organizations
F9 ODT
I
SSTL
On-Die Termination Control
Note: ODT (registered HIGH) enables termination resistance
internal to the DDR2 SDRAM. When enabled, ODT is
applied to each DQ, DQS, DQS and DM signal for ×4 and
DQ, DQS, DQS, RDQS, RDQS and DM for ×8
configurations. For ×16 configuration ODT is applied to
each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM
signal. An EMRS(1) control bit enables or disables the ODT
functionality.
Other Pins ×16 organization
K9
ODT
I
SSTL
On-Die Termination Control
Table 6
Abbreviations for Pin Type
Abbreviation
Description
I
O
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
I/O
AI
PWR
GND
NC
Ground
Not Connected
Table 7
Abbreviation
SSTL
LV-CMOS
CMOS
Abbreviations for Buffer Type
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
Data Sheet
18
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
2.1
TFBGA Ball Out Diagrams
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Figure 1
Notes
Pin Configuration for ×4 components, P-TFBGA-60 (top view)
2. Ball position L8 is A13 for 512-Mbit and is Not
Connected on 256-Mbit
1. VDDL and VSSDL are power and ground for the
DLL.They are isolated on the device fromVDD,
V
DDQ, VSS, and VSSQ
Data Sheet
19
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
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Figure 2
Notes
Pin Configuration for ×8 components, P-TFBGA-60 (top view)
4. VDDL and VSSDL are power and ground for the DLL.
They are isolated on the device from VDD, VDDQ
,
1. RDQS / RDQS are enabled by EMRS(1) command.
2. If RDQS / RDQS is enabled, the DM function is
disabled
3. When enabled, RDQS & RDQS are used as strobe
signals during reads.
V
SS and VSSQ.
5. Ball position L8 is A13 for 512-Mbit and is Not
Connected on 256-Mbit.
Data Sheet
20
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
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Notes
Pin Configuration for ×16 components, P-TFBGA-84 (top view)
2. LDM is the data mask signal for DQ[7:0], UDM is the
data mask signal for DQ[15:8]
1. UDQS/UDQS is data strobe for DQ[15:8],
LDQS/LDQS is data strobe for DQ[7:0]
3. VDDL and VDDSL are power and ground for the DLL.
They are isolated on the device from VDD, VDDQ
,
V
SS and VSSQ.
Data Sheet
21
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
2.2
256 Mbit DDR2 Addressing
Table 8
256-Mbit DDR2 Addressing
Configuration
Bank Address
Number of Banks
Auto-Precharge
Row Address
Column Address
Number of Column
Address Bits
64-Mbit x 4
BA[1:0]
4
A10 / AP
A[12:0]
A11, A[9:0]
11
32-Mbit x 8
BA[1:0]
4
A10 / AP
A[12:0]
A[9:0]
16-Mbit x 16
BA[1:0]
4
A10 / AP
A[12:0]
A[8:0]
Notes
1)
10
9
2)
3)
Number of I/Os
Page Size [Bytes]
4
8
16
1024 (1K)
1024 (1K)
1024 (1K)
1) Refered to as ’colbits’
2) Refered to as ’org’
3) PageSize = 2colbits× org/8 [Bytes]
Data Sheet
22
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
2.3
Block Diagrams
/$4 #ONTROL
2ECEIVERS
$RIVERS
2EAD ,ATCH
2OWꢃ!DDRESS -58
2EFRESH #OUNTER
!DDRESS 2EGISTER
-0"4ꢀꢁꢂꢀ
Figure 4
Notes
Block Diagram 16 Mbit ×4 I/O ×4 Internal Memory Banks
device; it does not represent an actual circuit
implementation.
3. LDM, UDM is a unidirectional signal (input only), but
is internally loaded to match the load of the
bidirectional LDQS and UDQS signals.
1. 64Mb × 4 Organisation with 13 Row, 2 Bank and 11
Column External Adresses
2. This Functional Block Diagram is intended to
facilitate user understanding of the operation of the
Data Sheet
23
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
/$4 #ONTROL
2ECEIVERS
$RIVERS
2EAD ,ATCH
2OWꢃ!DDRESS -58
2EFRESH #OUNTER
!DDRESS 2EGISTER
-0"4ꢀꢁꢂꢀ
Figure 5
Notes
Block Diagram 8 Mbit ×8 I/O ×4 Internal Memory Banks
device; it does not represent an actual circuit
implementation.
3. LDM, UDM is a unidirectional signal (input only), but
is internally loaded to match the load of the
bidirectional LDQS and UDQS signals.
1. 32Mb × 8 Organisation with 13 Row, 2 Bank and 10
Column External Adresses
2. This Functional Block Diagram is intended to
facilitate user understanding of the operation of the
Data Sheet
24
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
/$4 #ONTROL
2ECEIVERS
$RIVERS
2EAD ,ATCH
2OWꢃ!DDRESS -58
2EFRESH #OUNTER
!DDRESS 2EGISTER
-0"4ꢀꢁꢂꢀ
Figure 6
Notes
Block Diagram 4 Mbit ×16 I/O ×4 Internal Memory Banks
device; it does not represent an actual circuit
implementation.
3. LDM, UDM is a unidirectional signal (input only), but
is internally loaded to match the load of the
bidirectional LDQS and UDQS signals.
1. 16Mb × 16 Organisation with 13 Row, 2 Bank and 9
Column External Adresses
2. This Functional Block Diagram is intended to
facilitate user understanding of the operation of the
Data Sheet
25
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3
Functional Description
3.1
Simplified State Diagram
#+%,
)NITIALIZATION
3EQUENCE
3ELF
2EFRESH
/#$
CALIBRATION
32&
#+%(
02
3ETTING
-23 OR
%-23
)DLE
!LL BANKS
PRECHARGED
ꢃ%ꢄ-23
2%&
2EFRESHING
#+%,
#+%,
#+%(
!#4
0RECHARGE
0OWER
$OWN
!CTIVATING
#+%,
#+%,
#+%,
!CTIVE 0OWER
$OWN
#+%(
#+%,
!UTOMATIC 3EQUENCE
#OMMAND 3EQUENCE
"ANK
!CTIVE
7RITE
2EAD
7RITE
2EAD
72!
2$!
2EAD
7RITING
2EADING
7RITE
72!
2$!
72!
2$!
02ꢂ02!
7RITING
WITH !0
2EADING WITH
!0
02ꢂ02!
02ꢂ02!
0RECHARGING
-0&4ꢀꢀꢁꢀ
Figure 7
Simplified State Diagram
Note:This Simplified State Diagram is intended to
provide a floorplan of the possible state
bank, enabling / disabling on-die termination,
Power-Down entry / exit, timing restrictions
during state transitions - among other things - are
not captured in full detail.
transitions and the commands to control them. In
particular situations involving more than one
Data Sheet
26
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.2
Basic Functionality
Read and write accesses to the DDR2 SDRAM are address bits registered coincident with the Read or
burst oriented; accesses start at a selected location Write command are used to select the starting column
and continue for the burst length of four or eight in a location for the burst access and to determine if the
programmed sequence. Accesses begin with the Auto-Precharge command is to be issued. Prior to
registration of an Activate command, which is followed normal operation, the DDR2 SDRAM must be
by a Read or Write command. The address bits initialized. The following sections provide detailed
registered coincident with the activate command are information covering device initialization, register
used to select the bank and row to be accessed.The definition, command description and device operation.
3.3
Power On and Initialization
DDR2 SDRAM’s must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below
0.2 × VDDQ and ODT at a low state (all other inputs
may be undefined). To guarantee ODT off, VREF
must be valid and a low-level must be applied to the
ODT pin. Maximum power up interval for VDD / V
DDQ is specified as 20.0 ms. The power interval is
defined as the amount of time it takes for VDD / V
DDQ to power-up from 0 V to 1.8 V ± 100 mV. At least
one of these two sets of conditions must be met:
– VDD, VDDL and VDDQ are driven from a single
power converter output, AND
3. Apply NOP or Deselect commands and take CKE
high.
4. Continue NOP or Deselect Commands for 400 ns,
then issue a Precharge All command.
5. Issue EMRS(2) command.
6. Issue EMRS(3) command.
7. Issue EMRS(1) command to enable DLL.
8. Issue a MRS command for “DLL reset”.
9. Issue Precharge-all command.
10. Issue 2 or more Auto-refresh commands.
11. Issue the final MRS command to turn the DLL on
and to set the necessary operating parameter.
12. At least 200 clocks after step 8, issue EMRS(1)
commands to either execute the OCD calibration or
select the OCD default. Issue the final EMRS(1)
command to exit OCD calibration mode and set the
necessary operating parameters.
– VTT is limited to 0.95 V max, AND
– VREF tracks VDDQ/2
or
– Apply VDD before or at the same time as VDDL.
–
Apply VDDL before or at the same time as VDDQ.
–
Apply VDDQ before or at the same time as VTT & V
.
13. The DDR2 SDRAM is now ready for normal
operation.
REF
2. Start clock (CK, CK) and maintain stable power and
clock condition for a minimum of 200 µs.
tCHtCL
CK
/CK
tIS
tIS
CKE
ODT
ANY
PRE
ALL
PRE
ALL
NOP
EMRS
MRS
REF
MRS
EMRS
REF
Command
EMRS
CMD
tRFC
tRP
tMRD
tRFC
tMRD
tMRD
400ns
tRP
Follow OCD
Flowchart
tOIT
min 200 Cycle
DLL
RESET
DLL
OCD
OCD
CAL. MODE
EXIT
ENABLE
Default
Figure 8
Initialization Sequence after Power up
Data Sheet
27
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.4
Programming the Mode Register and Extended Mode Registers
For application flexibility, burst length, burst type, CAS may begin. All banks must be in a precharged state and
latency, DLL reset function, write recovery time (WR) CKE must be high at least one cycle before the Mode
are user defined variables and must be programmed Register Set Command can be issued. Either MRS or
with
a
Mode Register Set (MRS) command. EMRS Commands are activated by the low signals of
Additionally, DLL disable function, additive CAS CS, RAS, CAS and WE at the positive edge of the
latency, driver impedance, On Die Termination (ODT), clock.When bothbank addresses BA[1:0] are 0, the
single-ended strobe and Off Chip Driver impedance DDR2 SDRAM enables the MRS command. When the
adjustment (OCD) are also user defined variables and bank addresses BA0 is 1 and BA1 is 0, the DDR2
must be programmed with an Extended Mode Register SDRAM enables the EMRS(1) command. The address
Set (EMRS) command. Contents of the Mode Register input data during this cycle defines the parameters to
(MR) or Extended Mode Registers (EMR(1, 2, 3)) can be set as shown in the MRS and EMRS tables. A new
be altered by re-executing the MRS and EMRS command may be issued after the mode register set
Commands. If the user chooses to modify only a subset command cycle time (tMRD). MRS, EMRS and DLL
of the MR or EMR variables, all variables must be Reset do not affect array contents, which means
redefined when the MRS or EMRS commands are reinitialization including those can be executed any
issued. After initial power up, all MRS and EMRS time after power-up without affecting array contents.
Commands must be issued before read or write cycles
Data Sheet
28
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.5
DDR2 SDRAM Mode Register Set (MRS)
The mode register stores the data for controlling the command and clock cycle requirements during normal
various operating modes of DDR2 SDRAM. It programs operation as long as all banks are in the precharged
CAS latency, burst length, burst sequence, test mode, state. The mode register is divided into various fields
DLL reset, Write Recovery (WR) and various vendor depending on functionality. Burst length is defined by
specific options to make DDR2 SDRAM useful for A[2:0] with options of 4 and 8 bit burst length. Burst
various applications. The default value of the mode address sequence type is defined by A3 and CAS
register is not defined, therefore the mode register must latency is defined by A[6:4]. A7 is used for test mode
be written after power-up for proper operation. The and must be set to 0 for normal DRAM operation. A8 is
mode register is written by asserting low on CS, RAS, used for DLL reset. A[11:9] are used for write recovery
CAS, WE, BA[1:0], while controlling the state of time (WR) definition for Auto-Precharge mode. With
address pins A[12:0]. The DDR2 SDRAM should be in address bit A12 two Power-Down modes can be
all bank precharged (idle) mode with CKE already high selected, a “standard mode” and a “low-power” Power-
prior to writing into the mode register. The mode Down mode, where the DLL is disabled. Address bit
register set command cycle time (tMRD) is required to A13 and all “higher” address bits have to be set to 0 for
complete the write operation to the mode register. The compatibility with other DDR2 memory products with
mode register contents can be changed using the same higher memory densities.
"!ꢃ "!ꢂ "!ꢀ !ꢂꢄ !ꢂꢃ !ꢂꢂ !ꢂꢀ !ꢅ
!ꢆ
!ꢇ
4-
!ꢈ
!ꢉ
#,
!ꢁ
!ꢄ
"4
!ꢃ
!ꢂ
",
!ꢀ
72
W
$,,
ꢀ
0$
W
ꢀ
ꢀ
ꢀ
REGꢊ ADDR
W
W
W
W
W
-0"4ꢀꢁꢂꢀ
Table 9
Field
BA2
Mode Register Definition (BA[2:0] = 000B)
Bits Type1)
16
Description
reg. addr. Bank Address [2]
Note:BA2 not available on 256 Mbit and 512 Mbit components
0B BA2, Bank Address
BA1
BA0
A13
15
14
13
Bank Address [1]
0B
BA1, Bank Address
Bank Address [0]
0B
BA0, Bank Address
Address Bus[13]
Note:A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B A13, Address bit 13
PD
12
w
Active Power-Down Mode Select
0B
1B
PD, Fast exit
PD, Slow exit
Data Sheet
29
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
Table 9
Field
WR
Mode Register Definition (BA[2:0] = 000B) (cont’d)
Bits Type1)
Description
[11:9] w
Write Recovery2)
Note:All other bit combinations are illegal.
001B WR, 2
010B WR, 3
011B WR, 4
100B WR, 5
101B WR, 6
DLL
TM
CL
8
w
w
w
DLL Reset
0B
1B
DLL, No
DLL, Yes
Test Mode
7
0B
1B
TM, Normal Mode
TM, Vendor specific test mode
[6:4]
CAS Latency
Note:All other bit combinations are illegal.
010B CL, 23)
011B CL, 3
100B CL, 4
101B CL, 5
110B CL, 6
BT
BL
3
w
w
Burst Type
0B
1B
BT, Sequential
BT, Interleaved
Burst Length
[2:0]
Note:All other bit combinations are illegal.
010B BL, 4
011B BL, 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns)
by tCK (in ns) and rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed
to fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by
tCK.MIN
.
3) Implemented but not tested
Data Sheet
30
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.6
DDR2 SDRAM Extended Mode Register Set EMR(1)
The Extended Mode Register EMR(1) stores the data EMR(1) is not defined, therefore the extended mode
for enabling or disabling the DLL, output driver register must be written after power-up for proper
strength, additive latency, OCD program, ODT, DQS operation. The extended mode register is written by
and output buffers disable, RQDS and RDQS enable. asserting low on CS, RAS, CAS, WE, BA1 and high on
The default value of the extended mode register BA0, while controlling the state of the address pins
"!ꢃ "!ꢄ "!ꢀ !ꢄꢁ !ꢄꢃ !ꢄꢄ !ꢄꢀ !ꢅ
!ꢂ
!ꢆ
!ꢇ
2TT
!ꢈ
!ꢉ
!,
!ꢁ
!ꢃ
2TT
!ꢄ
!ꢀ
/#$ 0ROGRAM
W
ꢀ
1OFF 2$13 $13
$)# $,,
ꢀ
ꢄ
ꢀ
REGꢊ ADDR
W
W
W
W
W
W
W
-0"4ꢀꢁꢂꢀ
Table 10
Field
BA2
Extended Mode Register Definition (BA[2:0] = 001B)
Bits Type1)
Description
reg. addr. Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B BA2, Bank Address
16
BA1
BA0
A13
15
14
13
Bank Address [1]
0B
BA1, Bank Address
Bank Address [0]
0B
BA0, Bank Address
w
Address Bus[13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B A13, Address bit 13
Qoff
12
Output Disable
0B
1B
QOff, Output buffers enabled
QOff, Output buffers disabled
RDQS
DQS
11
Read Data Strobe Output (RDQS, RDQS)
0B
1B
RDQS, Disable
RDQS, Enable
10
Complement Data Strobe (DQS Output)
0B
1B
DQS, Enable
DQS, Disable
OCD
Program
[9:7]
Off-Chip Driver Calibration Program
000B OCD, OCD calibration mode exit, maintain setting
001B OCD, Drive (1)
010B OCD, Drive (0)
100B OCD, Adjust mode
111B OCD, OCD calibration default
Data Sheet
31
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
Table 10
Field
AL
Extended Mode Register Definition (BA[2:0] = 001B) (cont’d)
Bits Type1)
Description
[5:3]
Additive Latency
Note: All other bit combinations are illegal.
000B AL, 0
001B AL, 1
010B AL, 2
011B AL, 3
100B AL, 4
101B AL, 5
RTT
6,2
Nominal Termination Resistance of ODT
Note: See Table 27 “ODT DC Electrical Characteristics” on Page 77
00B RTT, ∞ (ODT disabled)
01B RTT, 75 Ohm
10B RTT, 150 Ohm
11B RTT, 50 Ohm
DIC
DLL
1
0
Off-chip Driver Impedance Control
0B
1B
DIC, Full (Driver Size = 100%)
DIC, Reduced
DLL Enable
0B
1B
DLL, Enable
DLL, Disable
1) w = write only register bits
A0 is used for DLL enable or disable. A1 is used for Address bit A12 have to be set to 0 for normal
enabling half-strength data-output driver. A2 and A6 operation. With A12 set to 1 the SDRAM outputs are
enables On-Die termination (ODT) and sets the Rtt disabled and in Hi-Z. 1 on BA0 and 0 for BA1 have to
value. A[5:3] are used for additive latency settings and be set to access the EMRS(1). A13 and all “higher”
A[9:7] enables the OCD impedance adjustment mode. address bits have to be set to 0 for compatibility with
A10 enables or disables the differential DQS and other DDR2 memory products with higher memory
RDQS signals, A11 disables or enables RDQS. densities. Refer to Extended Mode Register Definition.
3.7
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL Any time the DLL is reset, 200 clock cycles must occur
enable is required during power up initialization, and before a Read command can be issued to allow time for
upon returning to normal operation after having the DLL the internal clock to be synchronized with the external
disabled. The DLL is automatically disabled when clock. Failing to wait for synchronization to occur may
entering Self-Refresh operation and is automatically re- result in a violation of the tAC or tDQSCK parameters.
enabled and reset upon exit of Self-Refresh operation.
3.8
Output Disable (Qoff)
Under normal operation, the DRAM outputs are DRAM outputs allows users to measure IDD currents
enabled during Read operation for driving data (Qoff bit during Read operations, without including the output
in the EMR(1) is set to 0). When the Qoff bit is set to 1, buffer current and external load currents.
the DRAM outputs will be disabled. Disabling the
Data Sheet
32
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.9
Single-ended and Differential Data Strobe Signals
Table 11 lists all possible combinations for DQS, DQS, in ×8 components only. If RDQS is enabled in ×8
RDQS, RQDS which can be programmed by A[11:10] components, the DM function is disabled. RDQS is
address bits in EMRS. RDQS and RDQS are available active for reads and don’t care for writes.
Table 11
EMRS(1)
A11
Single-ended and Differential Data Strobe Signals
Strobe Function Matrix
Signaling
A10
RDQS/DM
RDQS
DQS
DQS
(RDQS Enable) (DQS Enable)
0 (Disable)
0 (Disable)
1 (Enable)
1 (Enable)
0 (Enable)
1 (Disable)
0 (Enable)
1 (Disable)
DM
DM
RDQS
RDQS
Hi-Z
Hi-Z
RDQS
Hi-Z
DQS
DQS
DQS
DQS
DQS
Hi-Z
DQS
Hi-Z
differential DQS signals
single-ended DQS signals
differential DQS signals
single-ended DQS signals
3.10
Extended Mode Register EMR(2)
The Extended Mode Registers EMR(2) and EMR(3) CKE already high prior to writing into the extended
are reserved for future use and must be programmed mode register. The mode register set command cycle
when setting the mode register during initialization.The time (tMRD) must be satisfied to complete the write
extended mode register EMR(2) is written by asserting operation to the EMR(2). Mode register contents can
LOW on CS, RAS, CAS, WE, BA0 and HIGH on BA1, be changed using the same command and clock cycle
while controlling the states of the address pins. The requirements during normal operation as long as all
DDR2 SDRAM should be in all bank precharge with banks are in precharge state.
"!ꢃ "!ꢄ "!ꢀ !ꢄꢁ !ꢄꢃ !ꢄꢄ !ꢄꢀ !ꢂ
!ꢅ
!ꢆ
!ꢇ
!ꢈ
!ꢉ
!ꢁ
!ꢃ
!ꢄ
!ꢀ
ꢀ
ꢀ
32&
ꢀ
ꢄ
ꢀ
REGꢊ ADDR
-0"4ꢀꢁꢂꢃ
Table 12
Field Bits
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B)
Type1)
Description
reg.addr Bank Address[2]
Note:BA2 is not available on 256Mbit and 512Mbit components
0B BA2, Bank Address
BA2
16
BA1
BA0
A
15
Bank Adress[1]
1B
BA1, Bank Address
14
Bank Adress[0]
0B
BA0, Bank Address
[13:8]
w
Address Bus[13:8]
Note:A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B A[13:8], Address bits
Data Sheet
33
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
Table 12
Field Bits
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B) (cont’d)
Type1)
Description
SRF
[7]
w
Address Bus[7]
Note:When DRAM is operated at 85 °C ≤ TCASE < 95 °C the extended self refresh rate
must be enabled by setting bit A7 to "1" before the self refresh mode can be
entered.
0B
1B
A7, disable
A7, enable, adapted self refresh rate for TCASE > 85 °C
A
[6:0]
w
Address Bus[6:0]
0B A[6:0], Address bits
1) w = write only
3.11
Extended Mode Register EMR(3)
The Extended Mode Register EMR(3) is reserved for initialization. The EMRS(3) is written by asserting low
future use and all bits except BA0 and BA1 must be on CS, RAS, CAS, WE, BA2 and high on BA0 and BA1,
programmed to 0 when setting the mode register during while controlling the state of the address pins.
"!ꢂ "!ꢃ "!ꢀ !ꢃꢄ !ꢃꢂ !ꢃꢃ !ꢃꢀ !ꢅ
!ꢆ
!ꢇ
ꢀ
!ꢈ
!ꢉ
!ꢁ
!ꢄ
!ꢂ
!ꢃ
!ꢀ
ꢀ
ꢃ
ꢃ
REGꢊ ADDR
-0"4ꢀꢁꢀꢀ
Table 13
Field
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B)
Bits Type1)
Description
BA2
16
reg.addr
Bank Address[2]
Note:BA2 is not available on 256Mbit and 512Mbit components
0B
BA2, Bank Address
BA1
BA0
A
15
14
Bank Adress[1]
1B
BA1, Bank Address
Bank Adress[0]
1B
BA0, Bank Address
[13:0] w
Address Bus[13:0]
Note:A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B A[13:0], Address bits
1) w = write only
Data Sheet
34
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.12
Off-Chip Driver (OCD) Impedance Adjustment
DDR2 SDRAM supports driver calibration feature and command being issued. MRS should be set before
the flow chart below is an example of the sequence. entering OCD impedance adjustment and On Die
Every calibration mode command should be followed Termination (ODT) should be carefully controlled
by “OCD calibration mode exit” before any other depending on system environment.
3TART
%-23ꢂ /#$ CALIBRATION MODE EXIT
%-23ꢂ $RIVE ꢆꢇꢈ
$1 ꢉ $13 (IGHꢊ $13 ,OW
%-23ꢂ $RIVE ꢆꢀꢈ
$1 ꢉ $13 ,OWꢊ $13 (IGH
!,, /+
!,, /+
4EST
4EST
.EED #ALIBRATION
.EED #ALIBRATION
%-23ꢂ /#$ CALIBRATION MODE EXIT
%-23ꢂ /#$ CALIBRATION MODE EXIT
%-23ꢂ
%NTER !DJUST -ODE
%-23ꢂ
%NTER !DJUST -ODE
", ꢃ ꢄ CODE INPUT TO ALL $1S
)NCꢅ $EC OR ./0
", ꢃ ꢄ CODE INPUT TO ALL $1S
)NCꢅ $EC OR ./0
%-23ꢂ /#$ CALIBRATION MODE EXIT
%-23ꢂ /#$ CALIBRATION MODE EXIT
%-23ꢂ /#$ CALIBRATION MODE EXIT
%ND
-0&4ꢀꢀꢁꢀ
Figure 9
OCD Impedance Adjustment Flow Chart
Note:MR should be set before entering OCD impedance adjustment and ODT should be carefully controlled
depending on system environment
Data Sheet
35
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
Extended Mode Register Set for OCD impedance adjustment
OCD impedance adjustment can be done using the temperature and voltage conditions. Output driver
following EMRS(1) mode. In drive mode all outputs are characteristics for OCD calibration default are specified
driven out by DDR2 SDRAM and drive of RDQS is in the following table. OCD applies only to normal full
dependent on EMR(1) bit enabling RDQS operation. In strength output drive setting defined by EMR(1) and if
Drive(1)mode, all DQ, DQS (and RDQS) signals are half strength is set, OCD default driver characteristics
driven HIGH and all DQS (and RDQS) signals are are not applicable. When OCD calibration adjust mode
driven LOW. InDrive(0) mode, all DQ, DQS (and is used, OCD default output driver characteristics are
RDQS) signals are driven LOW and all DQS (and not applicable. After OCD calibration is completed or
RDQS) signals are driven HIGH. In adjust mode, BL = driver strength is set to default, subsequent EMRS(1)
4 of operation code data must be used. In case of OCD commands not intended to adjust OCD characteristics
calibration default, output driver characteristics have a must specify A[9:7] as’000’ in order to maintain the
nominal impedance value of 18 Ohms during nominal default or calibrated value.
Table 14
Off Chip Driver Program
A9
0
0
0
1
A8
A7
0
1
0
0
Operation
OCD calibration mode exit
Drive(1) DQ, DQS, (RDQS) high and DQS (RDQS) low
Drive(0) DQ, DQS, (RDQS) low and DQS (RDQS) high
Adjust mode
0
0
1
0
1
1
1
OCD calibration default
OCD impedance adjust
To adjust output driver impedance, controllers must simultaneously and after OCD calibration, all DQs of a
issue the ADJUST EMRS(1) command along with a 4 given DDR2 SDRAM will be adjusted to the same driver
bit burst code to DDR2 SDRAM as in the following strength setting. The maximum step count for
table. For this operation, Burst Length has to be set to adjustment is 16 and when the limit is reached, further
BL = 4 via MRS command before activating OCD and increment or decrement code has no effect. The default
controllers must drive the burst code to all DQs at the setting may be any step within the maximum step count
same time. DT0 in the table means all DQ bits at bit range. When Adjust mode command is issued, AL from
time 0, DT1 at bit time 1, and so forth. The driver output previously set value must be applied.
impedance is adjusted for all DDR2 SDRAM DQs
Table 15
Off-Chip-Driver Adjust Program
4 bit burst code inputs to all DQs
Operation
DT0
0
0
0
0
1
0
0
1
DT1
0
0
0
1
0
1
1
0
DT2
0
0
1
0
0
0
1
0
DT3
0
1
0
0
0
1
0
1
Pull-up driver strength
NOP (no operation)
Increase by 1 step
Decrease by 1 step
NOP
Pull-down driver strength
NOP (no operation)
NOP
NOP
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Increase by 1 step
Decrease by 1 step
Decrease by 1 step
NOP
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Decrease by 1 step
Illegal
1
0
1
0
Other Combinations
Data Sheet
36
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
For proper operation of adjust mode, WL = RL - 1 = sequential or interleave). Burst length of 4 have to be
AL + CL - 1 clocks and tDS / tDH should be met as shown programmed in the MRS for OCD impedance
in Figure 10. Input data pattern for adjustment, DT[0:3] adjustment.
is fixed and not affected by MRS addressing mode (i.e.
CK, CK
CMD
NOP
NOP
NOP
EMRS(1)
NOP
NOP
NOP
EMRS(1)
NOP
WL
tWR
DQS
DQS_in
tDS tDH
DQ_in
DM
DT2
DT3
DT0
DT1
OCD1
OCD calibration
mode exit
OCD adjust mode
Figure 10 Timing Diagram Adjust Mode
Drive Mode
Both Drive(1) and Drive(0) are used for controllers to driven out tOIT after “enter drive mode” command and all
measure DDR2 SDRAM Driver impedance before OCD output drivers are turned-off tOIT after “OCD calibration
impedance adjustment. In this mode, all outputs are mode exit” command. See Figure 11.
CK, CK
CMD
NOP
NOP
NOP
EMRS(1)
tOIT
NOP
EMRS(1)
tOIT
NOP
NOP
NOP
DQS_in
DQ_in
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0
DQS high for Drive(1)
DQS high for Drive(0)
OCD calibration
mode exit
Enter Drive Mode
Figure 11 Timing Diagram Drive Mode
Data Sheet
37
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.13
On-Die Termination (ODT)
On-Die Termination (ODT) is a new feature on DDR2 the ODT control pin. UDQS and LDQS are terminated
components that allows a DRAM to turn on/off termi- only when enabled in the EMRS(1) by address bit
nation resistance for each DQ, DQS, DQS, DM for ×4 A10 = 0.
and DQ, DQS, DQS, DM, RDQS (DM/RDQS share the
same pin) and RDQS for ×8 configuration via the ODT
control pin. DQS and RDQS are only terminated when
enabled by EMR(1).
For ×16 configuration ODT is applied to each DQ, can be used for all active and standby modes. ODT is
UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via turned off and not supported in Self-Refresh mode.
The ODT feature is designed to improve signal integrity
of the memory channel by allowing the DRAM
controller to independently turn on/off termination resis-
tance for any or all DRAM devices. The ODT function
VDDQ
VDDQ
VDDQ
sw2
sw3
sw1
Rval2
Rval3
Rval1
DRAM
Input
Buffer
Input
Pin
Rval2
Rval3
Rval1
sw1
sw2
sw3
ODT_funct2
VSSQ
VSSQ
VSSQ
LE
Figure 12 Functional Representation of ODT
Switch sw1, sw2 or sw3 are enabled by the ODT pin. Target: Rval1 = Rval2 = Rval3 = 2 × Rtt
Selection between sw1, sw2 or sw3 is determined by
“Rtt (nominal)” in EMRS(1) address bits A6 & A2.
The ODT pin will be ignored if the Extended Mode
Register (EMRS(1)) is programmed to disable ODT.
Data Sheet
38
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
ODT Truth Tables
The ODT Truth Table shows which of the input pins are organisations (×4, ×8 and ×16). To activate termination
terminated depending on the state of address bit A10 of any of these pins, the ODT function has to be
and A11 in the EMRS(1) for all three device enabled in the EMRS(1) by address bits A6 and A2.
Table 16
Input Pin
ODT Truth Table
EMRS(1) Address Bit A10
EMRS(1) Address Bit A11
x4 components
DQ[3:0]
DQS
X
X
0
DQS
X
DM
X
x8 components
DQ[7:0]
DQS
X
X
0
DQS
X
1
1
0
RDQS
RDQS
DM
X
0
X
x16 components
DQ[7:0]
DQ[15:8]
LDQS
X
X
X
0
LDQS
X
X
UDQS
UDQS
X
0
LDM
UDM
X
X
Note:X = don’t care; 0 = bit set to low; 1 = bit set to high
Data Sheet
39
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
ODT timing modes
Depending on the operating mode asynchronous or
synchronous ODT timings apply.
•
•
Slow Exit Active Power Down Mode (with MRS bit
A12 is set to 1)
Precharge Power Down Mode
Asynchronous ODT timings (tAOFPD, tAONPD) apply when
the on-die DLL is disabled.
Synchronous ODT timings (tAOND, tAOFD, tAON, tAOF)
apply for all other modes.
These modes are:
T1
T3
T4
T5
T6
T7
T8
T0
T2
CK, CK
CKE
t
t
IS
IS
t
IS
ODT
tAOND (2 tck)
tAOFD (2.5 tck)
Rtt
DQ
tAON(min)
tAOF(min)
tAOF(max)
tAON(max)
ODT01
Figure 13 ODT Timing for Active and Standby (Idle) Modes (Synchronous ODT timings)
Notes
to turn on. ODT turn on time max. (tAON.MAX) is
when the ODT resistance is fully on. Both are
1. Synchronous ODT timings apply for Active Mode
and Standby Mode with CKE HIGH and for the
“Fast Exit” Active Power Down Mode (MRS bit A12
set to 0). In all these modes the on-die DLL is
enabled.
2. ODT turn-on time (tAON.MIN) is when the device
leaves high impedance and ODT resistance begins
measured from tAOND
.
3. ODT turn off time min. (tAOF.MIN) is when the device
starts to turn off the ODT resistance. ODT turn off
time max. (tAOF.MAX) is when the bus is in high
impedance. Both are measured from tAOFD
.
T
1
T
3
T
4
T
5
T
6
T
7
T
8
T
0
T
2
CK, CK
CKE
"low"
t
IS
ODT
DQ
t
IS
tAOFPDmax
tAOFPDmin
Rtt
tAONPD,min
tAONPD,max
ODT02
Figure 14 ODT Timing for Precharge Power-Down and Active Power-Down Mode
Note:Asynchronous ODT timings apply for Precharge Power-Down Mode and “Slow Exit” Active Power Down
Mode (MRS bit A12 set to 1), where the on-die DLL is disabled in this mode of operation.
Data Sheet
40
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
ODT timing mode switch
When entering the Power Down Modes “Slow Exit” Active Power Down and Precharge Power Down two additional
timing parameters (tANPD and tAXPD) define if synchronous or asynchronous ODT timings have to be applied.
Mode entry
As long as the timing parameter tANPD.MIN is satisfied can be applied. If tANPD.MIN is not satisfied,
when ODT is turned on or off before entering these asynchronous timing parameters apply.
power-down modes, synchronous timing parameters
T-5
T-4
T-3
T-2
T-1
T0
T1
T2
CK, CK
CKE
tANPD (3 tck)
tIS
ODT turn-off, tANPD >= 3 tck :
t
IS
ODT
Synchronous
timings apply
RTT
tAOFD
ODT turn-off, tANPD <3 tck :
ODT
Asynchronous
timings apply
RTT
tAOFPDmax
ODT turn-on, tANPD >= 3 tck :
tIS
tAOND
ODT
Synchronous
timings apply
RTT
t
IS
ODT turn-on, tANPD < 3 tck :
tAONPDmax
Asynchronous
timings apply
ODT
RTT
ODT03
Figure 15 ODT Mode Entry Timing Diagram
Data Sheet
41
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
Mode exit
As long as the timing parameter tAXPD.MIN is satisfied applied. If tAXPD.MIN is not satisfied, asynchronous timing
when ODT is turned on or off after exiting these power- parameters apply.
down modes, synchronous timing parameters can be
T0
T1
T5
T6
T7
T8
T9
T10
CK,
CK
tIS
tAXPD
CKE
tIS
ODT turn-off, tAXPD >= tAXPDmin:
ODT
Synchronous
timings apply
Rtt
tAOFD
ODT turn-off, tAXPD < tAXPDmin:
tIS
ODT
Asynchronous
timings apply
Rtt
tAOFPDmax
ODT turn-on, tAXPD >= tAXPDmin:
Synchronous
timings apply
tIS
ODT
Rtt
tAOND
tIS
ODT turn-on, tAXPD < tAXPDmin:
ODT
Asynchronous
timings apply
Rtt
tAONPDmax
ODT04
Figure 16 ODT Mode Exit Timing Diagram
Data Sheet
42
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.14
Bank Activate Command
The Bank Activate command is issued by holding CAS latency must be programmed into the device to delay
and WE HIGH with CS and RAS LOW at the rising edge the R/W command which is internally issued to the
of the clock. The bank addresses BA[1:0] are used to device. The additive latency value must be chosen to
select the desired bank. The row addresses A0 through assure tRCD.MIN is satisfied. Additive latencies of 0, 1, 2,
A12 are used to determine which row to activate in the 3, 4 and 5 are supported. Once a bank has been
selected bank for ×4 and ×8 organized components. activated it must be precharged before another Bank
For ×16 components row addresses A0 through A12 Activate command can be applied to the same bank.
have to be applied. The Bank Activate command must The bank active and precharge times are defined as
be applied before any Read or Write operation can be tRAS and tRP, respectively. The minimum time interval
executed. Immediately after the bank active command, between successive Bank Activate commands to the
the DDR2 SDRAM can accept a read or write command same bank is determined by tRC. The minimum time
(with or without Auto-Precharge) on the following clock interval between Bank Active commands to different
cycle. If a R/W command is issued to a bank that has banks is tRRD
not satisfied the tRCD.MIN specification, then additive
.
T0
T1
T2
T3
T4
Tn
Tn+1
Tn+2
Tn+3
CK, CK
Internal RAS-CAS delay tRCDmin.
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
Bank B
Col. Addr.
Bank A
Addr.
Bank B
Addr.
Bank A
Row Addr.
NOP
Address
Bank A to Bank B delay tRRD.
additive latency AL=2
Read A
Begins
Posted CAS
Bank A
Activate Read A
Posted CAS
Read B
Bank B
Activate
Bank A
Precharge
Bank B Bank A
Precharge Activate
NOP
Command
tRAS Row Active Time (Bank A)
tCCD
tRP Row Precharge Time (Bank A)
tRC Row Cycle Time (Bank A)
ACT
Figure 17 Bank Activate Command Cycle
RCD = 3, AL = 2, tRP = 3, tRRD = 2
t
Data Sheet
43
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.15
Read and Write Commands and Access Modes
After a bank has been activated, a read or write cycle the device during the Read or Write Command (CA[11,
can be executed. This is accomplished by setting RAS 9:0]). The second, third and fourth access will also
HIGH, CS and CAS LOW at the clock’s rising edge. WE occur within this segment, however, the burst order is a
must also be defined at this time to determine whether function of the starting address, and the burst
the access cycle is a read operation (WE HIGH) or a sequence.In case of a 8-bit burst operation (burst
write operation (WE LOW). The DDR2 SDRAM length = 8) the page length of 512 is divided into 64
provides a wide variety of fast access modes. A single uniquely addressable segments (8 bits x 4 I/O each).
Read or Write Command will initiate a serial read or The 8-bit burst operation will occur entirely within one
write operation on successive clock cycles at data rates of the 64 segments (defined by CA[7:0]) beginning with
of up to 533 Mb/sec/pin for main memory. The the column address supplied to the device during the
boundary of the burst cycle is restricted to specific Read or Write Command (CA[11, 9:0]). A new burst
segments of the page length. For example, the access must not interrupt the previous 4 bit burst
16 Mbit x 4 I/O x 4 Bank chip has a page length of 512 operation in case of BL = 4 setting. Therefore the
bits (defined by CA[11, 9:0]).In case of a 4-bit burst minimum CAS to CAS delay (tCCD) is a minimum of 2
operation (burst length = 4) the page length of 512
clocks for read or write cycles.For 8 bit burst operation
is divided into 128 uniquely addressable segments (4 (BL = 8) the minimum CAS to CAS delay (tCCD) is 4
bits x 4 I/O each). The 4-bit burst operation will occur clocks for read or write cycles.Burst interruption is
entirely within one of the 128 segments (defined by allowed with 8 bit burst operation. For details see
CA[8:0]) starting with the column address supplied to Chapter 3.20.
T0
T1
T2
T3
T4
T5
T6
T7
T12
CK, C K
CM D
N O P
tCCD
N O P
N O P
N O P
N O P
R E A D
B
N O P
R E A D
C
R E A D A
N O P
tCCD
DQ S,
DQ S
Dout A0 Dout A1
Dout A2 Dout A3 Dout B0 Dout B1
Dout B2 Dout B3 Dout C0 Dout C1
Dout C2 Dout C3
DQ
RB
Figure 18 Read Timing Example
CL = 3, AL = 0, RL = 3, BL = 4
Data Sheet
44
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.16
Posted CAS
Posted CAS operation is supported to make command latency (CL). Therefore if a user chooses to issue a
and data bus efficient for sustainable bandwidths in Read/Write command before the tRCD.MIN, then AL
DDR2 SDRAM. In this operation, the DDR2 SDRAM greater than 0 must be written into the EMR(1). The
allows a Read or Write command to be issued Write Latency (WL) is always defined as RL - 1 (Read
immediately after the bank activate command (or any Latency -1) where Read Latency is defined as the sum
time during the RAS to CAS delay time, tRCD period). of Additive Latency plus CAS latency (RL=AL+CL). If a
The command is held for the time of the Additive user chooses to issue a Read command after the
Latency (AL) before it is issued inside the device. The tRCD.MIN period, the Read Latency is also defined as
Read Latency (RL) is the sum of AL and the CAS RL = AL + CL.
1
0
2
3
4
5
6
7
8
9
10 11
CK, CK
WL = RL -1 = 4
Activate Read
Bank A Bank A
Write
Bank A
CMD
AL = 2
CL = 3
DQS,
DQS
tRCD
RL = AL + CL = 5
DQ
Dout0Dout1 Dout2Dout3
Din0 Din1 Din2 Din3
PostCAS
Figure 19 Activate to Read Timing Example: Read followed by a write to the same bank
Activate to Read delay < tRCD.MIN: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
1
0
2
3
4
5
6
7
8
9
10 11 12
CK, CK
WL = RL -1 = 4
Write
Bank A
Activate Read
Bank A Bank A
CMD
AL = 2
CL = 3
DQS,
DQS
tRCD
RL = AL + CL = 5
DQ
Dout0 Dout1Dout2 Dout3 Dout4 Dout5 Dout6 Dout7
Din0 Din1 Din2 D
PostCAS3
Figure 20 Read to Write Timing Example: Read followed by a write to the same bank
Activate to Read delay < tRCD.MIN: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8
Data Sheet
45
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
0
1
2
3
4
5
6
7
8
9
10
11
CK, CK
CMD
AL = 0
Activate
Bank A
Read
Bank A
Write
Bank A
CL = 3
WL = RL -1 = 2
DQS,
DQS
tRCD
RL = AL + CL = 3
DQ
Dout0
Dout1
Dout2
Dout3
Din0
Din1
Din2
Din3
PostCAS2
Figure 21 Read to Write Timing Example: Read followed by a write to the same bank
Activate to Read delay = tRCD.MIN: AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4
1
0
2
3
4
5
6
7
8
9
10 11 12 13
CK, CK
WL = 3
Write
Bank A
Activate
Bank A
Read
Bank A
CMD
tRCD > tRCDmin.
DQS,
DQS
RL = 4
DQ
PostCAS5
Figure 22 Read to Write Timing Example: Read followed by a write to the same bank
Activate to Read delay > tRCD.MIN: AL = 1, CL = 3, RL = 4, WL = 3, BL = 4
1
0
2
3
4
5
6
7
8
9
10 11 12 13
CK, CK
WL = 3
Write
Bank A
Activate
Bank A
Read
Bank A
CMD
tRCD > tRCDmin.
DQS,
DQS
RL = 4
DQ
PostCAS5
Figure 23 Write to Read Timing Example: Write followed by a read to the same bank
AL = 2, CL = 3, RL = 5, WL = 4, tWTR = 2, BL = 4
Data Sheet
46
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.17
Burst Mode Operation
Burst mode operation is used to provide a constant flow the MR. The burst type, either sequential or
of data to memory locations (write cycle), or from interleaved, is programmable and defined by the
memory locations (read cycle). The parameters that address bit 3 (A3) of the MR. Seamless burst read or
define how the burst mode will operate are burst write operations are supported. Interruption of a burst
sequence and burst length. The DDR2 SDRAM read or write operation is prohibited, when burst length
supports 4 bit and 8 bit burst modes only. For 8 bit burst = 4 is programmed. For burst interruption of a read or
mode, full interleave address ordering is supported, write burst when burst length = 8 is used, see
however, sequential address ordering is nibble based Chapter 3.19. A Burst Stop command is not supported
for ease of implementation. The burst length is on DDR2 SDRAM devices.
programmable and defined by the addresses A[2:0] of
Table 17
Burst Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing
(decimal)
Interleave Addressing
(decimal)
4
x 0 0
x 0 1
x 1 0
x 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
8
Notes
1. Page size for all 256 Mbit components is 1 KByte
2. Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR or DDR
components
Data Sheet
47
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.18
Read Command
The Read command is initiated by having CS and CAS onto the data bus. The first bit of the burst is
LOW while holding RAS and WE HIGH at the rising synchronized with the rising edge of the data strobe
edge of the clock. The address inputs determine the (DQS). Each subsequent data-out appears on the DQ
starting column address for the burst. The delay from pin in phase with the DQS signal in a source
the start of the command until the data from the first cell synchronous manner. The RL is equal to an additive
appears on the outputs is equal to the value of the read latency (AL) plus CAS latency (CL). The CL is defined
latency (RL). The data strobe output (DQS) is driven by the Mode Register Set (MRS). The AL is defined by
LOW one clock cycle before valid data (DQ) is driven the Extended Mode Register Set (EMRS(1)).
t
t
t
CK
CH
CL
CLK
CLK
CLK, CLK
t
DQS
DQSCK
t
AC
DQS,
DQS
DQS
t
RPST
Dout
t
RPRE
t
t
HZ
LZ
DQ
Dout
Dout
Dout
t
DQSQmax
t
DQSQmax
t
t
QH
QH
DO-Read
Figure 24 Basic Read Timing Diagram
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
READ A
NOP
NOP
NOP
<= t DQSCK
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
AL = 2
CL = 3
RL = 5
DQ
Dout A0
Dout A1
Dout A2
Dout A3
BRead523
Figure 25 Read Operation Example 1
RL = 5 (AL = 2, CL = 3, BL = 4)
Data Sheet
48
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, C K
N O P
N O P
N O P
N O P
N O P
N O P
R E A D A
N O P
N O P
CMD
<= tD Q S C K
DQ S,
DQ S
C L =
R L =
3
3
DQ's
Dout A0 Dout A1
Dout A2 Dout A3
Dout A4 Dout A5
Dout A6 Dout A7
BRead303
Figure 26 Read Operation Example 2
RL = 3 (AL = 0, CL = 3, BL = 8)
T0
T1
T3
T4
T5
T6
T7
T8
T9
CK, C K
CM D
P osted C A S
W R ITE A
P osted C A S
R E A D A
N O P
N O P
N O P
N O P
N O P
N O P
N O P
BL/2 + 2
DQ S,
DQ S
WL = RL - 1 = 4
RL = 5
DQ
Dout A0 Dout A1
Dout A2 Dout A3
Din A0
Din A1
Din A2
Din A3
BRBW514
Figure 27 Read followed by Write Example
RL = 5, WL = (RL-1) = 4, BL = 4
The minimum time from the read command to the write command is defined by a read-to-write turn-around time,
which is BL/2 + 2 clocks.
Data Sheet
49
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
READ B
Posted CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
AL = 2
CL = 3
RL = 5
DQ
Dout A0
Dout A1
Dout A2
Dout A3
Dout B0
Dout B1
Dout B2
Dout B3
SBR523
Figure 28 Seamless Read Operation Example 1
RL = 5, AL = 2, CL = 3, BL = 4
The seamless read operation is supported by enabling a read command at every BL / 2 number of clocks. This
operation is allowed regardless of same or different banks as long as the banks are activated.
T9
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
READ A
Posted CAS
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
CL = 3
RL = 3
DQ
Dout A0
Dout A1
Dout A2
Dout A3
Dout A4
Dout A5
Dout A6
Dout A7
Dout B0
Dout B1
Dout B2
Dout B3
Dout B4
SBR_BL8
Figure 29 Seamless Read Operation Example 2
RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting)
The seamless, non interrupting 8-bit read operation is supported by enabling a read command at every BL/2
number of clocks. This operation is allowed regardless of same or different banks as long as the banks are
activated.
Data Sheet
50
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.19
Write Command
The Write command is initiated by having CS, CAS and successive edges of the DQS until the burst length is
WE LOW while holding RAS HIGH at the rising edge of completed. When the burst has finished, any additional
the clock. The address inputs determine the starting data supplied to the DQ pins will be ignored. The DQ
column address. Write latency (WL) is defined by a signal is ignored after the burst write operation is
read latency (RL) minus one and is equal to (AL + CL – complete. The time from the completion of the burst
1). A data strobe signal (DQS) has to be driven LOW write to bank precharge is named “write recovery time”
(preamble) a time tWPRE prior to the WL. The first data (tWR) and is the time needed to store the write data into
bit of the burst cycle must be applied to the DQ pins at the memory array. tWR is an analog timing parameter
the first rising edge of the DQS following the preamble. (see Chapter 5) and is not the programmed value for
The tDQSS specification must be satisfied for write WR in the MRS.
cycles. The subsequent burst bit data are issued on
t DQSH
DQS
tDQSL
DQS,
DQS
DQS
t
t
WPRE
WPST
Din
Din
Din
Din
t
DS
t DH
Figure 30 Basic Write Timing
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK, CK
CMD
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge
<= t DQSS
Completion of
the Burst Write
DQS,
DQS
tWR
WL = RL-1 = 4
DQ
DIN A0
DIN A1 DIN A2 DIN A3
BW543
Figure 31 Write Operation Example 1
RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4
Data Sheet
51
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK, CK
CMD
Bank A
Activate
Posted CAS
WRITE A
NOP
NOP
NOP
Precharge
NOP
NOP
NOP
Completion of
the Burst Write
<= t DQSS
DQS,
DQS
tRP
tWR
WL = RL-1 = 2
DQ
DIN A0
DIN A1 DIN A2 DIN A3
BW322
Figure 32 Write Operation Example 2
RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK, CK
CMD
Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6
Posted CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
CL=3
AL=2
tWTR
WL = RL - 1 = 4
DQ
DIN A0 DIN A1 DIN A2 DIN A3
RL=5
BWBR
Figure 33 Write followed by Read Example
RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4
The minimum number of clocks from the write command to the read command is (CL - 1) +BL/2 + tWTR, where
WTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write recovery time (tWR
but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.
t
)
Data Sheet
52
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
WRITE A
Posted CAS
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
WL = RL - 1 = 4
DQ
DIN B0
DIN A0
DIN B1 DIN B2 DIN B3
DIN A1 DIN A2 DIN A3
SBR
Figure 34 Seamless Write Operation Example 1
RL = 5, WL = 4, BL = 4
The seamless write operation is supported by enabling a write command every BL/2 number of clocks. This
operation is allowed regardless of same or different banks as long as the banks are activated.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CM D
N O P
N O P
N O P
N O P
W R ITE A
N O P
N O P
N O P
W R ITE B
DQ S,
DQ S
W L = R L - 1 = 2
DQ
DIN B4
DIN B1 DIN B2 DIN B3
DIN B5 DIN
DIN B0
DIN A0
DIN A1 DIN A2 DIN A3
DIN A4
DIN A5 DIN A5 DIN A7
SBW_BL8
Figure 35 Seamless Write Operation Example 2
RL = 3, WL = 2, BL = 8, non interrupting
The seamless write operation is supported by enabling a write command at every BL/2 number of clocks. This
operation is allowed regardless of same or different banks as long as the banks are activated.
Data Sheet
53
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.20
Write Data Mask
One write data mask input (DM) for ×4 and ×8 insure matched system timing. Data mask is not used
components and two write data mask inputs (LDM, during read cycles. If DM is HIGH during a write burst
UDM) for ×16 components are supported on DDR2 coincident with the write data, the write data bit is not
SDRAM’s, consistent with the implementation on DDR written to the memory. For ×8 components the DM
SDRAM’s. It has identical timings on write operations function is disabled, when RDQS / RDQS are enabled
as the data bits, and though used in a uni-directional by EMRS(1).
manner, is internally loaded identically to data bits to
T
T
$13,
$13(
$13ꢄ $13
T
T
7034
702%
$IN
$1
$-
$IN
$IN
$IN
T
T
$3
$(
DONgT CARE
-044ꢀꢁꢂꢃ
Figure 36 Write Data Mask Timing
4ꢃ
4ꢀ
4ꢂ
4ꢄ
4ꢅ
4ꢁ
4ꢆ
4ꢇ
4ꢈ
4ꢉ
4ꢀꢃ
4ꢀꢀ
#,+
#,+
"ANK !
!CTIVATE
0RECHARGE
#-$
7RITE !
./0
./0
./0
./0
./0
ꢍ ꢋ T$133
./0
./0
./0
$13ꢊ
$13ꢊ
7, ꢋ 2, ꢌꢀ ꢋ ꢂ
T72
T20
$IN
!ꢃ
$IN
!ꢀ
$IN
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$IN
!ꢄ
$1
$-
-044ꢀꢁꢂꢃ
Figure 37 Write Operation with Data Mask Example
RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3, BL = 4
Data Sheet
54
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.21
Burst Interruption
Interruption of a read or write burst is prohibited for 6. Read or Write burst with Auto-Precharge enabled is
burst length of 4 and only allowed for burst length of 8
under the following conditions:
1. A Read Burst can only be interrupted by another
Read command. Read burst interruption by a Write
or Precharge Command is prohibited.
not allowed to be interrupted.
7. Read burst interruption is allowed by a Read with
Auto-Precharge command.
8. Write burst interruption is allowed by a Write with
Auto-Precharge command.
9. All command timings are referenced to burst length
set in the mode register. They are not referenced to
the actual burst. For example, Minimum Read to
Precharge timing is AL + BL/2 where BL is the burst
length set in the mode register and not the actual
burst (which is shorter because of interrupt).
Minimum Write to Precharge timing is WL + BL/ 2 +
2. A Write Burst can only be interrupted by another
Write command. Write burst interruption by a Read
or Precharge Command is prohibited.
3. Read burst interrupt must occur exactly two clocks
after the previous Read command. Any other Read
burst interrupt timings are prohibited.
4. Write burst interrupt must occur exactly two clocks
after the previous Write command. Any other Read
burst interrupt timings are prohibited.
5. Read or Write burst interruption is allowed to any
bank inside the DDR2 SDRAM.
t
WR, where tWR starts with the rising clock after the
un-interrupted burst end and not from the end of the
actual burst end.
T0
T1
T2
T3
T4
T5
T6
T7
T8
C K, CK
CM D
N O P
N O P
N O P
N O P
N O P
R E A D
B
N O P
N O P
R E A D
A
N O P
DQ S,
DQ S
D Q
Dout A0 Dout A1
Dout A2 Dout A3 Dout B0 Dout B1
Dout B2 Dout B3 Dout B4 Dout B5
Dout B6 Dout B7
RBI
Figure 38 Read Interrupt Timing Example 1
CL = 3, AL = 0, RL = 3, BL = 8
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CM D
N O P
N O P
N O P
N O P
W R IT E
A
N O P
W R ITE
B
N O P
N O P
N O P
DQ S,
DQ S
D Q
Din A0
Din A1
Din A2
Din A3
Din B0
Din B1
Din B2
Din B3
Dout B4 Din B5
Din B6
Din B7
WBI
Figure 39 Write Interrupt Timing Example 2
CL = 3, AL = 0, WL = 2, BL = 8
Data Sheet
55
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.22
Precharge Command
The Precharge Command is used to precharge or close The Pre-charge Command can be used to precharge
a bank that has been activated. The Precharge each bank independently or all banks simultaneously. 3
Command is triggered when CS, RAS and WE are
LOW and CAS is HIGH at the rising edge of the clock. bank to precharge when the command is issued.
address bits A10, BA[1:0] are used to define which
Table 18
Bank Selection for Precharge by Address Bits
A10
0
0
0
0
BA1
0
0
1
BA0
0
1
0
Precharge Bank(s)
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
All banks
1
1
1
Don’t Care
Don’t Care
Note:The bank address assignment is the same for activating and precharging a specific bank.
3.22.1
Read Followed by a Precharge
The following rules apply as long as the tRTP timing The term (tRTP - 2×tCK) is 0 clocks for operating
parameter - Internal Read to Precharge Command frequencies less or equal 266 MHz (DDR2-400 and
delay time - is less or equal two clocks, which is the DDR2-533 product speed sorts). The term (tRTP - 2×tCK)
case for operating frequencies less or equal 266 MHz is one clock for frequencies higher then 266 MHz
(DDR2 400 and 533 speed sorts).
(DDR2-667 and DDR2-800 speed sorts).
Minimum Read to Precharge command spacing to the A new bank active command may be issued to the
same bank = AL + BL/2 clocks. For the earliest possible same bank if the following two conditions are satisfied
precharge, the Precharge command may be issued on simultaneously:
the rising edge which is “Additive Latency (AL) + BL/2
1. The RAS precharge time (tRP) has been satisfied
clocks” after a Read Command, as long as the
from the clock at which the precharge begins.
2. The RAS cycle time (tRC.MIN) from the previous bank
activation has been satisfied.
minimum tRAS timing is satisfied.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Bank A
Activate
Posted CAS
READ A
NOP
AL + BL/2 clks
NOP
NOP
NOP
Precharge
NOP
NOP
tRP
DQS,
DQS
AL = 1
CL = 3
RL = 4
DQ
Dout A0
Dout A1
Dout A2
Dout A3
>=tRAS
CL = 3
>=tRC
>=tRTP
BR-P413
Figure 40 Read Operation Followed by Precharge Example 1
RL = 4 (AL = 1, CL = 3), BL = 4, tRTP ≤ 2 CKs
Data Sheet
56
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
READ A
Bank A
Activate
NOP
AL + BL/2 clks
NOP
NOP
NOP
Precharge
NOP
NOP
tRP
DQS,
DQS
AL = 1
CL = 3
RL = 4
DQ
Dout A0
Dout A1
Dout A2
Dout A3
Dout A4
Dout A5
Dout A6
Dout A7
>=tRAS
CL = 3
>=tRC
>=tRTP
BR-P413(8)
first 4-bit prefetch
second 4-bit prefetch
Figure 41 Read Operation Followed by Precharge Example 2
RL = 4 (AL = 1, CL = 3), BL = 8, tRTP ≤ 2 CKs
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Bank A
Activate
Posted CAS
READ A
NOP
NOP
tRP
NOP
NOP
NOP
NOP
Precharge
AL + BL/2 clks
DQS,
DQS
AL = 2
RL = 5
CL = 3
DQ
Dout A0
Dout A1
Dout A2
Dout A3
>=tRAS
CL = 3
>=tRC
>=tRTP
BR-P523
Figure 42 Read Operation Followed by Precharge Example 3
RL = 5 (AL = 2, CL = 3), BL = 4, tRTP ≤ 2 CKs
Data Sheet
57
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Bank A
Activate
Posted CAS
READ A
Precharge
A
NOP
NOP
NOP
NOP
NOP
tRP
NOP
AL + BL/2 clocks
DQS,
DQS
AL = 2
RL = 6
CL = 4
DQ
Dout A0
Dout A1
Dout A2
Dout A3
>=tRAS
CL = 4
>=tRC
>=tRTP
BR-P624
Figure 43 Read Operation Followed by Precharge Example 4
RL = 6, (AL = 2, CL = 4), BL = 4, tRTP ≤ 2 CKs
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CM D
B ank A
A ctivate
N O P
N O P
N O P
N O P
P recharge
R E A D A
N O P
N O P
tR P
A L + B L/2 clks + 1
DQ S,
DQ S
C L = 4
R L = 4
DQ
Dout A0 Dout A1
Dout A2 Dout A3 Dout A4 Dout A5
Dout A6 Dout A7
>=tR A S
>=tR TP
BR-P404(8)
first 4-bit prefetch
second 4-bit prefetch
R
Figure 44 Read Operation Followed by Precharge Example 5
RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 CKs
Data Sheet
58
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.22.2
Write followed by Precharge
Minimum Write to Precharge command spacing to the to the Precharge command. No Precharge command
same bank = WL + BL/2 + tWR. For write cycles, a delay should be issued prior to the tWR delay, as DDR2
must be satisfied from the completion of the last burst SDRAM does not support any burst interrupt by a
write cycle until the Precharge command can be Precharge command. tWR is an analog timing
issued. This delay is known as a write recovery time parameter (see Chapter 7) and is not the programmed
(tWR) referenced from the completion of the burst write value WR in the MR.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Precharge
A
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Completion of
the Burst Write
DQS,
DQS
tWR
WL = 3
DQ
DIN A0
DIN A1 DIN A2 DIN A3
BW-P3
Figure 45 Write followed by Precharge Example 1
WL = (RL - 1) = 3, BL = 4, tWR = 3
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK, CK
CMD
Precharge
A
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Completion of
the Burst Write
DQS,
DQS
tWR
WL = 4
DQ
DIN A0
DIN A1 DIN A2 DIN A3
BW-P4
Figure 46 Write followed by Precharge Example 2
WL = (RL - 1) = 4, BL = 4, tWR = 3
Data Sheet
59
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.23
Auto-Precharge Operation
Before a new row in an active bank can be opened, the internally on the rising edge which is CAS Latency (CL)
active bank must be precharged using either the Pre- clock cycles before the end of the read burst. Auto-
charge Command or the Auto-Precharge function. Precharge is also implemented for Write Commands.
When a Read or a Write Command is given to the The Precharge operation engaged by the Auto-
DDR2 SDRAM, the CAS timing accepts one extra Precharge command will not begin until the last data of
address, column address A10, to allow the active bank the write burst sequence is properly stored in the
to automatically begin precharge at the earliest memory array. This feature allows the precharge
possible moment during the burst read or write cycle. If operation to be partially or completely hidden during
A10 is LOW when the Read or Write Command is burst read cycles (dependent upon CAS Latency) thus
issued, then normal Read or Write burst operation is improving system performance for random data
executed and the bank remains active at the access. The RAS lockout circuit internally delays the
completion of the burst sequence. If A10 is HIGH when Precharge operation until the array restore operation
the Read or Write Command is issued, then the Auto- has been completed so that the Auto-Precharge
Precharge function is enabled. During Auto-Precharge, command may be issued with any read or write
a Read Command will execute as normal with the command.
exception that the active bank will begin to precharge
3.23.1
Read with Auto-Precharge
If A10 is 1 when a Read Command is issued, the Read Auto-Precharge to the next Activate command
with Auto-Precharge function is engaged. The DDR2 becomes AL + tRTP + tRP. For BL = 8 the time from Read
SDRAM starts an Auto-Precharge operation on the with Auto-Precharge to the next Activate command is
rising edge which is (AL + BL/2) cycles later from the AL + 2 + tRTP + tRP. Note that (tRTP + tRP) has to be
Read with AP command if tRAS.MIN and tRTP are rounded up to the next integer value. In any event
satisfied. If tRAS.MIN is not satisfied at the edge, the start internal precharge does not start earlier than two clocks
point of Auto-Precharge operation will be delayed until after the last 4-bit prefetch.
t
RAS.MIN is satisfied. If tRTP.MIN is not satisfied at the edge,
A new bank active command may be issued to the
same bank if the following two conditions are satisfied
simultaneously:
the start point of Auto-Precharge operation will be
delayed until tRTP.MIN is satisfied.
In case the internal precharge is pushed out by tRTP, tRP
starts at the point where the internal precharge
happens (not at the next rising clock edge after this
event). So for BL = 4 the minimum time from Read with
1. The RAS precharge time (tRP) has been satisfied
from the clock at which the Auto-Precharge begins.
2. The RAS cycle time (tRC) from the previous bank
activation has been satisfied.
Data Sheet
60
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, C K
CM D
B ank
A ctivate
P osted C A S
R E A D w /A P
N O P
N O P
N O P
N O P
N O P
N O P
N O P
A10 ="high"
Auto-Precharge Begins
AL + BL/2
RL = 5
DQ S,
DQ S
AL = 2
CL = 3
tRP
DQ
Dout A0 Dout A1
Dout A2 Dout A3
tRAS
tRCmin.
BR-AP5231
Figure 47 Read with Auto-Precharge Example 1, followed by an Activation to the Same Bank (tRC Limit)
RL = 5 (AL = 2, CL = 3), BL = 4, tRTP≤ 2 CKs
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CM D
B ank
A ctivate
P osted C A S
R E A D w /A P
N O P
N O P
N O P
N O P
N O P
N O P
N O P
A10 ="high"
Auto-Precharge Begins
tRAS(min)
DQ S,
DQ S
AL = 2
CL = 3
tRP
RL = 5
DQ
Dout A0 Dout A1
Dout A2 Dout A3
tRC
BR-AP5232
Figure 48 Read with Auto-Precharge Example 2, followed by an Activation to the Same Bank (tRAS Limit)
RL = 5 (AL = 2, CL = 3), BL = 4, tRTP≤ 2 CKs
Data Sheet
61
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, C K
CM D
B ank
A ctivate
P osted C A S
R E A D w /A P
N O P
N O P
N O P
N O P
N O P
N O P
N O P
A10 ="high"
AL + BL/2
tRP
Auto-Precharge Begins
DQ S,
DQ S
AL = 1
CL = 3
RL = 4
DQ
Dout A4 Dout A5
Dout A2 Dout A3
Dout A6 Dout A7
Dout A0 Dout A1
>= tRTP
BR-AP413(8)2
second 4-bit prefetch
first 4-bit prefetch
Figure 49 Read with Auto-Precharge Example 3, followed by an Activation to the Same Bank
RL = 4 (AL = 1, CL = 3), BL = 8, tRTP≤ 2 CKs
T0
T1
T2
T3
T4
T5
T6
T7
T8
A
CK, CK
CMD
Bank
Activate
Posted CAS
READ w/AP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
A10 ="high"
AL + tRTP + tRP
Auto-Precharge Begins
DQS,
DQS
AL = 1
CL = 4
RL = 5
DQ
Dout A0 Dout A1 Dout A2 Dout A3
tRTP
tRP
BR-AP4133
first 4-bit prefetch
Figure 50 Read with Auto-Precharge Example 4, followed by an Activation to the Same Bank,
RL = 5 (AL = 1, CL = 4), BL = 4, tRTP= 3 CKs
Data Sheet
62
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.23.2
Write with Auto-Precharge
If A10 is HIGH when a Write Command is issued, the 1. The last data-in to bank activate delay time (tDAL
Write with Auto-Precharge function is engaged. The WR + tRP) has been satisfied.
DDR2 SDRAM automatically begins precharge 2. The RAS cycle time (tRC) from the previous bank
=
operation after the completion of the write burst plus the
write recovery time delay (WR), programmed in the
MRS register, as long as tRAS is satisfied. The bank
undergoing Auto-Precharge from the completion of the
write burst may be reactivated if the following two
conditions are satisfied.
activation has been satisfied.
In DDR2 SDRAM’s the write recovery time delay (WR)
has to be programmed into the MRS mode register. As
long as the analog tWR timing parameter is not violated,
WR can be programmed between 2 and 6 clock cycles.
Minimum Write to Activate command spacing to the
same bank = WL + BL/2 + tDAL
.
T0
T1
T2
T3
T4
T5
T6
T7
CK, C K
CM D
W R ITE
w /A P
B ank A
A ctivate
N O P
N O P
N O P
N O P
N O P
N O P
N O P
A10 ="high"
Completion of the Burst Write
Auto-Precharge Begins
DQ S,
DQ S
WR
tRP
WL = RL-1 = 2
tDAL
DQ
DIN A0
DIN A1 DIN A2 DIN A3
tRCmin.
>=tRASmin.
BW-AP223
Figure 51 Write with Auto-Precharge Example 1 (tRC Limit)
WL = 2, tDAL = 6 (WR = 3, tRP = 3), BL = 4
T0
T3
T4
T5
T6
T7
T8
T12
T9
CK, C K
CM D
P osted C A S
W R ITE w /A P
B ank A
A ctivate
N O P
N O P
N O P
N O P
N O P
N O P
N O P
Completion of the Burst Write
A10 ="high"
Auto-Precharge Begins
DQ S,
DQ S
tRP
WR
tDAL
WL = RL-1 = 4
DQ
DIN A0
DIN A1 DIN A2 DIN A3
>=tRC
>=tRAS
BW-AP423
Figure 52 Write with Auto-Precharge Example 2 (WR + tRP Limit)
WL = 4, tDAL = 6 (WR = 3, tRP = 3), BL = 4
Data Sheet
63
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.23.3
Read or Write to Precharge Command Spacing Summary
The following table summarizes the minimum command delays between Read, Read w/AP, Write, Write w/AP to
the Precharge commands to the same banks and Precharge-All commands.
Table 19
Minimum Command Delays
From Command
To Command
Minimum Delay between “From Unit Note
Command” to “To Command”
1)2)
READ
PRECHARGE (to same banks as
READ)
PRECHARGE-ALL
PRECHARGE (to same banks as
READ w/AP)
PRECHARGE-ALL
PRECHARGE (to same banks as
WRITE)
PRECHARGE-ALL
PRECHARGE (to same banks as
WRITE w/AP)
PRECHARGE-ALL
AL + BL/2 + max(tRTP, 2) - 2×tCK
tCK
1)2)
1)2)
AL + BL/2 + max(tRTP, 2) - 2×tCK
AL + BL/2 + max(tRTP, 2) - 2×tCK
tCK
tCK
READ w/AP
WRITE
1)2)
2)
AL + BL/2 + max(tRTP, 2) - 2×tCK
WL + BL/2 + tWR
tCK
tCK
2)
2)
WL + BL/2 + tWR
WL + BL/2 + WR
tCK
tCK
WRITE w/AP
PRECHARGE
2)
2)
WL + BL/2 + WR
1
tCK
tCK
PRECHARGE (to same banks as
PRECHARGE)
PRECHARGE-ALL
2)
2)
2)
1
1
1
tCK
tCK
tCK
PRECHARGE-ALL PRECHARGE
PRECHARGE-ALL
1) RU{tRTP(ns) / tCK(ns)} must be used, where RU stands for “Round Up”
2) For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge
or precharge-all, issued to that bank. The precharge period is satisfied after tRP,all depending on the latest precharge
command issued to that bank
Data Sheet
64
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.23.4
Concurrent Auto-Precharge
DDR2 devices support the “Concurrent Auto- The minimum delay from a Read or Write command
Precharge” feature. A Read with Auto-Precharge with Auto-Precharge enabled, to a command to a
enabled, or a Write with Auto-Precharge enabled, may different bank, is summarized in the Command Delay
be followed by any command to the other bank, as long Table. As defined, the WL = RL - 1 for DDR2 devices
as that command does not interrupt the read or write which allows the command gap and corresponding
data transfer, and all other related limitations (e.g. data gaps to be minimized.
contention between Read data and Write data must be
avoided externally and on the internal data bus).
Table 20
Command Delay Table
From Command To Command (different bank, Minimum Delay with Concurrent Auto- Unit
Note
non-interrupting command)
Read or Read w/AP
Write or Write w/AP
Precharge Support
WRITE w/AP
Read w/AP
(CL -1) + (BL/2) + tWTR
BL/2
tCK
tCK
tCK
tCK
tCK
tCK
1)
1)
Precharge or Activate
Read or Read w/AP
Write or Write w/AP
1
BL/2
BL/2 + 2
1
Precharge or Activate
1) This rule only applies to a selective Precharge command to another bank, a Precharge-All command is illegal
3.24
Refresh
DDR2 SDRAM requires a refresh of all rows in any rolling 64 ms interval. The necessary refresh can be generated
in one of two ways: by explicit Auto-Refresh commands or by an internally timed Self-Refresh mode.
3.24.1
Auto-Refresh Command
Auto-Refresh is used during normal operation of the external address bus is required once this cycle has
DDR2 SDRAM’s. This command is non persistent, so it started.
must be issued each time a refresh is required. The
refresh addressing is generated by the internal refresh
controller. This makes the address bits ”don’t care”
during an Auto-Refresh command. The DDR2 SDRAM
requires Auto-Refresh cycles at an average periodic
When the refresh cycle has completed, all banks of the
SDRAM will be in the precharged (idle) state. A delay
between the Auto-Refresh Command and the next
Activate Command or subsequent Auto-Refresh
Command must be greater than or equal to the Auto-
Refresh cycle time (tRFC).
interval of tREFI.MAX
.
When CS, RAS and CAS are held LOW and WE HIGH To allow for improved efficiency in scheduling and
at the rising edge of the clock, the chip enters the Auto- switching between tasks, some flexibility in the
Refresh mode. All banks of the SDRAM must be absolute refresh interval is provided. A maximum of
precharged and idle for a minimum of the precharge eight Auto-Refresh commands can be posted to any
time (tRP) before the Auto-Refresh Command can be given DDR2 SDRAM, meaning that the maximum
applied. An internal address counter supplies the absolute interval between any Auto-Refresh command
addresses during the refresh cycle. No control of the and the next Auto-Refresh command is 9 ×tREFI
.
Data Sheet
65
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
CK, CK
"high"
CKE
> = t
> = t
> = t
RFC
N O P
RP
RFC
A U TO
R E FR E S H
A U TO
R E FR E S H
CMD
N O P
N O P
A N Y
P recharge
N O P
N O P
AR
Figure 53 Auto Refresh Timing
3.24.2
Self-Refresh Command
The Self-Refresh command can be used to retain data, clock after Self-Refresh entry is registered, however,
even if the rest of the system is powered down. When the clock must be restarted and stable before the
in the Self-Refresh mode, the DDR2 SDRAM retains device can exit Self-Refresh operation.
data without external clocking. The DDR2 SDRAM
device has a built-in timer to accommodate Self-
Refresh operation. The Self-Refresh Command is
defined by having CS, RAS, CAS and CKE held LOW
with WE HIGH at the rising edge of the clock. The
device must be in idle state and ODT must be turned off
before issuing Self Refresh command, by either driving
ODT pin LOW or using EMRS(1) command. Once the
command is registered, CKE must be held LOW to
keep the device in Self-Refresh mode. The DLL is
automatically disabled upon entering Self Refresh and
is automatically enabled upon exiting Self Refresh.
When the DDR2 SDRAM has entered Self-Refresh
mode all of the external control signals, except CKE,
are “don’t care”. The DRAM initiates a minimum of one
Auto Refresh command internally within tCKE period
once it enters Self Refresh mode. The clock is internally
disabled during Self-Refresh Operation to save power.
The minimum time that the DDR2 SDRAM must remain
in Self Refresh mode is tCKE. The user may change the
external clock frequency or halt the external clock one
The procedure for exiting Self Refresh requires a
sequence of commands. First, the clock must be stable
prior to CKE going back HIGH. Once Self-Refresh Exit
command is registered, a delay of at least tXSNR must
be satisfied before a valid command can be issued to
the device to allow for any internal refresh in progress.
CKE must remain HIGH for the entire Self-Refresh exit
period tXSRD for proper operation. Upon exit from Self
Refresh, the DDR2 SDRAM can be put back into Self
Refresh mode after tXSNR expires. NOP or deselect
commands must be registered on each positive clock
edge during the Self-Refresh exit interval tXSNR. ODT
should be turned off during tXSNR
.
The use of Self Refresh mode introduces the possibility
that an internally timed refresh event can be missed
when CKE is raised for exit from Self Refresh mode.
Upon exit from Self Refresh, the DDR2 SDRAM
requires a minimum of one extra auto refresh command
before it is put back into Self Refresh Mode.
Data Sheet
66
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
T4
T0
T5
Tm
Tr
T1
T2
T3
Tn
CK/CK
CKE
tRP
tis
tis
>=tXSRD
tCKE
tis
tAOFD
>= tXSNR
ODT
CMD
Read
Command
Self Refresh
Entry
Non-Read
Command
NOP
CK/CK may
be halted
CK/CK must
be stable
Figure 54 Self Refresh Timing
Notes
1. Device must be in the “All banks idle” state before
entering Self Refresh mode.
2. tXSRD (≥ 200 tCK) has to be satisfied for a Read or a
Read with Auto-Precharge command.
3. tXSNR has to be satisfied for any command except a
Read or a Read with Auto-Precharge command
4. Since CKE is an SSTL input, VREF must be
maintained during Self Refresh.
3.25
Power-Down
Power-down is synchronously entered when CKE is For Active Power-down two different power saving
registered LOW, along with NOP or Deselect modes can be selected within the MRS register,
command. CKE is not allowed to go LOW while mode address bit A12. When A12 is set to LOW this mode is
register or extended mode register command time, or referred as “standard active power-down mode” and a
read or write operation is in progress. CKE is allowed to fast power-down exit timing defined by the tXARD timing
go LOW while any other operation such as row parameter can be used. When A12 is set to HIGH this
activation, Precharge, Auto-Precharge or Auto-Refresh mode is referred as a power saving “low power active
is in progress, but power-down IDD specification will not power-down mode”. This mode takes longer to exit
be applied until finishing those operations.
The DLL should be in a locked state when power-down
from the power-down mode and the tXARDS timing
parameter has to be satisfied.
is entered. Otherwise DLL should be reset after exiting Entering power-down deactivates the input and output
power-down mode for proper read operation. DRAM buffers, excluding CK, CK, ODT and CKE. Also the DLL
design guarantees it’s DLL in a locked state with any is disabled upon entering Precharge Power-down or
CKE intensive operations as long as DRAM controller slow exit active power-down, but the DLL is kept
complies with DRAM specifications.
enabled during fast exit active power-down. In power-
down mode, CKE LOW and a stable clock signal must
be maintained at the inputs of the DDR2 SDRAM, and
all other input signals are “Don’t Care”. Power-down
duration is limited by 9 times tREFI of the device.
If power-down occurs when all banks are precharged,
this mode is referred to as Precharge Power-down; if
power-down occurs when there is a row active in any
bank, this mode is referred to as Active Power-down.
Data Sheet
67
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
Power-Down Entry
Active Power-down mode can be entered after an Active Power-down mode entry is prohibited as long as
Activate command. Precharge Power-down mode can a Write Burst and the internal write recovery is in
be entered after a Precharge, Precharge-All or internal progress. In case of a write command, active power-
precharge command. It is also allowed to enter power- down mode entry is allowed when WL + BL/2 + tWTR is
mode after an Auto-Refresh command or MRS / satisfied.
EMRS(1) command when tMRD is satisfied.
In case of a write command with Auto-Precharge,
Active Power-down mode entry is prohibited as long as Power-down mode entry is allowed after the internal
a Read Burst is in progress, meaning CKE should be precharge command has been executed, which is WL
kept HIGH until the burst operation is finished. + BL/2 + WR starting from the write with Auto-
Therefore Active Power-Down mode entry after a Read Precharge command. In this case the DDR2 SDRAM
or Read with Auto-Precharge command is allowed after enters the Precharge Power-down mode.
RL + BL/2 is satisfied.
Power-Down Exit
The power-down state is synchronously exited when applied with power-down exit latency, tXP, tXARD or t
CKE is registered HIGH (along with a NOP or Deselect XARDS, after CKE goes HIGH. Power-down exit
command). A valid, executable command can be latencies are defined in Chapter 7.2.
T0
T1
T2
Tn
Tn+1
Tn+2
CK, CK
V alid
C om m and
CM D
CKE
N O P
N O
N O P
Activate
N O P
P
tIS
tIS
tXARD or
tXARDS *)
Act.PD 0
Active
Power-Down
Exit
Active
Power-Down
Entry
Figure 55 Active Power-Down Mode Entry and Exit after an Activate Command
Note:Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed
state in the MR, address bit A12.
Data Sheet
68
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
Tn
Tn+1
T0
T1
T2
T3
T4
T5
T6
T7
Tn+2
C K, C K
Valid
Com m and
R EAD
R EAD w/A P
C M D
CKE
N O P
N
N O P
NO P
N O P
N O P
P
N O P
N O P
N O P
tIS
RL + BL/2
tIS
D Q S,
D Q S
CL = 3
RL = 4
tXARD or
tXARDS *)
AL = 1
DQ
Dout A0 Dout A1
Dout A2 Dout A3
Active
Power-Down
Entry
Active
Power-Down
Exit
Act.PD 1
Active Power-Down Mode Entry and Exit Example aftera Read Command
Figure 56
Note:Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed
state in the MR, address bit A12.
RL = 4 (AL = 1, CL =3), BL = 4
T0
T1
T2
T3
Tn
A
Tn+1
Tn+2
CK, CK
Precharge
*)
Valid
C om m and
CM D
C KE
N O P
N O P
N O P
N O P
N
NO P
N O P
tIS
tIS
tXP
tRP
Precharge
Power-Down
Entry
Precharge
Power-Down
Exit
Figure 57 Active Power-Down Mode Entry and Exit Example after a Write Command
WL = 2, tWTR = 2, BL = 4
Note:Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed
state in the MR, address bit A12.
Data Sheet
69
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
Tn
Tn+1
T0
T1
T2
T3
T4
T5
T6
T7
Tn+2
C K, CK
Valid
C om m and
W R ITE
w /A P
C M D
CKE
N O P
N O P
N O P
N O P
P
N O P
N O P
N
N O P
N O P
WL + BL/2 + WR
tIS
tIS
D Q S,
D Q S
WL = RL - 1 = 2
WR
tXARD or
tXARDS *)
DQ
DIN A0
DIN A1 DIN A2 DIN A3
Active
Power-Down
Entry
Active
Power-Down
Exit
Act.PD 3
Active Power-Down Mode Entry and Exit Example aftera Write Command with AP
Figure 58
WL = 2, WR = 3, BL = 4
Note:Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed
state in the MR, address bit A12. WR is the programmed value in the MRS mode register.
T0
T1
T2
T3
Tn
Tn+1
Tn+2
CK, CK
Valid
Command
CMD
CKE
NOP
NOP
NOP
Precharge
NOP
NOP
N
NOP
tIS
tIS
tXP
tRP
Precharge
Power-Down
Entry
Precharge
Power-Down
Exit
Figure 59 Precharge Power Down Mode Entry and Exit
Note:"Precharge" may be an external command or an internal precharge following Write with AP.
Data Sheet
70
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
Tn
CK, CK
tRFC
Valid
Command
Auto
Refresh
CM D
CKE
tXP
tis
CKE can go low one clock after an Auto-Refresh command
When tRFC expires the DRAM is in Precharge Power-Down Mode
ARPD
Figure 60 Auto-Refresh command to Power-Down entry
T0
T1
T2
T3
T4
T5
T6
T7
CK, CK
MRS or
EMRS
CM D
CKE
t
MRD
Enters Precharge Power-Down Mode
MRS_PD
Figure 61 MRS, EMRS command to Power-Down entry
3.26
Other Commands
3.26.1
No Operation Command
The No Operation Command (NOP) should be used in registered when CS is LOW with RAS, CAS, and WE
cases when the SDRAM is in a idle or a wait state. The held HIGH at the rising edge of the clock. A No
purpose of the No Operation Command is to prevent Operation Command will not terminate a previous
the SDRAM from registering any unwanted commands operation that is still executing, such as a burst read or
between operations. A No Operation Command is write cycle.
3.26.2
Deselect Command
The Deselect Command performs the same function as when CS is brought HIGH, the RAS, CAS, and WE
a No Operation Command. Deselect Command occurs signals become don’t care.
Data Sheet
71
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.27
Input Clock Frequency Change
During operation the DRAM input clock frequency can cycles after tRP and tAOFD have been satisfied the input
be changed under the following conditions:
clock frequency can be changed. A stable new clock
frequency has to be provided, before CKE can be
changed to a HIGH logic level again. After tXP has been
satisfied a DLL RESET command via EMRS(1) has to
be issued. During the following DLL re-lock period of
200 clock cycles, ODT must remain off. After the DLL-
re-lock period the DRAM is ready to operate with the
new clock frequency.
•
•
During Self-Refresh operation
DRAM is in Precharge Power-down mode and ODT
is completely turned off.
In the Precharge Power-down mode the DDR2-
SDRAM has to be in Precharged Power-down mode
and idle. ODT must be already turned off and CKE must
be at a logic LOW state. After a minimum of two clock
Ty+2
Tz
Ty+3
T0
T1
T2
T3
T4
Tx
Tx+1
Ty
Ty+1
CK, C K
D LL
R E SET
Valid
C om m and
C M D
CKE
N O P
N O P
N O P
N O P
N O P
N O P
N O P
N O P
N O P
N O P
tRP
tAOFD
tXP
200 clocks
Minimum 2 clocks
required before
Frequency Change
occurs here
Stable new clock
ODT is off during
DLL RESET
before power-down exit
changing the frequency
Frequ.Ch.
Figure 62 Input Frequency Change Example during Precharge Power-Down mode
Data Sheet
72
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Functional Description
3.28
Asynchronous CKE LOW Reset Event
In a given system, Asynchronous Reset event can occurs, the memory controller must satisfy a time delay
occur at any time without prior knowledge. In this (tDELAY) before turning off the clocks. Stable clocks must
situation, memory controller is forced to drop CKE exist at the input of DRAM before CKE is raised HIGH
asynchronously LOW, immediately interrupting any again. The DRAM must be fully re-initialized as
valid operation. DRAM requires CKE to be maintained described the initialization sequence (Power On and
HIGH for all valid operations as defined in this data Initialization, step 4 through 13). DRAM is ready for
sheet. If CKE asynchronously drops LOW during any normal operation after the initialization sequence. See
valid operation, the DRAM is not guaranteed to Chapter 7 for tDELAY specification.
preserve the contents of the memory array. If this event
stable clocks
CK, CK
tdelay
CKE
CKE drops low due to an
asynchronous reset event
Clocks can be turned off after
this point
Figure 63 Asynchronous Low Reset Event
Data Sheet
73
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Truth tables
4
Truth tables
Table 21
Function
Command Truth Table
CKE
CS RAS CAS WE BA0 A[12:11] A10 A[9:0] Notes
1)2)3)
BA1
Previous Current
Cycle
Cycle
4)5)
(Extended) Mode
Register Set
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
H
H
L
L
L
L
BA
OP Code
4)
H
H
L
H
L
H
L
L
H
L
L
L
L
L
L
L
L
X
H
L
L
L
H
H
L
L
H
H
X
H
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
4)6)
4)6)7)
X
H
H
H
H
L
4)5)
Single Bank Precharge H
H
H
H
H
H
BA
X
BA
BA
BA
X
X
L
H
X
X
4)
Precharge all Banks
Bank Activate
Write
Write with Auto-
Precharge
Read
Read with Auto-
Precharge
H
H
H
H
4)5)
Row Address
Column
Column
4)5)8)
4)5)8)
L
H
Column
Column
L
L
4)5)8)
4)5)8)
H
H
H
H
L
L
H
H
L
L
H
H
BA
BA
Column
Column
L
H
Column
Column
4)
No Operation
Device Deselect
Power Down Entry
H
H
H
X
X
L
L
H
X
X
H
X
H
H
X
X
H
X
H
H
X
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
4)
H
H
L
H
L
4)9)
4)9)
Power Down Exit
L
H
X
X
X
X
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means “H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode
Register.
6) VREF must be maintained during Self Refresh operation.
7) Self Refresh Exit is asynchronous.
8) Burst reads or writes at BL = 4 cannot be terminated. See Chapter 3.19 for details.
9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the
refresh requirements outlined in Chapter 3.23
Data Sheet
74
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Truth tables
Table 22
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State1) CKE
Command (N)2)3)
RAS, CAS, WE
Action (N)2)
Notes4)5)
Previous Cycle6) Current Cycle6)
(N-1)
(N)
L
H
L
H
L
7)8)11)
Power-Down
Self Refresh
L
L
L
L
H
X
Maintain Power-Down
7)9)10)11)
8)11)12)
DESELECT or NOP Power-Down Exit
Maintain Self Refresh
X
9)12)13)14)
7)9)10)11)15)
DESELECT or NOP Self Refresh Exit
DESELECT or NOP Active Power-Down Entry
Bank(s)
Active
All Banks Idle
9)10)11)15)
H
L
DESELECT or NOP Precharge Power-Down
Entry
7)11)14)16)
17)
H
L
AUTOREFRESH
Self Refresh Entry
Any State other H
than
listed above
H
Refer to the Command Truth Table
1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
See Chapter 3.23.
4) CKE must be maintained HIGH while the device is in OCD calibration mode.
5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by
the refresh requirements
8) “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven
HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid
input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2xtCKE + tIH.
12) VREF must be maintained during Self Refresh operation.
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR
period. Read commands may be issued only after tXSRD (200 clocks) is satisfied.
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.
15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations,
Precharge or Refresh operations are in progress. See Chapter 3.23 and Chapter 3.22.2 for a detailed list of restrictions.
16) Self Refresh mode can only be entered from the All Banks Idle state.
17) Must be a legal command as defined in the Command Truth Table.
Table 23
Data Mask (DM) Truth Table
Name (Function)
Write Enable
Write Inhibit
DM
L
H
DQs
Valid
X
Note
1)
1)
1) Used to mask write data; provided coincident with the corresponding data.
Data Sheet
75
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5
AC & DC Operating Conditions
5.1
Absolute Maximum Ratings
Table 24
Symbol
VDD
VDDQ
VDDL
VIN, VOUT
TSTG
Absolute Maximum Ratings
Parameter
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
Rating
Unit
V
V
V
V
Notes
1)2)
–1.0 to +2.3
–0.5 to +2.3
–0.5 to +2.3
–0.5 to +2.3
–55 to +100
1)2)
1)2)
1)
1)3)
°C
1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
3) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Table 25
Symbol
TOPER
DRAM Component Operating Temperature Range
Parameter
Rating
Unit
°C
Notes
1)2)3)4)
Operating Temperature
0 to 95
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation,
the DRAM case temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4) When operating this product in the 85 °C to 95°C TCASE temperature range, the High temperature Self Refresh has to be
enabled by setting EMR(2) bit A7 to “1”. Note, when the high Temperature Self Refresh is enabled there is an increase of
I
DD6 by approximately 50%.
Data Sheet
76
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.2
DC Characteristics
Table 26
Symbol
Recommended DC Operating Conditions (SSTL_18)
Parameter
Rating
Min.
Unit
Note
Typ.
1.8
Max.
1.9
1.9
1.9
0.51 ×VDDQ
1)
VDD
Supply Voltage
1.7
V
V
V
V
V
1)
VDDDL
VDDQ
VREF
VTT
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.7
0.49 ×VDDQ
1.8
1.8
0.5 ×VDDQ
VREF
1)
2)3)
4)
V
REF – 0.04
VREF + 0.04
1) VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
2) The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF
is expected to be about 0.5 ×VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
.
3) Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc)
4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in die dc level of VREF
.
Table 27
ODT DC Electrical Characteristics
Parameter / Condition
Termination resistor impedance value for
EMRS(1)[A6,A2] = [0,1]; 75 Ohm
Symbol
Rtt1(eff)
Min.
60
Nom.
75
Max.
90
Unit
Ω
Note
1)
1)
1)
2)
Termination resistor impedance value for
EMRS(1)[A6,A2] =[1,0]; 150 Ohm
Termination resistor impedance value for
EMRS(1)(A6,A2)=[1,1]; 50 Ohm
Rtt2(eff)
Rtt3(eff)
delta VM
120
40
150
50
180
Ω
Ω
%
60
Deviation of VM with respect to VDDQ / 2
–6.00
—
+ 6.00
1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac
)
respectively. Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)).
2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load:
delta VM = ((2 x VM / VDDQ) – 1) x 100%
Table 28
Symbol
IIL
Input and Output Leakage Currents
Parameter / Condition
Input Leakage Current; any input 0 V < VIN < VDD
Output Leakage Current; 0 V < VOUT < VDDQ
Min.
–2
–5
Max.
+2
+5
Unit
µA
µA
Note
1)
2)
IOL
1) All other pins not under test = 0 V
2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off
Data Sheet
77
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single relative to the rising or falling edges of DQS crossing at
ended or differential mode depending on the setting of REF. In differential mode, these timing relationships
V
the EMRS(1) “Enable DQS” mode bit; timing are measured relative to the crosspoint of DQS and its
advantages of differential mode are realized in system complement, DQS. This distinction in timing methods is
design. The method by which the DDR2 SDRAM pin verified by design and characterization but not subject
timing are measured is mode dependent. In single to production test. In single ended mode, the DQS (and
ended mode, timing relationships are measured RDQS) signals are internally disabled and don’t care.
Table 29
Symbol Parameter
DC & AC Logic Input Levels
DDR2-400 & DDR2-533
Min. Max.
DDR2-667 & DDR2-800
Min. Max.
Unit
V
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
DC input logic high
DC input low
AC input logic high
AC input low
V
–0.3
REF + 0.125
V
V
—
DDQ + 0.3
REF – 0.125
V
REF + 0.125
VDDQ + 0.3
–0.3
V
—
REF – 0.125
V
V
V
VREF + 0.250
V
REF + 0.200
—
V
REF – 0.250
—
VREF – 0.200
Table 30
Symbol
VREF
VSWING.MAX
SLEW
Single-ended AC Input Test Conditions
Condition
Value
0.5 x VDDQ
1.0
Unit
V
V
Note
1)
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum Slew Rate
1)
2)3)
1.0
V / ns
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the
range from VREF to VIL(ac).MAX for falling edges as shown in Figure 64.
3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac)
on the negative transitions.
Start of Falling Edge Input Timing
Start of Rising Edge Input Timing
V
V
V
DDQ
.MIN
IH (ac)
IH (dc) .MIN
REF
V
SWING.MAX
V
V
V
.MAX
IL (dc)
IL (ac) .MAX
SS
V
delta TF
V
delta TR
- V
V
V
REF
IL (ac).MAX
IH(ac).MIN - REF
Falling Slew =
Rising Slew =
delta TR
delta TF
Figure 64 Single-ended AC Input Test Conditions Diagram
Data Sheet
78
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
Table 31
Symbol
VIN(dc)
VID(dc)
VID(ac)
Differential DC and AC Input and Output Logic Levels
Parameter
Min.
Max.
Unit
—
—
V
Note
1)
DC input signal voltage
DC differential input voltage
AC differential input voltage
–0.3
0.25
0.5
V
V
V
DDQ + 0.3
DDQ + 0.6
DDQ + 0.6
2)
3)
4)
VIX(ac)
AC differential cross point input
voltage
0.5 ×VDDQ – 0.175
0.5 ×VDDQ + 0.175
V
5)
VOX(ac)
AC differential cross point output
voltage
0.5 ×VDDQ – 0.125
0.5 ×VDDQ + 0.125
V
1) VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
2) VID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc)
3) VID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac)
.
.
4) The value of VIX(ac) is expected to equal 0.5 ×VDDQ of the transmitting device and VIX(ac) is expected to track variations in V
DDQ. VIX(ac) indicates the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 ×VDDQ of the transmitting device and VOX(ac) is expected to track variations in
V
DDQ. VOX(ac) indicates the voltage at which differential input signals must cross.
VDDQ
VTR
Crossing Point
VID
VIX or VOX
VCP
VSSQ
SSTL18_3
Figure 65 Differential DC and AC Input and Output Logic Levels Diagram
Data Sheet
79
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.4
Output Buffer Characteristics
Table 32
Symbol
IOH
SSTL_18 Output DC Current Drive
Parameter
Output Minimum Source DC Current
SSTL_18
–13.4
13.4
Unit
mA
mA
Note
1)2)
2)3)
IOL
Output Minimum Sink DC Current
1) VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT–VDDQ) / IOH must be less than 21 Ohm for values of VOUT between VDDQ and VDDQ
–
280 mV.
2) The values of IOH(dc) and IOL(dc) are based on the conditions given in 1) and 3). They are used to test drive current capability
to ensure VIH.MIN. plus a noise margin and VIL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual
current values are derived by shifting the desired driver operating points along 21 Ohm load line to define a convenient
current for measurement.
3) VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
Table 33
Symbol
VOH
VOL
VOTR
SSTL_18 Output AC Test Conditions
Parameter
Minimum Required Output Pull-up
Maximum Required Output Pull-down
Output Timing Measurement Reference Level
SSTL_18
Unit
V
V
Note
1)
VTT + 0.603
VTT – 0.603
0.5 ×VDDQ
1)
V
1) SSTL_18 test load for VOH and VOL is different from the referenced load described in Chapter 8.1. The SSTL_18 test load
has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes
that ± 335 mV must be developed across the effectively 25 Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With
an additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the
ouput device (13.4 mA × 45 Ohm = 603 mV).
Table 34
Symbol
OCD Default Characteristics
Description
Min.
See Chapter 5.5
0
0
Nominal
Max.
Unit
Note
1)2)
—
—
—
Output Impedance
Pull-up / Pull down mismatch
Output Impedance step size
for OCD calibration
Ohms
Ohms
Ohms
1)2)3)
4)
—
—
4
1.5
1)5)6)7)8)
SOUT
Output Slew Rate
1.5
—
5.0
V / ns
1) Absolute Specifications (TOPER; VDD = 1.8 V ± 0.1 V; VDDQ = 1.8 V ± 0.1 V), altering OCD from default state no longer
requires DRAM to meet timing, voltage and slew rate specifications on I/O’s.
2) Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV;
(VOUT–VDDQ) / IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ – 280 mV. Impedance
measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = –280 mV; VOUT / IOL must be less than 23.4 Ohms
for values of VOUT between 0 V and 280 mV.
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and
represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18
± 0.75 Ohms under nominal conditions.
5) Slew Rates according to Chapter 8.2.1VIL(ac) to VIH(ac) with the load specified in Figure 72.
6) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured
from AC to AC. This is verified by design and characterization but not subject to production test.
7) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and
t
QHS specification.
8) DRAM output Slew Rate specification applies to 400, 533 and 667 MHz speed bins.
Data Sheet 80
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.5
Full Strength Output V-I Characteristics
DDR2 SDRAM output driver characteristics are defined show the driver characteristics graphically and the
for full strength default operation as selected by the tables show the same data suitable for input into
EMRS(1) bits A[9:7] =’111’. Figure 66 and Figure 67 simulation tools.
Table 35
Voltage (V)
Full Strength Default Pull-up Driver Characteristics
Pull-up Driver Current [mA]
Min.1)
0.00
IBIS Target low2)
0.00
IBIS Target high2)
0.00
Max.3)
0.00
–7.95
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
–4.30
–8.60
–12.90
–16.90
–20.05
–22.10
–23.27
–24.10
–24.73
–25.23
–25.65
–26.02
–26.35
–26.65
–26.93
–27.20
–27.46
—
–5.55
–5.90
–11.10
–16.00
–20.30
–24.00
–27.20
–29.80
–31.90
–33.40
–34.60
–35.50
–36.20
–36.80
–37.20
–37.70
–38.00
–38.40
–38.60
—
–11.80
–17.00
–22.20
–27.50
–32.40
–36.90
–40.80
–44.50
–47.70
–50.40
–52.50
–54.20
–55.90
–57.10
–58.40
–59.60
–60.80
—
–15.90
–23.85
–31.80
–39.75
–47.70
–55.55
–62.95
–69.55
–75.35
–80.35
–84.55
–87.95
–90.70
–93.00
–95.05
–97.05
–99.05
–101.05
—
1) The driver characteristics evaluation conditions are Minimum 95 °C (TCASE), VDDQ = 1.7 V, slow–slow process
2) The driver characteristics evaluation conditions are Nominal Default 25 °C (TCASE), VDDQ = 1.8 V, typical process
3) The driver characteristics evaluation conditions are Maximum 0 °C (TCASE). VDDQ = 1.9 V, fast–fast process
Data Sheet
81
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
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Figure 66 Full Strength Default Pull-up Driver Diagram
Table 36
Voltage (V)
Full Strength Default Pull–down Driver Characteristics
Pull-down Driver Current [mA]
Min.1)
0.00
Nominal Default low2) Nominal Default high2) Max.3)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
0.00
0.00
0.00
4.30
8.60
5.65
5.90
7.95
11.30
16.50
21.20
25.00
28.30
30.90
33.00
34.50
35.50
36.10
36.60
36.90
37.10
37.40
37.60
37.70
37.90
—
11.80
16.80
22.10
27.60
32.40
36.90
40.90
44.60
47.70
50.40
52.60
54.20
55.90
57.10
58.40
59.60
60.90
—
15.90
23.85
31.80
39.75
47.70
55.05
62.95
69.55
75.35
80.35
84.55
87.95
90.70
93.00
95.05
97.05
99.05
101.05
12.90
16.90
20.05
22.10
23.27
24.10
24.73
25.23
25.65
26.02
26.35
26.65
26.93
27.20
27.46
—
—
1) The driver characteristics evaluation conditions are Minimum 95 °C (TCASE), VDDQ = 1.7 V, slow-slow process
2) The driver characteristics evaluation conditions are Nominal Default 25 °C (TCASE), VDDQ = 1.8 V, typical process
3) The driver characteristics evaluation conditions are Maximum 0 °C (TCASE). VDDQ = 1.9 V, fast-fast process
Data Sheet
82
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
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Figure 67 Full Strength Default Pull–down Driver Diagram
5.5.1
Calibrated Output Driver V-I Characteristics
DDR2 SDRAM output driver characteristics are defined looking at one DQ only. If the calibration procedure is
for full strength calibrated operation as selected by the used, it is possible to cause the device to operate
procedure outlined in the Off-Chip Driver (OCD) outside the bounds of the default device characteristics
Impedance Adjustment. The Table 37 and Table 38 tables and figure. In such a situation, the timing
show the data in tabular format suitable for input into parameters in the specification cannot be guaranteed.
simulation tools. The nominal points represent a device It is solely up to the system application to ensure that
at exactly 18 ohms. The nominal low and nominal high the device is calibrated between the minimum and
values represent the range that can be achieved with a maximum default values at all times. If this can’t be
maximum 1.5 ohms step size with no calibration error guaranteed by the system calibration procedure, re-
at the exact nominal conditions only (i.e. perfect calibration policy and uncertainty with DQ to DQ
calibration procedure, 1.5 ohm maximum step size variation, it is recommended that only the default
guaranteed by specification). Real system calibration values to be used. The nominal maximum and
error needs to be added to these values. It must be minimum values represent the change in impedance
understood that these V-I curves are represented here from nominal LOW and HIGH as a result of voltage and
or in supplier IBIS models need to be adjusted to a temperature change from the nominal condition to the
wider range as a result of any system calibration error. maximum and minimum conditions. If calibrated at an
Since this is a system specific phenomena, it cannot be extreme condition, the amount of variation could be as
quantified here. The values in the calibrated tables much as from the nominal minimum to the nominal
represent just the DRAM portion of uncertainty while maximum or vice versa.
Data Sheet
83
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
Table 37
Full Strength Calibrated Pull-down Driver Characteristics
Voltage (V)
Calibrated Pull-down Driver Current [mA]
Nominal Minimum1) Nominal Low2) Nominal3)
Nominal High2) Nominal Maximum4)
(21 Ohms)
9.5
(18.75 Ohms) (18 ohms)
(17.25 Ohms)
11.8
(15 Ohms)
13.3
0.2
0.3
0.4
10.7
16.0
21.0
11.5
16.6
21.6
14.3
18.7
17.4
20.0
23.0
27.0
1) The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.7 V, any process
2) The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.8 V, any
process
3) The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.8 V, typical process
4) The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.9 V, any process
Table 38
Full Strength Calibrated Pull-up Driver Characteristics
Voltage (V) Calibrated Pull-up Driver Current [mA]
Nominal Minimum1) Nominal Low2) Nominal
Nominal High2) NominalMaximum4)
(17.25 Ohms) (15 Ohms)
(21 Ohms)
–9.5
(18.75 Ohms) (18 ohms)3)
0.2
0.3
0.4
–10.7
–16.0
–21.0
–11.4
–16.5
–21.2
–11.8
–17.4
–23.0
–13.3
–20.0
–27.0
–14.3
–18.3
1) The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.7 V, any process
2) The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.8V, any
process
3) The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.8 V, typical process
4) The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.9 V, any process
Data Sheet
84
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.6
Reduced Output Drive Characteristics
A driver mode with reduced output drive characteristics can be selected by setting address bit A1 in the EMRS(1)
extended mode register to 1.
Table 39
Voltage (V)
Reduced Strength Default Pull-up Driver Characteristics
Pull-up Driver Current [mA]
Min.1)
0.00
IBIS Target low2)
0.00
IBIS Target high2)
0.00
Max.3)
0.00
–4.77
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
–1.72
–3.44
–5.16
–6.76
–8.02
–8.84
–9.31
–9.64
–9.89
–10.09
–10.26
–10.41
–10.54
–10.66
–10.77
–10.88
–10.98
—
–3.20
–6.20
–9.04
–3.70
–7.22
–9.54
–10.56
–13.75
–16.78
–19.61
–22.20
–24.50
–26.46
–28.07
–29.36
–30.40
–31.24
–31.93
–32.51
–33.01
–33.46
–33.89
—
–14.31
–19.08
–23.85
–28.62
–33.33
–37.77
–41.73
–45.21
–48.21
–50.73
–52.77
–54.42
–55.80
–57.03
–58.23
–59.43
–60.63
–11.69
–14.11
–16.27
–18.16
–19.77
–21.10
–22.15
–22.96
–23.61
–24.61
–24.64
–25.07
–25.47
–25.85
–26.21
—
—
1) The driver characteristics evaluation conditions are Minimum 95 °C (TCASE), VDDQ = 1.7 V, slow–slow process
2) The driver characteristics evaluation conditions are Nominal Default 25 °C (TCASE), VDDQ = 1.8 V, typical process
3) The driver characteristics evaluation conditions are Maximum 0 °C (TCASE). VDDQ = 1.9 V, fast–fast process
Data Sheet
85
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
0,00
-20,00
-40,00
-60,00
-80,00
Minimum
IBIS Target Low
IBIS Target High
Maximum
0
0,2 0,4 0,6 0,8
1
1,2 1,4 1,6 1,8
2
VDDQ to VOUT (V)
Reduced Strength Default Pull-up Driver Diagram
Figure 68
Table 40
Reduced Strength Default Pull–down Driver Characteristics
Voltage (V)
Pull-down Driver Current [mA]
Min.1)
0.00
1.72
3.44
5.16
6.76
8.02
8.84
9.31
9.64
9.89
10.09
10.26
10.41
10.54
10.66
10.77
10.88
10.98
—
IBIS Target low2)
0.00
IBIS Target high2)
0.00
4.11
Max.3)
0.00
4.77
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
3.24
6.25
9.03
8.01
9.54
11.67
15.03
18.03
20.61
22.71
24.35
25.56
26.38
26.90
27.24
27.47
27.64
27.78
27.89
27.97
28.02
—
14.31
19.08
23.85
28.62
33.33
37.77
41.73
45.21
48.21
50.73
52.77
54.42
55.80
57.03
58.23
59.43
60.63
11.52
13.66
15.41
16.77
17.74
18.83
18.80
19.06
19.23
19.35
19.46
19.56
19.65
19.73
19.80
—
—
1) The driver characteristics evaluation conditions are Minimum 95 °C (TCASE), VDDQ = 1.7 V, slow-slow process
2) The driver characteristics evaluation conditions are Nominal Default 25 °C (TCASE), VDDQ = 1.8 V, typical process
3) The driver characteristics evaluation conditions are Maximum 0 °C (TCASE). VDDQ = 1.9 V, fast-fast process
Data Sheet
86
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
80
70
60
50
Minimum
IBIS Target Low
40
IBIS Target High
Maximum
30
20
10
0
0,2 0,4 0,6 0,8
VOUT to VSSQ (V)
1,2 1,4 1,6 1,8
0
1
2
Figure 69 Reduced Strength Default Pull–down Driver Diagram
5.7
Input / Output Capacitance
Table 41
Input / Output Capacitance
Symbol Parameter
DDR2-400 & DDR2-667
DDR2-800
Max. Min. Max.
Unit
DDR-2-533
Min. Max. Min.
CCK
CDCK
CI
Input capacitance, CK and CK
Input capacitance delta, CK and CK
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only
pins
1.0
—
1.0
—
2.0
0.25
2.0
1.0
—
1.0
—
2.0
0.25
2.0
1.0
—
1.0
—
2.0
pF
pF
pF
pF
0.25
1.75
0.25
CDI
0.25
0.25
CIO
Input/output capacitance,
2.5
—
4.0
0.5
2.5
—
3.5
0.5
2.5
—
3.5
0.5
pF
pF
DQ, DM, DQS, DQS, RDQS, RDQS
CDIO
Input/output capacitance delta,
DQ, DM, DQS, DQS, RDQS, RDQS
Data Sheet
87
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.8
Power & Ground Clamp V-I Characteristics
Power and Ground clamps are provided on address
The V-I characteristics for pins with clamps is shown in
(A[12:0], BA[1:0]), RAS, CAS, CS, WE, and ODT pins. Table 42.
Table 42
Power & Ground Clamp V-I Characteristics
Voltage across clamp (V)
Minimum Power Clamp
Current (mA)
Minimum Ground Clamp Current (mA)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
0
0
0
0
0
0
0
0
0.1
1.0
2.5
4.7
6.8
9.1
11.0
13.5
16.0
18.2
21.0
0
0
0
0
0
0
0
0
0.1
1.0
2.5
4.7
6.8
9.1
11.0
13.5
16.0
18.2
21.0
Data Sheet
88
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.9
Overshoot and Undershoot Specification
Table 43
AC Overshoot / Undershoot Specification for Address and Control Pins
Parameter
DDR2-400
DDR2-533
0.5
DD2-667
0.5
Unit
V
Maximum peak amplitude allowed for overshoot area 0.5
Maximum peak amplitude allowed for undershoot area 0.5
0.5
0.5
V
Maximum overshoot area above VDD
Maximum undershoot area below VSS
1.33
1.33
1.00
1.00
0.80
0.80
V.ns
V.ns
Maximum Amplitude
Overshoot Area
VDD
VSS
Undershoot Area
Maximum Amplitude
Time (ns)
Figure 70 AC Overshoot / Undershoot Diagram for Address and Control Pins
Table 44
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins
Parameter
DDR2-400
DDR2-533
0.5
DD2-667
0.5
Unit
V
Maximum peak amplitude allowed for overshoot area 0.5
Maximum peak amplitude allowed for undershoot area 0.5
0.5
0.5
V
Maximum overshoot area above VDDQ
Maximum undershoot area below VSSQ
0.38
0.38
0.28
0.28
0.23
0.23
V.ns
V.ns
Maximum Amplitude
Overshoot Area
VDDQ
VSSQ
Undershoot Area
Maximum Amplitude
Time (ns)
Figure 71 AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
Data Sheet
89
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Measurement Specifications and Conditions
6
Measurement Specifications and Conditions
Table 45
IDD Measurement Conditions
Parameter
Symbol Notes
IDD0
1)2)3)4)5)6)
Operating Current - One bank Active - Precharge
t
CK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid
commands. Address and control inputs are switching; Databus inputs are switching.
1)2)3)4)5)6)
Operating Current - One bank Active - Read - Precharge
IDD1
I
OUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0,
CL = CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control
inputs are switching; Databus inputs are switching.
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
Precharge Power-Down Current
IDD2P
All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data
bus inputs are floating.
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are
switching, Data bus inputs are switching.
Precharge Quiet Standby Current
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are
stable, Data bus inputs are floating.
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data
bus inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data
bus inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
Active Standby Current
All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH
between valid commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD)
;
t
CK = tCK(IDD); tRAS = tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching; IOUT = 0 mA.
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
Operating Current
IDD4W
IDD5B
IDD5D
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD)
;
t
CK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
Burst Refresh Current
t
CK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH
between valid commands, Other control and address inputs are switching, Data bus inputs
are switching.
Distributed Refresh Current
t
CK = tCK(IDD), Refresh command every tREFI = 7.8 µs interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are switching, Data bus inputs
are switching.
Data Sheet
90
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Measurement Specifications and Conditions
Table 45
IDD Measurement Conditions (cont’d)
Parameter
Self-Refresh Current
Symbol Notes
IDD6
1)2)3)4)5)6)
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are
floating, Data bus inputs are floating.
1)2)3)4)5)6)7)
Operating Bank Interleave Read Current
IDD7
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 ×tCK(IDD)
;
t
CK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address bus inputs are stable during deselects; Data bus is switching.
2. Timing pattern:
DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)
DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)
DDR2-533-444: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks)
DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)
DDR2-800-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D (22 clocks)
DDR2-800-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
(23 clocks)
DDR2-800-666: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D
(24 clocks)
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized.
3) IDD parameter are specified with ODT disabled.
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
5) Definitions for IDD: see Table 46
6) Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7.
7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Table 46
Parameter
LOW
Definition for IDD
Description
defined as VIN≤VIL(ac).MAX
HIGH
defined as VIN≥VIH(ac).MIN
STABLE
FLOATING
SWITCHING
defined as inputs are stable at a HIGH or LOW level
defined as inputs are VREF = VDDQ / 2
defined as: Inputs are changing between high and low every other clock (once per two clocks)
for address and control signals, and inputs changing between high and low every other clock
(once per clock) for DQ signals not including mask or strobes
Data Sheet
91
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Measurement Specifications and Conditions
Table 47
Symbol
I
DD Specification for HYB18T256xxxAF
–25F –2.5 –3 –3S
DDR2–800 DDR2–800 DDR2–667 DDR2–667 DDR2–533 DDR2–400
–3.7
–5
Unit
Notes
Max.
80
90
50
5
—
35
50
Max.
75
85
50
5
—
35
50
22
Max.
65
75
45
5
Max.
62
71
45
5
—
30
45
19
Max.
55
60
35
4.5
2
25
35
16
4.5
90
115
95
130
90
6
4.5
2
Max.
50
55
28
4.5
—
20
30
13
4.5
70
90
75
105
85
6
4.5
—
125
140
IDD0
IDD1
IDD2N
IDD2P
IDD2P(L)
IDD2Q
IDD3N
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1)
30
45
19
5
110
145
115
160
95
6
4.5
—
2)
3)
IDD3P(MRS= 0) 22
IDD3P(MRS= 1)
IDD4R
5
5
5
125
175
135
190
95
6
4.5
—
125
175
135
190
95
6
4.5
—
110
145
115
160
95
6
4.5
—
×4/×8
×16
×4/×8
×16
IDD4W
IDD5B
IDD5D
IDD6
IDD6(L)
IDD7
4)
4)
1)4)
165
180
155
170
145
165
138
157
135
150
×4/×8
×16
1) For LowPower Components
2) MRS(12)=0
3) MRS(12)=1
4) 0 ≤ TCASE ≤ 85°C
Data Sheet
92
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Measurement Specifications and Conditions
6.1
IDD Test Conditions
For testing the IDD parameters, the following timing parameters are used:
Table 48
IDD Measurement Test Condition for DDR2–800
Parameter
Symbol
–25F
DDR2–800
5
–2.5
DDR2–800
6
2.5
15
60
7.5
10
Unit Notes
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command period tRC.IDD
Active bank A to Active bank B command delay tRRD.IDD
CLIDD
tCK.IDD
tRCD.IDD
tCK
ns
ns
ns
2.5
12.5
57.5
7.5
1)
ns
2)
10
ns
Active to Precharge Command
tRAS.MIN.IDD
tRAS.MAX.IDD
tRP.IDD
45
45
70000
15
ns
ns
ns
ns
70000
12.5
75
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh command tRFC.IDD
75
period
Average periodic Refresh
interval
0°C ≤ TCASE ≤ 85°C tREFI
7.8
7.8
µs
1) ×4 & ×8 (1 KByte page size)
2) ×16 (2 KByte page size); not on 256M component
Table 49
IDD Measurement Test Conditions for DDR2–667
Parameter
Symbol
–3
–3S
Unit Notes
DDR2–667 4–4–4
DDR2–667 5–5–5
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh
command period
CL(IDD)
tCK(IDD)
tRCD(IDD)
tRC(IDD)
4
3
12
57
5
3
15
60
tCK
ns
ns
ns
1)
Active bank A to Active bank B
command delay
tRRD(IDD)
tRRD(IDD)
7.5
10
7.5
10
ns
ns
2)
Active to Precharge Command
tRAS.MIN(IDD) 45
tRAS.MAX(IDD) 70000
45
70000
15
ns
ns
ns
ns
Precharge Command Period
tRP(IDD)
12
75
Auto-Refresh to Active / Auto-Refresh tRFC(IDD)
75
command period
Average periodic Refresh interval
1) ×4 & ×8 (1 KByte Page Size)
tREFI
7.8
7.8
µs
2) ×16 (2 KByte Page Size); not on 256M component
Data Sheet
93
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Measurement Specifications and Conditions
Table 50
IDD Measurement Test Condition for DDR2–533C and DDR2–400B
Parameter
Symbol
–3.7
–5
Unit
Notes
DDR2–533 4–4–4
DDR2–400 3–3–3
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh
command period
CL(IDD)
tCK(IDD)
tRCD(IDD)
tRC(IDD)
4
3
5
15
55
tCK
ns
ns
ns
3.75
15
60
1)
2)
Active bank A to Active bank B
command delay
tRRD(IDD)
7.5
10
45
70000
15
75
7.5
10
40
70000
15
75
ns
ns
ns
ns
ns
ns
Active to Precharge Command
tRAS.MIN(IDD)
tRAS.MAX(IDD)
tRP(IDD)
Precharge Command Period
Auto-Refresh to Active / Auto-
Refresh command period
tRFC(IDD)
Average periodic Refresh interval tREFI
7.8
7.8
µs
1)×4 & ×8 (1 KByte Page Size)
2)×16 (2 KByte Page Size); not on 256M component
6.1.1
On Die Termination (ODT) Current
The ODT function adds additional current consumption consumption for any terminated input pin depends on
to the DDR2 SDRAM when enabled by the EMRS(1). whether the input pin is in tri-state or driving “0” or “1”,
Depending on address bits A6 & A2 in the EMRS(1) a as long a ODT is enabled during a given period of time.
full or reduced termination can be selected. The current See Table 51.
Table 51
ODT current per terminated input pin
ODT Current
EMRS(1) State
A6 = 0, A2 = 1
A6 = 1, A2 = 0
A6 = 1, A2 = 1
A6 = 0, A2 = 1
A6 = 1, A2 = 0
A6 = 1, A2 = 0
Min. Typ.
Max. Unit
Enabled ODT current per DQadded IDDQ
IODTO
5
6
7.5
mA/DQ
current for ODT enabled;
2.5
7.5
10
5
3
9
12
6
3.75
mA/DQ
ODT is HIGH; Data Bus inputs are floating
11.25 mA/DQ
Active ODT current per DQadded IDDQ current IODTT
for ODT enabled;
ODT is HIGH; worst case of Data Bus inputs are
stable or switching.
15
7.5
22.5
mA/DQ
mA/DQ
mA/DQ
15
18
Note:For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
94
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Electrical Characteristics
7
Electrical Characteristics
7.1
Speed Grade Defenitions
Table 52
Speed Grade Definition Speed Bins DDR2-800
Speed Grade
DDR2–800
–2.5F
5–5–5
DDR2–800
–2.5
6–6–6
Unit
Notes
IFX Sort Name
CAS-RCD-RP latencies
Parameter
tCK
—
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
tCK
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
Min.
5
Max.
8
Min.
5
Max.
8
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
3.75
2.5
8
8
3.75
3
8
8
2.5
8
2.5
45
60
15
15
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
45
70000
—
—
70000
—
—
57.5
12.5
12.5
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the
“Reference Load for Timing Measurements” according to Chapter 8.1 only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals
other than CK/CK, DQS / DQS, RDQS / RDQS is defined in Chapter 8.3.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT. See section 8 for the reference load for timing measurements.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI
.
Data Sheet
95
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Electrical Characteristics
Table 53
Speed Grade Definition Speed Bins for DDR2–667
Speed Grade
DDR2–667
–3
4–4–4
DDR2–667
–3S
5–5–5
Unit
Notes
IFX Sort Name
CAS-RCD-RP latencies
Parameter
tCK
—
ns
ns
ns
ns
ns
ns
ns
Symbol
tCK
tCK
Min.
5
Max.
8
Min.
5
Max.
8
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
3
8
3.75
3
8
8
tCK
3
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
45
57
12
12
70000
—
—
45
60
15
15
70000
—
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the
“Reference Load for Timing Measurements” according to Chapter 8.1 only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals
other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT. See section 8 for the reference load for timing measurements.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI
.
Data Sheet
96
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Electrical Characteristics
Table 54
Speed Grade Definition Speed Bins for DDR2-533C and DDR2-400B
Speed Grade
DDR2–533
–3.7
4–4–4
DDR2–400
–5
3–3–3
Unit
Note
IFX Sort Name
CAS-RCD-RP latencies
Parameter
tCK
—
ns
ns
ns
ns
ns
ns
ns
Symbol
tCK
tCK
Min.
5
Max.
8
Min.
5
Max.
8
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
3.75
3.75
45
8
8
5
8
tCK
5
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
70000
—
40
55
15
15
70000
—
—
60
15
—
15
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the
“Reference Load for Timing Measurements” according to Chapter 8.1 only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals
other than CK/CK, DQS / DQS, RDQS / RDQS is defined in Chapter 8.3.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT. See section 8 for the reference load for timing measurements.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI
.
Data Sheet
97
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Electrical Characteristics
7.2
AC Timing Parameters
Table 55
Parameter
Timing Parameter by Speed Grade - DDR2-800
Symbol
DDR2-800
Min.
–400
2
0.45
3
0.45
WR + tRP
tIS + tCK + tIH ––
Unit Note
1)2)3)4)5)6)
Max.
+400
—
0.55
—
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tAC
tCCD
tCH
tCKE
tCL
tDAL
tDELAY
ps
tCK
tCK
tCK
tCK
tCK
ns
0.55
—
7)
8)
9)
DQ and DM input hold time (differential data strobe)
DQ and DM input hold time (single ended data strobe)
DQ and DM input pulse width (each input)
tDH(base)
125
––
––
—
+350
—
200
+0.25
—
—
—
ps
ps
tCK
ps
tCK
ps
tCK
ps
ps
tCK
tCK
10)
t
DH1(base) ––
tDIPW
0.35
–350
0.35
—
–0.25
50
—
0.2
DQS output access time from CK / CK
tDQSCK
tDQSL,H
tDQSQ
tDQSS
tDS(base)
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data strobe)
11)
9)
9)
DQ and DM input setup time (single ended data strobe) tDS1(base)
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
tDSH
tDSS
tHP
tHZ
tIH(base)
tIPW
0.2
—
12)
13)
9)
MIN. (tCL, tCH)
—
250
0.6
tAC.MAX ps
—
—
ps
tCK
Address and control input pulse width
(each input)
9)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
175
2 x tAC.MIN
tAC.MIN
2
—
ps
13)
13)
tAC.MAX ps
tAC.MAX ps
—
tCK
ns
tOIT
0
12
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
tQH
tQHS
tREFI
t
—
—
—
75
0.9
0.40
HP – tQHS
—
300
7.8
3.9
—
1.1
0.60
ps
µs
µs
ns
tCK
tCK
14)15)
14)16)
17)
Auto-Refresh to Active/Auto-Refresh command period tRFC
Read preamble
Read postamble
13)
tRPRE
tRPST
13)
Data Sheet
98
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Electrical Characteristics
Table 55
Parameter
Timing Parameter by Speed Grade - DDR2-800
Symbol
DDR2-800
Min.
7.5
10
7.5
0.35 x tCK
0.40
15
tWR/tCK
7.5
Unit Note
1)2)3)4)5)6)
Max.
—
—
—
—
18)19)
20)20)
Active bank A to Active bank B command period
tRRD
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-Precharge
Write recovery time for write with Auto-Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
tRTP
tWPRE
tWPST
tWR
WR
tWTR
tXARD
21)
0.60
—
22)
23)
—
—
2
24)
Exit active power-down mode to Read command (slow tXARDS
8 – AL
2
—
—
tCK
tCK
exit, lower power)
Exit precharge power-down to any valid command (other tXP
than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
tCK
200
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V. See notes 3)4)5)6)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1
= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.
4) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3 of this data
sheet.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
6) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
9) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
10) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS/DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for tCL and tCH).
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows
as valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85 °C and 95 °C.
15) 0 ≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
Data Sheet
99
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Electrical Characteristics
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) x4 & x8 (1k page size)
19) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1.5
20) x16 (2k page size), not on 256Mbit component
21) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
22) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
23) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down
mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.
Table 56
Parameter
Timing Parameter by Speed Grade - DDR2-667
Symbol
DDR2-667
Min.
–450
2
0.45
3
0.45
WR + tRP
tIS + tCK + tIH ––
Unit Note
1)2)3)4)5)6)
Max.
+450
—
0.55
—
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tAC
tCCD
tCH
tCKE
tCL
tDAL
tDELAY
ps
tCK
tCK
tCK
tCK
tCK
ns
0.55
—
7)
8)
9)
DQ and DM input hold time (differential data strobe)
DQ and DM input hold time (single ended data strobe)
DQ and DM input pulse width (each input)
tDH(base)
175
––
––
—
+400
—
—
+0.25
—
—
—
ps
ps
tCK
ps
tCK
ps
tCK
ps
ps
tCK
tCK
10)
t
DH1(base) ––
tDIPW
0.35
–400
0.35
240
–0.25
100
—
0.2
0.2
DQS output access time from CK / CK
tDQSCK
tDQSL,H
tDQSQ
tDQSS
tDS(base)
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data strobe)
11)
9)
9)
DQ and DM input setup time (single ended data strobe) tDS1(base)
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
tDSH
tDSS
tHP
tHZ
tIH(base)
tIPW
—
12)
13)
9)
MIN. (tCL, tCH)
— tAC.MAX ps
275
—
—
ps
tCK
Address and control input pulse width
(each input)
0.6
9)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
200
2 x tAC.MIN
tAC.MIN
2
—
ps
13)
13)
tAC.MAX ps
tAC.MAX ps
—
12
—
—
tCK
ns
0
Data output hold time from DQS
Data hold skew factor
t
HP – tQHS
tQHS
340
ps
Data Sheet
100
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Electrical Characteristics
Table 56
Parameter
Timing Parameter by Speed Grade - DDR2-667
Symbol
DDR2-667
Min.
—
—
75
Unit Note
1)2)3)4)5)6)
Max.
7.8
3.9
—
14)15)
14)16)
17)
Average periodic refresh Interval
tREFI
µs
µs
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
Auto-Refresh to Active/Auto-Refresh command period tRFC
18)
Precharge-All (4 banks) command period
Read preamble
Read postamble
tRP
t
RP + 1tCK
—
13)
tRPRE
tRPST
tRRD
0.9
1.1
0.60
—
—
—
—
0.60
—
13)
0.40
7.5
10
7.5
0.35
0.40
15
tWR/tCK
7.5
2
19)20)
21)
Active bank A to Active bank B command period
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-Precharge
Write recovery time for write with Auto-Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
tRTP
tWPRE
tWPST
tWR
WR
tWTR
tXARD
22)
23)
24)
—
—
24)
Exit active power-down mode to Read command (slow tXARDS
7 – AL
2
—
—
tCK
tCK
exit, lower power)
Exit precharge power-down to any valid command (other tXP
than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
tCK
200
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V. See notes 3)4)5)6)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1
= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.
4) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3 of this data
sheet.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
6) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
9) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
10) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS/DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for tCL and tCH).
Data Sheet
101
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Electrical Characteristics
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows
as valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85 °C and 95 °C.
15) 0 ≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) tRP(A) for a Precharge-All command for an 8 bank device is equal to tRP + 1tCK, where tRP are the values for a single bank
precharge.
19) x4 & x8 (1k page size)
20) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1.5
21) x16 (2k page size), not on 256Mbit component
22) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
23) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
24) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down
mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.
Table 57
Parameter
Timing Parameter by Speed Grade - DDR2-533
Symbol
DDR2–533
Min.
–500
2
0.45
3
0.45
WR + tRP
tIS + tCK + tIH ––
Unit Note1)2)
3)4)5)6)
Max.
+500
—
0.55
—
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data
strobe)
DQ and DM input hold time (single ended data
strobe)
tAC
ps
tCCD
tCH
tCKE
tCL
tDAL
tDELAY
tCK
tCK
tCK
tCK
tCK
ns
0.55
—
7)
8)
9)
tDH(base)
225
–25
––
—
ps
9)
t
DH1(base)
ps
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ signals) tDQSQ
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
DQ and DM input setup time (single ended data
strobe)
tDIPW
tDQSCK
tDQSL,H
0.35
–450
0.35
—
–0.25
100
—
+450
—
300
+0.25
—
tCK
ps
tCK
ps
tCK
10)
tDQSS
tDS(base)
9)
ps
9)
t
DS1(base)
–25
—
ps
DQS falling edge hold time from CK (write cycle) tDSH
0.2
0.2
—
—
tCK
tCK
DQS falling edge to CK setup time (write cycle)
tDSS
tHP
11)
Clock half period
MIN. (tCL, tCH)
Data Sheet
102
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Electrical Characteristics
Table 57
Parameter
Timing Parameter by Speed Grade - DDR2-533 (cont’d)
Symbol DDR2–533
Unit Note1)2)
3)4)5)6)
Min.
—
Max.
tAC.MAX
—
12)
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tHZ
ps
ps
9)
tIH(base)
tIPW
375
0.6
—
tCK
9)
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
250
2 ° tAC.MIN
tAC.MIN
2
—
ps
ps
ps
12)
tAC.MAX
tAC.MAX
—
12)
tCK
ns
tOIT
0
12
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
tQH
tQHS
tREFI
t
HP – tQHS
—
400
7.8
3.9
—
—
—
—
75
ps
µs
µs
ns
13)14)
13)15)
16)
Auto-Refresh to Active/Auto-Refresh command
period
Precharge-All (4 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command period tRRD
tRFC
17)
tRP
tRPRE
tRPST
t
RP + 1tCK
—
ns
tCK
tCK
ns
12)
0.9
0.40
7.5
1.1
0.60
—
12)
1)18)19)
1)1)20)
10
—
ns
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-
Precharge
tRTP
7.5
—
—
0.60
—
ns
tCK
tCK
ns
tWPRE
tWPST
tWR
0.35xtCK
0.40
15
21)
Write recovery time for write with Auto-Precharge WR
t
WR/tCK
tCK
ns
tCK
22)
Internal Write to Read command delay
tWTR
7.5
2
—
—
23)
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
1)
Exit active power-down mode to Read command tXARDS
6 – AL
2
—
—
tCK
(slow exit, lower power)
Exit precharge power-down to any valid command tXP
tCK
(other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
tCK
200
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V. See notes 3)4)5)6)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1
= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.
Data Sheet
103
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Electrical Characteristics
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS,
RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS is defined in Chapter 8.3 of this data
sheet.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
6) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
9) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for tCL and tCH).
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as
valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85 °C and 95 °C.
14) 0 ≤ TCASE ≤ 85 °C
15) 85 < TCASE ≤ 95 °C
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
17) tRP(A) for a Precharge-All command for an 8 bank device is equal to tRP + 1tCK, where tRP are the values for a single bank
precharge.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1.5
19) x4 & x8
20) x16
21) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
22) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
23) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down
mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.
Table 58
Parameter
Timing Parameter by Speed Grade - DDR2-400
Symbol
DDR2-400
Min.
–600
2
0.45
3
0.45
WR + tRP
tIS + tCK + tIH ––
Unit Note
1)2)3)4)5)6)
Max.
+600
—
0.55
—
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tAC
tCCD
tCH
tCKE
tCL
tDAL
tDELAY
ps
tCK
tCK
tCK
tCK
tCK
ns
0.55
—
7)
8)
9)
DQ and DM input hold time (differential data strobe)
DQ and DM input hold time (single-ended strobe)
DQ and DM input pulse width (each input)
tDH(base)
275
––
––
—
ps
ps
tCK
10)
t
DH1(base) 25
tDIPW
0.35
Data Sheet
104
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Electrical Characteristics
Table 58
Parameter
Timing Parameter by Speed Grade - DDR2-400
Symbol
DDR2-400
Min.
–500
0.35
—
Unit Note
1)2)3)4)5)6)
Max.
+500
—
350
+0.25
—
—
—
—
DQS output access time from CK / CK
tDQSCK
tDQSL,H
tDQSQ
tDQSS
tDS(base)
ps
tCK
ps
tCK
ps
ps
tCK
tCK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data strobe)
DQ and DM input setup time (single-ended strobe)
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock half period
11)
–0.25
150
9)
9)
t
DS1(base) 25
tDSH
tDSS
tHP
tHZ
tIH(base)
tIPW
0.2
0.2
12)
13)
9)
MIN. (tCL, tCH)
—
475
0.6
Data-out high-impedance time from CK / CK
Address and control input hold time
tAC.MAX ps
—
—
ps
Address and control input pulse width
(each input)
tCK
9)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
350
2 x tAC.MIN
tAC.MIN
2
—
ps
13)
13)
tAC.MAX ps
tAC.MAX ps
—
tCK
ns
tOIT
0
12
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
tQH
tQHS
tREFI
t
HP – tQHS
—
—
—
—
75
450
7.8
3.9
—
ps
µs
µs
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
14)15)
14)16)
17)
Auto-Refresh to Active/Auto-Refresh command period tRFC
Precharge-All (4 banks) command period
Read preamble
Read postamble
18)
tRP
t
RP + 1tCK
—
13)
tRPRE
tRPST
tRRD
0.9
0.40
7.5
10
7.5
0.35
0.40
15
1.1
0.60
—
—
—
—
0.60
—
13)
19)20)
20)21)
Active bank A to Active bank B command period
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-Precharge
Write recovery time for write with Auto-Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
tRTP
tWPRE
tWPST
tWR
WR
tWTR
tXARD
22)
tWR/tCK
7.5
2
23)
24)
—
—
24)
Exit active power-down mode to Read command (slow tXARDS
6 – AL
2
—
—
tCK
tCK
exit, lower power)
Exit precharge power-down to any valid command
(other than NOP or Deselect)
tXP
Data Sheet
105
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Electrical Characteristics
Table 58
Parameter
Timing Parameter by Speed Grade - DDR2-400
Symbol
DDR2-400
Min.
Unit Note
1)2)3)4)5)6)
Max.
—
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
tXSNR
tXSRD
t
RFC +10
ns
200
—
tCK
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V. See notes 3)4)5)6)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1
= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.
4) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3 of this data
sheet.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
6) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
9) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
10) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS/DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for tCL and tCH).
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows
as valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85 °C and 95 °C.
15) 0 ≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) tRP(A) for a Precharge-All command for an 8 bank device is equal to tRP + 1tCK, where tRP are the values for a single bank
precharge.
19) x4 & x8 (1k page size)
20) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1.5
21) x16 (2k page size), not on 256Mbit component
22) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
23) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
24) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down
mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.
Data Sheet
106
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Electrical Characteristics
7.3
ODT AC Electrical Characteristics
Table 59
ODT AC Electrical Characteristics and Operating Conditions for DDR2-667 and DDR2-800
Symbol Parameter / Condition
Values
Min.
2
Unit
Note
Max.
2
tAOND
tAON
tAONPD
tAOFD
tAOF
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
tCK
ns
ns
tCK
ns
1)
tAC.MIN
t
AC.MAX + 0.7 ns
AC.MAX + 1 ns
t
AC.MIN + 2 ns 2 tCK +
t
2.5
tAC.MIN
2.5
2)
ODT turn-off
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency 3
ODT Power Down Exit Latency
tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns
—
—
tCK
tCK
8
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
max is when the ODT resistance is fully on. Both are measure from tAOND
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high
impedance. Both are measured from tAOFD
.
.
Table 60
ODT AC Electrical Characteristics and Operating Conditions for DDR2-533 and DDR2-400
Symbol Parameter / Condition
Values
Min.
2
Unit
Note
Max.
2
tAOND
tAON
tAONPD
tAOFD
tAOF
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
tCK
ns
ns
tCK
ns
1)
tAC.MIN
t
AC.MAX + 1 ns
AC.MAX + 1 ns
t
AC.MIN + 2 ns 2 tCK +
t
2.5
tAC.MIN
2.5
2)
ODT turn-off
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency 3
ODT Power Down Exit Latency
tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns
—
—
tCK
tCK
8
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
max is when the ODT resistance is fully on. Both are measure from tAOND
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high
impedance. Both are measured from tAOFD
.
.
Data Sheet
107
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HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
8
AC Timing Measurement Conditions
8.1
Reference Load for Timing Measurements
Figure 72 represents the timing reference load used in production test conditions, generally
a
coaxial
defining the relevant timing parameters of the device. It transmission line terminated at the tester electronics.
is not intended to either a precise representation of the This reference load is also used for output Slew Rate
typical system environment nor a depiction of the actual characterization. The output timing reference voltage
load presented by a production tester. System level for single ended signals is the crosspoint with VTT.
designers should use IBIS or other simulation tools to
correlate the timing reference load to a system
environment. Manufacturers correlate to their
The output timing reference voltage level for differential
signals is the crosspoint of the true (e.g. DQS) and the
complement (e.g. DQS) signal.
VDDQ
DQ
DQS
DQS
RDQS
RDQS
CK, CK
DUT
VTT = VDDQ / 2
25 Ohm
Timing Reference Points
Figure 72 Reference Load for Timing Measurements
8.2
Slew Rate Measurement Conditions
Output Slew Rate
8.2.1
For DQ and single ended DQS signals output Slew DQS – DQS = + 500 mV. Output Slew Rate is defined
Rate for falling and rising edges is measured between with the reference load according to Figure 72 and
V
TT – 250 mV and VTT + 250 mV.
verified by design and characterization, but not subject
to production test.
For differential signals (DQS / DQS) output Slew Rate
is measured between DQS - DQS = –500 mV and
8.2.2
Input Slew Rate - Differential signals
Input Slew Rate for differential signals (CK / CK, DQS / from CK – CK = +250 mV to CK – CK = –500mV for
DQS, RDQS / RDQS) for rising edges are measured falling edges.
from CK - CK = –250 mV to CK – CK = +500 mV and
Data Sheet
108
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
8.3
Input and Data Setup and Hold Time
8.3.1
Definition for Input Setup (tIS) and Hold Time (tIH)
Address and control input setup time (tIS) is referenced (tIH) is referenced from the input signal crossing at the
from the input signal crossing at the VIH(ac) level for a VIL(dc) level for a rising signal and VIH(dc) for a falling
rising signal and VIL(ac) for a falling signal applied to the signal applied to the device under test.
device under test. Address and control input hold time
CK
CK
t
t
t
t
IS
IH
IS IH
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF
min
min
max
max
IL(dc)
IL(ac)
SS
Figure 73 Input Setup and Hold Time
8.3.2
Definition for Data Setup (tDS) and Hold Time (tDH), differential Data Strobes
Data input setup time (tDS) with differential data strobe differential data strobe enabled MR[bit10]=0, is
enabled MR[bit10]=0, is referenced from the input referenced from the input signal crossing at the VIL(dc)
signal crossing at the VIH(ac) level to the differential data level to the differential data strobe crosspoint for a
strobe crosspoint for a rising signal, and from the input rising signal and VIH(dc) to the differential data strobe
signal crossing at the VIL(ac) level to the differential data crosspoint for a falling signal applied to the device
strobe crosspoint for a falling signal applied to the under test.
device under test.
DQS/DQS signals must be monotonic between
DQS/DQS signals must be monotonic between
V
IL(dc).MAX and VIH(dc).MIN
.
V
IL(dc).MAX and VIH(dc).MIN. Data input hold time (tDH) with
DQS
DQS
t
t
t
t
DS DH
DS DH
VDDQ
VIH(ac)
VIH(dc)
VREF
min
min
VIL(dc)
VIL(ac)
VSS
max
max
Figure 74 Data Setup and Hold Time (Differential Data Strobes)
Data Sheet 109
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
8.3.3
Definition Data Setup (tDS1) and Hold Time (tDH1), Single-Ended Data Strobes
Data input setup time (tDS1) with single-ended data input signal crossing at the VIH(dc) level to the single-
strobe enabled MR[bit10]=1, is referenced from the ended data strobe crossing VIH/L(ac) at the end of its
input signal crossing at the VIH(ac) level to the single- transition for a rising signal and from the input signal
ended data strobe crossing VIH/L(dc) at the start of its crossing at the VIL(dc) level to the single-ended data
transition for a rising signal, and from the input signal strobe crossing VIH/L(ac) at the end of its transition for a
crossing at the VIL(ac) level to the single-ended data falling signal applied to the device under test.
strobe crossing VIH/L(dc) at the start of its transition for a
The DQS signal must be monotonic between VIL(dc.MAX
falling signal applied to the device under test.
and VIH(dc).MIN
.
Data input hold time (tDH1) with single-ended data
strobe enabled MR[bit10]=1, is referenced from the
VDDQ
VIH(ac)
VIH(dc)
VREF
min
min
DQS
VIL(dc)
VIL(ac)
VSS
max
max
t
t
DS
t
DS
t
DH
DH
VDDQ
VIH(ac)
VIH(dc)
VREF
min
min
DQ
VIL(dc)
VIL(ac)
VSS
max
max
Figure 75 Data Setup and Hold Time (Single Ended Data Strobes)
Data Sheet
110
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
8.3.4
Slew Rate Definition for Input and Data Setup and Hold Times
Setup (tIS & tDS) nominal Slew Rate for a rising signal is level is used for derating value.(see Figure 77) Hold
defined as the Slew Rate between the last crossing of (tIH & tDH) nominal Slew Rate for a rising signal is
V
REF(dc) and the first crossing of VIH(ac).MIN. Setup (tIS & defined as the Slew Rate between the last crossing of
tDS) nominal Slew Rate for a falling signal is defined as VIL(dc).MAX and the first crossing of VREF(dc). Hold (tIH
&
the Slew Rate between the last crossing of VREF(dc) and tDH) nominal Slew Rate for a falling signal is defined as
the first crossing of VIL(ac).MAX. If the actual signal is the Slew Rate between the last crossing of VIH(dc).MIN
always earlier than the nominal Slew Rate line between and the first crossing of VREF(dc). If the actual signal is
shaded ‘VREF(dc) to ac region’, use nominal Slew Rate always later than the nominal Slew Rate line between
for derating value (see Figure 76). If the actual signal shaded ‘dc to VREF region’, use nominal Slew Rate for
is later than the nominal Slew Rate line anywhere derating value (see Figure 76). If the actual signal is
between shaded ‘VREF(dc) to ac region’, the Slew Rate of earlier than the actual signal from the dc level to VREF
a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 77)
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3ETUP 3LEW 2ATE ꢀ
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$ELTA 423
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RISING SIGNAL
FALLING SIGNAL
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(OLD 3LEW 2ATE
ꢀ
6)(ꢁDCꢂMIN ꢃ 62%&ꢁDCꢂ
$ELTA 4&(
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Figure 76 Slew Rate Definition Nominal
Data Sheet
111
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
#+ꢂ #+ FOR T)3 AND T)(
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6
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TANGENT LINE ;62%&ꢀDCꢁ ꢄ 6),ꢀACꢁMAX=
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TANGENT LINE ;6)(ꢀACꢁMIN ꢄ 62%&ꢀDCꢁ=
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RISING
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TANGENT LINE ;6)(ꢀDCꢁMIN ꢄ 62%&ꢀDCꢁ=
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Figure 77 Slew Rate Definition Tangent
Data Sheet
112
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
8.3.5
Setup (tIS) and Hold (tIH) Time Derating Tables
1. For all input signals the total input setup time and
input hold time required is calculated by adding the
data sheet value to the derating value respectively.
Example: tIS(total setup tine) = tIS(base) + ∆tIS
2. For slow Slew Rate the total setup time might be
negative (i.e. a valid input signal will not have
reached VIH(ac) / VIL(ac) at the time of the rising clock)
a valid input signal is still required to complete the
transition and reach VIH(ac) / VIL(ac). For Slew Rates
in between the values listed in the next tables, the
derating values may be obtained by linear
interpolation. These values are not subject to
production test. They are verified only by design
and characterization.
Table 61
Derating Values for Input Setup and Hold Time (DDR2-667 & DDR2-800)
Command / Address Slew Rate CK, CK Differential Slew Rate
Unit Note
(V/ns)
2.0 V/ns
∆tIS
1.5 V/ns
∆tIS
1.0 V/ns
∆tIS
∆tIH
∆tIH
∆tIH
1)2)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
+150
+143
+133
+120
+100
+67
+94
+89
+83
+75
+45
+21
0
+180
+173
+163
+150
+130
+97
+124
+119
+113
+105
+75
+210
+203
+193
+180
+160
+127
+60
+55
+47
+38
+26
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1)
1)
1)
1)
1)
+51
1)
0
+30
+30
1)
–5
–14
+25
+16
1)
–13
–31
+17
–1
1)
–22
–54
+8
–24
1)
–34
–83
–4
–53
–23
–65
1)
–60
–125
–188
–292
–375
–500
–708
–1125
–30
–70
–95
0
–40
1)
–100
–168
–200
–325
–517
–1000
–158
–262
–345
–470
–678
–1095
–128
–232
–315
–440
–648
–1065
1)
–138
–170
–295
–487
–970
–108
–140
–265
–457
–940
1)
1)
1)
ps
1)
ps
1) For all input signals tIS(total) = tIS(base) + ∆tIS and tIH(total) = tIH(base) + ∆tIH
2) For slow slewrate the total setup time might be negative (i.e. valid input signal will not have reached VIH(ac) / VIL(ac) at the
time of the rising clock) a valid signal is still required to complete the transistion and reach VIH(ac) / VIL(ac). For slew rates in
between the values listed in the next tables, the derating values may be obtained by linear interpolation. These values are
not subject to production test. They are verified only by design and characterisation.
Data Sheet
113
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
Table 62
Derating Values for Input Setup and Hold Time (DDR2-400 & DDR2-533)
Command / Address Slew Rate CK, CK Differential Slew Rate
Unit Note
(V/ns)
2.0 V/ns
∆ tIS
1.5 V/ns
∆tIS
1.0 V/ns
∆tIS
∆tIH
∆tIH
∆tIH
1)2)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
+187
+179
+167
+150
+125
+83
+94
+89
+83
+75
+45
+21
0
+217
+209
+197
+180
+155
+113
+30
+124
+119
+113
+105
+75
+247
+239
+227
+210
+185
+143
+60
+49
+35
+17
–7
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1)
1)
1)
1)
1)
+51
1)
0
+30
1)
–11
–14
+19
+16
1)
–25
–31
+5
–1
1)
–43
–54
–13
–24
1)
–67
–83
–37
–53
–23
–65
1)
–110
–175
–285
–350
–525
–800
–1450
–125
–188
–292
–375
–500
–708
–1125
–80
–95
–50
1)
–145
–255
–320
–495
–770
–1420
–158
–262
–345
–470
–678
–1095
–115
–225
–290
–465
–740
–1390
–128
–232
–315
–440
–648
–1065
1)
1)
1)
1)
ps
1)
ps
1) For all input signals tIS(total) = tIS(base) + ∆tIS and tIH(total) = tIH(base) + ∆tIH
2) For slow slewrate the total setup time might be negative (i.e. valid input signal will not have reached VIH(ac) / VIL(ac) at the
time of the rising clock) a valid signal is still required to complete the transistion and reach VIH(ac) / VIL(ac). For slew rates in
between the values listed in the next tables, the derating values may be obtained by linear interpolation. These values are
not subject to production test. They are verified only by design and characterisation.
Data Sheet
114
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
Table 63
Derating Values for Data Setup and Hold Time of Differential DQS (DDR2-667 & DDR2-800)
DQS, DQS Differential Slew Rate1)2)
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns
1.0 V/ns
0.8 V/ns
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
tDS
tDH tDS
tDH tDS
tDH tDS tDH tDS tDH tDS tDH tDS
tDH tDS
tDH tDS
tDH
2.0 +100 +45 +100 +45 +100 +45 —
1.5 +67 +21 +67 +21 +67 +21 +97 +33 —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0
0
0
0
0
0
+12 +12 +24 +24 —
—
—
—
—
—
—
—
—
—
—
—
—
–5
—
—
—
—
—
–14 –5
–14 +7 –2 +19 +10 +31 +22 —
—
—
—
—
—
–13 –31 –1 –19 +11 –7 +23 +5 +35 +17
—
—
—
—
—
—
—
—
–10 –42 +2 –30 +14 –18 +26 –6
+38 +6
—
—
—
—
—
—
–10 –59 +2 –47 +14 –35 +26 –23 +538 –11
—
—
—
—
–24 –89 –12 –77
—
0
–65 +12 –53
—
–52 –140 –20 –28 –28 –116
1) All units in ps.
2) For all input signals tDS(total) = tDS(base) + ∆tDS and tDH(total) = tDH(base) + ∆tDH
Data Sheet
115
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
Table 64
Derating Values for Data Setup and Hold Time of Differential DQS (DDR2-400 & -533)
DQS, DQS Differential Slew Rate1)2)
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns
1.0 V/ns
0.8 V/ns
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
tDS
tDH tDS
tDH tDS
tDH tDS tDH tDS tDH tDS tDH tDS
tDH tDS
tDH tDS
tDH
2.0 +125 +45 +125 +45 +125 +45 —
1.5 +83 +21 +83 +21 +83 +21 +95 +33 —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–11
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0
0
0
0
0
0
+12 +12 +24 +24 —
—
—
—
—
—
—
—
—
—
—
—
—
–11 –14 –11 –14 +1 –2 +13 +10 +25 +22 —
—
—
—
—
—
—
—
—
—
—
–25 –31 –13 –19 –1 –7 +11 +5 +23 +17
—
—
—
—
—
—
—
—
–31 –42 –19 –30 –7 –18 +5
–6
+17 +6
—
—
—
—
—
—
–43 –59 –31 –47 –19 –35 –7
—
—
–23 +5
—
—
–74 –89 –62 –77 –50 –65 –38 –53
–127 –140 –115 –128 –103 –116
—
—
1) All units in ps.
2) For all input signals tDS(total) = tDS(base) + ∆tDS and tDH(total) = tDH(base) + ∆tDH
Table 65
DQS, DQS Single-ended Slew Rate1)2)
2.0 V/ns 1.5 V/ns 1.0 V/ns 0.9 V/ns 0.8 V/ns 0.7 V/ns
Derating Values for Data Setup and Hold Time of Single-ended DQS (DDR2-400 & -533)
0.6 V/ns
0.5 V/ns
0.4 V/ns
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1
2.0 +188 +188 +167 +146 +125 +63 —
1.5 +146 +167 +125 +125 +83 +42 +81 +43 —
1.0 +63 +125 +42 +83
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
-2 +1 -7 -13 —
0.9 —
0.8 —
0.7 —
0.6 —
0.5 —
0.4 —
—
—
—
—
—
—
+31 +69 -11
-14 -13 -13 -18 -27 -29 -45
-31 -27 -30 -32 -44 -43 -62 -60 –86
—
—
—
—
—
—
—
—
—
—
-25
—
—
—
—
—
—
—
—
-45 -53 -50 -67 -61 -85 -78 -109 -108 -152 —
—
—
—
—
—
—
-74 -96 -85 -114 -102 -138 -132 -181 -183 -246
—
—
—
—
-128 -156 -145 -180 -175 -223 -226 -288
—
—
-210 -243 -240 -286 -291 -351
1) All units in ps.
2) For all input signals tDS1(total) = tDS1(base) + ∆tDS1 and tDH1(total) = tDH1(base) + ∆tDH1
Data Sheet
116
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Package Dimensions
9
Package Dimensions
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Figure 78 Package Pinout PG-TFBGA-60 (top view)
Data Sheet
117
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Package Dimensions
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Figure 79 Package Pinout PG-TFBGA-84 (top view)
Data Sheet
118
Rev. 1.4, 2005-08
09112003-LZPT-I17F
HYB18T256[40/80/16]0AF(L)–[2.5/25F/3/3S/3.7/5]
256-Mbit DDR2 SDRAM
Product Namenclature
10
Product Namenclature
Table 66
Example for
Nomenclature Fields and Examples
Field Number
1
2
3
4
5
6
7
8
9
10
11
DDR2 DRAM
HYB
18
T
512
16
0
A
C
–3.7
Table 67
Field
1
DDR2 Memory Components
Description
INFINEON
Component Prefix
Values
HYB
Coding
Constant
2
3
4
Interface Voltage [V]
DRAM Technology
Component Density [Mbit]
18
T
SSTL_18
DDR2
256 M
512 M
1 Gb
×4
×8
x16
look up table
First
256
512
1G
40
80
160
0 .. 9
A
5+6
Number of I/Os
7
8
Product Variations
Die Revision
B
Second
9
Package,
Lead-Free Status
C
FBGA,
lead-containing
F
L
FBGA, lead-free
low power product
DDR2–800 6–6–6
DDR2–800 5–5–5
DDR2–667 4–4–4
DDR2–667 5–5–5
DDR2–533 4–4–4
DDR2–400 3–3–3
Power
10
Speed Grade
–2.5
–25F
–3
–3S
–3.7
–5
11
N/A for Components
Data Sheet
119
Rev. 1.4, 2005-08
09112003-LZPT-I17F
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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