HYB25D256800BEL-5A [INFINEON]
DDR DRAM, 32MX8, 0.5ns, CMOS, PDSO66, TSOP2-66;
| 型号： | HYB25D256800BEL-5A |
| 厂家： | 
Infineon |
| 描述： | DDR DRAM, 32MX8, 0.5ns, CMOS, PDSO66, TSOP2-66 动态存储器 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总29页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum Jan. 2003, V0.9
Features
• Data mask (DM) for write data
CAS Latency and Clock Frequency
• DLL aligns DQ and DQS transitions with CK
Maximum Operating Frequency (MHz)
transitions
CAS Latency
DDR400B
-5
DDR400A
-5A
• Commands entered on each positive CK edge;
data and data mask referenced to both edges of
DQS
2
2.5
3
133
166
200
133
200
200
• Burst Lengths: 2, 4, or 8
• CAS Latency: (1.5), 2, 2.5, (3)
• Double data rate architecture: two data transfers
per clock cycle
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• Bidirectional data strobe (DQS) is transmitted
and received with data, to be used in capturing
data at the receiver
• 7.8ꢀs Maximum Average Periodic Refresh
Interval (8k refresh)
• DQS is edge-aligned with data for reads and is
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.6V ± 0.1V / VDD = 2.6V ± 0.1V
• TSOP66 package
center-aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
Description
The 256Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing 268,435,456
bits. It is internally configured as a quad-bank DRAM.
dent with the Read or Write command are used to select
the bank and the starting column location for the burst
access.
The 256Mb DDR SDRAM uses a double-data-rate archi-
tecture to achieve high-speed operation. The double data
rate architecture is essentially a 2n prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access
for the 256Mb DDR SDRAM effectively consists of a sin-
gle 2n-bit wide, one clock cycle data transfer at the inter-
nal DRAM core and two corresponding n-bit wide, one-
half-clock-cycle data transfers at the I/O pins.
The DDR SDRAM provides for programmable Read or
Write burst lengths of 2, 4 or 8 locations. An Auto Pre-
charge function may be enabled to provide a self-timed
row precharge that is initiated at the end of the burst
access.
As with standard SDRAMs, the pipelined, multibank archi-
tecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row
precharge and activation time.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SDRAM during
Reads and by the memory controller during Writes. DQS
is edge-aligned with data for Reads and center-aligned
with data for Writes.
An auto refresh mode is provided along with a power-sav-
ing power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2,
Class II compatible.
Note: The functionality described and the timing specifi-
cations included in this data sheet are for the DLL Enabled
mode of operation.
The 256Mb DDR SDRAM operates from a differential
clock (CK and CK; the crossing of CK going HIGH and CK
going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read
or Write command. The address bits registered coincident
with the Active command are used to select the bank and
row to be accessed. The address bits registered coinci-
2003-01-10, V0.9
Page 1 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Ordering Information
CAS-RCD-RP Clock CAS-RCD-RP Clock CAS-RCD-RP Clock
a
Org.
Speed
Package
Part Number
Latencies
(MHz) Latencies
(MHz) Latencies
(MHz)
HYB25D256800BT(L)-5A x8 3-3-3
HYB25D256160BT(L)-5A x16
HYB25D256800BT(L)-5 x8
200 2.5-3-3
200
166
2-3-3
133
DDR400A 66 Pin TSOP-II
DDR400B
HYB25D256160BT(L)-5 x16
a. HYB: designator for memory components
25D: DDR-I SDRAMs at Vddq=2.5V
256: 256Mb density
400/800/160: Product variations x4, x8 and x16
B: Die revision B
C/T: Package type FBGA and TSOP
L: Low power version (optional) - these components are specifically selected for low IDD6 Self Refresh currents
-5: speed grade - see table
2003-01-10, V0.9
Page 2 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Pin Configuration (TSOP66)
VDD
NC
VDD
DQ0
VDDQ
DQ1
DQ2
VSS
VSS
VSS
NC
VDD
DQ0
VDDQ
NC
1
2
3
4
5
66
65
64
63
62
DQ15
VSSQ
DQ14
DQ13
DQ7
VSSQ
NC
VDDQ
NC
VSSQ
NC
DQ0
DQ6
DQ3
DQ1
VSSQ
NC
VSSQ
DQ3
DQ4
VDDQ
DQ5
VDDQ
VDDQ
NC
VDDQ
NC
VSSQ
NC
6
61
60
59
58
57
DQ12
DQ11
VSSQ
7
NC
DQ5
VSSQ
NC
NC
DQ2
VDDQ
NC
8
VDDQ
NC
VSSQ
NC
9
DQ10
10
DQ3
DQ1
VSSQ
NC
DQ6
VSSQ
DQ7
NC
DQ9
VDDQ
DQ4
VDDQ
DQ2
VDDQ
11
12
56
55
VSSQ
NC
DQ8
NC
NC
NC
13
14
15
16
17
18
19
20
54
53
52
51
50
49
48
47
NC
NC
NC
NC
VSSQ
UDQS
NC
VSSQ
DQS
NC
VSSQ
DQS
NC
VDDQ
NC
VDDQ
NC
VDDQ
LDQS
NC
VDD
NC
NC
NC
VDD
NC
NC
NC
VDD
VREF
VSS
VREF
VSS
DM
VREF
VSS
DM
NC
LDM
UDM
WE
CAS
WE
CAS
WE
CAS
CK
CK
CK
CK
CK
CK
21
22
23
46
45
44
RAS
RAS
RAS
CKE
CKE
CKE
CS
NC
CS
NC
CS
NC
NC
A12
NC
A12
NC
A12
24
25
43
42
BA0
BA1
BA0
BA1
BA0
BA1
A11
A9
A11
A9
A11
A9
26
27
41
40
A8
A8
A8
A10/AP
A10/AP
A10/AP
28
29
39
38
A7
A7
A7
A0
A1
A2
A0
A1
A2
A0
A1
A2
A6
A5
A6
A5
A6
A5
30
31
37
36
A3
VDD
A3
A3
A4
VSS
A4
VSS
A4
VSS
32
33
35
34
VDD
VDD
16Mb x 16
32Mb x 8
64Mb x 4
2003-01-10, V0.9
Page 3 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Input/Output Functional Description
Symbol
Type
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data
is referenced to the crossings of CK and CK (both directions of crossing).
CK, CK
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down
and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asyn-
chronous for self refresh exit. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input
buffers, excluding CKE, are disabled during self refresh.
CKE
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for exter-
nal bank selection on systems with multiple banks. CS is considered part of the command
code. The standard pinout includes one CS pin.
CS
Input
Input
RAS, CAS, WE
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and
DQS loading.
DM
Input
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Pre-
charge command is being applied. BA0 and BA1 also determines if the mode register or
extended mode register is to be accessed during a MRS or EMRS cycle.
BA0, BA1
Address Inputs: Provide the row address for Active commands, and the column address
and Auto Precharge bit for Read/Write commands, to select one location out of the memory
array in the respective bank. A10 is sampled during a Precharge command to determine
whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide
the op-code during a Mode Register Set command.
A0 - A12
Input
DQ
DQS
NC
Input/Output
Input/Output
Data Input/Output: Data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data.
No Connect: No internal electrical connection is present.
DQ Power Supply: 2.6V Mꢀ0.1V.
DQ Ground
V
V
Supply
Supply
Supply
Supply
Supply
DDQ
SSQ
V
Power Supply: 2.6V Mꢀ0.1V.
Ground
DD
V
SS
V
SSTL_2 reference voltage: (V
/ 2)
DDQ
REF
2003-01-10, V0.9
Page 4 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Block Diagram (32Mb x 8)
CKE
CK
CK
CS
WE
CAS
RAS
Bank3
Bank2
Bank1
CK, CK
DLL
Mode
Registers
13
8192
Bank0
Memory
Array
Data
13
(8192 x 512x 16)
8
8
16
Sense Amplifiers
8
1
DQS
Generator
DQ0-DQ7,
DM
COL0
Mask
DQS
Input
Register
1
I/O Gating
DM Mask Logic
16
2
DQS
1
1
A0-A12,
BA0, BA1
Write
15
1
FIFO
1
&
16
2
16
2
512
Drivers
(x16)
8
8
8
8
8
clk
clk
Column
Decoder
in
out
Data
9
COL0
CK,
CK
Column-Address
Counter/Latch
10
COL0
1
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
2003-01-10, V0.9
Page 5 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Block Diagram (16Mb x 16)
CKE
CK
CK
CS
WE
CAS
RAS
Bank3
Bank2
Bank1
CK, CK
DLL
Mode
13
Registers
8192
Bank0
Memory
Array
Data
1
13
(8192 x 256x 32)
16
16
16
32
Sense Amplifiers
DQS
Generator
DQ0-DQ15,
DM
COL0
Mask
DQS
Input
Register
1
I/O Gating
DM Mask Logic
32
2
LDQS, UDQS
1
A0-A11,
15
Write
1
BA0, BA1
FIFO
1
1
&
32
2
32
2
256
Drivers
(x32)
16
16
16
16
16
clk
clk
Column
Decoder
in
out
Data
8
COL0
CK,
CK
Column-Address
9
Counter/Latch
COL0
2
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: UDM and LDM are unidirectional signals (input only), but is internally loaded to match the
load of the bidirectional DQ , UDQS and LDQS signals.
2003-01-10, V0.9
Page 6 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Functional Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456
bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-
data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM consists of a
single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide,
one-half clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the regis-
tration of an Active command, which is then followed by a Read or Write command. The address bits regis-
tered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write com-
mand are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed infor-
mation covering device initialization, register definition, command descriptions and device operation.
Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation. The following criteria must be met:
No power sequencing is specified during power up or power down given the following criteria:
VDD and VDDQ are driven from a single power converter output AND
VTT meets the specification AND
VREF tracks VDDQ/2
or
The following relationship must be followed:
VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V
VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V
VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a
read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200ꢀs delay prior to applying an executable command.
Once the 200ꢀs delay has been satisfied, a Deselect or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode
Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode
Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operat-
ing parameters. 200 clock cycles are required between the DLL reset and any executable command. During
the 200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock
cycles, a Precharge ALL command should be applied, placing the device in the “all banks idle” state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set
command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters
without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal
operation.
2003-01-10, V0.9
Page 7 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Register Definition
Mode Register
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Reg-
ister is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored
information until it is programmed again or the device loses power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating either of these requirements results in unspecified opera-
tion.
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable.
The burst length determines the maximum number of column locations that can be accessed for a given
Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the
interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively
selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block
if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai
when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most
significant column address bit for a given configuration). The remaining (least significant) address bit(s) is
(are) used to select the starting location within the block. The programmed burst length applies to both Read
and Write bursts.
2003-01-10, V0.9
Page 8 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Mode Register Operation
BA1 BA0 A12
A11 A10 A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Address Bus
Mode Register
0*
0*
CAS Latency
Burst Length
Operating Mode
A12 - A9
0
A8
0
A7
0
A6 - A0
Valid
Operating Mode
A3
Burst Type
Sequential
Interleave
Normal operation
Do not reset DLL
0
1
Normal operation
in DLL Reset
0
1
0
Valid
0
0
1
Reserved
Reserved
ꢁ
ꢁ
ꢁ
CAS Latency
Burst Length
A6
A5
0
A4
0
Latency
Reserved
Reserved
2
A2
0
A1
0
A0
0
Burst Length
0
0
0
0
1
1
1
1
Reserved
2
0
1
0
0
1
1
0
0
1
0
4
1
1
3 (optional)
Reserved
1.5 (optional)
2.5
0
1
1
8
0
0
1
0
0
Reserved
Reserved
Reserved
Reserved
0
1
1
0
1
1
0
1
1
0
1
1
Reserved
1
1
1
* BA0 and BA1 must be 0, 0 to select the Mode Register
(vs. the Extended Mode Register).
2003-01-10, V0.9
Page 9 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Burst Definition
Starting Column Address
Order of Accesses Within a Burst
Burst Length
A2
A1
A0
Type = Sequential
Type = Interleaved
0-1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0-1
2
4
1-0
1-0
0
0
1
1
0
0
1
1
0
0
1
1
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0
0
0
0
0
1
1
1
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
8
Notes:
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the
block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within
the block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access
within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps
within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as
the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address, as shown in Burst Definition on page 10.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command
and the availability of the first burst of output data. The latency can be programmed 2, 2.5 or 3 clocks. CAS
latency of 1.5 is an optional feature on this device.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally
coincident with clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
2003-01-10, V0.9
Page 10 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to
zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set com-
mand with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A
Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set
command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and
reserved states should not be used as unknown operation or incompatibility with future versions may result.
Required CAS Latencies
CAS Latency = 2, BL = 4
CK
CK
Read
NOP
NOP
NOP
NOP
NOP
Command
CL=2
DQS
DQ
CAS Latency = 2.5, BL = 4
CK
CK
Read
NOP
NOP
NOP
NOP
NOP
Command
CL=2.5
DQS
DQ
Shown with nominal t , t
, and t
.
DQSQ
Don’t Care
AC DQSCK
2003-01-10, V0.9
Page 11 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these addi-
tional functions include DLL enable/disable, and output drive strength selection (optional). These functions
are controlled via the bits shown in the Extended Mode Register Definition. The Extended Mode Register is
programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored informa-
tion until it is programmed again or the device loses power. The Extended Mode Register must be loaded
when all banks are idle, and the controller must wait the specified time before initiating any subsequent oper-
ation. Violating either of these requirements result in unspecified operation.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and
upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The
DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit
of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur before a Read command
can be issued. This is the reason 200 clock cycles must occur before issuing a Read or Write command upon
exit of self refresh operation.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. In addition this design version
supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during
mode register set. I-V curves for the normal and weak drive strength are included in this document.
2003-01-10, V0.9
Page 12 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Extended Mode Register Definition
A
BA1 BA0
A
A
A
9
A
A
A
A
A
A
A
0
A
A
0
12
Address Bus
8
7
6
5
4
3
2
1
11
10
Extended
Mode Register
0*
1*
Operating Mode
DS
DLL
Drive Strength
An - A3
0
A2 - A0
Valid
Operating Mode
A
Drive Strength
Normal
1
Normal Operation
0
All other states
Reserved
ꢁ
ꢁ
1
Weak
A
2
0
must be set to 0
A
DLL
0
0
Enable
Disable
1
* BA0 and BA1 must be 1, 0 to select the Extended Mode Register
(vs. the base Mode Register)
2003-01-10, V0.9
Page 13 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Commands
CommandsDeselect
The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM
is effectively deselected. Operations already in progress are not affected.
No Operation (NOP)
The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted
commands from being registered during idle or wait states. Operations already in progress are not affected.
Mode Register Set
The mode registers are loaded via inputs A0-A12, BA0 and BA1. See mode register descriptions in the Reg-
ister Definition section. The Mode Register Set command can only be issued when all banks are idle and no
bursts are in progress. A subsequent executable command cannot be issued until tMRD is met.
Active
The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row.
This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is
issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and com-
pleted before opening a different row in the same bank.
Read
The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 8, j = don’t care] for
x16, [i = 9, j = don’t care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. The value on
input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being
accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open
for subsequent accesses.
Write
The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8;
where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or
not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end
of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input
data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coin-
cident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the
DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that
byte/column location.
Precharge
The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in
all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge
command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated
as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any
2003-01-10, V0.9
Page 14 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no
open row in that bank, or if the previously open row is already in the process of precharging.
Auto Precharge
Auto Precharge is a feature which performs the same individual-bank precharge functions described above,
but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in
conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the
Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Pre-
charge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command.
Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the precharge (tRP) is completed. This is determined as if
an explicit Precharge command was issued at the earliest possible time, as described for each burst type in
the Operation section of this data sheet.
Burst Terminate
The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-
cently registered Read command prior to the Burst Terminate command is truncated, as shown in the Opera-
tion section of this data sheet.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS
(CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a
refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t
Care” during an Auto Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an aver-
age periodic interval of 7.8 ꢀs (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight Auto Refresh commands can be posted in the system,
meaning that the maximum absolute interval between any Auto Refresh command and the next Auto Refresh
command is 9 * 7.8 ꢀs (70.2ꢀs). This maximum absolute interval is short enough to allow for DLL updates
internal to the DDR SDRAM to be restricted to Auto Refresh cycles, without allowing too much drift in tAC
between updates.
Self Refresh
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The
Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The
DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self
Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except
CKE (low) are “Don’t Care” during Self Refresh operation.
The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to
CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because
time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both
refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
2003-01-10, V0.9
Page 15 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Truth Table 1a: Commands
Name (Function)
CS
H
L
RAS CAS
WE
X
Address
X
MNE
NOP
NOP
ACT
Notes
1, 9
Deselect (Nop)
X
H
L
X
H
H
L
No Operation (Nop)
H
H
H
L
X
1, 9
Active (Select Bank And Activate Row)
Read (Select Bank And Column, And Start Read Burst)
Write (Select Bank And Column, And Start Write Burst)
Burst Terminate
L
Bank/Row
Bank/Col
Bank/Col
X
1, 3
L
H
H
H
L
Read
Write
BST
1, 4
L
L
1, 4
L
H
H
L
L
1, 8
Precharge (Deactivate Row In Bank Or Banks)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
Mode Register Set
L
L
Code
X
PRE
1, 5
L
L
H
L
AR / SR
MRS
1, 6, 7
1, 2
L
L
L
Op-Code
1. CKE is HIGH for all commands shown except Self Refresh.
2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0
selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the
selected Mode Register.)
3. BA0-BA1 provide bank address and A0-A12 provide row address.
4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8for x16, i = 9 for x8 and 9, 11 for x4); A10 HIGH
enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature.
5. A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW.
7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with
Auto Precharge enabled or for write bursts
9. Deselect and NOP are functionally interchangeable.
Truth Table 1b: DM Operation
Name (Function)
Write Enable
Write Inhibit
DM
L
DQs
Valid
X
Notes
1
1
H
1. Used to mask write data; provided coincident with the corresponding data.
2003-01-10, V0.9
Page 16 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Truth Table 2: Clock Enable (CKE)
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
CKE n-1
CKEn
Current State
Command n
Action n
Notes
Previous Current
Cycle
Cycle
Self Refresh
Self Refresh
Power Down
Power Down
All Banks Idle
All Banks Idle
Bank(s) Active
L
L
L
H
L
X
Maintain Self-Refresh
Deselect or NOP
X
Exit Self-Refresh
1
L
Maintain Power-Down
Exit Power-Down
L
H
L
Deselect or NOP
Deselect or NOP
AUTO REFRESH
Deselect or NOP
H
H
H
Precharge Power-Down Entry
Self Refresh Entry
L
L
Active Power-Down Entry
See “Truth Table 3: Current State
Bank n - Command to Bank n
(Same Bank)” on page 18
H
H
1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t
) period. A mini-
XSNR
mum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
2003-01-10, V0.9
Page 17 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State
Any
CS
H
RAS CAS
WE
X
Command
Deselect
Action
Notes
1-6
X
H
L
X
H
H
NOP. Continue previous operation
NOP. Continue previous operation
L
H
No Operation
1-6
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
Active
AUTO REFRESH
MODE REGISTER SET
Read
Select and activate row
1-6
1-7
Idle
L
L
L
L
1-7
H
H
L
L
H
L
Select column and start Read burst
Select column and start Write burst
Deactivate row in bank(s)
1-6, 10
1-6, 10
1-6, 8
Row Active
L
Write
H
L
L
Precharge
Read
H
L
H
L
Select column and start new Read burst
Truncate Read burst, start Precharge
BURST TERMINATE
1-6, 10
1-6, 8
Read
(Auto Precharge
Disabled)
H
H
L
Precharge
BURST TERMINATE
Read
H
H
H
L
L
1-6, 9
H
L
Select column and start Read burst
Select column and start Write burst
Truncate Write burst, start Precharge
1-6, 10, 11
1-6, 10
1-6, 8, 11
Write
(Auto Precharge
Disabled)
L
Write
H
L
Precharge
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after t
has been met (if the previous state was self refresh).
t
XSNR / XSRD
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those
allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and t has been met.
RP
Row Active:
A row in the bank has been activated, and t
accesses are in progress.
has been met. No data bursts/accesses and no register
RCD
Read:
Write:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
Precharging:
Starts with registration of a Precharge command and ends when t is met. Once t is met, the bank is in the
RP
RP
idle state.
Row Activating: Starts with registration of an Active command and ends when t
“row active” state.
is met. Once t
is met, the bank is in the
RCD
RCD
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when t
RP
RP
has been met. Once t is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when t
RP
has been met. Once t is met, the bank is in the idle state.
RP
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and according Truth Table 4.
5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each
positive clock edge during these states.
Refreshing:
Starts with registration of an Auto Refresh command and ends when t
SDRAM is in the “all banks idle” state.
is met. Once t
is met, the DDR
RFC
RFC
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when t
has been met. Once
MRD
t
is met, the DDR SDRAM is in the “all banks idle” state.
MRD
Precharging All: Starts with registration of a Precharge All command and ends when t is met. Once t is met, all banks is in
RP
RP
the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes
with Auto Precharge disabled.
11. Requires appropriate DM masking.
2003-01-10, V0.9
Page 18 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
Current State
Any
CS
H
RAS CAS
WE
X
Command
Deselect
Action
Notes
1-6
X
H
X
H
NOP/continue previous operation
NOP/continue previous operation
L
H
No Operation
1-6
Any Command Otherwise
Allowed to Bank m
Idle
X
X
X
X
1-6
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
L
Active
Read
Select and activate row
1-6
1-7
Row Activating,
Active, or
Precharging
Select column and start Read burst
Select column and start Write burst
L
Write
1-7
H
H
L
L
Precharge
Active
1-6
L
H
H
L
Select and activate row
1-6
Read
(Auto Precharge
Disabled)
H
L
Read
Select column and start new Read burst
1-7
H
H
L
Precharge
Active
1-6
L
H
H
L
Select and activate row
1-6
Write
(Auto Precharge
Disabled)
H
H
L
Read
Select column and start Read burst
Select column and start new Write burst
1-8
L
Write
1-7
H
H
L
L
Precharge
Active
1-6
L
H
H
L
Select and activate row
1-6
H
H
L
Read
Select column and start new Read burst
Select column and start Write burst
1-7,10
1-7,9,10
1-6
Read (With
Auto Precharge)
L
Write
H
H
L
L
Precharge
Active
L
H
H
L
Select and activate row
1-6
H
H
L
Read
Select column and start Read burst
Select column and start new Write burst
1-7,10
1-7,10
1-6
Write (With
Auto Precharge)
L
Write
H
L
Precharge
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after t
has been met (if the previous state was self refresh).
t
XSNR / XSRD
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown
are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Excep-
tions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and t has been met.
RP
Row Active:
A row in the bank has been activated, and t has been met. No data bursts/accesses and no register
RCD
accesses are in progress.
Read:
Write:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
4. AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes
with Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. Concurrent Auto Precharge:
This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is enabled any
command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other
limitations apply (e.g. contention between READ data and WRITE data must be avoided). The mimimum delay from a read or write
command with auto precharge enable, to a command to a different banks is summarized in table 5.
2003-01-10, V0.9
Page 19 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Truth Table 5: Concurrent Auto Precharge
Minimum Delay with Con-
current Auto Precharge
Support
To Command
From Command
Units
(different bank)
Read or Read w/AP
1 + (BL/2) + tWTR
tCK
tCK
tCK
tCK
tCK
tCK
WRITE w/AP
Read w/AP
Write ot Write w/AP
Precharge or Activate
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
BL/2
1
BL/2
CL (rounded up)+ BL/2
1
2003-01-10, V0.9
Page 20 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Simplified State Diagram
Power
Applied
Power
On
Self
Refresh
Precharge
PREALL
REFS
REFSX
REFA
MRS
EMRS
Auto
Refresh
MRS
Idle
CKEL
CKEH
Active
Power
Down
ACT
Precharge
Power
Down
CKEH
CKEL
Burst Stop
Row
Active
Read
Write
Write A
Read A
Write
Read
Read
Read A
Write A
Read
A
PRE
Write
A
Read
A
PRE
PRE
Precharge
PREALL
PRE
Automatic Sequence
Command Sequence
PREALL = Precharge All Banks
MRS = Mode Register Set
EMRS = Extended Mode Register Set
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
REFA = Auto Refresh
CKEL = Enter Power Down
CKEH = Exit Power Down
ACT = Active
Write A = Write with Autoprecharge
Read A = Read with Autoprecharge
PRE = Precharge
2003-01-10, V0.9
Page 21 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Operating Conditions
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
V
V
, V
Voltage on I/O pins relative to V
ꢁ0.5 to VDDQꢂꢃ0.5
ꢁ0.5 to ꢂ3.6
IN
OUT
SS
V
Voltage on Inputs relative to V
V
IN
SS
V
DD
Voltage on V supply relative to V
ꢁ0.5 to ꢂ3.6
V
DD
SS
V
Voltage on V
supply relative to V
SS
ꢁ0.5 to ꢂ3.6
0 to ꢂ70
ꢁ55 to ꢂ150
1.0
V
DDQ
DDQ
T
Operating Temperature (Ambient)
Storage Temperature (Plastic)
Power Dissipation
LC
LC
W
A
T
STG
P
D
I
Short Circuit Output Current
50
mA
OUT
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sec-
tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Input and Output Capacitances
Parameter
Input Capacitance: CK, CK
Package
TSOP
TSOP
TSOP
TSOP
TSOP
TSOP
Symbol
Min.
2.0
-
Max.
3.0
Units
pF
Notes
C
1
1
I1
Delta Input Capacitance CK, CK
C
C
0.25
3.0
pF
dI1
Input Capacitance: All other input-only pins
Delta Input Capacitance: All other input-only pins
Input/Output Capacitance: DQ, DQS, DM
Delta Input/Output Capacitance : DQ, DQS, DM
C
2.0
-
pF
1
I2
0.5
pF
1
dI2
C
4.0
-
5.0
pF
1, 2
1
IO
C
0.5
pF
dIO
1. These values are guaranteed by design and are tested on a sample base only. V
= V = 2.6V ± 0.1V, f = 100MHz, T = 25LC,
DD A
DDQ
V
(DC) = V
, VOUT (Peak to Peak) 0.2V. Unused pins are tied to ground .
OUT
DDQ/2
2. DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching
at the board level
2003-01-10, V0.9
Page 22 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Electrical Characteristics and DC Operating Conditions
(0°C ? TAꢃ?ꢃ70LC; VDDQ = 2.6V Mꢃ0.1V, VDD = ꢂꢃ2.6V Mꢃ0.1V )
Symbol
Parameter
Min
2.50
2.50
0
Max
Units Notes
V
Supply Voltage
2.70
V
V
V
V
V
V
V
V
V
1, 2
1, 2
DD
V
I/O Supply Voltage
2.70
DDQ
V
, V
Supply Voltage, I/O Supply Voltage
I/O Reference Voltage
0
SS
SSQ
V
V
/2-50mV
V
/2+50mV
DDQ
2, 3
2, 4
2
REF
DDQ
V
I/O Termination Voltage (System)
Input High (Logic1) Voltage
V
V
ꢁ 0.04
ꢂ 0.15
V
ꢂ 0.04
REF
TT
REF
REF
V
V
ꢂ 0.3
IH(DC)
DDQ
V
Input Low (Logic0) Voltage
ꢁꢀ0.3
V
ꢁ 0.15
REF
2
IL(DC)
IN(DC)
ID(DC)
V
V
Input Voltage Level, CK and CK Inputs
Input Differential Voltage, CK and CK Inputs
VI-Matching Pullup Current to Pulldown Current
ꢁꢀ0.3
0.36
0.71
V
ꢂ 0.3
ꢂ 0.6
2
DDQ
DDQ
V
2, 5
6
VI
1.4
Ratio
Input Leakage Current. Any input 0V ? V ?ꢃV
(All other pins not under test ꢄ 0V)
IN
DD
I
ꢁꢀ2
ꢁꢀ5
2
5
ꢃA
ꢃA
2
2
I
Output Leakage Current
I
OZ
(DQs are disabled; 0V ? V ?ꢃV
out
DDQ
I
Output High Current, Normal Strength Driver (VOUT ꢄ 1.95 V)
Output Low Current, Normal Strength Driver (VOUT ꢄ 0.35 V)
ꢁꢀ16.2
mA
mA
OH
I
16.2
OL
1. This is the DC voltage supplied at the DRAM and is inclusive all noise up to 10MHz. The DRAM does not generate any noise that
exceeds ±150mV above 10MHz and does meet full functionality with up to ±150mV above 10MHz at the DRAM that is generated
by the DRAM itself. Any noise above 10MHz at the DRAM generated from any other source than the DRAM itself may not exceed
the DC voltage range of 2.6V ±100mV. The AC and DC tolerances of the data sheet are additive.
2. Inputs are not recognized as valid until VREF stabilizes.
3. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed ± 2% of the DC value.
4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set
equal to VREF, and must track variations in the DC level of VREF
.
5. VID is the magnitude of the difference between the input level on CK and the input level on CK
6. The ration of the pullup current to the pulldown current is specified for the same temperature and voltage, over the
entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0V. For a given output, it rep-
resents the maximum difference between pullup and pulldown drivers due to process variation.
2003-01-10, V0.9
Page 23 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
IDD Specification and Conditions
(0 LC ?ꢀTA ?ꢀ70ꢀLCꢁꢀVDDQ = 2.5V Mꢀ0.2V; VDD = 2.5V Mꢀ0.2V)
DDR200
-8
DDR266A
-7
DDR266
-7F
DDR333
-6
DDR400A/B
-5
Notes
4
Symbol Parameter/Condition
Unit
typ. max. typ. max. typ. max. typ. max. typ.
max.
115
120
125
135
x4/x8
x16
70 90 75 100 83 110 85 110
72 95 77 105 86 115 88 115
80 100 90 110 98 120 100 120
83 105 94 115 102 125 104 125
90
mA
mA
mA
mA
Operating Current
: one bank; active / precharge; tRC = tRC MIN;
IDD0 DQ, DM, and DQS inputs changing once per clock cycle; address
and control inputs changing once every two clock cycles
1, 2
1, 2
1,2
1,2
1,2
1,2
1, 2
1, 2
1, 2
1,2
1, 2, 3
1,2
100
105
115
x4/x8
x16
Operating Current
: one bank; active/read/precharge;
IDD1 burst length 4;
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current
CKE <= VIL MAX
: all banks idle; power-down mode;
IDD2P
5
7
6
8
6
8
6
9
6
9
mA
mA
mA
mA
Precharge Floating Standby Current
: /CS>=VIHMIN, all banks idle;
IDD2F CKE >= VIH MIN; address and other control inputs changing once per clock cycle, VIN 30 35 35 40 35 40 45 55
= VREF for DQ, DQS and DM.
46
24
17
56
34
24
Precharge Quiet Standby Current
: /CS>=VIHMIN, all banksidle;
IDD2Q CKE >= VIH MIN; address and other control inputs stable
at >= VIHMINor <=VILMAX; VIN = VREF for DQ, DQS and DM.
18 22 20 25 20 25 25 28
Active Power-Down Standby Current
: one bank active; power-down mode;
CKE <= VIL MAX; VIN = VREF for DQ, DQS and DM.
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
13 16 15 18 15 18 18 21
Active Standby Current
: one bank active; CS >= VIH MIN;
x4/x8
x16
40 45 50 55 50 55 60 65
42 50 52 60 52 60 63 70
79 95 95 115 95 115 110 140
89 110 107 130 107 130 124 160
85 105 105 125 105 125 125 145
96 120 119 140 119 140 141 165
57
60
69
74
mA
mA
mA
mA
mA
mA
CKE >= VIH MIN; tRC=tRASMAX; DQ, DM, and DQS inputs
changing twice per clock cycle; address and control inputs changing
onceper clock cycle
Operating Current
: one bank active; BL2; reads; continuous burst;
x4/x8
x16
115
140
125
150
145
175
150
180
address and control inputs changing once per clock cycle; 50%of
data outputs changing on every clock edge; CL2 for DDR200 and
DDR266(A), CL3 for DDR333 and DDR400; IOUT = 0mA
Operating Current
: one bank active; Burst = 2; writes; continuous
x4/x8
x16
burst; address and control inputs changing once per clock cycle;
50%of data outputs changing on every clock edge; CL2 for
DDR200 and DDR266(A), CL3 for DDR333 and DDR400
Auto-Refresh Current
: tRC=tRFCMIN, distributed refresh
126 170 135 180 135 180 144 190
155
1.6
195
mA
standard version 1.5 2.5 1.5 2.5 1.5 2.5 1.5 2.5
2.6
1.30
280
310
mA
mA
Self-RefreshCurrent
IDD6
: CKE <= 0.2V; external clock on
lowpower version 1.20 1.25 1.20 1.25 1.20 1.25 1.20 1.25 1.25
x4/x8
x16
150 210 171 225 171 225 208 270
158 220 180 235 180 235 218 285
240
260
Operating Current
: four bank; four bank interleaving with burst
IDD7 length 4;
Refer to the following page for detailed test conditions.
mA
1. IDDspecifications are tested after the device is properly initialized and measured
at 100 MHz for DDR200, 133 MHz for DDR266(A) and 166 MHz for DDR333
2. Input slewrate = 1V/ns.
3. Enables on-chip refresh and address counters
4. Test conditionfor typical values: VDD=2.5V,Ta=25°C, test conditionfor maximumvalues: test limit at VDD= 2.7V ,Ta = 10°C
2003-01-10, V0.9
Page 24 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Detailed test conditions for DDR SDRAM IDD1 and IDD7
IDD1 : Operating current : One bank operation
1. Only one bank is accessed with tRC(min) , Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0 mA
2. Timing patterns
- DDR200 (100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRCD = 2 * tCK, tRAS = 5 * tCK
Setup: A0 N R0 N N P0 N
Read : A0 N R0 N N P0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRCD = 3 * tCK, tRC = 9 * tCK, tRAS = 5 * tCK
Setup: A0 N N R0 N P0 N N N
Read : A0 N N R0 N P0 N NN - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333 (166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRCD = 3 * tCK, tRC = 9 * tCK, tRAS = 5 * tCK
Setup: A0 N N R0 N P0 N N N
Read : A0 N N R0 N P0 N N N - repeat the same timing with random address changing
50% of data changing at every burst
3.Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7 : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min) , Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0 mA
2. Timing patterns
- DDR200 (100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRRD = 2 * tCK, tRCD= 3 * tCK, Read with autoprecharge
Setup: A0 N A1 R0 A2 R1 A3 R2
Read : A0 R3 A1 R0 A2 R1 A3 R2- repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRRD = 2 * tCK, tRCD = 3 * tCK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333 (166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRRD = 2 * tCK, tRCD = 3 * tCK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
3.Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
2003-01-10, V0.9
Page 25 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
AC Characteristics
(Notes 1-6 apply to the following Tables: Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS
.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. The figure below represents the timing reference load used in defining the relevant timing parameters of the part. It is
not intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing ref-
erence load to a system environment. Manufacturers will correlate to their production test conditions (generally a
coaxial transmission line terminated at the tester electronics).
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still refer-
enced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC
input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between
VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively
switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not
ring back above (below) the DC input LOW (HIGH) level)
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating,DDR SDRAM
Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest JEDEC
specification for DDR components
AC Output Load Circuit Diagram / Timing Reference Load
VTT
50ꢅ
Output
Timing Reference Point
(VOUT
)
30pF
AC Operating Conditions )
(0 °C ?ꢀTA ?ꢀ70ꢀLCꢁꢀVDDQ = 2.6V Mꢀ0.1V; VDD = 2.6V Mꢀ0.1V)
Symbol
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
Input Differential Voltage, CK and CK Inputs
Min
+ 0.31
REF
Max
Unit
V
Notes
1, 2
V
V
IH(AC)
V
V
ꢁ 0.31
REF
V
1, 2
IL(AC)
ID(AC)
IX(AC)
V
V
0.7
V
+ 0.6
V
1, 2, 3
1, 2, 4
DDQ
Input Closing Point Voltage, CK and CK Inputs
0.5*V
ꢁ 0.2 0.5*V
ꢂ 0.2
DDQ
V
DDQ
1. Input slew rate = 1V/nsꢄ
2. Inputs are not recognized as valid until V
stabilizes.
REF
3. V is the magnitude of the difference between the input level on CK and the input level on CK.
ID
4. The value of V is expected to equal 0.5*V
of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
2003-01-10, V0.9
Page 26 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Electrical Characteristics & AC Timing - Absolute Specifications
(0 LC ?ꢀTA ?ꢀ70ꢀLCꢁꢀVDDQ = 2.6V Mꢀ0.1V; VDD = 2.6V Mꢀ0.1V) (Part 1 of 2)
DDR400A
-5A
DDR400B
-5
Symbol
Parameter
Unit Notes
Min.
-0.5
Max.
+0.5
+0.55
0.55
Min.
Max.
+0.5
+0.55
0.55
t
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
-0.5
-0.55
0.45
0.45
ns
ns
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
AC
t
-0.55
0.45
0.45
DQSCK
t
t
CH
CK
CK
t
CK low-level width
0.55
0.55
t
CL
HP
CK
CK
CK
DH
t
t
t
t
Clock Half Period
min (t , t
)
min (t , t
)
ns
ns
ns
ns
ns
ns
CL CH
CL CH
CL = 3.0
5
10
5
10
Clock cycle time
CL = 2.5
CL = 2.0
5
10
10
6
10
10
7.5
0.40
0.40
2.2
1.75
7.5
0.40
0.40
2.2
1.75
t
DQ and DM input hold time
DQ and DM input setup time
t
DS
t
Control & Addr. input pulse width (each input)
DQ and DM input pulse width (each input)
Data-out high-impedence time from CK/CK
Data-out low-impedence time from CK/CK
ns 1-4,10
ns 1-4, 10
ns 1-4, 5
ns 1-4, 5
IPW
t
DIPW
t
+0.65
+0.65
+0.65
+0.65
HZ
t
-0.65
0.72
-0.65
0.72
LZ
Write command to 1st DQS latching
transition
t
1.28
1.28
t
1-4
1-4
DQSS
DQSQ
CK
DQS-DQ skew
(DQS & associated DQ signals)
t
+0.4
+0.5
+0.4
+0.5
ns
t
Data hold skew factor
ns
1-4
1-4
1-4
1-4
1-4
1-4
QHS
t
DQ output hold time from DQS
DQS input low (high) pulse width (write cycle)
DQS falling edge to CK setup time (write cycle)
DQS falling edge hold time from CK (write cycle)
Mode register set command cycle time
Write preamble setup time
t
-t
t
-t
QH
HP QHS
HP QHS
ns
t
t
0.35
0.2
0.2
2
0.35
0.2
0.2
2
t
DQSL,H
CK
CK
CK
CK
t
t
t
t
DSS
DSH
t
t
MRD
WPRES
0
0
ns 1-4, 7
t
Write postamble
0.40
0.25
0.60
0.40
0.25
0.60
t
t
1-4, 6
1-4
WPST
WPRE
CK
CK
t
Write preamble
Address and control input setup
t
fast slew rate
time
0.6
0.6
0.6
0.6
ns
ns
IS
2-4,
10,11
Address and control input hold
t
fast slew rate
time
IH
t
Read preamble
0.9
0.40
40
1.1
0.60
0.9
0.40
40
1.1
0.60
t
1-4
1-4
1-4
1-4
RPRE
CK
CK
t
Read postamble
t
RPST
t
Active to Precharge command
Active to Active/Auto-refresh command period
70,000
70,000
ns
ns
RAS
t
55
55
RC
Auto-refresh to Active/Auto-refresh command
period
t
65
65
ns
1-4
RFC
2003-01-10, V0.9
Page 27 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Electrical Characteristics & AC Timing - Absolute Specifications
(0 LC ?ꢀTA ?ꢀ70ꢀLCꢁꢀVDDQ = 2.6V Mꢀ0.1V; VDD = 2.6V Mꢀ0.1V) (Part 2 of 2)
DDR400A
-5A
DDR400B
-5
Symbol
Parameter
Unit Notes
Min.
15
Max.
Min.
Max.
t
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B command
Write recovery time
15
15
15
10
15
ns
ns
ns
ns
ns
1-4
1-4
1-4
1-4
1-4
RCD
t
15
RP
t
15
RAP
RRD
t
10
t
15
WR
DAL
WTR
Auto precharge write recovery
+ precharge time
t
t
1-4,9
CK
t
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
1
1
t
1-4
1-4
1-4
CK
t
t
75
75
ns
XSNR
XSRD
200
200
t
CK
Average Periodic Refresh Interval (8192 refresh
commands per 64ms refresh period)
t
7.8
7.8
ꢃs 1-4, 8
REFI
1. Input slew rate >= 1V/ns for DDR400
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the
input reference level for signals other than CK/CK, is V CK/CK slew rate are >= 1.0 V/ns
REF.
3. Inputs are not recognized as valid until V
stabilizes.
REF
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics
(Note 3) is V
.
TT
5. t and t transitions occur in the same access time windows as valid data transitions. These parameters are
HZ
LZ
not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving
(LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this
parameter, but system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this
CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device.
When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a
previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time,
depending on t
.
DQSS
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual sys-
tem clock cycle time.
10. These parameters guarantee device timing, but they are not necessarilty tested on each device
11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew
rate >1.0 V/ns, measured between VOH(ac) and VOL(ac)
2003-01-10, V0.9
Page 28 of 29
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Electrical Characteristics & AC Timing for DDR400 - Applicable Specifications
Expressed in Clock Cycles (0 LC ?ꢀTA ?ꢀ70ꢀLCꢁꢀVDDQ = 2.6V Mꢀ0.1V; VDD = 2.6V Mꢀ0.1V,
DDR400A/B
Symbol
Parameter
Units
Notes
Min
2
Max
t
Mode register set command cycle time
t
t
t
t
1-54
1-5
1-5
1-5
MRD
CK
CK
CK
CK
t
Write preamble
0.25
8
WPRE
t
Active to Precharge command
Active to Active/Auto-refresh command period
16000
RAS
t
11
RC
Auto-refresh to Active/Auto-refresh
command period
t
13
t
1-5
RFC
RCD
CK
t
Active to Read or Write delay
3
3
t
t
t
t
t
t
t
t
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
CK
CK
CK
CK
CK
CK
CK
CK
t
Precharge command period
RP
t
Active bank A to Active bank B command
Write recovery time
2
RRD
t
3
WR
DAL
WTR
t
Auto precharge write recovery + precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
5
t
1
t
10
200
XSNR
XSRD
t
1. Input slew rate = 1V/ns
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for
signals other than CK/CK, is V
REF.
3. Inputs are not recognized as valid until V
stabilizes.
REF
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V
.
TT
5. t and t transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a spe-
HZ
LZ
cific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
2003-01-10, V0.9
Page 29 of 29
相关型号：
©2020 ICPDF网 联系我们和版权申明