HYB25D512160AEL-7_技术文档

HYB25D512400/800/160AT(L)

512-MBit Double Data Rata SDRAM

Preliminary Datasheet V0.91, 2002-11-14

Features

• DLL aligns DQ and DQS transitions with CK

transitions

CAS Latency and Frequency

Maximum Operating Frequency (MHz)

• Commands entered on each positive CK edge;

data and data mask referenced to both edges of

DQS

CAS Latency

DDR200

-8

DDR266A

-7

DDR333

-6

2

100

125

133

143

133

166

2.5

• Burst Lengths: 2, 4, or 8

• CAS Latency: (1.5), 2, 2.5, 3

• Double data rate architecture: two data transfers

per clock cycle

• Auto Precharge option for each burst access

• Auto Refresh and Self Refresh Modes

• Bidirectional data strobe (DQS) is transmitted

and received with data, to be used in capturing

data at the receiver

• 7.8ꢀs Maximum Average Periodic Refresh

Interval

• DQS is edge-aligned with data for reads and is

center-aligned with data for writes

• 2.5V (SSTL_2 compatible) I/O

• V_DDQ= 2.5V Mꢁ0.2V

• V_DD= 2.5V Mꢁ0.2V

• Differential clock inputs (CK and CK)

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• TSOP66 package

Description

The 512Mb DDR SDRAM is a high-speed CMOS,

dynamic random-access memory containing 536,870,912

bits. It is internally configured as a quad-bank DRAM.

dent with the Read or Write command are used to select

the bank and the starting column location for the burst

access.

The 512Mb DDR SDRAM uses a double-data-rate archi-

tecture to achieve high-speed operation. The double data

rate architecture is essentially a 2n prefetch architecture

with an interface designed to transfer two data words per

clock cycle at the I/O pins. A single read or write access

for the 512Mb DDR SDRAM effectively consists of a sin-

gle 2n-bit wide, one clock cycle data transfer at the inter-

nal DRAM core and two corresponding n-bit wide, one-

half-clock-cycle data transfers at the I/O pins.

The DDR SDRAM provides for programmable Read or

Write burst lengths of 2, 4 or 8 locations. An Auto Pre-

charge function may be enabled to provide a self-timed

row precharge that is initiated at the end of the burst

access.

As with standard SDRAMs, the pipelined, multibank archi-

tecture of DDR SDRAMs allows for concurrent operation,

thereby providing high effective bandwidth by hiding row

precharge and activation time.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver.

DQS is a strobe transmitted by the DDR SDRAM during

Reads and by the memory controller during Writes. DQS

is edge-aligned with data for Reads and center-aligned

with data for Writes.

An auto refresh mode is provided along with a power-sav-

ing power-down mode. All inputs are compatible with the

JEDEC Standard for SSTL_2. All outputs are SSTL_2,

Class II compatible.

Note: The functionality described and the timing specifi-

cations included in this data sheet are for the DLL Enabled

mode of operation.

The 512Mb DDR SDRAM operates from a differential

clock (CK and CK; the crossing of CK going HIGH and CK

going LOW is referred to as the positive edge of CK).

Commands (address and control signals) are registered at

every positive edge of CK. Input data is registered on both

edges of DQS, and output data is referenced to both

edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst

oriented; accesses start at a selected location and con-

tinue for a programmed number of locations in a pro-

grammed sequence. Accesses begin with the registration

of an Active command, which is then followed by a Read

or Write command. The address bits registered coincident

with the Active command are used to select the bank and

row to be accessed. The address bits registered coinci-

V0.91, 2002-11-14

Page 1 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Ordering Information

CAS

Latency

Clock

(MHz)

CAS

Latency

Clock

(MHz)

Part Number (INF)

Speed

Org.

Package

HYB25D512400AT(L)-8 *)

HYB25D512800AT(L)-8

HYB25D512160AT(L)-8

x 4

x 8

125

143

166

100

133

DDR200

x 16

HYB25D512400AT(L)-7

HYB25D512800AT(L)-7

HYB25D512160AT(L)-7

x 4

x 8

2.5

2

DDR266A

DDR333

66 pin TSOP-II

x 16

HYB25D512400AT(L)-6

HYB25D512800AT(L)-6

HYB25D512160AT(L)-6

x 4

x 8

x 16

*) Low Power Versions have a “L” in the partnumber, e. g. HYB25D512400ATL-8.

These components are specifically selected for low IDD6 Self Refresh currents.

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Page 2 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Pin Configuration TSOP66

V_DD

DQ0

V_DDQ

NC

V_SS

NC

1

2

3

4

5

66

65

64

63

62

NC

V_DDQ

NC

DQ0

V_DDQ

DQ1

DQ2

V_SSQ

DQ3

DQ4

V_DDQ

DQ5

DQ15

V_SSQ

DQ14

DQ13

DQ7

V_SSQ

NC

V_SSQ

NC

DQ0

V_SSQ

NC

DQ6

DQ3

DQ1

V_DDQ

DQ12

DQ11

V_SSQ

V_DDQ

NC

V_DDQ

NC

V_SSQ

NC

6

61

60

59

58

57

7

NC

DQ5

V_SSQ

NC

DQ2

V_DDQ

NC

8

V_DDQ

NC

V_SSQ

NC

9

DQ10

10

DQ3

DQ1

V_SSQ

NC

DQ6

V_SSQ

DQ7

NC

DQ9

V_DDQ

DQ4

V_DDQ

DQ2

V_DDQ

11

12

56

55

V_SSQ

NC

DQ8

NC

13

14

15

16

17

18

19

20

54

53

52

51

50

49

48

47

NC

V_SSQ

UDQS

NC

V_SSQ

DQS

NC

V_SSQ

DQS

NC

V_DDQ

NC

V_DDQ

NC

V_DDQ

LDQS

NC

V_DD

NC

V_DD

NC

V_DD

NC

V_REF

V_SS

V_REF

V_SS

DM

V_REF

V_SS

DM

NC

LDM

UDM

WE

CAS

WE

CAS

WE

CAS

CK

21

22

23

46

45

44

RAS

CKE

CS

NC

CS

NC

CS

NC

A12

NC

A12

NC

A12

24

25

43

42

BA0

BA1

BA0

BA1

BA0

BA1

A11

A9

A11

A9

A11

A9

26

27

41

40

A8

A10/AP

28

29

39

38

A7

A0

A1

A2

A0

A1

A2

A0

A1

A2

A6

A5

A6

A5

A6

A5

30

31

37

36

A3

V_DD

A3

V_DD

A4

V_SS

A4

V_SS

A4

V_SS

32

33

35

34

V_DD

32Mb x 16

64Mb x 8

128Mb x 4

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Input/Output Functional Description

Symbol

Type

Function

Clock: CK and CK are differential clock inputs. All address and control input signals are sam-

pled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data

is referenced to the crossings of CK and CK (both directions of crossing).

CK, CK

Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and

device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down

and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).

CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asyn-

chronous for self refresh exit. CKE must be maintained high throughout read and write

accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input

buffers, excluding CKE, are disabled during self refresh.

CKE

Input

Chip Select: All commands are masked when CS is registered HIGH. CS provides for exter-

nal bank selection on systems with multiple banks. CS is considered part of the command

code. The standard pinout includes one CS pin.

CS

Input

RAS, CAS, WE

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM

is sampled HIGH coincident with that input data during a Write access. DM is sampled on

both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and

DQS loading.

DM

Input

Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Pre-

charge command is being applied. BA0 and BA1 also determines if the mode register or

extended mode register is to be accessed during a MRS or EMRS cycle.

BA0, BA1

Address Inputs: Provide the row address for Active commands, and the column address

and Auto Precharge bit for Read/Write commands, to select one location out of the memory

array in the respective bank. A10 is sampled during a Precharge command to determine

whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one

bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide

the op-code during a Mode Register Set command.

A0 - A12

Input

DQ

DQS

NC

Input/Output

Data Input/Output: Data bus.

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-

tered in write data. Used to capture write data.

No Connect: No internal electrical connection is present.

DQ Power Supply: 2.5V Mꢀ0.2V.

DQ Ground

V

Supply

DDQ

V

SSQ

V

Power Supply: 2.5V Mꢀ0.2V.

Ground

DD

V

SS

V

SSTL_2 reference voltage: (V

/ 2)

REF

DDQ

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Block Diagram (128Mbit x 4)

CKE

CK

CS

WE

CAS

RAS

Bank3

Bank2

Bank1

CK, CK

DLL

Mode

13

Registers

8192

Bank0

Memory

Array

15

13

Data

(8192 x 2048 x 8)

4

8

Sense Amplifiers

1

DQS

Generator

DQ0-DQ3,

DM

COL0

Mask

DQS

Input

Register

1

I/O Gating

DM Mask Logic

8

2

DQS

1

A0-A12,

15

Write

1

BA0, BA1

FIFO

1

&

8

2

8

2048

(x8)

2

Drivers

4

clk

Column

Decoder

in

out

Data

11

COL0

CK,

CK

Column-Address

12

Counter/Latch

COL0

1

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Block Diagram (64Mbit x 8)

CKE

CK

CS

WE

CAS

RAS

Bank3

Bank2

Bank1

CK, CK

DLL

Mode

13

Registers

8192

Bank0

Memory

Array

15

13

Data

1

(8192 x 1024 x 16)

8

16

Sense Amplifiers

DQS

Generator

DQ0-DQ7,

DM

COL0

Mask

DQS

Input

Register

1

I/O Gating

DM Mask Logic

16

2

DQS

1

A0-A12,

15

Write

1

8

BA0, BA1

FIFO

1

&

16

2

16

2

1024

(x16)

Drivers

8

clk

Column

Decoder

in

out

Data

10

COL0

CK,

CK

Column-Address

Counter/Latch

11

COL0

1

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Block Diagram (32Mbit x 16)

CKE

CK

CS

WE

CAS

RAS

Bank3

Bank2

Bank1

CK, CK

DLL

Mode

13

Registers

15

8192

Bank0

Memory

Array

Data

13

(8192 x 512x 32)

16

32

Sense Amplifiers

1

DQS

Generator

DQ0-DQ15,

DM

COL0

Mask

DQS

Input

Register

1

I/O Gating

DM Mask Logic

32

2

LDQS, UDQS

1

A0-A12,

15

Write

1

BA0, BA1

FIFO

1

&

32

2

32

2

512

Drivers

(x32)

16

clk

Column

Decoder

in

out

Data

9

COL0

CK,

CK

Column-Address

10

Counter/Latch

COL0

2

1

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: UDM and LDM are unidirectional signals (input only), but is internally loaded to match the

load of the bidirectional DQ , UDQS and LDQS signals.

V0.91, 2002-11-14

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Functional Description

The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912

bits. The 512Mb DDR SDRAM is internally configured as a quad-bank DRAM.

The 512Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-

data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM consists of a

single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide,

one-half clock cycle data transfers at the I/O pins.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and

continue for a programmed number of locations in a programmed sequence. Accesses begin with the regis-

tration of an Active command, which is then followed by a Read or Write command. The address bits regis-

tered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1

select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write com-

mand are used to select the starting column location for the burst access.

Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed infor-

mation covering device initialization, register definition, command descriptions and device operation.

Initialization

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other

than those specified may result in undefined operation. The following criteria must be met:

No power sequencing is specified during power up or power down given the following criteria:

V_DDand V_DDQare driven from a single power converter output

V_TTmeets the specification

A minimum resistance of 42 ohms limits the input current from the V_TTsupply into any pin and V_REF

tracks V_DDQ/2

or

The following relationship must be followed:

V_DDQis driven after or with V_DDsuch that V_DDQ< V_DD+ 0.3 V

V_TTis driven after or with V_DDQsuch that V_TT< V_DDQ+ 0.3V

V_REFis driven after or with V_DDQsuch that V_REF< V_DDQ+ 0.3V

The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a

read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR

SDRAM requires a 200ꢀs delay prior to applying an executable command.

Once the 200ꢀs delay has been satisfied, a Deselect or NOP command should be applied, and CKE should

be brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode

Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode

Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operat-

ing parameters. 200 clock cycles are required between the DLL reset and any executable command. During

the 200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock

cycles, a Precharge ALL command should be applied, placing the device in the “all banks idle” state.

Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set

command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters

without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal

operation.

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Register Definition

Mode Register

The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition

includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Reg-

ister is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored

information until it is programmed again or the device loses power (except for bit A8, which is self-clearing).

Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved),

A4-A6 specify the CAS latency, and A7-A12 specify the operating mode.

The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time

before initiating the subsequent operation. Violating either of these requirements results in unspecified opera-

tion.

Burst Length

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable.

The burst length determines the maximum number of column locations that can be accessed for a given

Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the

interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is effectively

selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block

if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai

when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most

significant column address bit for a given configuration). The remaining (least significant) address bit(s) is

(are) used to select the starting location within the block. The programmed burst length applies to both Read

and Write bursts.

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Mode Register Operation

BA1 BA0 A12

A11 A10 A9

A8

A7

A6

A5

A4

A3

BT

A2

A1

A0

Address Bus

0*

CAS Latency

Burst Length

Mode Register

Operating Mode

A12 - A9

0

A8

0

A7

0

A6 - A0

Valid

Operating Mode

A3

Burst Type

Sequential

Interleave

Normal operation

Do not reset DLL

0

1

Normal operation

in DLL Reset

0

1

0

Valid

0

1

Test Mode

Reserved

ꢂ

CAS Latency

Burst Length

A6

0

A5

0

A4

0

Latency

Reserved

2

A2

0

A1

0

A0

0

Burst Length

Reserved

2

0

1

0

1

0

1

0

1

0

4

0

1

3

0

1

8

1

0

Reserved

1.5 (optional)

2.5

1

0

Reserved

1

0

1

0

1

0

1

0

1

Reserved

1

* BA0 and BA1 must be 0, 0 to select the Mode Register

(vs. the Extended Mode Register).

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Burst Definition

Starting Column Address

Order of Accesses Within a Burst

Burst Length

A2

A1

A0

Type = Sequential

Type = Interleaved

0-1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0-1

2

4

1-0

0

1

0

1

0

1

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

0

1

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

8

Notes:

1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the

block.

2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within

the block.

3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access

within the block.

4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps

within the block.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as

the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst

length, the burst type and the starting column address, as shown in Burst Definition on page 11.

Read Latency

The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command

and the availability of the first burst of output data. The latency can be programmed 2, 2.5 and 3 clocks. CAS

latency of 1.5 is an optional feature on this device.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally

coincident with clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Operating Mode

The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to

zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set com-

mand with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A

Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set

command to select normal operating mode.

All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and

reserved states should not be used as unknown operation or incompatibility with future versions may result.

Required CAS Latencies

CAS Latency = 2, BL = 4

CK

Read

NOP

Command

CL=2

DQS

DQ

CAS Latency = 2.5, BL = 4

CK

Read

NOP

Command

CL=2.5

DQS

DQ

Shown with nominal t , t

, and t

.

DQSQ

Don’t Care

AC DQSCK

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Page 12 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Extended Mode Register

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these addi-

tional functions include DLL enable/disable, and output drive strength selection (optional). These functions

are controlled via the bits shown in the Extended Mode Register Definition. The Extended Mode Register is

programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored informa-

tion until it is programmed again or the device loses power. The Extended Mode Register must be loaded

when all banks are idle, and the controller must wait the specified time before initiating any subsequent oper-

ation. Violating either of these requirements result in unspecified operation.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and

upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The

DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit

of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur before a Read command

can be issued. This is the reason 200 clock cycles must occur before issuing a Read or Write command upon

exit of self refresh operation.

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II. In addition this design version

supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during

mode register set. I-V curves for the normal and weak drive strength are included in this document.

Extended Mode Register Definition

A

BA1 BA0

A

0

12

Address Bus

11

10

9

8

7

6

5

4

3

2

1

Extended

Mode Register

0*

1*

Operating Mode

DS

DLL

0*

Drive Strength

An - A3

0

A2 - A0

Valid

Operating Mode

A

Drive Strength

Normal

1

Normal Operation

0

All other states

Reserved

ꢂ

1

Weak

A

DLL

0

Enable

Disable

1

* BA0 and BA1 must be 1, 0 to select the Extended Mode Register

(vs. the base Mode Register)

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512-Mbit Double Data Rate SDRAM

Commands

Deselect

The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM

is effectively deselected. Operations already in progress are not affected.

No Operation (NOP)

The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted

commands from being registered during idle or wait states. Operations already in progress are not affected.

Mode Register Set

The mode registers are loaded via inputs A0-A12, BA0 and BA1. See mode register descriptions in the Reg-

ister Definition section. The Mode Register Set command can only be issued when all banks are idle and no

bursts are in progress. A subsequent executable command cannot be issued until t_MRDis met.

Active

The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The

value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row.

This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is

issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and com-

pleted before opening a different row in the same bank.

Read

The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0,

BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 8, j = don’t care] for

x16, [i = 9, j = don’t care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. The value on

input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being

accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open

for subsequent accesses.

Write

The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0,

BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8;

where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or

not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end

of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input

data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coin-

cident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the

DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that

byte/column location.

Precharge

The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in

all banks. The bank(s) will be available for a subsequent row access a specified time (t_RP) after the Precharge

command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case

where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any

Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no

open row in that bank, or if the previously open row is already in the process of precharging.

Auto Precharge

Auto Precharge is a feature which performs the same individual-bank precharge functions described above,

but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in

conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the

Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Pre-

charge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command.

Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must

not issue another command to the same bank until the precharge (t_RP) is completed. This is determined as if

an explicit Precharge command was issued at the earliest possible time, as described for each burst type in

the Operation section of this data sheet.

Burst Terminate

The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-

cently registered Read command prior to the Burst Terminate command is truncated, as shown in the Opera-

tion section of this data sheet.

Auto Refresh

Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS

(CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a

refresh is required.

The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t

Care” during an Auto Refresh command. The 512Mb DDR SDRAM requires Auto Refresh cycles at an aver-

age periodic interval of 7.8 ꢀs (maximum).

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute

refresh interval is provided. A maximum of eight Auto Refresh commands can be posted in the system,

meaning that the maximum absolute interval between any Auto Refresh command and the next Auto Refresh

command is 9 * 7.8 ꢀs (70.2ꢀs). This maximum absolute interval is short enough to allow for DLL updates

internal to the DDR SDRAM to be restricted to Auto Refresh cycles, without allowing too much drift in t_AC

between updates.

Self Refresh

The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is

powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The

Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The

DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self

Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except

CKE (low) are “Don’t Care” during Self Refresh operation.

The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to

CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for t_XSNRbecause

time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both

refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.

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512-Mbit Double Data Rate SDRAM

Truth Table 1a: Commands

Name (Function)

CS

H

L

RAS CAS

WE

X

Address

X

MNE

NOP

ACT

Notes

1, 9

Deselect (Nop)

X

H

L

X

H

L

No Operation (Nop)

H

L

X

1, 9

Active (Select Bank And Activate Row)

Read (Select Bank And Column, And Start Read Burst)

Write (Select Bank And Column, And Start Write Burst)

Burst Terminate

L

Bank/Row

Bank/Col

X

1, 3

L

H

L

Read

Write

BST

1, 4

L

1, 4

L

H

L

1, 8

Precharge (Deactivate Row In Bank Or Banks)

Auto Refresh Or Self Refresh (Enter Self Refresh Mode)

Mode Register Set

L

Code

X

PRE

1, 5

L

H

L

AR / SR

MRS

1, 6, 7

1, 2

L

Op-Code

1. CKE is HIGH for all commands shown except Self Refresh.

2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0

selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the

selected Mode Register.)

3. BA0-BA1 provide bank address and A0-A12 provide row address.

4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, i = 9 for x8 and 9, 11 for x4); A10 HIGH

enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature.

5. A10 LOW: BA0, BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW.

7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with

Auto Precharge enabled or for write bursts

9. Deselect and NOP are functionally interchangeable.

Truth Table 1b: DM Operation

Name (Function)

Write Enable

Write Inhibit

DM

L

DQs

Valid

X

Notes

1

H

1. Used to mask write data; provided coincident with the corresponding data.

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Operations

Bank/Row Activation

Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank

must be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and

BA1 (see Activating a Specific Row in a Specific Bank), which decode and select both the bank and the row

to be activated. After opening a row (issuing an Active command), a Read or Write command may be issued

to that row, subject to the t_RCDspecification. A subsequent Active command to a different row in the same

bank can only be issued after the previous active row has been “closed” (precharged). The minimum time

interval between successive Active commands to the same bank is defined by t_RC. A subsequent Active com-

mand to another bank can be issued while the first bank is being accessed, which results in a reduction of

total row-access overhead. The minimum time interval between successive Active commands to different

banks is defined by t_RRD

.

Activating a Specific Row in a Specific Bank

CK

HIGH

CKE

CS

RAS

CAS

WE

RA = row address.

BA = bank address.

RA

BA

A0-A12

BA0, BA1

Don’t Care

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

t_RCDand t_RRDDefinition

CK

RD/WR

ACT

NOP

ACT

NOP

Command

ROW

BA x

ROW

BA y

COL

BA y

A0-A12

BA0, BA1

t

RCD

RRD

Don’t Care

Reads

Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts

are initiated with a Read command, as shown on Read Command on page 19.

The starting column and bank addresses are provided with the Read command and Auto Precharge is either

enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts pre-

charge at the completion of the burst, provided t_RAShas been satisfied. For the generic Read commands

used in the following illustrations, Auto Precharge is disabled.

During Read bursts, the valid data-out element from the starting column address is available following the

CAS latency after the Read command. Each subsequent data-out element is valid nominally at the next posi-

tive or negative clock edge (i.e. at the next crossing of CK and CK). Read Burst: CAS Latencies (Burst Length

= 4) on page 20 shows general timing for each supported CAS latency setting. DQS is driven by the DDR

SDRAM along with output data. The initial low state on DQS is known as the read preamble; the low state

coincident with the last data-out element is known as the read postamble. Upon completion of a burst,

assuming no other commands have been initiated, the DQs goes High-Z. Data from any Read burst may be

concatenated with or truncated with data from a subsequent Read command. In either case, a continuous

flow of data can be maintained. The first data element from the new burst follows either the last element of a

completed burst or the last desired data element of a longer burst which is being truncated. The new Read

command should be issued x cycles after the first Read command, where x equals the number of desired

data element pairs (pairs are required by the 2n prefetch architecture). This is shown on Consecutive Read

Bursts: CAS Latencies (Burst Length = 4 or 8) on page 21. A Read command can be initiated on any clock

cycle following a previous Read command. Nonconsecutive Read data is illustrated on Non-Consecutive

Read Bursts: CAS Latencies (Burst Length = 4) on page 22. Full-speed Random Read Accesses: CAS

Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 23.

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Read Command

CK

HIGH

CKE

CS

RAS

CAS

WE

x4: A0-A9, A11

x8: A0-A9

CA

x16: A0-A8

EN AP

A10

DIS AP

BA

CA = column address

BA = bank address

EN AP = enable Auto Precharge

DIS AP = disable Auto Precharge

BA0, BA1

Don’t Care

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Read Burst: CAS Latencies (Burst Length = 4)

CAS Latency = 2

CK

Read

NOP

Command

Address

BA a,COL n

CL=2

DQS

DQ

DOa-n

CAS Latency = 2.5

CK

Read

NOP

Command

Address

BA a,COL n

CL=2.5

DQS

DQ

DOa-n

Don’t Care

DO a-n = data out from bank a, column n.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal t , t , and t

.

DQSQ

AC DQSCK

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 2

CK

Read

NOP

Read

NOP

Command

Address

BAa, COL n

BAa, COL b

CL=2

DQS

DQ

DOa-n

DOa-b

CAS Latency = 2.5

CK

Read

NOP

Read

NOP

Command

Address

BAa, COL n

BAa,COL b

CL=2.5

DQS

DQ

DOa- n

DOa- b

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).

When burst length = 4, the bursts are concatenated.

When burst length = 8, the second burst interrupts the first.

Don’t Care

3 subsequent elements of data out appear in the programmed order following DO a-n.

3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b.

Shown with nominal t , t

, and t

.

AC DQSCK

DQSQ

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512-Mbit Double Data Rate SDRAM

Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)

CAS Latency = 2

CK

Read

NOP

Read

NOP

Command

Address

BAa, COL n

BAa, COL b

CL=2

DQS

DQ

DO a-n

DOa- b

CAS Latency = 2.5

CK

Read

NOP

Read

NOP

Command

Address

BAa, COL n

BAa, COL b

CL=2.5

DQS

DQ

DO a-n

DOa- b

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).

3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).

Shown with nominal t , t , and t

.

DQSQ

AC DQSCK

Don’t Care

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)

CAS Latency = 2

CK

Read

BAa, COL x

CL=2

Read

NOP

Command

Address

BAa, COL n

BAa, COL b

BAa, COL g

DQS

DQ

DOa-n

DOa-n'

DOa-x

DOa-x'

DOa-b

DOa-b’

DOa-g

CAS Latency = 2.5

CK

Read

NOP

Command

Address

BAa, COL n

BAa, COL x

BAa, COL b

BAa, COL g

CL=2.5

DQS

DQ

DOa-n

DOa-n'

DOa-x

DOa-x'

DOa-b

DOa-b’

DO a-n, etc. = data out from bank a, column n etc.

n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).

Reads are to active rows in any banks.

Don’t Care

Shown with nominal t , t

, and t

.

AC DQSCK

DQSQ

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Data from any Read burst may be truncated with a Burst Terminate command, as shown on Terminating a

Read Burst: CAS Latencies (Burst Length = 8) on page 25. The Burst Terminate latency is equal to the read

(CAS) latency, i.e. the Burst Terminate command should be issued x cycles after the Read command, where

x equals the number of desired data element pairs.

Data from any Read burst must be completed or truncated before a subsequent Write command can be

issued. If truncation is necessary, the Burst Terminate command must be used, as shown on Read to Write:

CAS Latencies (Burst Length = 4 or 8) on page 26. The example is shown for t_DQSS(min). The t_DQSS(max)

case, not shown here, has a longer bus idle time. t_DQSS(min) and t_DQSS(max) are defined in the section on

Writes.

A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that

Auto Precharge was not activated). The Precharge command should be issued x cycles after the Read com-

mand, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch archi-

tecture). This is shown on Read to Precharge: CAS Latencies (Burst Length = 4 or 8) on page 27 for Read

latencies of 2 and 2.5. Following the Precharge command, a subsequent command to the same bank cannot

be issued until t_RPis met. Note that part of the row precharge time is hidden during the access of the last data

elements.

In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as

described above) provides the same operation that would result from the same Read burst with Auto Pre-

charge enabled. The disadvantage of the Precharge command is that it requires that the command and

address busses be available at the appropriate time to issue the command. The advantage of the Precharge

command is that it can be used to truncate bursts.

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Terminating a Read Burst: CAS Latencies (Burst Length = 8)

CAS Latency = 2

CK

Read

NOP

BST

NOP

Command

Address

BAa, COL n

CL=2

DQS

DQ

DOa-n

No further output data after this point.

DQS tristated.

CAS Latency = 2.5

CK

Read

NOP

BST

NOP

Command

Address

BAa, COL n

CL=2.5

DQS

DQ

DOa-n

No further output data after this point.

DQS tristated.

DO a-n = data out from bank a, column n.

Cases shown are bursts of 8 terminated after 4 data elements.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal t , t , and t

Don’t Care

.

DQSQ

AC DQSCK

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Read to Write: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 2

CK

Read

BST

NOP

Write

NOP

Command

Address

BAa, COL n

BAa, COL b

CL=2

t

(min)

DQSS

DQS

DQ

DI a-b

DOa-n

DM

CAS Latency = 2.5

CK

Read

BST

NOP

Write

NOP

Command

Address

BAa, COL n

BAa, COL b

CL=2.5

t

(min)

DQSS

DQS

DQ

DOa-n

Dla-b

DM

DO a-n = data out from bank a, column n

.

DI a-b = data in to bank a, column b

1 subsequent elements of data out appear in the programmed order following DO a-n.

Data In elements are applied following Dl a-b in the programmed order, according to burst length.

Shown with nominal t , t , and t

.

DQSQ

Don’t Care

AC DQSCK

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Read to Precharge: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 2

CK

Read

NOP

PRE

NOP

ACT

Command

t

RP

BA a, COL n

BA a or all

BA a, ROW

Address

CL=2

DQS

DQ

DOa-n

CAS Latency = 2.5

CK

Read

NOP

PRE

NOP

ACT

Command

t

RP

BA a or all

BA a, COL n

BA a, ROW

Address

CL=2.5

DQS

DQ

DOa-n

DO a-n = data out from bank a, column n.

Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal t , t , and t

.

DQSQ

AC DQSCK

Don’t Care

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Writes

Write bursts are initiated with a Write command, as shown on Write Command on page 29.

The starting column and bank addresses are provided with the Write command, and Auto Precharge is either

enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at

the completion of the burst. For the generic Write commands used in the following illustrations, Auto Pre-

charge is disabled.

During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the

write command, and subsequent data elements are registered on successive edges of DQS. The Low state

on DQS between the Write command and the first rising edge is known as the write preamble; the Low state

on DQS following the last data-in element is known as the write postamble. The time between the Write com-

mand and the first corresponding rising edge of DQS (t_DQSS) is specified with a relatively wide range (from

75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the two extreme

cases (i.e. t_DQSS(min) and t_DQSS(max)). Write Burst (Burst Length = 4) on page 30 shows the two extremes of

t_DQSSfor a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the

DQs and DQS enters High-Z and any additional input data is ignored.

Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either

case, a continuous flow of input data can be maintained. The new Write command can be issued on any pos-

itive edge of clock following the previous Write command. The first data element from the new burst is applied

after either the last element of a completed burst or the last desired data element of a longer burst which is

being truncated. The new Write command should be issued x cycles after the first Write command, where x

equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). Write to

Write (Burst Length = 4) on page 31 shows concatenated bursts of 4. An example of non-consecutive Writes

is shown on Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) on page 32. Full-speed random

write accesses within a page or pages can be performed as shown on Random Write Cycles (Burst Length =

2, 4 or 8) on page 33. Data for any Write burst may be followed by a subsequent Read command. To follow a

Write without truncating the write burst, t_WTR(Write to Read) should be met as shown on Write to Read: Non-

Interrupting (CAS Latency = 2; Burst Length = 4) on page 34.

Data for any Write burst may be truncated by a subsequent Read command, as shown in the figures on Write

to Read: Interrupting (CAS Latency = 2; Burst Length = 8) on page 35 to Write to Read: Nominal DQSS, Inter-

rupting (CAS Latency = 2; Burst Length = 8) on page 37. Note that only the data-in pairs that are registered

prior to the t_WTRperiod are written to the internal array, and any subsequent data-in must be masked with

DM, as shown in the diagrams noted previously.

Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without

truncating the write burst, t_WRshould be met as shown on Write to Precharge: Non-Interrupting (Burst Length

= 4) on page 38.

Data for any Write burst may be truncated by a subsequent Precharge command, as shown in the figures on

Write to Precharge: Interrupting (Burst Length = 4 or 8) on page 39 to Write to Precharge: Nominal DQSS (2

bit Write), Interrupting (Burst Length = 4 or 8) on page 41. Note that only the data-in pairs that are registered

prior to the t_WRperiod are written to the internal array, and any subsequent data in should be masked with

DM. Following the Precharge command, a subsequent command to the same bank cannot be issued until t_RP

is met.

In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time

(as described above) provides the same operation that would result from the same burst with Auto Pre-

charge. The disadvantage of the Precharge command is that it requires that the command and address bus-

ses be available at the appropriate time to issue the command. The advantage of the Precharge command is

that it can be used to truncate bursts.

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512-Mbit Double Data Rate SDRAM

Write Command

CK

HIGH

CKE

CS

RAS

CAS

WE

x4: A0-A9, A11

x8: A0-A9

CA

x16: A0-A8

EN AP

A10

DIS AP

BA

CA = column address

BA = bank address

EN AP = enable Auto Precharge

DIS AP = disable Auto Precharge

BA0, BA1

Don’t Care

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write Burst (Burst Length = 4)

Maximum DQSS

T1

T2

T3

T4

CK

Write

NOP

Command

BA a, COL b

Address

t

(max)

DQSS

DQS

DQ

Dla-b

DM

Minimum DQSS

T4

T1

T2

T3

CK

Write

NOP

Command

BA a, COL b

Address

t

(min)

DQSS

DQS

DQ

Dla-b

DM

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

A10 is Low with the Write command (Auto Precharge is disabled).

Don’t Care

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write to Write (Burst Length = 4)

Maximum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Write

NOP

Command

Address

BAa, COL b

BAa, COL n

t

(max)

DQSS

DQS

DQ

DI a-b

DI a-n

DM

Minimum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Write

NOP

Command

Address

BA, COL b

BA, COL n

t

(min)

DQSS

DQS

DQ

DI a-b

DI a-n

DM

DI a-b = data in for bank a, column b, etc.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

3 subsequent elements of data in are applied in the programmed order following DI a-n.

A non-interrupted burst is shown.

Don’t Care

Each Write command may be to any bank.

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Page 31 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4)

T1

T2

T3

T4

T5

CK

Write

NOP

Write

NOP

Command

Address

BAa, COL b

BAa, COL n

t

(max)

DQSS

DQS

DQ

DI a-b

DI a-n

DM

DI a-b, etc. = data in for bank a, column b, etc.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

3 subsequent elements of data in are applied in the programmed order following DI a-n.

A non-interrupted burst is shown.

Don’t Care

Each Write command may be to any bank.

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HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Random Write Cycles (Burst Length = 2, 4 or 8)

Maximum DQSS

T1

T2

T3

T4

T5

CK

Write

Command

Address

BAa, COL b

BAa, COL x

BAa, COL n

BAa, COL a

BAa, COL g

t

(max)

DQSS

DQS

DQ

DI a-b

DI a-b’

DI a-x

DI a-x’

DI a-n

DI a-n’

DI a-a

DI a-a’

DM

Minimum DQSS

T5

T1

T2

T3

T4

CK

Write

Command

Address

BAa, COL b

BAa, COL x

BAa, COL n

BAa, COL a

BAa, COL g

t

(min)

DQSS

DQS

DQ

DI a-g

DI a-b

DI a-b’

DI a-x

DI a-x’

DI a-n

DI a-n’

DI a-a

DI a-a’

DM

DI a-b, etc. = data in for bank a, column b, etc.

b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).

Each Write command may be to any bank.

Don’t Care

V0.91, 2002-11-14

Page 33 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)

Maximum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Read

NOP

Command

t

WTR

BAa, COL b

BAa, COL n

Address

CL = 2

t

(max)

DQSS

DQS

DQ

DI a-b

DM

Minimum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Read

NOP

Command

t

WTR

BAa, COL n

BAa, COL b

Address

CL = 2

t

(min)

DQSS

DQS

DQ

DI a-b

DM

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

t

is referenced from the first positive CK edge after the last data in pair.

WTR

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands may be to any bank.

Don’t Care

V0.91, 2002-11-14

Page 34 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)

Maximum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Read

NOP

Command

t

WTR

BAa, COL n

BAa, COL b

Address

CL = 2

t

(max)

DQSS

DQS

DQ

DIa- b

1

DM

Minimum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Read

NOP

Command

t

WTR

BAa, COL n

BAa, COL b

Address

CL = 2

t

(min)

DQSS

DQS

DQ

DI a-b

DM

1

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 4 data elements are written.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

is referenced from the first positive CK edge after the last data in pair.

t

WTR

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

1 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

V0.91, 2002-11-14

Page 35 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS

Latency = 2; Burst Length = 8)

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Read

NOP

Command

t

WTR

BAa, COL n

BAa, COL b

Address

CL = 2

t

(min)

DQSS

DQS

DQ

DI a-b

1

2

DM

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 3 data elements are written.

2 subsequent elements of data in are applied in the programmed order following DI a-b.

is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)

t

WTR

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

1 = This bit is correctly written into the memory array if DM is low.

2 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

V0.91, 2002-11-14

Page 36 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Read

NOP

Command

t

WTR

BAa, COL n

BAa, COL b

Address

CL = 2

t

(nom)

DQSS

DQS

DQ

DI a-b

DM

1

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 4 data elements are written.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

is referenced from the first positive CK edge after the last desired data in pair.

t

WTR

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

1 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

V0.91, 2002-11-14

Page 37 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write to Precharge: Non-Interrupting (Burst Length = 4)

Maximum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

PRE

Command

t

WR

BA (a or all)

BA a, COL b

Address

t

(max)

RP

DQSS

DQS

DQ

DI a-b

DM

Minimum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

PRE

Command

t

WR

BA (a or all)

BA a, COL b

Address

t

RP

t

(min)

DQSS

DQS

DQ

DI a-b

DM

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

t

is referenced from the first positive CK edge after the last data in pair.

WR

Don’t Care

A10 is Low with the Write command (Auto Precharge is disabled).

V0.91, 2002-11-14

Page 38 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write to Precharge: Interrupting (Burst Length = 4 or 8)

Maximum DQSS

T5 T6

T1

T2

T3

T4

CK

Write

NOP

PRE

NOP

Command

t

WR

BA (a or all)

BA a, COL b

Address

t

(max)

RP

DQSS

2

DQS

DQ

DI a-b

1

3

DM

Minimum DQSS

T5 T6

T1

T2

T3

T4

CK

Write

NOP

PRE

NOP

Command

t

WR

BA a, COL b

BA (a or all)

Address

t

(min)

RP

2

DQSS

DQS

DQ

DI a-b

3

1

DM

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 2 data elements are written.

1 subsequent element of data in is applied in the programmed order following DI a-b.

is referenced from the first positive CK edge after the last desired data in pair.

t

WR

The Precharge command masks the last 2 data elements in the burst, for burst length = 8.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point.

3 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

V0.91, 2002-11-14

Page 39 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting

(Burst Length = 4 or 8)

T1

T2

T3

T4

T5

T6

CK

Write

NOP

PRE

NOP

Command

t

WR

BA a, COL b

BA (a or all)

Address

t

(min)

RP

2

DQSS

DQS

DQ

DI a-b

1

3

4

DM

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 1 data element is written.

is referenced from the first positive CK edge after the last desired data in pair.

t

WR

The Precharge command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point.

3 = This bit is correctly written into the memory array if DM is low.

4 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

V0.91, 2002-11-14

Page 40 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)

T1

T2

T3

T4

T5

T6

CK

Write

NOP

PRE

NOP

Command

t

WR

BA a, COL b

BA (a or all)

Address

t

(nom)

RP

DQSS

2

DQS

DQ

DI a-b

3

1

DM

DI a-b = Data In for bank a, column b.

An interrupted burst is shown, 2 data elements are written.

1 subsequent element of data in is applied in the programmed order following DI a-b.

is referenced from the first positive CK edge after the last desired data in pair.

t

WR

The Precharge command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point.

Don’t Care

3 = These bits are incorrectly written into the memory array if DM is low.

V0.91, 2002-11-14

Page 41 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Precharge Command

CK

HIGH

CKE

CS

RAS

CAS

WE

A0-A9, A11, A12

All Banks

A10

One Bank

BA

BA0, BA1

BA = bank address

(if A10 is Low, otherwise Don’t Care).

Don’t Care

Precharge

The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks.

The bank(s) will be available for a subsequent row access some specified time (t_RP) after the Precharge com-

mand is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where

only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged,

inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and

must be activated prior to any Read or Write commands being issued to that bank.

V0.91, 2002-11-14

Page 42 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Power-Down

Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down

occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs

when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down

deactivates the input and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down

mode, so for maximum power savings, the user has the option of disabling the DLL prior to entering Power-

down. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur

before a Read command can be issued. In power-down mode, CKE Low and a stable clock signal must be

maintained at the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. However, power-

down duration is limited by the refresh requirements of the device, so in most applications, the self refresh

mode is preferred over the DLL-disabled power-down mode.

The power-down state is synchronously exited when CKE is registered HIGH (along with a Nop or Deselect

command). A valid, executable command may be applied one clock cycle later.

Power Down

CK

t

IS

CKE

Command

VALID

NOP

VALID

NOP

No column

access in

progress

Exit

power down

mode

Don’t Care

Enter Power Down mode

(Burst Read or Write operation

must not be in progress)

V0.91, 2002-11-14

Page 43 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Truth Table 2: Clock Enable (CKE)

1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.

3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.

4. All states and sequences not shown are illegal or reserved.

CKE n-1

CKEn

Current State

Command n

Action n

Notes

Previous Current

Cycle

Self Refresh

Power Down

All Banks Idle

Bank(s) Active

L

H

L

X

Maintain Self-Refresh

Deselect or NOP

X

Exit Self-Refresh

1

L

Maintain Power-Down

Exit Power-Down

L

H

L

Deselect or NOP

AUTO REFRESH

Deselect or NOP

H

Precharge Power-Down Entry

Self Refresh Entry

L

Active Power-Down Entry

See “Truth Table 3: Current State

Bank n - Command to Bank n

(Same Bank)” on page 45

H

1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t

) period. A mini-

XSNR

mum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.

V0.91, 2002-11-14

Page 44 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)

Current State

Any

CS

H

RAS CAS

WE

X

Command

Deselect

Action

Notes

1-6

X

H

L

X

H

NOP. Continue previous operation

L

H

No Operation

1-6

L

H

L

Active

AUTO REFRESH

MODE REGISTER SET

Read

Select and activate row

1-6

1-7

Idle

L

1-7

H

L

H

L

Select column and start Read burst

Select column and start Write burst

Deactivate row in bank(s)

1-6, 10

1-6, 8

Row Active

L

Write

H

L

Precharge

Read

H

L

H

L

Select column and start new Read burst

Truncate Read burst, start Precharge

BURST TERMINATE

1-6, 10

1-6, 8

Read

(Auto Precharge

Disabled)

H

L

Precharge

BURST TERMINATE

Read

H

L

1-6, 9

H

L

Select column and start Read burst

Select column and start Write burst

Truncate Write burst, start Precharge

1-6, 10, 11

1-6, 10

1-6, 8, 11

Write

(Auto Precharge

Disabled)

L

Write

H

L

Precharge

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after t

has been met (if the previous state was self refresh).

t

XSNR / XSRD

2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those

allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle:

The bank has been precharged, and t has been met.

RP

Row Active:

A row in the bank has been activated, and t

accesses are in progress.

has been met. No data bursts/accesses and no register

RCD

Read:

Write:

A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank.

Precharging:

Starts with registration of a Precharge command and ends when t is met. Once t is met, the bank is in the

RP

idle state.

Row Activating: Starts with registration of an Active command and ends when t

“row active” state.

is met. Once t

is met, the bank is in the

RCD

Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when t

RP

has been met. Once t is met, the bank is in the idle state.

Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when t

RP

has been met. Once t is met, the bank is in the idle state.

RP

Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these

states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.

5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each

positive clock edge during these states.

Refreshing:

Starts with registration of an Auto Refresh command and ends when t

SDRAM is in the “all banks idle” state.

is met. Once t

is met, the DDR

RFC

Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when t

has been met. Once

MRD

t

is met, the DDR SDRAM is in the “all banks idle” state.

MRD

Precharging All: Starts with registration of a Precharge All command and ends when t is met. Once t is met, all banks is in

RP

the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.

10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes

with Auto Precharge disabled.

11. Requires appropriate DM masking.

V0.91, 2002-11-14

Page 45 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

Current State

Any

CS

H

RAS CAS

WE

X

Command

Deselect

Action

Notes

1-6

X

H

X

H

NOP/continue previous operation

L

H

No Operation

1-6

Any Command Otherwise

Allowed to Bank m

Idle

X

1-6

L

H

L

H

L

H

L

Active

Read

Select and activate row

1-6

1-7

Row Activating,

Active, or

Precharging

Select column and start Read burst

Select column and start Write burst

L

Write

1-7

H

L

Precharge

Active

1-6

L

H

L

Select and activate row

1-6

Read

(Auto Precharge

Disabled)

H

L

Read

Select column and start new Read burst

1-7

H

L

Precharge

Active

1-6

L

H

L

Select and activate row

1-6

Write

(Auto Precharge

Disabled)

H

L

Read

Select column and start Read burst

Select column and start new Write burst

1-8

L

Write

1-7

H

L

Precharge

Active

1-6

L

H

L

Select and activate row

1-6

H

L

Read

Select column and start new Read burst

Select column and start Write burst

1-7,10

1-7,9,10

1-6

Read (With

Auto Precharge)

L

Write

H

L

Precharge

Active

L

H

L

Select and activate row

1-6

H

L

Read

Select column and start Read burst

Select column and start new Write burst

1-7,10

1-6

Write (With

Auto Precharge)

L

Write

H

L

Precharge

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after t

has been met (if the previous state was self refresh).

t

XSNR / XSRD

2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown

are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Excep-

tions are covered in the notes below.

3. Current state definitions:

Idle:

The bank has been precharged, and t has been met.

RP

Row Active:

A row in the bank has been activated, and t

accesses are in progress.

has been met. No data bursts/accesses and no register

RCD

Read:

Write:

A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Read with Auto Precharge Enabled: See note 10.

Write with Auto Precharge Enabled: See note 10.

4. AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes

with Auto Precharge disabled.

8. Requires appropriate DM masking.

9. A Write command may be applied after the completion of data output.

Concurrent Auto Precharge:

This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is enabled any

command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limita-

tions apply (e.g. contention between READ data and WRITE data must be avoided). The mimimum delay from a read or write command

with auto precharge enable, to a command to a different banks is summarized in table 5.

V0.91, 2002-11-14

Page 46 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Truth Table 5: Concurrent Auto Precharge

Minimum Delay with Con-

current Auto Precharge

Support

To Command

From Command

Units

(different bank)

Read or Read w/AP

1 + (BL/2) + tWTR

tCK

WRITE w/AP

Read w/AP

Write ot Write w/AP

Precharge or Activate

Read or Read w/AP

Write or Write w/AP

Precharge or Activate

BL/2

1

BL/2

CL (rounded up)+ BL/2

1

V0.91, 2002-11-14

Page 47 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Simplified State Diagram

Power

Applied

Power

On

Self

Refresh

Precharge

PREALL

REFS

REFSX

REFA

MRS

EMRS

Auto

Refresh

MRS

Idle

CKEL

CKEH

Active

Power

Down

ACT

Precharge

Power

Down

CKEH

CKEL

Burst Stop

Row

Active

Read

Write

Write A

Read A

Write

Read

Read A

Write A

Read

A

PRE

Write

A

Read

A

PRE

Precharge

PREALL

PRE

Automatic Sequence

Command Sequence

PREALL = Precharge All Banks

MRS = Mode Register Set

EMRS = Extended Mode Register Set

REFS = Enter Self Refresh

REFSX = Exit Self Refresh

REFA = Auto Refresh

CKEL = Enter Power Down

CKEH = Exit Power Down

ACT = Active

Write A = Write with Autoprecharge

Read A = Read with Autoprecharge

PRE = Precharge

V0.91, 2002-11-14

Page 48 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Operating Conditions

Absolute Maximum Ratings

Symbol

Parameter

Rating

Units

V

, V

Voltage on I/O pins relative to V

ꢂ0.5 to V_DDQꢃꢁ0.5

ꢂ0.5 to ꢃ3.6

IN

OUT

SS

V

Voltage on Inputs relative to V

V

IN

SS

V

DD

Voltage on V supply relative to V

ꢂ0.5 to ꢃ3.6

V

DD

SS

V

Voltage on V

supply relative to V

SS

ꢂ0.5 to ꢃ3.6

0 to ꢃ70

ꢂ55 to ꢃ150

1.5

V

LC

W

DDQ

T

Operating Temperature (Ambient)

Storage Temperature (Plastic)

Power Dissipation

A

T

STG

P

D

I

Short Circuit Output Current

50

mA

OUT

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sec-

tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Input and Output Capacitances

Parameter

Symbol

Min.

2.0

-

Max.

3.0

Units

pF

Notes

Input Capacitance: CK, CK

Delta Input Capacitance

C

1

I1

C

0.25

3.0

pF

dI1

Input Capacitance: All other input-only pins

Input/Output Capacitance: DQ, DQS, DM

Delta Input/Output Capacitance : DQ, DQS, DM

C

2.0

4.0

-

pF

1

I2

IO

C

5.0

pF

1, 2

1

C

0.5

pF

dIO

1. These values are guaranteed by design and are tested on a sample base only. V

= V = 2.5V ± 0.2V, f = 100MHz, T = 25LC,

DD A

DDQ

V

(DC) = V

, VOUT (Peak to Peak) 0.2V. Unused pins are tied to ground

OUT

DDQ/2

2. DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching

at the board level.

V0.91, 2002-11-14

Page 49 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Electrical Characteristics and DC Operating Conditions

(0°C ? T_Aꢁ?ꢁ70LC; V_DDQ= 2.5V Mꢁ0.2V, V_DD= ꢃꢁ2.5V Mꢁ0.2V)

Symbol

Parameter

Min

2.3

Max

2.7

Units

V

Notes

V

Supply Voltage

1

DD

V

I/O Supply Voltage

2.3

2.7

V

DDQ

V

, V

Supply Voltage, I/O Supply Voltage

I/O Reference Voltage

0

V

SS

SSQ

V

0.49 x V

0.51 x V

V

1, 2

1, 3

1

REF

DDQ

V

I/O Termination Voltage (System)

Input High (Logic1) Voltage

V

ꢁ 0.04

ꢂ 0.15

V

ꢂ 0.04

REF

V

TT

REF

V

ꢂ 0.3

DDQ

V

IH(DC)

V

Input Low (Logic0) Voltage

ꢁꢀ0.3

V

ꢁ 0.15

REF

V

1

IL(DC)

IN(DC)

ID(DC)

V

Input Voltage Level, CK and CK Inputs

Input Differential Voltage, CK and CK Inputs

VI-Matching Pullup Current to Pulldown Current

Input Leakage Current

ꢁꢀ0.3

0.36

0.71

V

ꢂ 0.3

ꢂ 0.6

V

1

DDQ

V

1, 4

5

VI

1.4

Ratio

I

ꢁꢀ2

ꢁꢀ5

2

5

ꢃA

1

I

Any input 0V ? V ?ꢁV (All other pins not under test ꢄ 0V)

IN

DD

Output Leakage Current

(DQs are disabled; 0V ? V ?ꢁV

I

OZ

out

DDQ

I

Output High Current, Normal Strength Driver (V_OUTꢄ 1.95 V)

Output Low Current, Normal Strength Driver (V_OUTꢄ 0.35 V)

ꢁꢀ15.2

mA

1

OH

I

15.2

OL

1. Inputs are not recognized as valid until V_REFstabilizes.

2. V_REFis expected to be equal to 0.5 V_DDQof the transmitting device, and to track variations in the DC level of the

same. Peak-to-peak noise on V_REFmay not exceed ± 2% of the DC value.

3. V_TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set

equal to V_REF, and must track variations in the DC level of V_REF

.

4. V_IDis the magnitude of the difference between the input level on CK and the input level on CK.

5. The ration of the pullup current to the pulldown current is specified for the same temperature and voltage, over the

entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0V. For a given output, it rep-

resents the maximum difference between pullup and pulldown drivers due to process variation.

V0.91, 2002-11-14

Page 50 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Normal Strength Pulldown and Pullup Characteristics

1. The nominal pulldown V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the

inner bounding lines of the V-I curve.

2. The full variation in driver pulldown current from minimum to maximum process, temperature, and voltage

lie within the outer bounding lines of the V-I curve.

Normal Strength Pulldown Characteristics

140

Maximum

120

100

Nominal High

80

60

40

Nominal Low

Minimum

20

0

0.5

1

1.5

2

2.5

V_DDQ- V_OUT(V)

3. The nominal pullup V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the

inner bounding lines of the V-I curve.

4. The full variation in driver pullup current from minimum to maximum process, temperature, and voltage lie

within the outer bounding lines of the V-I curve.

Normal Strength Pullup Characteristics

0

-20

Minimum

Nominal Low

-40

-60

-80

-100

-120

-140

-160

Nominal High

Maximum

0

0.5

1

1.5

2

2.5

V

_{DDQ -}V_out(V)

5. The full variation in the ratio of the maximum to minimum pullup and pulldown current does not exceed

1.7, for device drain to source voltages from 0.1 to 1.0.

6. The full variation in the ratio of the nominal pullup to pulldown current should be unity M 10ꢅ, for device

drain to source voltages from 0.1 to 1.0V.

V0.91, 2002-11-14

Page 51 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Normal Strength Pulldown and Pullup Currents

Pulldown Current (mA)

Pullup Current (mA)

Nominal

Low

Nominal

High

Nominal

Low

Nominal

High

Voltage (V)

Min

Max

Min

Max

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

6.0

6.8

13.5

20.1

26.6

33.0

39.1

44.2

49.8

55.2

60.3

65.2

69.9

74.2

78.4

82.3

85.9

89.1

92.2

95.3

97.2

99.1

100.9

101.9

102.8

103.8

104.6

105.4

4.6

9.6

ꢁ6.1

ꢁ7.6

ꢁ14.5

ꢁ21.2

ꢁ27.7

ꢁ34.1

ꢁ40.5

ꢁ46.9

ꢁ53.1

ꢁ59.4

ꢁ65.5

ꢁ71.6

ꢁ77.6

ꢁ83.6

ꢁ89.7

ꢁ95.5

ꢁ101.3

ꢁ107.1

ꢁ112.4

ꢁ118.7

ꢁ124.0

ꢁ129.3

ꢁ134.6

ꢁ139.9

ꢁ145.2

ꢁ150.5

-155.3

-160.1

ꢁ4.6

ꢁ10.0

ꢁ20.0

12.2

18.1

24.1

29.8

34.6

39.4

43.7

47.5

51.3

54.1

56.2

57.9

59.3

60.1

60.5

61.0

61.5

62.0

62.5

62.9

63.3

63.8

64.1

64.6

64.8

65.0

9.2

18.2

ꢁ12.2

ꢁ18.1

ꢁ24.0

ꢁ29.8

ꢁ34.3

ꢁ38.1

ꢁ41.1

ꢁ43.8

ꢁ46.0

ꢁ47.8

ꢁ49.2

ꢁ50.0

ꢁ50.5

ꢁ50.7

ꢁ51.0

ꢁ51.1

ꢁ51.3

ꢁ51.5

ꢁ51.6

ꢁ51.8

ꢁ52.0

ꢁ52.2

ꢁ52.3

ꢁ52.5

-52.7

-52.8

ꢁ9.2

13.8

18.4

23.0

27.7

32.2

36.8

39.6

42.6

44.8

46.2

47.1

47.4

47.7

48.0

48.4

48.9

49.1

49.4

49.6

49.8

49.9

50.0

50.2

50.4

50.5

26.0

ꢁ13.8

ꢁ18.4

ꢁ23.0

ꢁ27.7

ꢁ32.2

ꢁ36.0

ꢁ38.2

ꢁ38.7

ꢁ39.0

ꢁ39.2

ꢁ39.4

ꢁ39.6

ꢁ39.9

ꢁ40.1

ꢁ40.2

ꢁ40.3

ꢁ40.4

ꢁ40.5

ꢁ40.6

ꢁ40.7

ꢁ40.8

ꢁ40.9

ꢁ41.0

-41.1

-41.2

ꢁ29.8

33.9

ꢁ38.8

41.8

ꢁ46.8

49.4

ꢁ54.4

56.8

ꢁ61.8

63.2

ꢁ69.5

69.9

ꢁꢄꢄꢅꢆ

76.3

ꢁ85.2

82.5

ꢁ93.0

88.3

ꢁ100.6

ꢁ108.1

ꢁ115.5

ꢁ123.0

ꢁ130.4

ꢁ136.7

ꢁ144.2

ꢁ150.5

ꢁ156.9

ꢁ163.2

ꢁ169.6

ꢁ176.0

ꢁ181.3

ꢁ187.6

-192.9

-198.2

93.8

99.1

103.8

108.4

112.1

115.9

119.6

123.3

126.5

129.5

132.4

135.0

137.3

139.2

140.8

Pulldown and Pullup Process Variations and Conditions

Nominal

Minimum

Maximum

25 LC

0 LC

70 LC

Operating Temperature

/ V

2.5V

2.3V

2.7V

V

DD

DDQ

V0.91, 2002-11-14

Page 52 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Weak Strength Pulldown and Pullup Characteristics

Weak Strength Pulldown Characteristics

80

70

60

50

40

30

20

10

0

Maximum

Typical high

Typical low

Minimum

0,0

0,5

1,0

1,5

Vout [V]

2,0

2,5

1. The weak pulldown V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the

inner bounding lines of the V-I curve

2. The weak pullup V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the

inner bounding lines of the V-I curve.

3. The full variation in driver pullup current from minimum to maximum process, temperature, and voltage lie

within the outer bounding lines of the V-I curve.

Weak Strength Pullup Characteristics

0,0

0,5

1,0

1,5

2,0

2,5

-10,0

-20,0

-30,0

-40,0

-50,0

-60,0

-70,0

-80,0

Minimum

Typical low

Typical high

Maximum

Vout [V]

4. The full variation in the ratio of the maximum to minimum pullup and pulldown current does not exceed

1.7, for device drain to source voltages from 0.1 to 1.0.

5. The full variation in the ratio of the nominal pullup to pulldown current should be unity M 10ꢅ, for device

drain to source voltages from 0.1 to 1.0V.

V0.91, 2002-11-14

Page 53 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Weak Strength Driver Pulldown and Pullup Characteristics

Pulldown Current (mA)

Pullup Current (mA)

Nominal

Low

Nominal

High

Nominal

Low

Nominal

High

Voltage (V)

Min

Max

Min

Max

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

3.4

3.8

2.6

5.0

-3.5

-4.3

-2.6

-5.0

6.9

7.6

5.2

9.9

-6.9

-8.2

-5.2

-9.9

10.3

13.6

16.9

19.6

22.3

24.7

26.9

29.0

30.6

31.8

32.8

33.5

34.0

34.3

34.5

34.8

35.1

35.4

35.6

35.8

36.1

36.3

36.5

36.7

36.8

11.4

15.1

18.7

22.1

25.0

28.2

31.3

34.1

36.9

39.5

42.0

44.4

46.6

48.6

50.5

52.2

53.9

55.0

56.1

57.1

57.7

58.2

58.7

59.2

59.6

7.8

14.6

19.2

23.6

28.0

32.2

35.8

39.5

43.2

46.7

50.0

53.1

56.1

58.7

61.4

63.5

65.6

67.7

69.8

71.6

73.3

74.9

76.4

77.7

78.8

79.7

-10.3

-13.6

-16.9

-19.4

-21.5

-23.3

-24.8

-26.0

-27.1

-27.8

-28.3

-28.6

-28.7

-28.9

-29.0

-29.2

-29.3

-29.5

-29.6

-29.7

-29.8

-29.9

-12.0

-15.7

-19.3

-22.9

-26.5

-30.1

-33.6

-37.1

-40.3

-43.1

-45.8

-48.4

-50.7

-52.9

-55.0

-56.8

-58.7

-60.0

-61.2

-62.4

-63.1

-63.8

-64.4

-65.1

-65.8

-7.8

-14.6

-19.2

-23.6

-28.0

-32.2

-35.8

-39.5

-43.2

-46.7

-50.0

-53.1

-56.1

-58.7

-61.4

-63.5

-65.6

-67.7

-69.8

-71.6

-73.3

-74.9

-76.4

-77.7

-78.8

-79.7

10.4

13.0

15.7

18.2

20.8

22.4

24.1

25.4

26.2

26.6

26.8

27.0

27.2

27.4

27.7

27.8

28.0

28.1

28.2

28.3

28.4

28.5

28.6

-10.4

-13.0

-15.7

-18.2

-20.4

-21.6

-21.9

-22.1

-22.2

-22.3

-22.4

-22.6

-22.7

-22.8

-22.9

-23.0

-23.1

-23.2

-23.3

V0.91, 2002-11-14

Page 54 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating

Conditions, I_DDSpecifications and Conditions, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to V_SS

.

2. Tests for AC timing, I_DD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply

voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

3. The figure below represents the timing reference load used in defining the relevant timing parameters of the part. It is

not intended to be either a precise representation of the typical system environment nor a depiction of the actual load

presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing ref-

erence load to a system environment. Manufacturers will correlate to their production test conditions (generally a

coaxial transmission line terminated at the tester electronics).

4. AC timing and I_DDtests may use a V_ILto V_IHswing of up to 1.5V in the test environment, but input timing is still refer-

enced to V_REF(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC

input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between

V_IL(AC)and V_IH(AC)

.

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively

switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not

ring back above (below) the DC input LOW (HIGH) level)

6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating,DDR SDRAM

Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest JEDEC

specification for DDR components

AC Output Load Circuit Diagram / Timing Reference Load

V_TT

50ꢆ

Output

Timing Reference Point

(V_OUT

)

30pF

AC Operating Conditions

(0 °C ?ꢀT_A?ꢀ70ꢀLCꢁꢀV_DDQ= 2.5V Mꢀ0.2V; V_DD= 2.5V Mꢀ0.2V)

Symbol

Parameter/Condition

Min

+ 0.31

REF

Max

Unit

V

Notes

1, 2

V

Input High (Logic 1) Voltage, DQ, DQS, and DM Signals

Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals

Input Differential Voltage, CK and CK Inputs

V

IH(AC)

V

ꢁ 0.31

REF

V

1, 2

IL(AC)

ID(AC)

IX(AC)

V

0.7

V

+ 0.6

V

1, 2, 3

1, 2, 4

DDQ

Input Closing Point Voltage, CK and CK Inputs

0.5*V

ꢁ 0.2 0.5*V

ꢂ 0.2

DDQ

V

DDQ

1. Input slew rate = 1V/nsꢅ

2. Inputs are not recognized as valid until V

stabilizes.

REF

3. V is the magnitude of the difference between the input level on CK and the input level on CK.

ID

4. The value of V is expected to equal 0.5*V

of the transmitting device and must track variations in the DC level of the same.

IX

DDQ

V0.91, 2002-11-14

Page 55 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

IDD Specification and Conditions

DDR200

DDR266

DDR333

Notes

4

Symbol

Parameter/Condition

Unit

typical max typical max typical max

Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK = tCK MIN;

IDD0 DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs

changing once every two clock cycles

103

120

113

130

127

145

mA

1, 2

x4/x8

126

130

140

145

139

144

155

160

151

156

170

175

Operating Current: one bank; active/read/precharge; Burst = 4;

IDD1

Refer to the following page for detailed test conditions.

x16

Precharge Power-Down Standby Current: all banks idle; power-down mode;

CKE <= VIL MAX; tCK = tCK MIN

IDD2P

6.5

25

9

7

10

35

28

18

45

7.5

36

28

16

43

11

41

33

20

50

Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle;

CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs changing once per

clock cycle, VIN = VREF for DQ, DQS and DM.

IDD2F

IDD2Q

IDD3P

28

23

15

37

31

24

14

38

Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle;

CKE >= VIH MIN; tCK = tCK MIN; address and other control inputs stable

at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.

20

Active Power-Down Standby Current: one bank active; power-down mode;

CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and DM.

11.5

31

Active Standby Current: one bank active; CS >= VIH MIN; CKE >= VIH MIN;

IDD3N tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and DQS inputs changing twice per clock

cycle; address and control inputs changing once per clock cycle

Operating Current: one bank active; Burst = 2; reads; continuous

burst; address and control inputs changing once per clock cycle;

IDD4R 50% of data outputs changing on every clock edge;

x4/x8

113

121

135

145

140

151

165

175

167

179

195

210

mA

1, 2

CL = 2 for DDR200, and DDR266A, CL=3 for DDR333;

tCK = tCK MIN; IOUT = 0mA

x16

Operating Current: one bank active; Burst = 2; writes; continuous

burst; address and control inputs changing once per clock cycle;

50% of data outputs changing on every clock edge; CL = 2 for

DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN

x4/x8

107

117

125

135

133

145

155

165

157

172

185

200

IDD4W

mA

1, 2

x16

Auto-Refresh Current: tRC = tRFC MIN, distributed refresh

IDD5

IDD6

IDD7

222

2.7

250

237

265

248

275

standard version

5.0

2.5

2.8

2.4

5.0

2.5

2.8

2.4

5.0

2.5

mA

Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK

MIN

1, 2, 3

1, 2

low power version 2.4

264

310

320

279

294

330

340

339

355

380

400

x4/x8

Operating Current: four bank; four bank interleaving with BL=4;

Refer to the following page for detailed test conditions.

mA

277

x16

1. IDD specifications are tested after the device is properly initialized and measured

at 100 MHz for DDR200, 133 MHz for DDR266 and 166 MHz for DDR333

2. Input slew rate = 1V/ns.

3. Enables on-chip refresh and address counters

4. Test condition for typical values : VDD = 2.5V ,Ta = 25°C, test condition for maximum values: test limit at VDD = 2.7V ,Ta = 10°C

V0.91, 2002-11-14

Page 56 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

IDD Current Measurement Conditions

IDD1 : Operating current : One bank operation

1. Only one bank is accessed with t_RC(min), Burst Mode, Address and Control inputs on NOP edge are changing once

per clock cycle. l_out= 0 mA

2. Timing patterns

- DDR200 (100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRCD = 2 * tCK, tRAS = 5 * tCK

Setup: A0 N R0 N N P0 N

Read : A0 N R0 N N P0 N - repeat the same timing with random address changing

50% of data changing at every burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRCD = 3 * tCK, tRC = 9 * tCK, tRAS = 5 * tCK

Setup: A0 N N R0 N P0 N N N

Read : A0 N N R0 N P0 N NN - repeat the same timing with random address changing

50% of data changing at every burst

- DDR333 (166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRCD = 3 * tCK, tRC = 9 * tCK, tRAS = 5 * tCK

Setup: A0 N N R0 N P0 N N N

Read : A0 N N R0 N P0 N N N - repeat the same timing with random address changing

50% of data changing at every burst

3.Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

IDD7 : Operating current: Four bank operation

1. Four banks are being interleaved with t_RC(min), Burst Mode, Address and Control inputs on NOP edge are not

changing. l_out= 0 mA

2. Timing patterns

- DDR200 (100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRRD = 2 * tCK, tRCD= 3 * tCK, Read with autoprecharge

Setup: A0 N A1 R0 A2 R1 A3 R2

Read : A0 R3 A1 R0 A2 R1 A3 R2- repeat the same timing with random address changing

50% of data changing at every burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRRD = 2 * tCK, tRCD = 3 * tCK

Setup: A0 N A1 R0 A2 R1 A3 R2 N R3

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing

50% of data changing at every burst

- DDR333 (166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRRD = 2 * tCK, tRCD = 3 * tCK

Setup: A0 N A1 R0 A2 R1 A3 R2 N R3

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing

50% of data changing at every burst

3.Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

V0.91, 2002-11-14

Page 57 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Electrical Characteristics & AC Timing - Absolute Specifications

(0 LC ?ꢀT_A?ꢀ70ꢀLCꢁꢀV_DDQ= 2.5V Mꢀ0.2V; V_DD= 2.5V Mꢀ0.2V) (Part 1 of 2)

DDR200

-8

DDR266A

-7

DDR333

-6

Symbol

Parameter

Unit Notes

Min

ꢁ 0.8

0.45

Max

ꢂ 0.8

0.55

Min

Max

ꢂ 0.75

0.55

Min

Max

ꢂ 0.7

ꢂ 0.6

0.55

t

DQ output access time from CK/CK

DQS output access time from CK/CK

CK high-level width

ꢁ 0.75

0.45

ꢁ 0.7

ꢁ 0.6

0.45

ns

1-4

AC

t

DQSCK

t

CH

CK

t

CK low-level width

0.45

0.55

t

CL

HP

CK

DH

t

Clock Half Period

min (t , t

)

min (t , t

)

min (t , t )

CL CH

ns

CL CH

CL = 3.0

8

12

7

12

6

12

Clock cycle time

CL = 2.5

CL = 2.0

8

12

6

12

10

0.6

2.5

2.0

7.5

0.5

2.2

1.75

7.5

0.45

2.2

1.75

t

DQ and DM input hold time

DQ and DM input setup time

t

DS

t

Control and Addr. input pulse width (each input)

DQ and DM input pulse width (each input)

ns 1-4,10

IPW

t

DIPW

Data-out high-impedence time from

CK/CK

t

ꢁ 0.8

0.75

ꢂ 0.8

1.25

ꢂ 0.6

1.0

ꢁ 0.75

0.75

ꢂ 0.75

1.25

ꢁ 0.7

0.75

ꢂ 0.7

1.25

ns 1-4, 5

HZ

Data-out low-impedence time from

CK/CK

t

LZ

Write command to 1st DQS latching

transition

t

1-4

DQSS

DQSQ

CK

DQS-DQ skew

(DQS & associated DQ signals)

t

TSOP66

ꢂ 0.5

0.75

ꢂ 0.45

0.55

ns

Data hold skew factor

TSOP66

t

ns

QHS

t

DQ/DQS output hold time

t

-t

t

-t

t

-t

1-4

QH

HP QHS

ns

t

DQS input low (high) pulse width (write cycle)

DQS falling edge to CK setup time (write cycle)

DQS falling edge hold time from CK (write cycle)

Mode register set command cycle time

Write preamble setup time

0.35

0.2

2

0.35

0.2

2

0.35

0.2

2

t

DQSL,H

CK

t

DSS

DSH

MRD

t

0

ns 1-4, 7

WPRES

t

Write postamble

0.40

0.25

1.1

0.9

0.40

0.60

0.40

0.25

0.9

1.0

0.9

1.0

0.9

0.40

0.60

0.40

0.25

0.75

0.8

0.75

0.8

0.9

0.40

0.60

t

1-4, 6

1-4

WPST

CK

t

Write preamble

t

WPRE

fast slew rate

ns

Address and control input setup

time

t

IS

slow slew rate

2-4,

10,11

fast slew rate

Address and control input hold

time

t

IH

slow slew rate

t

Read preamble

Read postamble

1.1

t

1-4

RPRE

CK

t

0.60

t

RPST

V0.91, 2002-11-14

Page 58 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Electrical Characteristics & AC Timing - Absolute Specifications

(0 LC ?ꢀT_A?ꢀ70ꢀLCꢁꢀV_DDQ= 2.5V Mꢀ0.2V; V_DD= 2.5V Mꢀ0.2V) (Part 2 of 2)

DDR200

-8

DDR266A

-7

DDR333

-6

Symbol

Parameter

Unit Notes

Min

50

Max

Min

Max

Min

Max

t

Active to Precharge command

120,000

45

65

120,000

42

60

70,000

ns

1-4

RAS

t

Active to Active/Auto-refresh command period

70

RC

Auto-refresh to Active/Auto-refresh command

period

t

80

75

72

ns

1-4

RFC

RCD

t

Active to Read or Write delay

Precharge command period

Active to Autoprecharge delay

Active bank A to Active bank B command

Write recovery time

20

15

20

15

18

12

15

ns

1-4

t

RP

t

RAP

RRD

t

WR

DAL

WTR

Auto precharge write recovery

+ precharge time

t

(twr/tck) + (trp/tck)

t

1-4,9

CK

t

Internal write to read command delay

Exit self-refresh to non-read command

Exit self-refresh to read command

Average Periodic Refresh Interval

1

t

1-4

t

80

75

ns

XSNR

XSRD

200

t

CK

t

7.8

ꢃs 1-4, 8

REFI

1. Input slew rate >= 1V/ns for DDR333 & DDR266 and = 1V/ns for DDR200

2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for

signals other than CK/CK, is V CK/CK slew rate are >= 1.0 V/ns.

REF.

3. Inputs are not recognized as valid until V

stabilizes.

REF

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V

.

TT

5. t and t transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a spe-

HZ

LZ

cific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) degrades accordingly.

7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid

transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in

progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH,

LOW, or transitioning from HIGH to LOW at this time, depending on t

.

DQSS

8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.

9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.

10. These parameters guarantee device timing, but they are not necessarily tested on each device

11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/ns, mea-

sured between VOH(ac) and VOL(ac)

V0.91, 2002-11-14

Page 59 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Electrical Characteristics & AC Timing for DDR266A - Applicable Specifications

Expressed in Clock Cycles (0 LC ?ꢀT_A?ꢀ70ꢀLCꢁꢀV_DDQ= 2.5V Mꢀ0.2V; V_DD= 2.5V Mꢀ0.2V)

DDR266A @ CL=2

Symbol

Parameter

Units

Notes

Min

2

Max

t

Mode register set command cycle time

t

1-5

MRD

CK

t

Write preamble

0.25

6

WPRE

t

Active to Precharge command

Active to Active/Auto-refresh command period

16000

RAS

t

9

RC

Auto-refresh to Active/Auto-refresh

command period

t

10

t

1-5

RFC

RCD

CK

t

Active to Read or Write delay

3

t

1-5

CK

t

Precharge command period

RP

RRD

t

Active bank A to Active bank B command

Write recovery time

2

t

2

WR

DAL

WTR

t

Auto precharge write recovery + precharge time

Internal write to read command delay

Exit self-refresh to non-read command

Exit self-refresh to read command

5

t

1

t

10

200

XSNR

XSRD

t

1. Input slew rate = 1V/ns

2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for

signals other than CK/CK, is V

REF.

3. Inputs are not recognized as valid until V

stabilizes.

REF

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V

.

TT

5. t and t transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a spe-

HZ

LZ

cific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

V0.91, 2002-11-14

Page 60 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Timing Diagrams

Data Input (Write) (Timing Burst Length = 4)

t_DQSL

t_DQSH

DQS

t_DH

t_DS

DI n

DQ

t_DH

t_DS

DM

DI n = Data In for column n.

3 subsequent elements of data in are applied in programmed order following DI n.

Don’t Care

Data Output (Read) (Timing Burst Length = 4)

DQS

t_{DQSQ max}

t_QH

DQ

t

(Data output hold time from DQS)

QH

t

.

t

and t are only shown once and are shown referenced to different edges of DQS, only for clarify of illustration.

QH

DQSQ

and t both apply to each of the four relevant edges of DQS.

QH

t

is used to determine the worst case setup time for controller data capture.

DQSQ max.

is used to determine the worst case hold time for controller data capture.

QH

V0.91, 2002-11-14

Page 61 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Initialize and Mode Register Sets

V0.91, 2002-11-14

Page 62 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Power Down Mode

V0.91, 2002-11-14

Page 63 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Auto Refresh Mode

V0.91, 2002-11-14

Page 64 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Self Refresh Mode

V0.91, 2002-11-14

Page 65 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Read without Auto Precharge (Burst Length = 4)

V0.91, 2002-11-14

Page 66 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Read with Auto Precharge (Burst Length = 4)

V0.91, 2002-11-14

Page 67 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Bank Read Access (Burst Length = 4)

V0.91, 2002-11-14

Page 68 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write without Auto Precharge (Burst Length = 4)

V0.91, 2002-11-14

Page 69 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write with Auto Precharge (Burst Length = 4)

V0.91, 2002-11-14

Page 70 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Bank Write Access (Burst Length = 4)

V0.91, 2002-11-14

Page 71 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Write DM Operation (Burst Length = 4)

V0.91, 2002-11-14

Page 72 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Package Dimensions

Plastic Package, P-TSOPII-66

(400mil; 66 lead

)

Thin Small Outline Package

G auge P lane

10,16±0,13

0,5±0,1

0,65 B asic

0,805 R E F

0.1

Seating Plane

±0,08

0,3

11,76±0,2

22,22±0,13

TS O P 66

Lead #1

V0.91, 2002-11-14

Page 73 of 77

HYB25D512400/800/160AT(L)

512-MBit Double Data Rata SDRAM

Preliminary Datasheet V0.91, 2002-11-14

Random Write Cycles

Write to Read: Non-Interrupting

Write to Read: Interrupting

34

35

36

TABLE OF CONTENT

Features

1

Write to Read: Minimum DQSS, Interrupting 37

Write to Read: Nominal DQSS, Interrupting 38

Description

1

2

3

4

5

6

7

Write to Precharge: Non-Interrupting

Write to Precharge: Interrupting

Write to Precharge: Minimum DQSS

Write to Precharge: Nominal DQSS

Precharge

Precharge Command

Power-Down

Truth Table 2: Clock Enable (CKE)

Truth Table 3: Current State (Same Bank)

39

40

41

42

43

44

45

46

Pin Configuration TSOP66

Input/Output Functional Description

Ordering Information

Block Diagram (128Mbit x 4)

Block Diagram (64Mbit x 8)

Block Diagram (32Mbit x 16)

Functional Description

Initialization

Register Definition

Mode Register Operation

Burst Definition

Operating Mode

Required CAS Latencies

Extended Mode Register

Extended Mode Register Definition

8

9

10

11

12

13

14

Truth Table 4: Current State (Different bank) 47

Truth Table 5: Concurrent Auto Precharge

48

50

Simplified State Diagram

Operating Conditions

Absolute Maximum Ratings

51

52

53

55

57

58

59

60

Input and Output Capacitances

DC Electrical Operating Conditions

Normal Strength Characteristics

Weak Strength Characteristics

AC Characteristics

AC Output Load Circuit Diagram

AC Operating Conditions

IDD Specification and Conditions

IDD Current Measurement Conditions

Electrical Characteristics & AC Timing

Commands

15

16

17

Deselect, No Operation (NOP)

Mode Register Set

Active

Read

Write

Precharge

Auto Precharge

Burst Terminate

Auto Refresh

Self Refresh

Truth Table 1a: Commands

Truth Table 1b: DM Operation

Timing Diagrams

Data Input (Write)

Data Output (Read)

Initialize and Mode Register Sets

Power Down Mode

Auto Refresh Mode

Self Refresh Mode

Read without Auto Precharge (BL = 4)

Read with Auto Precharge (BL = 4)

Bank Read Access (Burst Length = 4)

Write without Auto Precharge (BL = 4)

63

64

65

66

67

68

69

70

71

Operations

Bank/Row Activation

Read Command

18

20

21

22

23

24

26

27

28

29

31

32

Read Burst: CAS Latencies

Consecutive Read Bursts

Non-Consecutive Read Bursts

Random Read Accesses

Terminating a Read Burst

Read to Write

Read to Precharge

Write Command

Write Burst

Write with Auto Precharge (Burst Length = 4) 72

Bank Write Access (Burst Length = 4)

Write DM Operation (Burst Length = 4)

Package Dimensions

73

74

75

TABLE OF CONTENT

76

Write to Write

Write to Write: Max DQSS, Non-Consecutive

33

V0.91, 2002-11-14

Page 74 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Attention please !

As far as patents or other rights of third parties are concerned, liability is only

assumed for components, not for applications, processes and circuits

implemented within components or assemblies. This information describes

the type of components and shall not be considered as assured

characteristics. Terms of delivery and rights to change design reserved.

For questions on technology, delivery and prices please contact INFINEON

Technologies Offices in Munich or the INFINEON Technologies Sales Offices

and Representatives worldwide.

Due to technical requirements components may contain dangerous

substances. For information on the types in question please contact your

nearest INFINEON Technologies office or representative.

Packing

Please use the recycling operators known to you. We can help you - get in

touch with your nearest sales office. By agreement we will take packing

material back, if it is sorted. You must bear the costs of transport. For packing

material that is returned to us unsorted or which we are not obliged to accept,

we shall have to invoice you for any costs incurred.

Components used in life-support devices or systems must be expressly

authorized for such purpose!

Critical components¹of INFINEON Technologies, may only be used in life-

support devices or systems²with the express written approval of INFINEON

Technologies.

1. A critical component is a component used in a life-support device or system

whose failure can reasonably be expected to cause the failure of that life-

support device or system, or to affect the safety or effectiveness of that device

or system.

2. Life support devices or systems are intended (a) to be implanted in the

human body, or (b) to support and/or maintain and sustain human life. If they

fail, it is reasonable to assume that the health of the user may be endangered.

V0.91, 2002-11-14

Page 75 of 77


型号：	HYB25D512160AEL-7
厂家：	Infineon
描述：	DDR DRAM, 32MX16, 0.75ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66 动态存储器双倍数据速率光电二极管
文件：	总75页 (文件大小：2025K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYB25D512160AEL-7 [INFINEON]

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