HYB25D512400AR-8 [INFINEON]
DDR DRAM Module, 128MX4, CMOS, PDMA66, 0.400 INCH, PLASTIC, TSSOP2-66;
| 型号： | HYB25D512400AR-8 |
| 厂家： | 
Infineon |
| 描述： | DDR DRAM Module, 128MX4, CMOS, PDMA66, 0.400 INCH, PLASTIC, TSSOP2-66 动态存储器 双倍数据速率 光电二极管 |
| 文件： | 总4页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYB25D512400A/BS/R
Stacked 512-MBit DDR-SDRAM
Preliminary Datasheet 2002-09-27 (Rev. 0.92)
Features
CAS Latency and Frequency
• Four internal banks for concurrent operation
• Data mask (DM) for write data
Maximum Operating Frequency (MHz)
DDR266F DDR266A DDR266B DDR200
CAS Latency
• DLL aligns DQ and DQS transitions with CK
transitions.
-7F
133
143
-7
-7.5
125
133
-8
2
133
143
100
125
• Commands entered on each positive CK edge;
data and data mask referenced to both edges of
DQS
2.5
• Two 256Mbit DDR-SDRAM packages stacked
with two seperate chip-select (CS) inputs
• Burst lengths: 2, 4, or 8
• Double data rate architecture: two data transfers
per clock cycle
• CAS Latency: 2, 2.5
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• Bidirectional data strobe (DQS) is transmitted
and received with data, to be used in capturing
data at the receiver
• 7.8 µs Maximum Average Periodic Refresh
Interval
• DQS is edge-aligned with data for reads and is
center-aligned with data for writes
• 2.5V (SSTL_2 compatible) I/O
• V
= 2.5V ± 0.2V / V = 2.5V ± 0.2V
DD
DDQ
• Differential clock inputs (CK and CK)
• Stacked two TSOP66 packages
Description
The Stacked 512Mb DDR SDRAM is a high-speed
CMOS, dynamic random-access memory containing
two 256Mbit SDRAM with 268,435,456 bits. It is
internally configured as two quad-bank DRAM.
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and
output data is referenced to both edges of DQS, as
well as to both edges of CK.
The two 256Mb DDR SDRAM use a double-data-
rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O
pins. A single read or write access for the 256Mb
DDR SDRAM effectively consists of a single 2n-bit
wide, one clock cycle data transfer at the internal
DRAM core and two corresponding n-bit wide, one-
half-clock-cycle data transfers at the I/O pins. The
upper and lower 256Mbit component can be
selected by two seperated chip-select input signal
CS0 and CS1
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with
the registration of an Active command, which is then
followed by a Read or Write command. The address
bits registered coincident with the Active command
are used to select the bank and row to be accessed.
The address bits registered coincident with the
Read or Write command are used to select the bank
and the starting column location for the burst
access.
The DDR SDRAM provides for programmable Read
or Write burst lengths of 2, 4 or 8 locations. An Auto
Precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end
of the burst access.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the
DDR SDRAM during Reads and by the memory
controller during Writes. DQS is edge-aligned with
data for Reads and center-aligned with data for
Writes.
An auto refresh mode is provided along with a
power-saving power-down mode. All inputs are
compatible with the JEDEC Standard for SSTL_2.
All outputs are SSTL_2, Class II compatible.
The zwo 256Mb DDR SDRAM operate from a differ-
ential clock (CK and CK; the crossing of CK going
HIGH and CK going LOW is referred to as the posi-
tive edge of CK). Commands (address and control
2002-09-27 (0.92)
Page 1 of 4
HYB25D512400A/BS/R
Stacked 512-MBit DDR-SDRAM
Ordering Information
CAS
Latency
Clock
(MHz)
CAS
Latency
Clock
(MHz)
Part Number
Speed
Org.
Package
HYB25D512400AS-7
HYB25D512400AS-7.5
HYB25D512400AS-8
HYB25D512400AR-7
HYB25D512400AR-7.5
HYB25D512400AR-8
143
133
125
143
133
125
133
125
100
133
125
100
DDR266A
DDR266B
DDR200
x 4
x 4
x 4
x 4
x 4
x 4
Two stacked
66 pin TSOP-II
packages
2.5
2.5
2
2
(Soldering Process)
DDR266A
DDR266B
DDR200
Two stacked 66 pin
TSOP-II packages
(Laser Welding
Process)
CAS
Latency
Clock
(MHz)
CAS
Latency
Clock
(MHz)
Part Number
Speed
Org.
Package
HYB25D512400BS-7F
HYB25D512400BS-7
HYB25D512400BS-7.5
HYB25D512400BS-8
HYB25D512400BR-7F
HYB25D512400BR-7
HYB25D512400BR-7.5
HYB25D512400BR-8
143
143
133
125
143
143
133
125
133
133
125
100
133
133
125
100
DDR266F
DDR266A
DDR266B
DDR200
x4
x 4
x 4
x 4
x4
Two stacked
66 pin TSOP-II
packages
2.5
2.5
2
2
(Soldering Process)
DDR266F
DDR266A
DDR266B
DDR200
Two stacked
66 pin TSOP-II
packages
x 4
x 4
x 4
(Laser Welding
Process)
2002-09-27 (0.92)
Page 2 of 4
HYB25D512400A/BS/R
Stacked 512-MBit DDR-SDRAM
Pin Configuration
VDD
NC
1
2
3
4
5
66
VSS
NC
65
64
63
62
VDDQ
NC
VSSQ
NC
DQ0
DQ3
VSSQ
NC
6
61
60
59
58
57
VDDQ
NC
7
NC
8
NC
VDDQ
NC
9
VSSQ
NC
10
DQ1
VSSQ
NC
11
12
56
55
DQ2
VDDQ
13
14
15
16
17
18
19
20
54
53
52
51
50
49
48
47
NC
NC
NC
VSSQ
DQS
NC
VDDQ
NC
NC
VDD
NU
VREF
VSS
DM*
NC
WE
21
22
46
45
CK
CK
CAS
RAS
23
24
25
44
CKE0
CS0
CS1
43
42
CKE1
A12
BA0
BA1
26
27
28
29
41
40
39
38
A11
A9
A8
A10/AP
A7
A0
A1
A2
A6
A5
30
31
37
36
A3
A4
32
33
35
34
VDD
VSS
66-pin Plastic TSOP-II 400mil
64Mb x 4
I
Column Address Table
Organization
Column Address
64Mb x 4
32Mb x 8
A0-A9, A11
A0-A9
*DM is internally loaded to match DQ and DQS identically.
2002-09-27 (0.92)
Page 3 of 4
HYB25D512400A/BS/R
Stacked 512-MBit DDR-SDRAM
Block Diagram for one SDRAM component (64Mb x 4)
CKE
CK
CK
CSx
WE
CAS
Bank3
RAS
Bank2
Bank1
CK, CK
DLL
Mode
13
Registers
8192
Bank0
Memory
Array
Data
15
13
(8192 x 1024 x 8)
4
4
4
8
Sense Amplifiers
1
DQS
Generator
DQ0-DQ3,
DM
COL0
Mask
DQS
Input
Register
1
I/O Gating
DM Mask Logic
8
2
DQS
1
1
A0-A12,
BA0, BA1
Write
15
1
FIFO
1
&
8
2
8
1024
(x8)
2
Drivers
4
4
4
4
4
clk
clk
Column
Decoder
in
out
Data
10
COL0
CK,
CK
Column-Address
Counter/Latch
11
COL0
1
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
2002-09-27 (0.92)
Page 4 of 4
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