HYB3116405BTL-60_技术文档

3.3V 4M x 4-Bit EDO-Dynamic RAM

HYB3116405BJ/BT(L) -50/-60/-70

HYB3117405BJ/BT(L) -50/-60/-70

Advanced Information

• 4 194 304 words by 4-bit organization

• 0 to 70 °C operating temperature

• Performance

-50

50

13

25

84

20

-60

60

15

30

-70

70

20

35

t

RAS access time

ns

RAC

CAC

AA

CAS access time

Access time from address

Read/Write cycle time

104 124 ns

25 30 ns

RC

Hyper page mode (EDO)

cycle time

HPC

• Single + 3.3 V (± 0.3V ) supply

• Low power dissipation

max. 396 active mW (HYB3117405BJ/BT-50)

max. 363 active mW (HYB3117405BJ/BT-60)

max. 330 active mW (HYB3117405BJ/BT-70)

max. 360 active mW (HYB3116405BJ/BT-50)

max. 324 active mW (HYB3116405BJ/BT-60)

max. 288 active mW (HYB3116405BJ/BT-70)

7.2 mW standby (LV-TTL)

3.6 mW standby (LV-CMOS)

720 µW standby for L-version

• Output unlatched at cycle end allows two-dimensional chip selection

• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,

Self Refresh and test mode

• Hyper page mode (EDO) capability

• All inputs, outputs and clocks fully TTL-compatible

• 2048 refresh cycles / 32 ms for HYB3117405

4096 refresh cycles / 64 ms for HYB3116405

• Plastic Package:

P-SOJ-26/24-1 (300 mil)

P-TSOPII-26/24-1 (300mil)

Semiconductor Group

1

3.96

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

The HYB 3116(7)405BJ/BT(L) is a 16MBit dynamic RAM organized as 4194304 words by 4-bits.

The HYB 3116(7)405BJ/BT(L) utilizes a submicron CMOS silicon gate process technology, as well

as advanced circuit techniques to provide wide operating margins, both internally and for the system

user. Multiplexed address inputs permit the HYB 3116(7)405BJ/BT(L) to be packaged in a standard

SOJ 26/24 300 mil or TSOPII-26/24 300 mil wide plastic package. These packages provide high

system bit densities and are compatible with commonly used automatic testing and insertion

equipment. System-oriented features include single + 3.3 V (± 0.3 V) power supply, direct

interfacing with high-performance logic device families.The HYB3116405BTL parts have a very low

power „sleep mode“ supported by Self Refresh.

Ordering Information

Type

Ordering Code

Q67100-Q1119

Q67100-Q1120

Package

Descriptions

HYB 3117405BJ-50

HYB 3117405BJ-60

HYB 3117405BJ-70

HYB 3117405BT-50

HYB 3117405BT-60

HYB 3117405BT-70

HYB 3116405BJ-50

HYB 3116405BJ-60

HYB 3116405BJ-70

HYB 3116405BT-50

HYB 3116405BT-60

HYB 3116405BT-70

HYB 3116405BTL-50

HYB 3116405BTL-60

HYB 3116405BTL-70

P-SOJ-26/24-1 300 mil

P-TSOPII-26/24-1 300 mil

P-SOJ-26/24-1 300 mil

P-TSOPII-26/24-1 300 mil

DRAM (access time 50 ns)

DRAM (access time 60 ns)

DRAM (access time 70 ns)

DRAM (access time 50 ns)

DRAM (access time 60 ns)

DRAM (access time 70 ns)

DRAM (access time 50 ns)

DRAM (access time 60 ns)

DRAM (access time 70 ns)

DRAM (access time 50 ns)

DRAM (access time 60 ns)

DRAM (access time 70 ns)

LP-DRAM (access time 50 ns)

LP-DRAM (access time 60 ns)

LP-DRAM (access time 70 ns)

Q67100-Q1135

Q67100-Q1136

Q67100-Q1184

Q67100-Q1127

Q67100-Q1128

Q67100-Q1143

Q67100-Q1144

Q67100-Q1186

on request

Semiconductor Group

2

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

Vcc

1

2

3

4

5

6

26

25

24

23

22

21

Vss

I/O4

I/O3

CAS

OE

Vcc

I/O1

I/O2

WE

RAS

A11

1

2

3

4

5

6

26

25

24

23

22

21

Vss

I/O4

I/O3

CAS

OE

I/O1

I/O2

WE

RAS

N.C.

A9

A10

A0

A1

A2

A3

8

9

10

11

12

19

18

17

16

15

14

A8

A7

A6

A5

A4

Vss

A10

A0

A1

A2

A3

8

9

10

11

12

13

19

18

17

16

15

14

A8

A7

A6

A5

A4

Vss

VCC 13

VCC

HYB3117405BJ/BT

HYB3116405BJ/BT

P-SOJ-26/24-1

(300mil)

P-TSOPII-26/24-1 (300mil)

Pin Configuration

Pin Names

A0 to A10 Row & Column Address Inputs for HYB3117405

A0 to A11 Row Address Inputs for HYB3116405

A0 to A9

RAS

Column Address Inputs for HYB3116405

Row Address Strobe

OE

Output Enable

I/O1 -I/O4 Data Input/Output

CAS

WE

V_CC

Column Address Strobe

Read/Write Input

Power Supply (+ 3.3 V)

Ground (0 V)

V_SS

N.C.

not connected

Semiconductor Group

3

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

I/O1 I/O2 I/O3 I/O4

WE

&

.

CAS

Data in

Buffer

Data out

Buffer

OE

No. 2 Clock

Generator

4

Column

Address

Buffer(11)

11

Column

Decoder

11

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

Refresh

Sense Amplifier

I/O Gating

Controller

4

Refresh

Counter (11)

2048

x4

11

A10

Row

Address

Buffers(11)

Row

Decoder

Memory Array

2048x2048x4

11

2048

No. 1 Clock

Generator

RAS

Block Diagram for HYB3117405

Semiconductor Group

4

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

I/O1 I/O2 I/O3 I/O4

WE

&

.

CAS

Data in

Buffer

Data out

Buffer

OE

No. 2 Clock

Generator

4

Column

Address

Buffer(10)

10

Column

Decoder

10

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

Refresh

Sense Amplifier

I/O Gating

Controller

4

Refresh

Counter (12)

1024

x4

12

A10

A11

Row

Address

Buffers(12)

Row

Decoder

Memory Array

4096x1024x4

12

4096

No. 1 Clock

Generator

RAS

Block Diagram for HYB3116405

Semiconductor Group

5

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

Absolute Maximum Ratings

Operating temperature range ............................................................................................0 to 70°C

Storage temperature range.........................................................................................– 55 to 150 °C

Input/output voltage ................................................................................-0.5 to min(Vcc+0.5, 4.6) V

Power supply voltage.................................................................................................- 0.5 V to 4.6 V

Power dissipation.................................................................................................................... 0.5 W

Data out current (short circuit) ................................................................................................ 50 mA

Note:

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of

the device. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

DC Characteristics (values in brackets for HYB3117405)

T_A= 0 to 70 °C, V_SS= 0 V, V_CC= 3.3 V ± 0.3 V, t_T= 2 ns

Parameter

Symbol

Limit Values

Unit Test

Condition

min.

max.

Vcc+0.5

0.8

1)

Input high voltage

V_IH

V_IL

2.0

– 0.5

2.4

–

V

Input low voltage

V

TTL Output high voltage (I_OUT= – 2 mA)

TTL Output low voltage (I_OUT= 2 mA)

CMOS Output high voltage (I_OUT= –100 uA)

CMOS Output low voltage (I_OUT= 100 uA)

V_OH

V_OL

V_OH

V_OL

I_I(L)

–

V

0.4

V

VCC-0.2 –

V

–

0.2

V

1)

Input leakage current

(0 V ≤ V_IH≤ Vcc + 0.3V, all other pins = 0 V)

– 10

10

µA

Output leakage current

(DO is disabled, 0 V ≤ V_OUT≤ Vcc + 0.3V)

I_O(L)

I_CC1

– 10

10

µA

Average V_CCsupply current:

-50 ns version

2) 3) 4)

–

100(120) mA

90 (110) mA

80 (100) mA

-60 ns version

-70 ns version

(RAS, CAS, address cycling, t_RC= t_RCmin.)

Standby V_CCsupply current (RAS = CAS = V_IH) I_CC2

–

2

mA

–

Semiconductor Group

6

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

DC Characteristics (values in brackets for HYB3117405)

T_A= 0 to 70 °C, V_SS= 0 V, V_CC= 3.3 V ± 0.3 V, t_T= 2 ns

Parameter Symbol

Limit Values

Unit Test

Condition

min.

max.

Average V_CCsupply current, during RAS-only I_CC3

2) 4)

refresh cycles:

-50 ns version

-60 ns version

-70 ns version

–

100(120) mA

90 (110) mA

80 (100) mA

(RAS cycling: CAS = V_IH, t_RC= t_RCmin.)

Average V_CCsupply current, during hyper page I_CC4

2) 3) 4)

mode EDO):

-50 ns version

-60 ns version

-70 ns version

–

70 (70)

55 (55)

45 (45)

mA

(RAS = V_IL, CAS, address cycling, t_PC= t_PCmin.)

1)

Standby V_CCsupply current

(RAS = CAS = V_CC– 0.2 V)

I_CC5

–

1

200

mA

µA

L-version

Average V_CCsupply current, during CAS-

before-RAS refresh mode: -50 ns version

-60 ns version

I_CC6

2) 4)

–

100(120) mA

90 (110) mA

80 (100) mA

-70 ns version

(RAS, CAS cycling, t_RC= t_RCmin.)

I_CC7

_

1

mA

Average Self Refresh Current

250

µA

L-version

(CBR cylce with tRAS>TRASSmin., CAS held low,

WE=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)

Capacitance

T_A= 0 to 70 °C,V_CC= 3.3 V ± 0.3V, f = 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A10, A11)

Input capacitance (RAS, CAS, WE, OE)

I/O capacitance (I/O1 - I/O4)

C_I1

C_I2

C_IO

–

5

7

pF

Semiconductor Group

7

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

5)6)

16E

AC Characteristics

T_A= 0 to 70 °C,V_CC= 5 V ± 10 %, t_T= 2 ns

Symbol

Unit Note

Parameter

Limit Values

-60

-50

-70

min. max. min. max. min. max.

common parameters

Random read or write cycle time t_RC

84

30

50

8

–

104

40

60

10

0

–

124

50

70

12

0

–

ns

RAS precharge time

t_RP

–

RAS pulse width

t_RAS

t_CAS

t_ASR

t_RAH

t_ASC

t_CAH

t_RCD

t_RAD

t_RSH

t_CSH

t_CRP

t_T

10k

–

10k

–

10k

–

CAS pulse width

Row address setup time

Row address hold time

Column address setup time

Column address hold time

RAS to CAS delay time

RAS to column address delay

RAS hold time

0

8

–

10

0

–

10

0

–

0

–

8

–

10

14

12

15

50

5

–

12

14

12

17

60

5

–

12

10

13

40

5

37

25

45

30

–

53

35

–

CAS hold time

–

CAS to RAS precharge time

Transition time (rise and fall)

–

1

50

64

32

256

1

50

64

32

256

1

50

64

32

ns

7

Refresh period for HYB5116405 t_REF

Refresh period for HYB5117405 t_REF

–

ms

–

Refresh period for L-version

t_REF

–

256 ms

Read Cycle

Access time from RAS

Access time from CAS

t_RAC

t_CAC

–

50

13

25

13

–

60

15

30

15

–

70

17

35

17

–

ns 8, 9

ns 8,10

ns

–

Access time from column address t_AA

–

OE access time

t_OEA

–

Column address to RAS lead time t_RAL

25

0

30

0

35

0

ns

Read command setup time

Read command hold time

t_RCS

t_RCH

t_RRH

–

ns

0

–

0

–

0

–

ns 11

Read command hold time

referenced to RAS

0

–

0

–

0

–

CAS to output in low-Z

t_CLZ

0

–

0

–

0

–

ns

8

Semiconductor Group

8

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

5)6)

16E

AC Characteristics (cont’d)

T_A= 0 to 70 °C,V_CC= 5 V ± 10 %, t_T= 2 ns

Symbol

Unit Note

Parameter

Limit Values

-60

-50

-70

min. max. min. max. min. max.

Output buffer turn-off delay

Output turn-off delay from OE

Data to CAS low delay

Data to OE low delay

t_OFF

t_OEZ

t_DZC

t_DZO

t_CDD

t_ODD

0

13

–

0

15

–

0

17

–

ns 12

ns 13

ns 14

0

–

0

–

0

–

CAS high to data delay

OE high to data delay

10

–

13

–

15

–

Write Cycle

Write command hold time

Write command pulse width

Write command setup time

t_WCH

t_WP

8

–

10

0

–

10

0

–

ns

8

ns

t_WCS

0

ns 15

ns

Write command to RAS lead time t_RWL

Write command to CAS lead time t_CWL

13

0

15

0

17

0

ns

Data setup time

Data hold time

t_DS

t_DH

ns 16

8

10

12

Read-modify-Write Cycle

Read-write cycle time

RAS to WE delay time

CAS to WE delay time

t_RWC

t_RWD

t_CWD

113

64

–

138

77

–

162

89

–

ns

ns 15

ns

27

32

36

Column address to WE delay time t_AWD

39

47

54

OE command hold time

t_OEH

10

13

15

Hyper Page Mode (EDO) Cycle

Hyper page mode (EDO) cycle

time

t_HPC

t_CP

20

–

25

–

30

–

ns

CAS precharge time

8

–

10

–

10

–

Access time from CAS precharge t_CPA

–

27

–

32

–

37

–

ns

7

Output data hold time

t_COH

t_RAS

5

RAS pulse width in EDO mode

50

200k 60

200k 70

200k ns

Semiconductor Group

9

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

5)6)

16E

AC Characteristics (cont’d)

T_A= 0 to 70 °C,V_CC= 5 V ± 10 %, t_T= 2 ns

Symbol

Unit Note

Parameter

Limit Values

-60

-50

-70

min. max. min. max. min. max.

CAS precharge to RAS Delay

t_RHPC

27

–

32

–

37

–

ns

Hyper Page Mode (EDO) Read-modify-Write Cycle

Hyper page mode (EDO) read-

write cycle time

t_PRWC

58

–

68

49

–

77

56

–

ns

CAS precharge to WE

t_CPWD

41

–

CAS-before-RAS Refresh Cycle

CAS setup time

t_CSR

t_CHR

t_RPC

t_WRP

10

5

–

10

5

–

10

5

–

ns

CAS hold time

RAS to CAS precharge time

Write to RAS precharge time

10

Write hold time referenced to RAS t_WRH

CAS-before-RAS Counter Test Cycle

CAS precharge time

t_CPT

35

–

40

–

40

–

ns

Self Refresh Cycle

RAS pulse width

RAS precharge

CAS hold time

t_RASS

t_RPS

t_CHS

100k _

ns 17

95

_

110

-50

_

130

-50

_

-50

Test Mode

Write command setup time

Write command hold time

CAS hold time

t_WTS

t_WTH

t_CHRT

10

30

–

10

30

–

10

30

–

ns

Semiconductor Group

10

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

Notes:

1) All voltages are referenced to V_SS.

2) I_CC1, I_CC3, I_CC4and I_CC6depend on cycle rate.

3) I_CC1and I_CC4depend on output loading. Specified values are obtained with the output open.

4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during

a hyper page mode (EDO) cycle

5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has

to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,

a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.

6) AC measurements assume t_T= 2 ns.

7) V_{IH (min.)}and V_{IL (max.)}are reference levels for measuring timing of input signals. Transition times are also

measured between V_IHand V_IL.

8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined

by the latter of t is measured from tristate.

, t

, t ,t

, t

. t

RAC CAC AA CPA OEA CAC

9) Operation within the t_{RCD (max.)}limit ensures that t_{RAC (max.)}can be met. t_{RCD (max.)}is specified as a reference point

only. If t_RCDis greater than the specified t_{RCD (max.)}limit, then access time is controlled by t_CAC

.

10) Operation within the t_{RAD (max.)}limit ensures that t_{RAC (max.)}can be met. t_{RAD (max.)}is specified as a reference point

only. If t_RADis greater than the specified t_{RAD (max.)}limit, then access time is controlled by t_AA.

11) Either t_RCHor t_RRHmust be satisfied for a read cycle.

12) t_{OFF (max.)}, t_{OEZ (max.)}define the time at which the output achieves the open-circuit conditions and are not

referenced to output voltage levels. t_OFFis referenced from the rising edge of RAS or CAS, whichever occurs

last.

13) Either t_DZCor t_DZOmust be satisfied.

14) Either t_CDDor t_ODDmust be satisfied.

15) t_WCS, t_RWD, t_CWDand t_AWDare not restrictive operating parameters. They are included in the data sheet as

electrical characteristics only. If t_WCS> t_{WCS (min.)}, the cycle is an early write cycle and data out pin will remain

open-circuit (high impedance) through the entire cycle; if t_RWD> t_{RWD (min.)}, t_CWD> t_{CWD (min.)}and t_AWD> t_{AWD (min.)}

,

the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above

sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.

16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge

in read-write cycles.

17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM

operation:

If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR

refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.

If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the

refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately

after exit from Self Refresh

Semiconductor Group

11

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

Waveforms

t_RC

t_RAS

t_RP

V

IH

RAS

CAS

Address

WE

V

IL

t_CSH

t_CRP

t_RSH

t_CAS

t_RCD

V

IH

V

IL

t_RAD

t_ASC

t_RAL

t_CAH

t_ASR

V

IH

Column

Row

V

IL

t_RCH

t_RAH

t_RCS

t_RRH

V

IH

V

IL

t_AA

t_OEA

V

IH

OE

V

IL

t_CDD

t_DZC

t_ODD

t_DZO

V

IH

I/O

(Inputs)

V

t_CAC

t_CLZ

IL

t_OFF

t_OEZ

V

OH

I/O

(Outputs)

Hi Z

Valid Data Out

Hi Z

V

OL

t_RAC

WL1

“H” or “L”

Read Cycle

Semiconductor Group

12

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

t_RC

t_RAS

t_RP

V

IH

RAS

CAS

Address

WE

V

IL

t_CSH

t_CRP

t_RCD

t_RSH

V

t_CAS

IH

V

IL

t_RAD

t_ASC

t_RAL

t_CAH

t_ASR

.

V

IH

Row

Column

V

IL

t_CWL

t_RAH

t_WCS

V

t_WP

IH

V

IL

t_WCH

t_RWL

V

IH

OE

V

IL

t_DH

t_DS

V

IH

I/O

(Inputs)

Valid Data In

V

IL

V

OH

I/O

(Outputs)

Hi Z

V

OL

WL2

“H” or “L”

Write Cycle (Early Write)

Semiconductor Group

13

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

t_RC

t_RAS

t_RP

V

IH

RAS

CAS

Address

WE

V

IL

t_CSH

t_CRP

t_RCD

t_RSH

t_CAS

V

IH

V

IL

t_RAD

t_ASC

t_RAL

t_CAH

t_ASR

.

V

IH

Row

Column

V

IL

t_CWL

t_RWL

t_WP

t_RAH

V

IH

V

IL

t_OEH

V

IH

OE

V

t_ODD

t_DS

t_OEZ

IL

t_DH

t_DZO

t_DZC

V

IH

I/O

(Inputs)

Valid Data

V

IL

t_CLZ

t_OEA

V

OH

Hi-Z

I/O

(Outputs)

Hi-Z

V

OL

WL3

“H” or “L”

Write Cycle (OE Controlled Write)

Semiconductor Group

14

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

t_RWC

t_RAS

t_RP

V

IH

RAS

t_CSH

V

IL

t_RSH

t_CAS

t_RCD

t_CRP

V

IH

V

CAS

IL

t_RAH

t_CAH

t_ASR

t_ASC

t_ASR

V

IH

Address

Row

Column

Row

V

IL

t_CWL

t_RWL

t_WP

t_AWD

t_RAD

t_CWD

t_RWD

V

IH

WE

OE

V

IL

t_AA

t_RCS

t_OEH

t_OEA

V

IH

V

IL

t_DS

t_DH

t_DZO

t_DZC

V

IH

Valid

Data in

I/O

(Inputs)

V

IL

t_CLZ

t_CAC

t_ODD

t_OEZ

V

OH

I/O

(Outputs)

Data

Out

V

OL

t_RAC

“H” or “L”

WL4

Read-Write (Read-Modify-Write) Cycle

Semiconductor Group

15

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

t_RP

t_RAS

V

t_RCD

t_RHCP

IH

RAS

V

IL

t_RSH

t_CAS

t_CRP

t_HPC

t_CAS

t_CRP

t_CAS

t_CP

V

IH

CAS

V

IL

t_CSH

t_RAL

t_CAH

t

t_ASC

^RAHt_ASC

t_ASC

t_CAH

t_ASR

V

IH

Address

Column 2

Column N

Row

Column 1

V

IL

t_RAD

t_RRH

t_RCH

t_RCS

V

IH

WE

OE

V

t^CAC

CAC

t

IL

AA

t

AA

t

t_OES

t_OEA

t

OFF

CPA

t

t^CPA

V

OH

V

OL

t_RAC

t_AA

t_CAC

OEZ

t

t_COH

t_CLZ

V

I/O

IH

Data Out

1

Data Out

N

(Output)

2

V

IL

WL5

“H” or “L”

Hyper Page Mode (EDO) Read Cycle

Semiconductor Group

16

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

t_RP

t_RAS

V

t_RCD

t_RHCP

IH

RAS

V

IL

t_CRP

t_RSH

t_CAS

t_HPC

t_CAS

t_CRP

t_CAS

t_CP

V

IH

CAS

V

IL

t_CSH

t_RAH

t_RAL

t_CAH

t_ASC

t_CAH

t_ASC

t_CAH

t_ASR

V

IH

Row

Addr

Address

Column 1

Column 2

Column N

V

IL

t_RAD

t_RWL

t_CWL

t_WCH

t_WP

t_WCS

t_WCH

t_WP

t_WCH

t_WP

V

IH

WE

V

IL

V

OH

OE

V

OL

t_DS

t_DH

t_DS

t_DH

t_DS

V

IH

Data In 1

Data In 2

Data In N

I/O (Input)

V

IL

“H” or “L”

WL8

Hyper Page Mode (EDO) Early Write Cycle

Semiconductor Group

17

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

R

SA

t

PR

t

P

RC

t

H

L

EO

WR

t

WC

t

PW

HD

t

SRH

t

DS

t

ARL

t

DO

t

ACS

D

t

D

W

WC

D

t

A

WA

C

E

A

t

H

t

Z

t

AC

PC

LC

A

t

A

t

H

L

SAC

ZDC

EO

t

WC

t

HD

PW

t

C

SD

SP

t

S

D

RPW

A

Z

AC

t

DO

t

D

t

EO

D

W

t

W

D

t

A

WA

PC

t

Z

A

EO

t

ACH

LC

PC

t

A

t

C

L

DZ

SA

t

PC

H

t

WC

t

EO

t

PW

t

HD

t

Z

SD

t

EO

t

DO

D

t

S

AC

WC

D

t

A

D

WA

EO

H

t

C

WR

Z

t

SCH

AC

t

AC

LC

t

A

t

SAC

t

ZDO

t

C

S

D

AR

ZDC

CR

t

CR

t

D

AR

H

t

AR

t

R

SA

t

WL17

Hyper Page Mode (EDO) Late Write and Read-Modify-Write Cycle

Semiconductor Group

18

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

t_RC

t_RAS

t_RP

V

IH

RAS

V

IL

t_CRP

t_RPC

V

IH

CAS

V

IL

t_RAH

t_ASR

V

IH

Address

Row

V

IL

V

OH

I/O

(Outputs)

HI-Z

V

OL

“H” or “L”

WL9

RAS-Only Refresh Cycle

Semiconductor Group

19

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

t_RP

t_RASS

t_RPS

V

IH

RAS

CAS

V

IL

t_RPC

t_CP

t_CRP

t_CHS

t_CSR

V

IH

V

IL

t_WRP

t_WRH

V

IH

WE

OE

V

IL

V

IH

V

IL

t_CDD

V

IH

I/O

(Inputs)

V

IL

ODD

t

t_OEZ

V

OH

I/O

HI-Z

(Outputs)

V

OL

t_OFF

WL13

“H” or “L”

Self Refresh

Semiconductor Group

20

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

t^RC

t_RP

t_RAS

V

IH

RAS

CAS

V

IL

t_RPC

t_CP

t_CSR

t_CRP

t_RPC

t_CHR

V

IH

V

IL

t_WRP

t_WRH

V

IH

WE

OE

V

IL

t_OEZ

V

IH

V

IL

t_CDD

V

IH

I/O

(Inputs)

V

IL

ODD

t

V

OH

I/O

(Outputs)

HI-Z

V

OL

t_OFF

“H” or “L”

WL10

CAS-Before-RAS Refresh Cycle

Semiconductor Group

21

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

t_RC

t_RP

t_RAS

V

IH

RAS

V

IL

t_RSH

t_RCD

t_CRP

t_CHR

V

IH

CAS

V

t_RAD

IL

t_WRP

t_ASC

t_ASR

t_RAH

t_WRH

t_CAH

t_ASR

V

IH

Column

Address

Row

V

IL

t_RRH

t_RCS

V

IH

WE

OE

V

IL

t_AA

t_OEA

V

IH

V

IL

t_DZC

t_DZO

t_CDD

t_ODD

V

IH

I/O

(Inputs)

V

IL

t_CAC

t_OFF

t_CLZ

t_OEZ

t_RAC

V

OH

I/O

(Outputs)

Valid Data Out

HI-Z

V

OL

WL11

“H” or “L”

Hidden Refresh Cycle (Read)

Semiconductor Group

22

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

t_RC

t_RP

t_RAS

V

t_RAS

IH

RAS

V

IL

t_RCD

t_RSH

t_CHR

t_CRP

V

IH

CAS

t_RAD

V

IL

t_RAH

t_ASR

t_ASC

t_CAH

t_ASR

V

IH

Address

Row

Column

Row

V

IL

t_WCS

t_WRPt_WRH

t_WCH

t_WP

V

IH

WE

V

IL

t_DS

t_DH

V

IH

I/O

(Input)

Valid Data

V

IL

V

OH

I/O

(Output)

HI-Z

V

OL

“H” or “L”

WL12

Hidden Refresh Cycle (Early Write)

Semiconductor Group

23

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

t

RP

t_RAS

Read Cycle:

RAS

V

IH

IL

V

t_RSH

t_CAS

t_CP

t_CHR

t_CSR

CAS

V

IH

V

t_RAL

IL

t_ASR

t_ASCt_CAH

Column

t_AA

V

IH

IL

Address

WE

Row

V

t_WRP

t_RRH

t_RCH

V

IH

IL

t_CAC

V

t_WRH

t_OEA

t_RCS

V

IH

IL

OE

V

t_CDD

t_DZC

V

t_ODD

I/O

IH

IL

(Inputs)

V

t_DZO

t_OFF

t_CLZ

t_OEZ

Out

V

I/O

(Outputs)

OH

OL

Data

V

t_WCS

t_WRP

t_RWL

t_CWL

t_WCH

Write Cycle:

WE

V

IH

IL

V

t_WRH

V

IH

IL

OE

t_DS

t_DH

I/O

(Inputs)

V

IH

IL

Data In

V

I/O

(Outputs)

V

IH

HI-Z

V

IL

CAS-Before-RAS Refresh Counter Test Cycle

Semiconductor Group

24

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

t_RC

t_RP

t_RAS

t_RP

V

IH

RAS

CAS

V

t_RPC

IL

t_CSR

t_CP

t_CHR

t_CRP

t_RPC

V

IH

V

IL

t_RAH

t_ASR

V

IH

Address

WE

Row

V

IL

t_WTS

t_WTH

V

IH

V

IL

V

IH

OE

V

IL

t_ODD

V

I/O

(Inputs)

IH

HI-Z

V

IL

t_CDD

t_OEZ

V

OH

I/O

(Outputs)

HI-Z

V

OL

t_OFF

“H” or “L”

WL15

Test Mode Entry

Semiconductor Group

25

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

Package Outlines

Plastic Package P-SOJ-26/24-1 (300 mil)

(Small Outline J-leads, SMD)

Semiconductor Group

26


型号：	HYB3116405BTL-60
厂家：	Infineon
描述：	3.3V 4M x 4-Bit EDO-Dynamic RAM 3.3V 4M ×4位EDO- RAM动态
文件：	总26页 (文件大小：286K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYB3116405BTL-60 [INFINEON]

相关型号：

HYB3116405BTL-70

HYB3117400BJ-50

HYB3117400BJ-60

HYB3117400BJ-70

HYB3117400BT-50

HYB3117400BT-60

HYB3117400BT-70

HYB3117400BTL-60

HYB3117405BJ-50

HYB3117405BJ-60

HYB3117405BJ-70

HYB3117405BT-50