HYB314100BJ-50 [INFINEON]
4M x 1-Bit Dynamic RAM Low Power 4M x 1-Bit Dynamic RAM; 4M ×1位动态RAM低功耗4M ×1位动态随机存储器
| 型号： | HYB314100BJ-50 |
| 厂家： | 
Infineon |
| 描述： | 4M x 1-Bit Dynamic RAM Low Power 4M x 1-Bit Dynamic RAM |
| 文件： | 总23页 (文件大小：1155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4M x 1-Bit Dynamic RAM
HYB 314100BJ/BJL -50/-60/-70
Low Power 4M x 1-Bit Dynamic RAM
Advanced Information
• 4 194 304 words by 1-bit organization
• 0 to 70 ˚C operating temperature
• Fast Page Mode Operation
• Performance:
-50
50
13
25
95
35
-60
-70
70
20
35
tRAC
tCAC
tAA
RAS access time
60
15
30
ns
ns
ns
CAS access time
Access time from address
Read/Write cycle time
Fast page mode cycle time
tRC
110 130 ns
40 45 ns
tPC
• Single + 3.3 V (± 0.3 V ) supply with a built-in Vbb generator
• Low power dissipation
max. 252 mW active (-50 version)
max. 216 mW active (-60 version)
max. 198 mW active (-70 version)
• Standby power dissipation:
7.2 mW max. standby (TTL)
3.6 mW max. standby (CMOS)
720 µW max. standby (CMOS) for Low Power Version
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh,
hidden refresh and test mode capability
• All inputs and outputs TTL-compatible
• 1024 refresh cycles / 16 ms
• 1024 refresh cycles / 128 ms Low Power Version
• Plastic Packages: P-SOJ-26/20-5 with 300 mil width
Semiconductor Group
1
4.96
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
The HYB 314100BJ/BJL is the new generation dynamic RAM organized as 4 194 304 words by
1-bit. The HYB 314100BJ/BJL utilizes CMOS silicon gate process as well as advances circuit
techniques to provide wide operation margins, both internally and for the system user. Multiplexed
address inputs permit the HYB 514100BJ/BJL to be packed in a standard plastic P-SOJ-26/20
package. This package size provides high system bit densities and is compatible with commonly
used automatic testing and insertion equipment. System oriented features include single + 3.3 V
(± 0.3 V) power supply, direct interfacing with high performance logic device families.
Ordering Information
Type
Ordering Code
Package
Descriptions
HYB 314100BJ-50
Q67100-Q2035
P-SOJ-26/20-5
3.3 V DRAM
(access time 50 ns)
HYB 314100BJ-60
HYB 314100BJ-70
HYB 314100BJL-50
HYB 314100BJL-60
HYB 314100BJL-70
Q67100-Q2037
Q67100-Q2039
on request
P-SOJ-26/20-5
P-SOJ-26/20-5
P-SOJ-26/20-5
P-SOJ-26/20-5
P-SOJ-26/20-5
3.3 V DRAM
(access time 60 ns)
3.3 V DRAM
(access time 70 ns)
3.3 V Low Power DRAM
(access time 50 ns)
on request
3.3 V Low Power DRAM
(access time 60 ns)
on request
3.3 V Low Power DRAM
(access time 70 ns)
Semiconductor Group
2
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Pin Configuration
(top view)
P-SOJ-26/20-5
Pin Names
A0-A10
RAS
CAS
WE
Address Input
Row Address Strobe
Column Address Strobe
Read/Write Input
Data In
DI
DO
Data Out
VCC
Power Supply (+ 3.3 V)
Ground (0 V)
VSS
N.C.
No Connection
Semiconductor Group
3
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Block Diagram
Semiconductor Group
4
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Absolute Maximum Ratings
Operating temperature range ............................................................................................0 to 70 ˚C
Storage temperature range......................................................................................– 55 to + 150 ˚C
Input/output voltage ........................................................................... – 1 to + min (VCC + 0.5, 4.6) V
Power Supply voltage.................................................................................................. – 1 to + 4.6 V
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V , tT = 5 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
1)
1)
1)
1)
Input high voltage
VIH
2.0
– 1.0
2.4
–
VCC + 0.5 V
Input low voltage
VIL
0.8
–
V
TTL Output high voltage (IOUT = – 2 mA)
TTL Output low voltage (IOUT = 2 mA)
CMOS Output high voltage (IOUT = – 100 µA)
CMOS Output low voltage (IOUT = 100 µA)
VOH
VOL
VOH
VOL
II(L)
V
0.4
V
VCC – 0.2 –
V
–
0.2
V
1)
Input leakage current, any input
– 10
10
µA
(0 V < Vin < VCC + 0.3 V, all other input = 0 V)
1)
Output leakage current
(DO is disabled, 0 V < VOUT < VCC)
IO(L)
ICC1
– 10
10
µA
2) 3)4)
Average VCC supply current
-50 version
mA
_
–
–
70
60
55
-60 version
-70 version
Standby VCC supply current
(RAS = CAS = WE = VIH)
ICC2
ICC3
–
2
mA
mA
–
2)4)
Average VCC supply current during RAS-only
refresh cycles
-50 version
-60 version
-70 version
_
–
–
70
60
55
2) 3)4)
Average VCC supply current during fast page
ICC4
ICC5
5
mA
mode operation
-50 version
-60 version
-70 version
–
–
50
45
40
1)
Standby VCC supply current
(RAS = CAS = WE = VCC – 0.2 V)
–
1
200
mA
µA
L-version
Semiconductor Group
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
DC Characteristics (cont’d)
TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V , tT = 5 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
2)4)
Average VCC supply current during
CAS before RAS refresh mode
-50 version
ICC6
mA
–
–
–
70
60
55
-60 version
-70 version
For Low Power Version only:
ICC7
–
250
µA
–
Battery backup current (average power supply
current in battery backup mode):
(CAS = CAS before RAS cycling or 0.2 V,
WE = VCC – 0.2 V or 0.2 V,
A0 to A10 = VCC – 0.2 V or 0.2 V;
DI = VCC – 0.2 V or 0.2 V or open,
t
RC = 125 µs, tRAS = tRAS min = 1 µs)
Capacitance
TA = 0 to 70 ˚C; VCC = 3.3 V ± 0.3 V; f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A10, DI)
Input capacitance (RAS, CAS, WE)
Output capacitance (DO)
CI1
CI2
CIO
–
–
–
5
7
7
pF
pF
pF
Semiconductor Group
6
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
5)6)
AC Characteristics
TA = 0 to 70 ˚C, VCC = 3.3 V ± 0.3 V, tT = 5 ns
Parameter
Symbol
Limit Values
-60
Unit
Note
-50
-70
min. max. min. max. min. max.
Common Parameters
Random read or write cycle time tRC
95
35
50
13
0
–
110
40
60
15
0
–
130
50
70
20
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RAS precharge time
RAS pulse width
tRP
–
–
–
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
10k
10k
–
10k
10k
–
10k
10k
–
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
8
–
10
0
–
10
0
–
0
–
–
–
10
18
13
–
15
20
15
–
15
20
15
–
37
25
45
30
50
35
RAS to column address delay
time
RAS hold time
tRSH
tCSH
tCRP
tT
13
50
5
15
60
5
–
20
70
5
–
ns
ns
ns
ns
ms
CAS hold time
–
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
–
–
–
3
50
16
128
3
50
16
128
3
50
16
7
tREF
tREF
–
–
–
Refresh period for L-version
–
–
–
128 ms
Read Cycle
Access time from RAS
Access time from CAS
tRAC
tCAC
tAA
–
–
–
50
13
25
–
–
–
60
15
30
–
–
–
70
20
35
ns
ns
ns
8, 9
8, 9
8,10
Access time from column
address
Column addr. to RAS lead time tRAL
25
0
–
–
–
–
30
0
–
–
–
–
35
0
–
–
–
–
ns
ns
ns
ns
Read command setup time
Read command hold time
tRCS
tRCH
tRRH
0
0
0
11
11
Read command hold time
referenced to RAS
0
0
0
CAS to output in low-Z
tCLZ
0
–
0
–
0
–
ns
8
Semiconductor Group
7
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
5)6)
AC Characteristics (cont’d)
TA = 0 to 70 ˚C, VCC = 3.3 V ± 0.3 V, tT = 5 ns
Parameter
Symbol
Limit Values
-60
Unit
Note
-50
-70
min. max. min. max. min. max.
Output buffer turn-off delay
tOFF
0
13
0
15
0
20
ns
12
Write Cycle
Write command hold time
Write command pulse width
Write command setup time
tWCH
tWP
8
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
8
tWCS
0
13
Write command to RAS lead time tRWL
Write command to CAS lead time tCWL
13
13
0
15
15
0
20
20
0
Data setup time
Data hold time
tDS
tDH
14
14
10
10
15
Read-Modify-Write Cycle
Read-write cycle time
RAS to WE delay time
CAS to WE delay time
tRWC
tRWD
tCWD
tAWD
115
50
–
–
–
–
130
60
–
–
–
–
155
70
–
–
–
–
ns
ns
ns
ns
13
13
13
13
15
20
Column address to WE delay
time
25
30
35
Fast Page Mode Cycle
Fast page mode cycle time
CAS precharge time
tPC
35
10
–
–
40
10
–
–
45
10
–
–
ns
ns
ns
tCP
–
–
–
Access time from CAS
precharge
tCPA
30
35
40
7
RAS pulse width
tRAS
50
30
200 k 60
35
200 k 70
40
200 k ns
– ns
CAS precharge to RAS Delay
tRHCP
–
–
Semiconductor Group
8
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
5)6)
AC Characteristics (cont’d)
TA = 0 to 70 ˚C, VCC = 3.3 V ± 0.3 V, tT = 5 ns
Parameter
Symbol
Limit Values
-60
Unit
Note
-50
-70
min. max. min. max. min. max.
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle tPRWC
time
55
–
–
60
35
–
–
70
40
–
–
ns
ns
CAS precharge to WE
tCPWD
30
CAS-before-RAS refresh cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
tWRH
10
10
5
–
–
–
–
–
10
10
5
–
–
–
–
–
10
10
5
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
RAS to CAS precharge time
Write to RAS precharge time
10
10
10
10
10
10
Write hold time referenced to
RAS
CAS-before-RAS counter test
cycle
CAS precharge time
tCPT
35
–
40
–
40
–
ns
Test Mode
Write command setup time
Write command hold time
tWTS
tWTH
10
10
–
–
10
10
–
–
10
10
–
–
ns
ns
Semiconductor Group
9
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during
a fast page mode cycle (tPC).
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at VOL = 0.8 and VOH = 2.0 V.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point
only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC
.
10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA.
11)Either tRCH or tRRH must be satisfied for a read cycle.
12)tOFF (max.) defines the time at which the outputs achieve the open-circuit condition and are not referenced to
output voltage levels.
13)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the data out pin will remain
open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and
t
CPWD > tCPWD (min.), the cycle is a read-write cycle and DO will contain data read from the selected cells. If neither
of the above sets of conditions is satisfied, the condition of the DO pin (at access time) is indeterminate.
14)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
Semiconductor Group
10
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Read Cycle
Semiconductor Group
11
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Write Cycle (Early Write)
Semiconductor Group
12
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
13
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
14
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Fast Page Mode Read Cycle
Semiconductor Group
15
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Fast Page Mode Early Write Cycle
Semiconductor Group
16
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
RAS-Only Refresh Cycle
Semiconductor Group
17
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
CAS-Before-RAS Refresh Cycle
Semiconductor Group
18
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Hidden Refresh Cycle (Read)
Semiconductor Group
19
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Hidden Refresh Cycle (Early Write)
Semiconductor Group
20
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
21
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Test Mode Entry
Test Mode
The HYB314100BJ/BJL is organized 4 194 304 words by 1- bit but can internally be configured as
524 288 words by 8-bits. A WE, CAS-before-RAS cycle puts the device into Test Mode.
In Test Mode, data is written into 8 sectors in parallel and retrieved the same way. If, upon reading,
all bits are equal, the data output pin indicates a “1”. If any of the bits differ, the data output pin
indicates a “0”. In Test Mode the 4M DRAM can be tested as if it were a 512K DRAM. Test Mode
is exited by any refresh operation which is not a WE, CAS- before-RAS cycle. Addresses A10R,
A10C and A0C do not care during Test Mode.
Semiconductor Group
22
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Package Outlines
Plastic Package P-SOJ-26/20-5
(Plastic Small Outline J-leaded Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Dimensions in mm
Semiconductor Group
23
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