HYB314175BJ-50_技术文档

3.3V 256 K x 16-Bit EDO-DRAM

HYB 314175BJ-50/-55/-60

HYB 314175BJL-50/-55/-60

3.3V 256 K x 16-Bit EDO-DRAM

(Low power version with Self Refresh)

Preliminary Information

• 262 144 words by 16-bit organization

• 0 to 70 °C operating temperature

• Fast access and cycle time

• Low Power dissipation

max. 450 mW active (-50 version)

max. 432 mW active (-55 version)

max. 378 mW active (-60 version)

• Standby power dissipation

7.2 mW standby (TTL)

• RAS access time:

50 ns (-50 version)

55 ns (-55 version)

60 ns (-60 version)

3.6 mW max. standby (CMOS)

0.72 mW max. standby (CMOS) for

Low Power Version

• CAS access time:

13ns (-50 & -55 version)

15 ns (-60 version)

• Output unlatched at cycle end allows two-

dimensional chip selection

• Read, write, read-modify write, CAS-

before-RAS refresh, RAS-only refresh,

hidden-refresh and hyper page (EDO)

mode capability

• Cycle time:

89 ns (-50 version)

94 ns (-55 version)

104 ns (-60 version)

• Hype page mode (EDO) cycle time

20 ns (-50 & -55 version)

25 ns (-60 version)

• 2 CAS / 1 WE control

• Self Refresh (L-Version)

• All inputs and outputs TTL-compatible

• 512 refresh cycles / 16 ms

• 512 refresh cycles / 128 ms

Low Power Version only

• High data rate

50 MHz (-50 & -55 version)

40 MHz (-60 version)

• Plastic Packages:

• Single + 3.3 V (±0.3 V) supply with a built-

P-SOJ-40-1 400mil width

in VBB generator

The HYB 314175BJ/BJL is the new generation dynamic RAM organized as 262 144 words by

16-bit. The HYB 314175BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit

techniques to provide wide operation margins, both internally and for the system user. Multiplexed

address inputs permit the HYB 314175BJ/BJL to be packed in a standard plastic 400mil wide

P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with

commonly used automatic testing and insertion equipment. System oriented features include Self

Refresh (L-Version), single + 3.3 V (± 0.3 V) power supply, direct interfacing with high performance

logic device families.

Semiconductor Group

1

7.96

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Ordering Information

Type

Ordering Code

Q67100 - Q2148

on request

Package

Description

HYB 314175BJ-50

HYB 314175BJ-55

HYB 314175BJ-60

HYB 314175BJL-50

HYB 314175BJL-55

HYB 314175BJL-60

P-SOJ-40-1

3.3 V 50 ns 256 Kx16 EDO-DRAM

3.3 V 55 ns 256 Kx16 EDO-DRAM

3.3 V 60 ns 256 Kx16 EDO-DRAM

3.3 V 50 ns 256 Kx16 EDO- DRAM

3.3 V 55 ns 256 Kx16 EDO- DRAM

3.3 V 60 ns 256 Kx16 EDO-DRAM

Q67100 - Q2149

on request

Truth Table

RAS

LCAS UCAS WE

OE

I/O1-I/O8

I/O9-I/O16

Operation

H

L

H

L

H

L

H

High-Z

Standby

L

H

L

High-Z

Dout

High-Z

Dout

Refresh

Lower byte read

Upper byte read

Word read

H

L

High-Z

Dout

L

Dout

L

H

L

H

Din

Don't care

Din

Lower byte write

Upper byte write

Word write

H

L

Don't care

Din

L

Din

L

H

High-Z

Pin Names

A0-A8

RAS

Address Inputs

Row Address Strobe

Column Address Strobe

Read/Write Input

Output Enable

UCAS, LCAS

WE

OE

I/O1 – I/O16

V_CC

Data Input/Output

Power Supply (+ 3.3 V)

Ground (0 V)

V_SS

N.C.

No Connection

Semiconductor Group

2

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Pin Configuration

(top view)

P-SOJ-40-1

Semiconductor Group

3

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Block Diagram

Semiconductor Group

4

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Absolute Maximum Ratings

Operating temperature range ........................................................................................ 0 to + 70 °C

Storage temperature range..................................................................................... – 55 to + 150 °C

Input/output voltage ..................................................................................... – 1 to (V_CC+ 0.5, 4.6) V

Power supply voltage................................................................................................... – 1 to + 4.6 V

Data out current (short circuit) ................................................................................................ 50 mA

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

DC Characteristics

T_A= 0 to 70 °C; V_SS= 0 V; V_CC= 3.3 V ± 0.3 V, t_T= 2 ns

Parameter

Symbol

Limit Values

min. max.

Unit Notes

1

Input high voltage

V_IH

V_IL

2.4

– 1.0

2.4

–

V

_CC+ 0.5

V

1

Input low voltage

0.8

–

V

1

LVTTL Output high voltage (I_OUT= – 2.0 mA)

LVTTL Output low voltage (I_OUT= 2 mA)

V_OH

V_OL

V

1

0.4

–

V

1

LVCMOS Output high voltage (I_OUT= – 100 µA) V_OH

2.4

–

V

1

LVCMOS Output low voltage (I_OUT= 100 µA)

V_OL

I_I(L)

0.4

10

V

1

Input leakage current, any input

– 10

µA

(0 V < V_IN< 7 V, all other inputs = 0 V)

1

Output leakage current

(DO is disabled, 0 V < V_OUT< V_CC)

I_O(L)

I_CC1

– 10

–

10

µA

Average V_CCsupply current:

2, 3, 4

mA

-50 version

-55 version

-60 version

125

120

105

Standby V_CCsupply current

(RAS = LCAS = UCAS = WE = V_IH)

I_CC2

I_CC3

–

2

mA

–

Average V_CCsupply current during

RAS-only refresh cycles:

2, 4

-50 version

-55 version

-60 version

125

120

105

Semiconductor Group

5

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

DC Characteristics (cont’d)

Parameter

Symbol

Limit Values

Unit Test

Condition

min.

max.

2, 3, 4

Average V_CCsupply current during

–

hyper page mode (EDO) operation:

I_CC4

-50 version

-55 version

-60 version

115

100

mA

1

Standby V_CCsupply current

I_CC5

–

1

(RAS = LCAS = UCAS = WE = V_CC– 0.2 V)

2, 4

Average V_CCsupply current during

CAS-before-RAS refresh mode:

-50 version

I_CC6

125

120

105

mA

-55 version

-60 version

Standby V_CCcurrent (L-version)

(RAS = LCAS = UCAS = WE = V_CC– 0.2 V)

I_CC5

I_CCS

–

200

250

µA

Self Refresh Current (L-version)

(RAS, LCAS, UCAS = 0.2V

A0 – A8 = V_CC– 0.2 V or 0.2 V)

Capacitance

T_A= 0 to 70 °C; V_CC= 3.3 V ± 0.3 V, f = 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A8)

C_I1

–

5

7

pF

Input capacitance (RAS, UCAS, LCAS, WE, OE) C_I2

Output capacitance (l/O1 to l/O16)

C_IO

Semiconductor Group

6

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

AC Characteristics ^{5) 6)}

T_A= 0 to 70 °C; V_SS= 0 V; V_CC= 3.3 V ± 0.3 V, t_T= 2 ns

Parameter

Symbol

Limit Values

-55

Unit Note

-50

-60

min max min max min max

Common Parameters

Random read or write cycle time

RAS precharge time

t_RC

89

35

50

8

–

94

35

–

104 –

40

ns

t_RP

–

RAS pulse width

t_RAS

t_CAS

t_ASR

t_RAH

t_ASC

t_CAH

t_RCD

10k 55

10k 60

10k 10

10k ns

CAS pulse width

10k

–

8

Row address setup time

Row address hold time

Column address setup time

Column address hold time

RAS to CAS delaytime

0

–

0

–

ns

ms

8

–

8

–

10

0

–

0

–

0

–

8

–

8

–

10

14

12

15

50

5

–

12

10

13

40

5

37

25

–

12

10

13

45

5

43

30

–

45

30

–

RAS to column address delay time t_RAD

RAS hold time

t_RSH

t_CSH

t_CRP

t_T

CAS hold time

–

CAS to RAS precharge time

Transition time(rise and fall)

Refresh period

–

7

1

50

16

1

50

16

1

50

16

t_REF

–

Refresh period (L-version)

–

128 –

128 ms

Read Cycle

8, 9

8,10

Access time from RAS

Access time from CAS

Access time from column address

OE access time

t_RAC

t_CAC

t_AA

–

50

13

25

13

–

55

13

25

13

–

60

15

30

15

–

ns

–

t_OEA

–

Column address to RAS lead time t_RAL

25

0

25

0

30

0

Read command setup time

Read command hold time

t_RCS

t_RCH

t_RRH

–

11

0

–

0

–

0

–

Read command hold time ref. to

RAS

0

–

0

–

0

–

8

CAS to output inlow-Z

t_CLZ

0

7

–

0

–

0

–

ns

Semiconductor Group

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Parameter

Symbol

Limit Values

-55

Unit Note

-50

-60

min max min max min max

12

ns

Output buffer turn-off delay from

CAS

t_OFF

0

13

0

13

0

15

12

ns

Output buffer turn-off delay from OE t_OEZ

0

13

–

0

13

–

0

15

–

13

ns

Data to OE low delay

CAS high to data delay

OE high to data delay

t_DZO

t_CDD

t_ODD

0

14

ns

10

–

10

–

13

–

14

ns

–

Write Cycle

Write command hold time

Write command pulse width

Write command setup time

Write command to RAS lead time

Write command to CAS lead time

Data setup time

t_WCH

t_WP

8

–

8

–

10

0

–

ns

8

15

ns

t_WCS

t_RWL

t_CWL

t_DS

0

13

0

13

0

15

0

ns

16

ns

16

ns

Data hold time

t_DH

8

10

0

13

ns

Data to CAS low delay

t_DZC

0

Read-modify-Write Cycle

Read-write cycle time

RAS to WE delay time

CAS to WE delay time

t_RWC

t_RWD

t_CWD

118 –

122 –

138 –

ns

15

ns

64

27

39

10

–

69

27

39

10

–

77

32

47

13

–

15

ns

15

ns

Column address to WE delay time t_AWD

OE command hold time

t_OEH

ns

Hyper Page Mode (EDO) Cycle

Hyper page mode cycle time

CAS precharge time

t_HPC

t_CP

20

8

–

20

8

–

25

10

–

ns

–

7

Access time from CAS precharge

Output data hold time

t_CPA

t_COH

t_RAS

–

27

–

27

–

32

–

ns

5

ns

200k

RAS pulse width in hyper page

mode

50

55

60

RAS hold time from CAS precharge t_RHCP

27

8

–

27

–

32

–

ns

Semiconductor Group

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Parameter

Symbol

Limit Values

-55

Unit Note

-50

-60

min max min max min max

Hyper Page Mode (EDO) Read-Modify-Write Cycle

Hyper page mode read/write cycle t_PRWC

time

58

–

58

41

–

68

49

–

ns

CAS precharge to WE delay time

t_CPWD

41

CAS before RAS Refresh Cycle

CAS setup time

t_CSR

t_CHR

t_RPC

t_WRP

t_WRH

5

–

5

–

5

–

ns

CAS hold time

10

5

10

5

10

5

RAS to CAS precharge time

Write to RAS precharge time

Write to RAS hold time

10

CAS-before-RAS Counter Test Cycle

CAS precharge time

t_CPT

35

–

35

–

40

–

ns

Self Refresh Cycle (L-Version only)

RAS pulse width

t_RASS

t_RPS

t_CHS

100 –

95

– 50 –

100 –

110 –

– 50 –

100 –

110 –

– 50 –

µs

ns

RAS precharge time

CAS hold time

–

Semiconductor Group

9

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Notes:

1) All voltages are referenced to V_SS.

2) I_CC1, I_CC3, I_CC4and I_CC6depend on cycle rate.

3) I_CC1and I_CC4depend on output loading. Specified values are obtained with the output open.

4) Address can be changed once or less while RAS = V_il. In case of I_CC4it can be changed once or less during

a hyper page mode (EDO) cycle

5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has

to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,

a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.

6) AC measurements assume t_T= 2 ns.

7) V_IH

and V_{IL (max.)}are reference levels for measuring timing of input signals. Transition times are also

(min.)

measured between V_IHand V_IL.

8) Measured with the specified current load and 100 pF at V_ol= 0.8 V and V_oh= 2.0 V. Access time is determined

by the latter of t_RAC, t_CAC, t_AA, t_CPA, t_OEA. t_CACis measured from tristate.

9) Operation within the t_{RCD (max.)}limit ensures that t_{RAC (max.)}can be met. t_{RCD (max.)}is specified as a reference point

only. If t_RCDis greater than the specified t_{RCD (max.)}limit, then access time is controlled by t_CAC

.

10) Operation within the t_{RAD (max.}limit ensures that t_{RAC (max.)}can be met. t_{RAD (max.)}is specified as a reference point

)

only. If t_RADis greater than the specified t_{RAD (max.)}limit, then access time is controlled by t_AA.

11) Either t_RCHor t_RRHmust be satisfied for a read cycle.

12) t_{OFF (max.)}, t_{OEZ (max.)}define the time at which the output achieves the open-circuit conditions and are not

referenced to output voltage levels. t_OFFis referenced from the rising edge of RAS or CAS, whichever occurs

last.

13) Either t_DZCor t_DZOmust be satisfied.

14) Either t_CDDor t_ODDmust be satisfied.

15) t_WCS, t_RWD, t_CWDand t_AWDare not restrictive operating parameters. They are included in the data sheet as

electrical characteristics only. If t_WCS> t_{WCS (min.)}, the cycle is an early write cycle and data out pin will remain

open-circuit (high impedance) through the entire cycle; if t_RWD> t_{RWD (min.)}, t_CWD> t_{CWD (min.)}and t_AWD> t_{AWD (min.)}

,

the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above

sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.

16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge

in read-write cycles.

Semiconductor Group

10

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Read Cycle

Semiconductor Group

11

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Write Cycle (Early Write)

Semiconductor Group

12

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Write Cycle (OE Controlled Write)

Semiconductor Group

13

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Read-Write (Read-Modify-Write) Cycle

Semiconductor Group

14

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Hyper Page Mode (EDO) Read Cycle

Semiconductor Group

15

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Hyper Page Mode (EDO) Early Write Cycle

Semiconductor Group

16

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Hyper Page Mode (EDO) Late Write and Read-Modify-Write Cycles

Semiconductor Group

17

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

RAS-Only Refresh Cycle

Semiconductor Group

18

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

CAS-Before-RAS Refresh Cycle

Semiconductor Group

19

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

CAS before RAS Self Refresh Cycle (L-version only)

Semiconductor Group

20

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Hidden Refresh Cycle (Read)

Semiconductor Group

21

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Hidden Refresh Cycle (Early Write)

Semiconductor Group

22

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

CAS/-Before-RAS Refresh Counter Test Cycle

Semiconductor Group

23

HYB 314175BJ/BJL-50/-55/-60

3.3V 256K x 16 EDO-DRAM

Package Outline

Plastic Package, P-SOJ- 40-1 (SMD)

(Plastic Small Outline J-leaded Package)

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

SMD = Surface Mounted Device

Dimensions in mm

Semiconductor Group

24


型号：	HYB314175BJ-50
厂家：	Infineon
描述：	3.3V 256 K x 16-Bit EDO-DRAM 3.3V 256 K x 16-Bit EDO-DRAM Low power version with Self Refresh 3.3V 256的K× 16位EDO -DRAM 3.3V 256的K× 16位EDO -DRAM的低功率版与自刷新内存集成电路光电二极管动态存储器
文件：	总24页 (文件大小：1309K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYB314175BJ-50 [INFINEON]

相关型号：

HYB314175BJ-50-

HYB314175BJ-55

HYB314175BJ-60

HYB314175BJL-50

HYB314175BJL-55

HYB314175BJL-60

HYB314265BJ-45

HYB314265BJ-50

HYB314265BJL-45

HYB314265BJL-50

HYB314400BJ-50

HYB314400BJ-50-