HYB3164405BT-40 [INFINEON]
16M x 4-Bit Dynamic RAM; 16M ×4位动态RAM
| 型号： | HYB3164405BT-40 |
| 厂家： | 
Infineon |
| 描述： | 16M x 4-Bit Dynamic RAM |
| 文件： | 总29页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16M x 4-Bit Dynamic RAM
HYB 3164405BJ/BT(L) -40/-50/-60
HYB 3165405BJ/BT(L) -40/-50/-60
(4k & 8k Refresh, EDO-version)
Preliminary Information
• 16 777 216 words by 4-bit organization
• 0 to 70 °C operating temperature
• Hyper Page Mode - EDO - operation
• Performance:
-40
40
10
20
69
16
-50
50
13
25
84
20
-60
60
t
t
t
t
t
RAS access time
ns
ns
ns
ns
ns
RAC
CAC
AA
CAS access time
15
Access time from address
Read/write cycle time
30
104
25
RC
Hyper page mode (EDO)
cycle time
HPC
• Single + 3.3 V (± 0.3V) power supply
• Low power dissipation:
max. 306 active mW ( HYB 3164405BJ/BT(L)-40)
max. 252 active mW ( HYB 3164405BJ/BT(L)-50)
max. 216 active mW ( HYB 3164405BJ/BT(L)-60)
max. 486 active mW ( HYB 3165405BJ/BT(L)-40)
max. 396 active mW ( HYB 3165405BJ/BT(L)-50)
max. 324 active mW ( HYB 3165405BJ/BT(L)-60)
7.2 mW standby (LVTTL)
3.6 mW standby (LVMOS)
720 µA standby for L-version
• Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh
• Self refresh (L-version only)
• 8192 refresh cycles/128 ms, 13 R/ 11C addresses (HYB 3164405BJ/BT)
4096 refresh cycles / 64 ms, 12 R/ 12C addresses (HYB 3165405BJ/BT)
• 128 msec refresh period for L-versions
• Plastic Package:
P-SOJ-32-1
P-TSOPII-32-1
400 mil HYB 3164(5)400BJ
400 mil HYB 3164(5)400BT(L)
Semiconductor Group
1
12.97
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
This HYB3164(5)405B is a 64 MBit dynamic RAM organized 16 777 216 by 4 bits. The device is
fabricated in SIEMENS’most advanced 0,25 µm-CMOS silicon gate process technology. The circuit
and process design allow this device to achieve high performance and low power dissipation. The
HYB3164(5)405B operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL
or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)400B to be packaged in a
400mil wide SOJ-32 or TSOP-32 plastic package. These packages provide high system bit
densities and are compatible with commonly used automatic testing and insertion equipment.The
HYB3164(5)405BTL parts have a very low power „sleep mode“supported by Self Refresh.
Ordering Information
Type
Ordering
Code
Package
Descriptions
8k-refresh versions:
HYB 3164405BJ-40
HYB 3164405BJ-50
HYB 3164405BJ-60
HYB 3164405BT-40
HYB 3164405BT-50
HYB 3164405BT-60
HYB 3164405BTL-50
HYB 3164405BTL-60
4k-refresh versions:
HYB 3165405BJ-40
HYB 3165405BJ-50
HYB 3165405BJ-60
HYB 3165405BT-40
HYB 3165405BT-50
HYB 3165405BT-60
HYB 3165405BTL-50
HYB 3165405BTL-60
P-SOJ-32-1
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
P-SOJ-32-1
P-SOJ-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-SOJ-32-1
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
P-SOJ-32-1
P-SOJ-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
Semiconductor Group
2
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
P-SOJ-32-1 (400 mil)
P-TSOPII-32-1 (400 mil)
O
VSS
I/O4
I/O3
N.C.
N.C.
N.C.
CAS
OE
VCC
I/O1
32
31
30
29
28
27
1
2
3
4
I/O2
N.C.
N.C.
N.C.
5
6
N.C.
WE
26
7
25
24
23
22
21
20
19
18
17
8
RAS
A12 / N.C. *
A11
9
.
10
11
12
13
14
15
A0
A1
A10
A9
A2
A8
A3
A4
A7
A6
A5
VCC
16
VSS
* Pin 24 is A12 for HYB 3164405BJ/BT(L) and N.C. for HYB 3165405BJ/BT(L)
Pin Configuration
Pin Names
A0-A12
A0-A11
RAS
Address Inputs for 8k-refresh version HYB 3164405BJ/BT(L)
Address Inputs for 4k-refresh version HYB 3165405BJ/BT(L)
Row Address Strobe
OE
Output Enable
I/O1-I/O4
CAS
Data Input/Output
Column Address Strobe
Read/Write Input
WE
Vcc
Power Supply ( + 3.3V)
Ground
Vss
Semiconductor Group
3
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
TRUTH TABLE
FUNCTION
RAS
CAS
WE
OE
ROW
ADDR ADDR
COL
I/O1-
I/O4
Standby
H
H - X
L
X
H
X
L
X
X
High Impedance
Data Out
Read
L
ROW
ROW
ROW
ROW
ROW
n/a
COL
COL
COL
Early-Write
L
L
L
X
Data In
Delayed-Write
L
L
H - L
H - L
H
H
Data In
Read-Modify-Write
Hyper Page Mode Read 1st Cycle
2nd Cycle
L
L
L
L - H
L
COL Data Out, Data In
H - L
H - L
H - L
H - L
H - L
H - L
H
COL
COL
COL
COL
Data Out
Data Out
Data In
L
H
L
Hyper Page Mode Write 1st Cycle
2nd Cycle
L
L
X
ROW
n/a
L
L
X
Data In
Hyper Page Mode RMW 1st Cycle
2st Cycle
L
H - L
H - L
X
L - H
L - H
X
ROW
n/a
COL Data Out, Data In
COL Data Out, Data In
L
RAS only refresh
CAS-before-RAS refresh
Test Mode Entry
L
ROW
X
n/a
n/a
High Impedance
High Impedance
High Impedance
Data Out
H - L
H - L
L-H-L
L-H-L
H - L
L
H
X
L
L
X
X
n/a
Hidden Refresh
READ
L
H
L
ROW
ROW
X
COL
COL
X
WRITE
L
L
X
Data In
Self Refresh
L
H
X
High Impedance
(L-version only)
Semiconductor Group
4
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
I/O4
I/O1 I/O2
WE
&
.
CAS
Data in
Buffer
Data out
Buffer
OE
No. 2 Clock
Generator
4
4
Column
Address
Buffer(12)
12
Column
Decoder
12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Refresh
4
Sense Amplifier
I/O Gating
Controller
Refresh
Counter (12)
4096
x4
12
A10
A11
Row
Address
Buffers(12)
Row
Decoder
Memory Array
12
12
4096
4096 x 4096 x 4
No. 1 Clock
Generator
RAS
Block Diagram for HYB 3164405BJ/BT(L)
Semiconductor Group
5
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
I/O4
I/O1 I/O2
WE
&
.
CAS
Data in
Buffer
Data out
Buffer
OE
No. 2 Clock
Generator
4
4
Column
Address
Buffer(11)
11
Column
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Decoder
Refresh
4
Sense Amplifier
I/O Gating
Controller
Refresh
Counter (13)
2048
x4
13
A10
A11
A12
Row
Address
Buffers(13)
Row
Decoder
Memory Array
13
13
8192
8192 x 2048 x 4
No. 1 Clock
Generator
RAS
Block Diagram for HYB 3165405BJ/BT(L)
Semiconductor Group
6
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
Absolute Maximum Ratings
Operating temperature range.............................................................................................. 0 to 70 °C
Storage temperature range......................................................................................... – 55 to 150 °C
Input/output voltage.................................................................................. -0.5 to min (Vcc+0.5,4.6) V
Power supply voltage.................................................................................................... -0.5V to 4.6 V
Power dissipation............................................................................................................... .....0.62 W
Data out current (short circuit)................................................................................................ ..50 mA
Note
Stresses above those listed under „Absolute Maximum Ratings“may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
Unit Note
min.
max.
Vcc+0.3
0.8
Input high voltage
Input low voltage
VIH
VIL
2.0
– 0.3
2.4
V
V
V
1)
1)
Output high voltage (LVTTL)
VOH
–
Output „H“level voltage (Iout = -2mA)
Output low voltage (LVTTL)
Output „L“level voltage (Iout = +2mA)
VOL
VOH
VOL
II(L)
–
Vcc-0.2
-
0.4
-
V
V
Output high voltage (LVCMOS)
Output „H“level voltage (Iout = -100uA)
Ouput low voltage (LVCMOS)
Output „L“level voltage (Iout = +100uA)
0.2
2
V
Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
– 2
µA
µA
Output leakage current
IO(L)
– 2
2
(DO is disabled, 0 V < Vout < Vcc )
Semiconductor Group
7
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
DC-Characteristics (contd’ )
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter
Symbol refresh version Unit Note
4k row 8k row
Operating Current
-40 ns version
ICC1
135
110
90
85
70
60
mA 2) 3) 4)
mA
mA
-50 ns version
-
-60 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
Standby Current (RAS=CAS= Vih)
RASOnlyRefreshCurrent:
ICC2
ICC3
2
2
mA
–
-
- 40 ns version
-50 ns version
-60 ns version
135
110
90
85
70
60
mA 2) 4)
mA
mA
(RAS cycling: CAS = VIH: tRC = tRC min.)
Hyper Page Mode (EDO) Current:
ICC4
-40 ns version
-50 ns version
-60 ns version
100
65
45
100
65
45
mA 2) 3) 4)
mA
(RAS = VIL, CAS, address cycling: tHPC=tHPC min.)
Standby Current (RAS=CAS= Vcc-0.2V)
ICC5
ICC5
1
1
mA
–
–
200
200
µA
Standby Current (L-Version)
(RAS=CAS= Vcc-0.2V)
CAS Before RAS Refresh Current
- 40 ns version
ICC6
135
110
90
85
70
60
mA 2) 4)
mA
-50 ns version
-60 ns version
(RAS, CAS cycling: tRC = tRC min.)
Self Refresh Current (L-version only)
ICC7
400
400
µA
(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
Capacitance
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A11,A12)
Input capacitance (RAS, CAS, WE, OE)
I/O capacitance (I/O1-I/O4)
CI1
CI2
CIO
–
–
–
5
7
7
pF
pF
pF
Semiconductor Group
8
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
5)6)
AC64-2E
AC Characteristics
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
- 50 - 60
-
40
min. max. min. max. min. max.
Common Parameters
Random read or write cycle time
RAS pulse width
tRC
69
40
6
–
84
50
8
–
104
60
10
40
10
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100k
100k
100k
100k
100k
100k
tRAS
tCAS
tRP
CAS pulse width
RAS precharge time
25
6
–
–
30
8
–
–
–
–
CAS precharge time
tCP
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tT
0
–
0
–
–
5
–
7
–
10
0
–
0
–
0
–
–
5
–
7
–
10
14
12
10
48
5
–
9
30
20
–
11
9
37
25
45
30
–
7
6
8
CAS hold time
32
5
–
40
5
–
CAS to RAS precharge time
Transition time (rise and fall)
–
–
–
1
50
128
64
128
1
50
1
50
ns
7
Refresh period for 8k-refresh-version tREF
Refresh period for 4k-refresh version tREF
–
–
128
64
–
128 ms
64 ms
128 ms
–
–
–
Refresh period for L-versions
tREF
–
–
128
–
Read Cycle
Access time from RAS
Access time from CAS
Access time from column address
OE access time
tRAC
tCAC
tAA
–
–
40
10
20
10
–
–
–
50
13
25
13
–
–
–
60
15
30
15
–
ns 8, 9
ns 8, 9
ns 8,10
ns
–
–
–
tOEA
tRAL
tRCS
tRCH
–
–
–
Column address to RAS lead time
Read command setup time
Read command hold time
20
0
25
0
30
0
ns
–
–
–
ns
0
–
0
–
0
–
ns 11
Semiconductor Group
9
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
5)6)
AC64-2E
AC Characteristics (cont’d)
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
- 50 - 60
-
40
min. max. min. max. min. max.
Read command hold time
referenced to RAS
tRRH
0
–
0
–
0
–
ns 11
CAS to output in low-Z
tCLZ
tOFF
0
0
–
10
10
–
0
0
–
13
13
–
0
0
–
15
15
–
ns
8
Output buffer turn-off delay
ns 12
ns 12
ns 13
ns 13
ns 14
ns 14
Output buffer turn-off delay from OE tOEZ
0
0
0
Data to CAS low delay
Data to OE low delay
CAS high to data delay
OE high to data delay
tDZC
tDZO
tCDD
tODD
0
0
0
0
–
0
–
0
–
10
10
–
13
13
–
15
15
–
–
–
–
Write Cycle
Write command hold time
Write command pulse width
Write command setup time
Write command to RAS lead time
Write command to CAS lead time
Data setup time
tWCH
tWP
5
5
0
6
6
0
5
–
–
–
–
–
–
–
7
7
0
8
8
0
7
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
ns
ns
tWCS
tRWL
tCWL
tDS
ns 15
ns
10
10
0
ns
ns 16
ns 16
Data hold time
tDH
10
Read-modify-Write Cycle
Read-write cycle time
tRWC
tRWD
tCWD
tAWD
tOEH
89
52
22
32
5
–
–
–
–
–
109
65
28
40
7
–
–
–
–
–
133
77
–
–
–
–
–
ns
RAS to WE delay time
ns 15
ns 15
ns 15
ns
CAS to WE delay time
32
Column address to WE delay time
OE command hold time
47
10
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time tHPC
16
–
–
22
–
20
–
–
27
–
24
–
–
32
–
ns
Access time from CAS precharge
Output data hold time
tCPA
tCOH
ns
ns
7
3
5
5
Semiconductor Group
10
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
5)6)
AC64-2E
AC Characteristics (cont’d)
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
- 50 - 60
-
40
min. max. min. max. min. max.
200k
–
200k
–
200k
–
RAS pulse width in hyper page mode tRAS
40
22
5
50
27
5
60
32
5
ns
ns
ns
ns
ns
ns
CAS precharge to RAS Delay
OE pulse width
tRHPC
tOEP
–
–
–
OE hold time from CAS high
tOEHC
5
–
5
–
5
–
Output buffer turn-off delay from WE tWEZ
0
10
–
0
13
–
0
15
–
OE setup time prior to CAS
tOES
5
5
5
Hyper Page Mode (EDO) Read-
modify-Write Cycle
Hyper page mode (EDO) read-write tPRWC
cycle time
44
34
–
–
54
42
–
–
63
49
–
–
ns
ns
CAS precharge to WE
tCPWD
CAS before RAS Refresh Cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
tWRH
5
5
5
5
5
–
–
–
–
–
5
5
5
5
5
–
–
–
–
–
5
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
10
5
RAS to CAS precharge time
Write to RAS precharge time
Write hold time referenced to RAS
10
10
Self Refresh Cycle (L-versions only)
100k
69
100k
84
RAS pulse width
RAS precharge time
CAS hold time
tRASS
tRPS
tCHS
_
–
–
100k
104
-50
_
–
–
ns 17
ns 17
ns 17
–
–
-50
-50
Test Mode Cycle
Write command setup time
Write command hold time
tWTS
tWTH
5
5
–
–
5
5
–
–
5
5
–
–
ns 18
ns 18
Semiconductor Group
11
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
Notes:
1) All voltages are referenced to VSS.
Vih may overshoot to Vcc + 0.2V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse
width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = Vil. In the case of ICC4 it can be changed once or less
during a hyper page mode cycle ( thpc).
5) An initial pause of 100 µs is required after power-up followed by 8 RAS-only-refresh cycles, before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.
16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in
Read-Modify-Write cycles.
17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refresh in an evenly distributed manner over the refresh interval using CBR refresh
cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh.
If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the
refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey
after exit from Self Refresh
18) In a Test Mode Read Cycle, the value of trac, taa, tcac and tcpa are delayed by 5 ns from the specified value.
These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated
timings must be adjusted by 5 ns.
Semiconductor Group
12
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRC
tRAS
tRP
V
IH
RAS
CAS
Address
WE
V
IL
tCSH
tCRP
tRSH
tCAS
tRCD
V
IH
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
V
IH
Column
Row
Row
V
IL
tRCH
tRAH
tRCS
tRRH
V
IH
V
IL
tAA
tOEA
V
IH
OE
V
IL
tCDD
tDZC
tODD
tDZO
V
IH
I/O
(Inputs)
V
tCAC
tCLZ
IL
tOFF
tOEZ
V
OH
I/O
(Outputs)
Hi Z
Valid Data Out
Hi Z
V
OL
tRAC
WL1
“H ” o r “L ”
Read Cycle
Semiconductor Group
13
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
CAS
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Row
Row
Column
Address
V
IL
tCWL
tRAH
tWCS
V
tWP
IH
WE
OE
V
IL
tWCH
tRWL
V
IH
V
IL
tDH
tDS
V
IH
I/O
(Inputs)
Valid Data In
V
IL
V
OH
I/O
(Outputs)
Hi Z
V
OL
WL2
“H ” o r “L ”
Write Cycle (Early Write)
Semiconductor Group
14
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRC
tRAS
tRP
V
IH
RAS
CAS
Address
WE
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Row
Row
Column
V
IL
tCWL
tRWL
tWP
tRAH
V
IH
V
IL
tOEH
V
IH
OE
V
tODD
tDS
tOEZ
IL
tDH
tDZO
tDZC
V
IH
I/O
(Inputs)
Valid Data
V
IL
tCLZ
tOEA
V
OH
Hi-Z
I/O
(Outputs)
Hi-Z
V
OL
WL3
“H ” o r “L ”
Write Cycle (OE Controlled Write)
Semiconductor Group
15
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRWC
tRAS
tRP
V
IH
RAS
tCSH
V
IL
tRSH
tCAS
tRCD
tCRP
V
IH
V
CAS
IL
tRAH
tCAH
tASR
tASC
tASR
V
IH
Address
Row
Column
Row
V
IL
tCWL
tRWL
tWP
tAWD
tRAD
tCWD
tRWD
V
IH
WE
OE
V
IL
tAA
tRCS
tOEH
tOEA
V
IH
V
IL
tDS
tDH
tDZO
tDZC
V
IH
Valid
Data in
I/O
(Inputs)
V
IL
tCLZ
tCAC
tODD
tOEZ
V
OH
I/O
(Outputs)
Data
Out
V
OL
tRAC
“H ” o r “L ”
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
16
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRP
tRAS
V
tRCD
tRHPC
IH
RAS
V
IL
tRSH
tCAS
tCRP
tHPC
tCAS
tCRP
tCAS
tCP
V
IH
CAS
V
IL
tCSH
tRAH
tRAL
tCAH
tCAH
tASC
tASC
tASC
tCAH
tASR
V
IH
Address
Column 2
Column N
Row
Column 1
V
IL
tRAD
tRRH
tRCH
tRCS
V
IH
WE
OE
V
tCAC
tAA
tCPA
tCAC
tAA
tCPA
IL
tOES
tOEA
tOFF
V
OH
V
OL
tRAC
tAA
tCAC
tOEZ
tCOH
tCOH
tCLZ
V
I/O
IH
Data Out
1
Data Out
Data Out
N
(Output)
2
V
IL
WL5
“H ” o r “L ”
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
17
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRP
tRAS
V
tRCD
tRHCP
IH
RAS
V
IL
tRSH
tCAS
tCRP
tHPC
tCAS
tCRP
tCAS
tCP
V
IH
CAS
V
IL
tCSH
tRAH
tRAL
tCAH
tASC
tASC
tASC
tCAH
tCAH
tASR
V
IH
Address
Column N
Column 2
Row
Column 1
V
IL
tRAD
tRRH
tRCH
tRCS
V
IH
WE
OE
CAC
t
tCAC
tAA
tCPA
V
IL
tAA
CPA
tOFF
tOES
tOEA
t
tOEHC
tOEHC
V
OH
V
OL
tOEP
tOEZ
tOEP
tOEA
tRAC
tAA
tCAC
tOEA
OEZ
t
tOEZ
tCLZ
V
I/O
IH
Data Out
1
Data Out
2
Data Out
N
(Output)
V
IL
WL6
“H ” o r “L ”
Hyper Page Mode (EDO) Read Cycle (OE Control)
Semiconductor Group
18
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRP
tRAS
V
tRCD
tRHPC
IH
RAS
V
IL
tRSH
tCAS
tCRP
tHPC
tCAS
tCRP
tCAS
tCP
V
IH
CAS
V
IL
tCSH
tRAH
tRAL
tCAH
tASC
tASC
tASC
tCAH
tCAH
tASR
V
IH
Address
Column 2
Column N
Row
Column 1
V
IL
tRAD
AA
t
AA
t
tRRH
tRCH
tRCS
tRCH
tRCH
tRCS
tRCS
V
IH
WE
V
IL
tWP
tWP
tCAC
CAC
t
OFF
t
tOES
tOEA
CPA
t
CPA
t
V
OH
OE
V
OL
tRAC
tAA
tCAC
OEZ
t
tWEZ
tWEZ
tCLZ
V
I/O
IH
Data Out
2
Data Out
1
Data Out
N
(Output)
V
IL
WL7
“H ” o r “L ”
Hyper Page Mode (EDO) Read Cycle (WE Control)
Semiconductor Group
19
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRP
tRAS
V
tRCD
tRHPC
IH
RAS
V
IL
tCRP
tRSH
tCAS
tHPC
tCAS
tCRP
tCAS
tCP
V
IH
CAS
V
IL
tCSH
tRAH
tRAL
tCAH
tASC
tASC
tCAH
tASC
tCAH
tASR
V
IH
Row
Addr
Address
Column 1
Column 2
Column N
V
IL
tRAD
tRWL
tCWL
tCWL
tCWL
tWCH
tWP
tWCS
tWCS
tWCS
tWCH
tWP
tWCH
tWP
V
IH
WE
V
IL
V
OH
OE
V
OL
tDH
tDS
tDS
tDH
tDH
tDS
V
IH
Data In 1
Data In 2
Data In N
I/O (Input)
V
IL
“H ” o r “L ”
WL8
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
20
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRP
tRAS
V
tRCD
IH
RAS
V
IL
tRSH
tCAS
tCRP
tHPC
tCAS
tCRP
tCAS
tCP
tCP
V
IH
CAS
V
IL
tCSH
tRAH
tRAL
tCAH
tCAH
tASC
tASC
tASC
tCAH
tASR
V
IH
Address
Column N
Column 2
Row
Column 1
V
IL
tRAD
tCWL
tCWL
tCWL
tRWL
tRCS
tRCS
tRCS
V
IH
WE
V
IL
tWP
tOEH
tWP
tWP
tOEH
tOEH
V
OH
OE
V
OL
tODD
tODD
tDS
tDH
tDS
tDS
tDH
tDH
tODD
V
I/O
(Input)
IH
Data In
2
Data In
1
Data In
N
V
IL
WL16
“H ” o r “L ”
Hyper Page Mode (EDO) Late Write Cycle
Semiconductor Group
21
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
SAR
t
RP
t
P
RC
t
L
L
EOH
WR
t
WC
t
t
PW
HD
t
t
H
SR
L
t
DS
D
t
S
AR
t
DO
t
AC
D
t
WC
D
t
DW
WA
P
C
A
A
t
H
t
Z
t
AC
PC
LC
AC
t
t
t
t
A
t
C
L
SAC
ZD
EOH
t
t
t
WC
t
HD
PW
t
t
C
W
SD
t
S
D
ASP
RP
R
AC
t
t
DO
t
D
t
EOZ
t
D
W
W
D
t
WA
PC
t
t
H
Z
A
EOA
t
AC
LC
PC
t
t
t
A
t
C
L
DZ
SAC
t
t
PC
t
WC
t
EOH
t
PW
t
HD
t
SD
t
D
OEZ
t
DO
D
t
S
AC
WC
D
t
t
H
WA
EOA
H
t
C
WRD
Z
t
t
SC
AC
t
AC
LC
t
A
t
t
t
O
SAC
t
ZD
t
C
C
S
D
AR
ZD
CR
t
t
t
CR
t
D
AR
H
t
AR
t
SAR
t
WL17
Hyper Page Mode (EDO) Read-Modify-Write Cycle
Semiconductor Group
22
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCRP
tRPC
V
IH
CAS
V
IL
tRAH
tASR
tASR
V
IH
Address
Row
Row
V
IL
V
OH
I/O
(Outputs)
HI-Z
V
OL
“H ” o r “L ”
WL9
RAS Only Refresh Cycle
Semiconductor Group
23
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRC
tRP
tRP
tRAS
V
IH
RAS
CAS
V
IL
tRPC
tCP
tCSR
tCRP
tRPC
tCHR
V
IH
V
IL
tWRP
tWRH
V
IH
WE
OE
V
IL
tOEZ
V
IH
V
IL
tCDD
V
IH
I/O
(Inputs)
V
IL
tODD
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
“H ” o r “L ”
WL10
CAS-before-RAS Refresh Cycle
Semiconductor Group
24
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRC
tRC
tRP
tRP
tRAS
tRAS
V
IH
RAS
V
IL
tRSH
tRCD
tCRP
tCHR
V
IH
CAS
V
tRAD
IL
tWRP
tASC
tASR
tRAH
tWRH
tCAH
tASR
V
IH
Column
Address
Row
Row
V
IL
tRRH
tRCS
V
IH
WE
OE
V
IL
tAA
tOEA
V
IH
V
IL
tDZC
tDZO
tCDD
tODD
V
IH
I/O
(Inputs)
V
IL
tCAC
tOFF
tCLZ
tOEZ
tRAC
V
OH
I/O
(Outputs)
Valid Data Out
HI-Z
V
OL
WL11
“H ” o r “L ”
Hidden Refresh Read Cycle
Semiconductor Group
25
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRC
tRC
tRP
tRP
tRAS
V
tRAS
IH
RAS
V
IL
tRCD
tRSH
tCHR
tCRP
V
IH
CAS
V
tRAD
IL
tRAH
tASR
tASC
tCAH
tASR
V
IH
Address
Row
Column
Row
V
IL
tWCS
tWRP tWRH
tWCH
tWP
V
IH
WE
V
IL
tDS
tDH
V
IH
I/O
(Input)
Valid Data
V
IL
V
OH
I/O
(Output)
HI-Z
V
OL
“H ” o r “L ”
WL12
Hidden Refresh Early Write Cycle
Semiconductor Group
26
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRASS
tRP
tRPS
V
IH
RAS
CAS
V
IL
tRPC
tCP
tCRP
tCHS
tCSR
V
IH
V
IL
tWRP
tWRH
V
IH
WE
OE
V
IL
V
IH
V
IL
tCDD
V
IH
I/O
(Inputs)
V
IL
ODD
t
tOEZ
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
WL13
“H ” o r “L ”
Self Refresh (Sleep Mode)
Semiconductor Group
27
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
tRC
tRP
tRAS
tRP
V
IH
RAS
CAS
V
tRPC
IL
tCSR
tCP
tCHR
tCRP
tRPC
V
IH
V
IL
tRAH
tASR
V
IH
Address
WE
Row
V
IL
tWTS
tWTH
V
IH
V
IL
V
IH
OE
V
IL
tODD
V
I/O
(Inputs)
IH
HI-Z
V
IL
tCDD
tOEZ
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
“H ” o r “L ”
WL15
Test Mode Entry Cycle
Semiconductor Group
28
HYB3164(5)405BJ/BT(L)-40/-50/-60
16M x 4-DRAM
Package Outlines
Plastic Package P-SOJ-32-1 (400 mil)
(Small Outline J-lead, SMD)
Plastic Package P-TSOPII-32-1 (400 mil)
(Small Outline J-lead, SMD)
Semiconductor Group
29
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