HYB3164800J [INFINEON]
8M x 8-Bit Dynamic RAM; 8M ×8位动态随机存储器
| 型号： | HYB3164800J |
| 厂家： | 
Infineon |
| 描述： | 8M x 8-Bit Dynamic RAM |
| 文件： | 总28页 (文件大小：455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8M x 8-Bit Dynamic RAM
(4k & 8k Refresh)
HYB 3164800J/T -50/-60
HYB 3165800J/T -50/-60
Preliminary Information
• 8 388 608 words by 8-bit organization
• 0 to 70 ˚C operating temperature
• Fast access and cycle time
RAS access time:
50 ns (-50 version)
60 ns (-60 version)
Cycle time:
90 ns (-50 version)
110 ns (-60 version)
CAS access time:
13 ns ( -50 version)
15 ns ( -60 version)
• Fast page mode cycle time
35 ns (-50 version)
40 ns (-60 version)
• Single + 3.3 V (± 0.3V) power supply
• Low power dissipation
max. 396 active mW ( HYB 3164800J/T-50)
max. 360 active mW ( HYB 3164800J/T-60)
max. 504 active mW ( HYB 3165800J/T-50)
max. 432 active mW ( HYB 3165800J/T-60)
7.2 mW standby (TTL)
720 W standby (MOS)
• Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh modes
• Fast page mode capability
• 8192 refresh cycles/128 ms , 13 R/ 10C addresses (HYB 3164800J/T)
• 4096 refresh cycles/ 64 ms , 12 R/ 11C addresses (HYB 3165800J/T)
• Plastic Package:
P-SOJ-34-1
P-TSOPII-34-1 500 mil
500 mil
HYB 3164(5)800J
HYB 3164(5)800T
Semiconductor Group
121
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
This device is a 64 MBit dynamic RAM organized 8 388 608 by 8 bits. The device is fabricated in
SIEMENS/IBM’s most advanced first generation 64Mbit CMOS silicon gate process technology.
The circuit and process design allow this device to achieve high performance and low power
dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either
LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)800J/T to be
packaged in a 500 mil wide SOJ-34 or TSOP-34 plastic package. These packages provide high
system bit densities and are compatible with commonly used automatic testing and insertion
equipment.
Ordering Information
Type
Ordering
Code
Package
Descriptions
HYB 3164800J-50
HYB 3164800J-60
on request
on request
P-SOJ-34-1
500 mil DRAM (access time 50 ns)
500 mil DRAM (access time 60 ns)
500 mil DRAM (access time 50 ns)
500 mil DRAM (access time 60 ns)
500 mil DRAM (access time 50 ns)
500 mil DRAM (access time 60 ns)
500 mil DRAM (access time 50 ns)
500 mil DRAM (access time 60 ns)
P-SOJ-34-1
HYB 3164800T-50 on request
HYB 3164800T-60 on request
P-TSOPII-34-1
P-TSOPII-34-1
P-SOJ-34-1
HYB 3165800J-50
HYB 3165800J-60
on request
on request
P-SOJ-34-1
HYB 3165800T-50 on request
HYB 3165800T-60 on request
P-TSOPII-34-1
P-TSOPII-34-1
Pin Names
A0-A12
A0-A11
RAS
Address Inputs for HYB 3164800J/T
Address Inputs for HYB 3165800J/T
Row Address Strobe
Output Enable
OE
I/O1-I/O8
CAS
Data Input/Output
Column Address Strobe
Read/Write Input
Power Supply ( + 3.3V)
Ground
WRITE
Vcc
Vss
Semiconductor Group
122
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
P-SOJ-34-1 (500 mil)
P-TSOPII-34-1 (500 mil)
Pin Configuration
Semiconductor Group
123
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
TRUTH TABLE
FUNCTION
RAS
CAS
WRITE
OE
ROW
ADDR ADDR
COL
I/O1-
I/O8
Standby
H
L
L
L
L
L
L
L
H - X
L
X
H
X
L
X
X
High Impedance
Data Out
Read
ROW
ROW
ROW
ROW
ROW
n/a
COL
COL
COL
Early-Write
L
L
X
Data In
Delayed-Write
Read-Modify-Write
Fast Page Mode Read
L
H - L
H - L
H
H
Data In
L
L - H
L
COL Data Out, Data In
1st Cycle
2nd Cycle
1st Cycle
H - L
H - L
H - L
COL
COL
COL
Data Out
Data Out
Data In
H
L
Fast Page Mode Early
Write
L
X
ROW
2nd Cycle
1st Cycle
2st Cycle
L
L
H - L
H - L
H - L
H
L
H - L
H - L
X
X
L - H
L - H
X
n/a
ROW
n/a
COL
Data In
Fast Page Mode RMW
COL Data Out, Data In
COL Data Out, Data In
L
RAS only refresh
CAS-before-RAS refresh
Test Mode Entry
L
ROW
X
n/a
n/a
High Impedance
High Impedance
High Impedance
Data Out
H - L
H - L
L-H-L
L-H-L
L
H
X
L
L
X
X
n/a
Hidden Refresh
READ
L
H
L
ROW
ROW
COL
COL
WRITE
L
L
X
Data In
Semiconductor Group
124
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Block Diagram for HYB 3165800J/T
Semiconductor Group
125
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Block Diagram for HYB 3164800J/T
Semiconductor Group
126
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Absolute Maximum Ratings
Operating temperature range..............................................................................................0 to 70 ˚C
Storage temperature range.........................................................................................– 55 to 150 ˚C
Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................-0.5V to 4.6 V
Power dissipation......................................................................................................................1.0 W
Data out current (short circuit)..................................................................................................50 mA
Note
Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.
DC Characteristics
TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165800J/T)
Parameter
Symbol
Limit Values
Unit Note
min.
max.
Vcc+0.3
0.8
Input high voltage
Input low voltage
VIH
VIL
2.0
V
V
V
1)
1)
– 0.3
2.4
Output high voltage (LVTTL)
VOH
–
Output „H“ level voltage (Iout = -2mA)
Output low voltage (LVTTL)
Output „L“level voltage (Iout = +2mA)
VOL
VOH
VOL
II(L)
–
0.4
V
Output high voltage (LVCMOS)
Output „H“ level voltage (Iout = -100uA)
Vcc-0.2 -
V
Ouput low voltage (LVCMOS)
Output „L“ level voltage (Iout = +100uA)
-
0.2
V
Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
– 2
– 2
2
2
µA
µA
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
IO(L)
ICC1
Average Vcc supply current:
-50 ns version
-60 ns version
–
–
110 (140) mA 2) 3) 4)
100 (120) mA
(RAS, CAS, address cycling: tRC = tRC min.)
Standby Vcc supply current
(RAS=CAS= Vih)
ICC2
–
2
mA
–
Semiconductor Group
127
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
DC Characteristics (cont’d)
TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165800J/T)
Parameter
Symbol
Limit Values
min. max.
Unit Note
Average Vcc supply current, during RAS-only
ICC3
refresh cycles:
-50 ns version
-60 ns version
–
–
110 (140) mA 2) 4)
100 (120) mA
(RAS cycling: CAS = VIH: tRC = tRC min.)
Average Vcc supply current,
ICC4
during fast page mode:
-50 ns version
-60 ns version
–
–
85 (85)
75 (75)
mA 2) 3) 4)
mA
(RAS = V , CAS, address cycling: tPC=tPC min.)
IL
ICC5
–
200
A
–
Standby Vcc supply current
(RAS=CAS= Vcc-0.2V)
Average Vcc supply current, during CAS-before- ICC6
RAS refresh mode:
-50 ns version
-60 ns version
–
–
110 (140) mA 2) 4)
100 (120) mA
(RAS, CAS cycling: tRC = tRC min.)
ICC7
–
400
A
Self Refresh Current
Average Power Supply Current during Self Refresh.
(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
Capacitance
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A11,A12)
Input capacitance (RAS, CAS, WRITE, OE)
I/O capacitance (I/O1-I/O8)
CI1
CI2
CIO
–
–
–
5
7
7
pF
pF
pF
Semiconductor Group
128
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
AC Characteristics (note: 6,7,8)
TA = 0 to 70 ˚C,VCC = 3.3 ± 0.3V
Parameter
Symbol
HYB
3164(5)800
J/T-50
HYB
3164(5)800
J/T-60
Unit Note
min.
max. min.
max.
common parameters
Random read or write cycle time
RAS precharge time
tRC
90
30
50
13
0
–
110
40
60
15
0
–
ns
ns
ns
ns
ns
ns
ns
ns
tRP
–
–
RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tT
100k
100k
–
100k
100k
–
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
8
–
10
0
–
0
–
–
10
18
13
13
50
5
–
10
20
15
15
60
5
–
37
25
–
45
30
–
ns
ns
ns
ns
CAS hold time
–
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period for HYB3164800
Refresh period for HYB3165800
–
–
7
3
30
128
64
3
30
128
64
ns
tREF
tREF
–
–
ms
ms
–
–
Read Cycle
8, 9
8, 9
8, 10
8
Access time from RAS
Access time from CAS
Access time from column address
OE access time
tRAC
tCAC
tAA
–
50
13
25
13
–
–
60
15
30
15
–
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
tOEA
tRAL
tRCS
tRCH
–
–
Column address to RAS lead time
Read command setup time
Read command hold time
25
0
30
0
–
–
11
11
0
–
0
–
Read command hold time referenced tRRH
0
–
0
–
to RAS
Semiconductor Group
129
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
AC Characteristics (cont’d)(note: 6,7,8)
TA = 0 to 70 ˚C,VCC = 3.3 ± 0.3V
Parameter
Symbol
HYB
3164(5)800
J/T-50
HYB
3164(5)800
J/T-60
Unit Note
min.
max. min.
max.
–
8
CAS to output in low-Z
Output buffer turn-off delay
Output buffer turn-off delay from OE
Data to OE low delay
tCLZ
tOFF
tOEZ
tDZO
tCDD
tODD
0
–
0
ns
ns
ns
ns
ns
ns
12
12
13
14
14
–
13
13
–
–
15
15
–
–
–
0
0
CAS high to data delay
13
13
–
15
15
–
OE high to data delay
–
–
Write Cycle
Write command hold time
Write command pulse width
Write command setup time
Write command to RAS lead time
Write command to CAS lead time
Data setup time
tWCH
tWP
8
–
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
8
15
tWCS
tRWL
tCWL
tDS
0
13
13
0
15
15
0
16
16
13
Data hold time
tDH
10
0
10
0
CAS delay time from Din
tDZC
Read-Modify-Write Cycle
Read-write cycle time
tRWC
tRWD
tCWD
tAWD
tOEH
126
68
31
43
13
–
–
–
–
–
150
80
35
50
15
–
–
–
–
–
ns
ns
ns
ns
ns
15
15
15
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
OE command hold time
Fast Page Mode Cycle
Fast page mode cycle time
CAS precharge time
tPC
35
10
–
–
40
10
–
–
ns
ns
ns
ns
tCP
–
–
8
Access time from CAS precharge
RAS pulse width
tCPA
tRAS
30
200k
35
200k
50
60
Semiconductor Group
130
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
AC Characteristics (cont’d)(note: 6,7,8)
TA = 0 to 70 ˚C,VCC = 3.3 ± 0.3V
Parameter
Symbol
HYB
3164(5)800
J/T-50
HYB
3164(5)800
J/T-60
Unit Note
min.
max. min.
max.
CAS precharge to RAS Delay
tRHCP
30
–
35
–
ns
Fast Page Mode Read-Modify-Write
Cycle
Fast page mode read-write cycle time tPRWC
71
48
–
–
80
55
–
–
ns
ns
CAS precharge to WE
tCPWD
CAS-before-RAS refresh cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
tWRH
5
–
–
–
–
–
5
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
10
5
10
5
RAS to CAS precharge time
Write to RAS precharge time
Write hold time referenced to RAS
10
10
10
10
CAS-before-RAS counter test cycle
CAS precharge time
tCPT
25
–
30
–
ns
Test mode cycle
Write command setup time
Write command hold time
tWTS
tWTH
10
10
–
–
10
10
–
–
ns
ns
Self Refresh Cycle
RAS pulse width
RAS precharge time
CAS hold time
17
17
17
tRASS
tRPS
tCHS
100k
90
–
–
–
100k
110
-50
–
–
–
ns
ns
-50
Semiconductor Group
131
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less
during a fast page mode cycle ( tpc).
5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.
16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in
Read-Modify-Write cycles.
17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refresh in an evenly distributed manner over the refresh iterval using CBR refresh
cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh.
If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the
refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey
after exit from Self Refresh
Semiconductor Group
132
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCSH
tCRP
tRSH
tCAS
tRCD
V
IH
CAS
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
V
IH
Column
Address
Row
Address
Row
Address
Address
WRITE
OE
V
IL
tRCH
t
RAH tRCS
tRRH
V
IH
V
IL
tAA
tOEA
V
IH
V
IL
tCDD
tDZC
tODD
tDZO
V
IH
I/O1-I/O84
(Inputs)
V
tCAC
tCLZ
IL
tOFF
tOEZ
V
OH
I/O1-I/O8
(Outpus)
Hi Z
Valid Data Out
Hi Z
V
OL
tRAC
“H” or “L”
Read Cycle
Semiconductor Group
133
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
CAS
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Column
Address
Row
Address
Row
Address
Address
WRITE
OE
V
IL
tCWL
tRAH
tWCS
V
tWP
IH
V
IL
tWCH
tRWL
V
IH
V
IL
tDS
tDH
V
IH
I/O1-I/O8
(Inputs
Valid Data In
V
IL
V
OH
I/O1-I/O8
(Outputs)
Hi Z
V
OL
“H” or “L”
Write Cycle (Early Write)
Semiconductor Group
134
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
CAS
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Row
Column
Address
Row
Address
WRITE
OE
Address
Address
V
IL
tCWL
tRWL
tWP
tRAH
V
IH
V
IL
tOEH
V
IH
V
tODD
tOEZ
IL
tDH
tDZO
tDZC
tDS
V
IH
I/O1-I/O8
(Inputs)
Valid Data
V
IL
tCLZ
tOEA
V
OH
Hi-Z
Hi-Z
I/O1-I/O8
(Outputs)
V
OL
“H” or “L”
Write Cycle (OE Controlled Write)
Semiconductor Group
135
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRWC
tRAS
tRP
V
IH
RAS
tCSH
V
IL
tRSH
tCAS
tRCD
tCRP
V
IH
V
CAS
IL
tCAH
tRAH
tASR
tASC
tASR
V
IH
Column
Address
Row
Address
Row
Address
Address
V
IL
tCWL
tRWL
tWP
tAWD
tRAD
tCWD
tRWD
V
IH
WRITE
V
IL
tAA
tOEA
tRCS
tOEH
V
IH
OE
V
IL
tDZO
tDS
tDH
tDZC
V
IH
Valid
Data in
I/O1-I/O8
(Inputs)
V
IL
tCLZ
tCAC
tODD
tOEZ
V
OH
I/O1-I/O8
(Outputs)
Data
Out
V
OL
tRAC
“H” or “L”
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
136
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
137
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRASP
tRP
V
IH
RAS
V
IL
tRHCP
tRSH
tPC
tRCD
tCP
tCRP
tCAS
tCAS
tCAS
V
IH
CAS
V
IL
tCSH
tCAH
tRAH
tCAH
tCAH
tASR
tASC
tASR
tASC
tASC
V
IH
Row
Addr
Column
Address
Column
Address
Row
Address
Column
Address
Address
V
IL
tRAD
tRCS
tRCH
tRCH
tRCS
tRCS
V
IH
WRITE
V
IL
tCPA
tAA
tCPA
tAA
tOEA
tRRH
tAA
tOEA
tOEA
V
IH
OE
V
IL
tDZC
tDZO
tDZC
tDZO
tDZC
tCDD
tODD
tDZO
tODD
tODD
V
IH
I/O1-I/O8
(Inputs)
V
IL
tCAC
tCAC
tCLZ
tCAC
tCLZ
tOFF
tOEZ
tOFF
tOFF
tOEZ
tOFF
tOEZ
tCLZ
V
OH
I/O1-I/O8
(Outputs)
Valid
Data Out
Valid
Data Out
Valid
Data Out
V
OL
“H” or “L”
Fast Page Mode Read Cycle
Semiconductor Group
138
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRASP
tRP
V
IH
RAS
V
IL
tPC
tCAS
tRSH
tCAS
tCRP
tCAS
tRCD
tCP
V
IH
CAS
V
IL
tRAL
tRAH
tASR
tCAH
tCAH
tCAH
tASC
tASR
tASC
tASC
V
IH
Row
Addr
Column
Address
Column
Address
Column
Address
Column
Address
Address
V
IL
tCWL
tRWL
tWCS
tWCH
tWP
tCWL
tWCS
tCWL
tWCS
tWCH
tWP
tRAD
tWCH
tWP
V
IH
WRITE
V
IL
V
IH
OE
V
IL
tDH
tDH
tDH
tDS
tDS
tDS
V
IH
I/O1-I/O8
(Inputs)
Valid
Data In
Valid
Data In
Valid
Data In
V
IL
V
OH
I/O1-I/O8
(Outputs)
HI-Z
V
OL
“H” or “L”
Fast Page Mode Early Write Cycle
Semiconductor Group
139
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCRP
tRPC
V
IH
CAS
V
IL
tRAH
tASR
tASR
V
IH
Row
Row
Address
Address
Address
V
IL
V
OH
I/O1-I/O8
(Outputs)
HI-Z
V
OL
“H” or “L”
RAS-Only Refresh Cycle
Semiconductor Group
140
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRP
tRP
tRAS
V
IH
RAS
CAS
V
IL
tCRP
tRPC
tCP
tCSR
tRPC
tCHR
V
IH
V
IL
tWRP
tWRH
V
IH
WRITE
V
IL
tOEZ
V
IH
OE
V
IL
tCDD
V
IH
I/O1-I/O8
(Inputs)
V
IL
tODD
V
OH
I/O1-I/O8
(Outputs)
HI-Z
V
OL
tOFF
“H” or “L”
CAS-Before-RAS Refresh Cycle
Semiconductor Group
141
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRC
tRP
tRP
tRAS
tRAS
V
IH
RAS
V
IL
tRSH
tRCD
tCRP
tCHR
V
IH
CAS
V
tRAD
tRAH
IL
tWRP
tASC
tASR
tWRH
tCAH
tASR
V
IH
Column
Address
Row
Address
Row
Addr
Address
V
IL
tRRH
tRCS
V
IH
WRITE
V
IL
tAA
tOEA
V
IH
OE
V
IL
tDZC
tCDD
tODD
tDZO
V
IH
I/O1-I/O8
(Inputs)
V
IL
tOFF
tCAC
tCLZ
tOEZ
tRAC
V
OH
I/O1-I/O8
(Outputs)
Valid Data Out
HI-Z
V
OL
“H” or “L”
Hidden Refresh Cycle (Read)
Semiconductor Group
142
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRC
tRP
tRP
tRAS
V
tRAS
IH
RAS
V
IL
tRCD
tRSH
tCHR
tCRP
V
IH
CAS
tRAD
V
IL
tRAH
tASR
tASC
tCAH
tASR
V
IH
Row
Address
Row
Addr
Column
Address
Address
V
IL
tWCS
tWCH
tWP
V
IH
WRITE
OE
V
IL
V
IH
V
IL
tDS
tDH
V
IH
I/O1-I/O8
(Inputs)
Valid Data
V
IL
V
OH
I/O1-I/O8
(Outputs)
HI-Z
V
OL
“H” or “L”
Hidden Refresh Cycle (Early Write)
Semiconductor Group
143
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRP
tRAS
V
IH
RAS
CAS
V
IL
tRSH
tCAS
tCHR
tCPT
tCSR
V
IH
V
IL
tRAL
tCAH
tASR
tASC
V
IH
Row
Column
Address
Read Cycle
WRITE
V
Address
Address
IL
tAA
tWRP
tRRH
tRCH
tRCS
tCAC
tWRH
V
IH
V
IL
tOEA
V
IH
OE
V
IL
tDZC
tDZO
tCDD
tODD
V
I/O1-I/O8
(Inputs)
IH
V
IL
tOFF
tCLZ
tOEZ
V
I/O1-I/O8
(Outputs)
OH
OL
Valid Data
Out
V
tWCS
tWRP
tRWL
tCWL
tWCH
Write Cycle
WRITE
tWRH
V
IH
V
IL
V
V
IH
IL
OE
tDH
tDS
I/O1-I/O8
(Inputs)
V
IH
Valit
Data In
V
IL
tCWL
tRWL
I/O1-I/O8
(Outputs)
V
tAWD
tCWD
IH
HI-Z
V
tWRP
Read-Modify-WriteILCycle
tRCS
tWRH
tWP
V
IH
tCAC
V
WRITE
OE
IL
tAA
tOEA
tOEH
V
IH
V
IL
tDS
tDZC
tDZO
tDH
V
V
IH
IL
I/O1-I/O8
(Inputs)
Data In
tODD
tOEZ
tCAC
tCLZ
V
I/O1-I/O8
(Outputs)
OH
OL
HI-Z
HI-Z
D.Out
V
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
144
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRP
tRAS
tRP
V
IH
RAS
CAS
V
IL
tRPC
tCP
tCRP
tRPC
tCHR
tCSR
V
IH
V
IL
tRAH
tASR
V
IH
Row
Address
Adress
WRITE
V
IL
tWTH
tWTS
V
IH
V
IL
V
IH
OE
V
IL
tODD
V
I/O1-I/O8 IH
(Inputs)
V
IL
tCDD
tOEZ
V
OH
I/O1-I/O8
(Outputs)
HI-Z
V
OL
tOFF
“H” or “L”
Test Mode Entry
Semiconductor Group
145
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRP
tRASS
tRPS
V
IH
RAS
CAS
V
IL
tCRP
tRPC
tCP
tCHS
tCSR
V
IH
V
IL
tWRP
tWRH
V
IH
WRITE
V
IL
tOEZ
V
IH
OE
V
IL
tCDD
V
IH
I/O1-I/O8
(Inputs)
V
IL
tODD
V
OH
I/O1-I/O8
(Outputs)
HI-Z
V
OL
tOFF
“H” or “L”
CAS-before-RAS Self Refresh
Semiconductor Group
146
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Package Outlines
P-SOJ-34-1 (500 mil)
(Plastic Small Outline J-leaded Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
147
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
P-TSOPII-34-1 (500 mil)
(Plastic Thin Small Outline Package Type
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
148
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