HYB3165405TL-60 [INFINEON]
16M x 4-Bit Dynamic RAM; 16M ×4位动态RAM
| 型号： | HYB3165405TL-60 |
| 厂家： | 
Infineon |
| 描述： | 16M x 4-Bit Dynamic RAM |
| 文件： | 总32页 (文件大小：474K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16M x 4-Bit Dynamic RAM
(4k & 8k Refresh, EDO-version)
HYB 3164405J/T(L) -50/-60
HYB 3165405J/T(L) -50/-60
Preliminary Information
• 16 777 216 words by 4-bit organization
• 0 to 70 ˚C operating temperature
• Fast access and cycle time
RAS access time:
50 ns (-50 version)
60 ns (-60 version)
Cycle time:
84 ns (-50 version)
104 ns (-60 version)
CAS access time:
13 ns ( -50 version)
15 ns ( -60 version)
• Hyper page mode (EDO) cycle time
20 ns (-50 version)
25 ns (-60 version)
• Single + 3.3 V (± 0.3V) power supply
• Low power dissipation
max. 396 active mW ( HYB 3164405J/T(L)-50)
max. 360 active mW ( HYB 3164405J/T(L)-60)
max. 504 active mW ( HYB 3165405J/T(L)-50)
max. 432 active mW ( HYB 3165405J/T(L)-60)
7.2 mW standby (TTL)
720 W standby (MOS)
14.4 mW Self Refresh (L-version only)
• Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh modes
• Hyper page mode (EDO) capability
• 8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164405J/T(L))
• 4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165405J/T(L))
• Plastic Package:
P-SOJ-34-1
P-TSOPII-34-1 500 mil
500 mil
HYB 3164(5)400J
HYB 3164(5)400T
Semiconductor Group
89
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
This HYB3164(5)405 is a 64 MBit dynamic RAM organized 16 777 216 by 4 bits. The device is
fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process
technology. The circuit and process design allow this device to achieve high performance and low
power dissipation. The HYB3164(5)405 operates with a single 3.3 +/-0.3V power supply and
interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB
3164(5)400J/T to be packaged in a 500mil wide SOJ-34 or TSOP-34 plastic package. These
packages provide high system bit densities and are compatible with commonly used automatic
testing and insertion equipment.The HYB3164(5)405TL parts have a very low power „sleep mode“
supported by Self Refresh.
Ordering Information
Type
Ordering
Code
Package
Descriptions
HYB 3164405J-50
HYB 3164405J-60
on request
on request
P-SOJ-34-1
500 mil DRAM (access time 50 ns)
500 mil DRAM (access time 60 ns)
500 mil DRAM (access time 50 ns)
500 mil DRAM (access time 60 ns)
500 mil DRAM (access time 50 ns)
500 mil DRAM (access time 60 ns)
500 mil DRAM (access time 50 ns)
500 mil DRAM (access time 60 ns)
500 mil DRAM (access time 50 ns)
500 mil DRAM (access time 60 ns)
500 mil DRAM (access time 50 ns)
500 mil DRAM (access time 60 ns)
P-SOJ-34-1
HYB 3164405T-50 on request
HYB 3164405T-60 on request
HYB 3164405TL-50 on request
HYB 3164405TL-60 on request
P-TSOPII-34-1
P-TSOPII-34-1
P-TSOPII-34-1
P-TSOPII-34-1
P-SOJ-34-1
HYB 3165405J-50
HYB 3165405J-60
on request
on request
P-SOJ-34-1
HYB 3165405T-50 on request
HYB 3165405T-60 on request
HYB 3165405TL-50 on request
HYB 3165405TL-60 on request
P-TSOPII-34-1
P-TSOPII-34-1
P-TSOPII-34-1
P-TSOPII-34-1
Pin Names
A0-A12
A0-A11
RAS
Address Inputs for HYB 3164405J/T(L)
Address Inputs for HYB 3165405J/T(L)
Row Address Strobe
Output Enable
OE
I/O1-I/O4
CAS
Data Input/Output
Column Address Strobe
Read/Write Input
WRITE
Vcc
Power Supply ( + 3.3V)
Ground
Vss
Semiconductor Group
90
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
P-SOJ-34-1 (500 mil)
P-TSOPII-34-1 (500 mil)
Pin Configuration
Semiconductor Group
91
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
TRUTH TABLE
FUNCTION
RAS
CAS
WRITE
OE
ROW
ADDR ADDR
COL
I/O1-
I/O4
Standby
H
H - X
L
X
H
X
L
X
X
High Impedance
Data Out
Read
L
ROW
ROW
ROW
ROW
ROW
n/a
COL
COL
COL
Early-Write
L
L
L
X
Data In
Delayed-Write
L
L
H - L
H - L
H
H
Data In
Read-Modify-Write
Hyper Page Mode Read 1st Cycle
2nd Cycle
L
L
L
L - H
L
COL Data Out, Data In
H - L
H - L
H - L
H - L
H - L
H - L
H
COL
COL
COL
COL
Data Out
Data Out
Data In
L
H
L
Hyper Page Mode Write 1st Cycle
2nd Cycle
L
L
X
ROW
n/a
L
L
X
Data In
Hyper Page Mode RMW 1st Cycle
2st Cycle
L
H - L
H - L
X
L - H
L - H
X
ROW
n/a
COL Data Out, Data In
COL Data Out, Data In
L
RAS only refresh
CAS-before-RAS refresh
Test Mode Entry
L
ROW
X
n/a
n/a
High Impedance
High Impedance
High Impedance
Data Out
H - L
H - L
L-H-L
L-H-L
H - L
L
H
X
L
L
X
X
n/a
Hidden Refresh
READ
L
H
L
ROW
ROW
X
COL
COL
X
WRITE
L
L
X
Data In
Self Refresh
L
H
X
High Impedance
(L-version only)
Semiconductor Group
92
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Block Diagram for HYB 3164405J/T(L)
Semiconductor Group
93
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Block Diagram for HYB 3165405J/T(L)
Semiconductor Group
94
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Absolute Maximum Ratings
Operating temperature range..............................................................................................0 to 70 ˚C
Storage temperature range.........................................................................................– 55 to 150 ˚C
Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................-0.5V to 4.6 V
Power dissipation......................................................................................................................1.0 W
Data out current (short circuit)..................................................................................................50 mA
Note
Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.
DC Characteristics
TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165405J/T)
Parameter
Symbol
Limit Values
Unit Note
min.
max.
Vcc+0.3
0.8
Input high voltage
Input low voltage
VIH
VIL
2.0
V
V
V
1)
1)
– 0.3
2.4
Output high voltage (LVTTL)
VOH
–
Output „H“ level voltage (Iout = -2mA)
Output low voltage (LVTTL)
Output „L“level voltage (Iout = +2mA)
VOL
VOH
VOL
II(L)
–
0.4
V
Output high voltage (LVCMOS)
Output „H“ level voltage (Iout = -100uA)
Vcc-0.2 -
V
Ouput low voltage (LVCMOS)
Output „L“ level voltage (Iout = +100uA)
-
0.2
V
Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
– 2
– 2
2
2
µA
µA
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
IO(L)
ICC1
Average Vcc supply current:
-50 ns version
-60 ns version
–
–
110 (140) mA 2) 3) 4)
100 (120) mA
(RAS, CAS, address cycling: tRC = tRC min.)
Standby Vcc supply current
(RAS=CAS= Vih)
ICC2
–
2
mA
–
Semiconductor Group
95
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
DC Characteristics (cont’d)
TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165405J/T)
Parameter
Symbol
Limit Values
min. max.
Unit Note
Average Vcc supply current, during RAS-only
ICC3
refresh cycles:
-50 ns version
-60 ns version
–
–
110 (140) mA 2) 4)
100 (120) mA
(RAS cycling: CAS = VIH: tRC = tRC min.)
AverageVccsupplycurrent,during
ICC4
hyperpage mode (EDO):
-50 ns version
–
–
115 (150) mA 2) 3) 4)
100 (120) mA
-60 ns version
(RAS = V , CAS, address cycling: tHPC=tHPC min.)
IL
ICC5
–
200
A
–
Standby Vcc supply current
(RAS=CAS= Vcc-0.2V)
Average Vcc supply current, during CAS-before- ICC6
RAS refresh mode:
-50 ns version
-60 ns version
–
–
110 (140) mA 2) 4)
100 (120) mA
(RAS, CAS cycling: tRC = tRC min.)
ICC7
–
400
A
Self Refresh Current (L-version only)
Average Power Supply Current during Self Refresh.
(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
Capacitance
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A11,A12)
Input capacitance (RAS, CAS, WRITE, OE)
I/O capacitance (I/O1-I/O4)
CI1
CI2
CIO
–
–
–
5
7
7
pF
pF
pF
Semiconductor Group
96
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
5)6)
AC Characteristics
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V , tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
-50
max. min.
-60
max.
min.
common parameters
Random read or write cycle time
RAS precharge time
tRC
84
30
50
8
–
104
40
60
10
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRP
–
–
RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tT
100k
10k
–
100k
10k
–
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
0
8
–
10
0
–
0
–
–
8
–
10
14
12
10
50
5
–
12
10
8
37
25
45
30
–
CAS hold time
45
5
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period for HYB3164405
Refresh period for HYB3165405
–
–
1
50
128
64
1
50
128
64
ns
7
tREF
tREF
–
–
ms
ms
–
–
Read Cycle
Access time from RAS
Access time from CAS
Access time from column address
OE access time
tRAC
tCAC
tAA
–
50
13
25
13
–
–
60
15
30
15
–
ns
ns
ns
ns
ns
ns
ns
ns
8, 9
8, 9
8,10
–
–
–
–
tOEA
tRAL
tRCS
tRCH
–
–
Column address to RAS lead time
Read command setup time
Read command hold time
25
0
30
0
–
–
0
–
0
–
11
11
Read command hold time referenced to tRRH
0
–
0
–
RAS
Semiconductor Group
97
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
5)6)
AC Characteristics (cont’d)
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V , tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
-50
max. min.
-60
max.
min.
0
CAS to output in low-Z
tCLZ
tOFF
tOEZ
tDZC
tDZO
tCDD
tODD
–
0
–
ns
ns
ns
ns
ns
ns
ns
8
Output buffer turn-off delay
Output buffer turn-off delay from OE
Data to CAS low delay
0
13
13
–
0
15
15
–
12
12
13
13
14
14
0
0
0
0
Data to OE low delay
0
–
0
–
CAS high to data delay
OE high to data delay
13
13
–
15
15
–
–
–
Write Cycle
Write command hold time
Write command pulse width
Write command setup time
Write command to RAS lead time
Write command to CAS lead time
Data setup time
tWCH
tWP
8
7
0
8
8
0
7
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
tWCS
tRWL
tCWL
tDS
15
10
10
0
16
16
Data hold time
tDH
10
Read-modify-Write Cycle
Read-write cycle time
tRWC
tRWD
tCWD
tAWD
tOEH
111
67
30
42
7
–
–
–
–
–
135
79
34
49
10
–
–
–
–
–
ns
ns
ns
ns
ns
RAS to WE delay time
15
15
15
CAS to WE delay time
Column address to WE delay time
OE command hold time
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time
CAS precharge time
tHPC
tCP
20
8
–
25
10
–
–
ns
ns
ns
ns
ns
–
–
Access time from CAS precharge
Output data hold time
tCPA
tCOH
tRAS
–
27
–
35
–
7
5
5
RAS pulse width in hyper page mode
50
200k
60
200k
Semiconductor Group
98
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
5)6)
AC Characteristics (cont’d)
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V , tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
-50
max. min.
-60
max.
min.
27
7
CAS precharge to RAS Delay
OE pulse width
tRHCP
tOEP
–
–
–
–
35
10
10
10
–
–
–
–
ns
ns
ns
ns
OE hold time from CAS high
tOEHC
7
WE pulse width to output disable at CAS tWPZ
7
high
Output buffer turn-off delay from WE
tWPZ
0
10
0
10
ns
Hyper Page Mode (EDO) Read-
modify-Write Cycle
Hyper page mode (EDO) read-write
cycle time
tPRWC
51
41
–
–
66
49
–
–
ns
ns
CAS precharge to WE
tCPWD
CAS before RAS refresh cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
tWRH
5
8
5
8
8
–
–
–
–
–
5
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
10
5
RAS to CAS precharge time
Write to RAS precharge time
Write hold time referenced to RAS
10
10
CAS-before-RAS counter test cycle
CAS precharge time (CAS-before-RAS tCPT
35
–
40
–
ns
counter test cycle)
Self Refresh Cycle
RAS pulse width during self refresh
RAS precharge time during self refresh tRPS
CAS hold time during self refresh tCHS
tRASS
100k
84
_
_
_
100k
104
-50
_
_
_
ns
ns
ns
17
17
17
-50
Semiconductor Group
99
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
5)6)
AC Characteristics (cont’d)
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V , tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
-50
max. min.
-60
max.
min.
Test Mode
Write command setup time
Write command hold time
tWTS
tWTH
10
10
–
–
10
10
–
–
ns
ns
18)
18)
Semiconductor Group
100
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Notes:
1) All voltages are referenced to VSS.
Vih may overshoot to VV + 0.2V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse width
< 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less
during a hyper page mode cycle ( thpc).
5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.
16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in
Read-Modify-Write cycles.
17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refresh in an evenly distributed manner over the refresh interval using CBR refresh
cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh.
If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the
refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey
after exit from Self Refresh
18) In a Test Mode Read Cycle, the value of trac, taa, tcac and tcpa are delayed by 5 ns from the specified value.
These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated
timings must be adjusted by 5 ns.
Semiconductor Group
101
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRAS
tRP
V
IH
RAS
CAS
Address
WE
V
IL
tCSH
tCRP
tRSH
tCAS
tRCD
V
IH
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
V
IH
Column
Row
Row
V
IL
tRCH
tRAH
tRCS
tRRH
V
IH
V
IL
tAA
tOEA
V
IH
OE
V
IL
tCDD
tDZC
tODD
tDZO
V
IH
I/O
(Inputs)
V
tCAC
tCLZ
IL
tOFF
tOEZ
V
OH
I/O
(Outputs)
Hi Z
Valid Data Out
Hi Z
V
OL
tRAC
WL1
“H” or “L”
Read Cycle
Semiconductor Group
102
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRAS
tRP
V
IH
RAS
CAS
Address
WE
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Row
Row
Column
V
IL
tCWL
tRAH
tWCS
V
tWP
IH
V
IL
tWCH
tRWL
V
IH
OE
V
IL
tDH
tDS
V
IH
I/O
(Inputs)
Valid Data In
V
IL
V
OH
I/O
(Outputs)
Hi Z
V
OL
WL2
“H” or “L”
Write Cycle (Early Write)
Semiconductor Group
103
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRAS
tRP
V
IH
RAS
CAS
Address
WE
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Row
Row
Column
V
IL
tCWL
tRWL
tWP
tRAH
V
IH
V
IL
tOEH
V
IH
OE
V
tODD
tDS
tOEZ
IL
tDH
tDZO
tDZC
V
IH
I/O
(Inputs)
Valid Data
V
IL
tCLZ
tOEA
V
OH
Hi-Z
Hi-Z
I/O
(Outputs)
V
OL
WL3
“H” or “L”
Write Cycle (OE Controlled Write)
Semiconductor Group
104
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRWC
tRAS
tRP
V
IH
RAS
tCSH
V
IL
tRSH
tCAS
tRCD
tCRP
V
IH
V
CAS
IL
tRAH
tCAH
tASR
tASC
tASR
V
IH
Address
Row
Column
Row
V
IL
tCWL
tRWL
tWP
tAWD
tRAD
tCWD
tRWD
V
IH
WE
OE
V
IL
tAA
tRCS
tOEH
tOEA
V
IH
V
IL
tDS
tDH
tDZO
tDZC
V
IH
Valid
Data in
I/O
(Inputs)
V
IL
tCLZ
tCAC
tODD
tOEZ
V
OH
I/O
(Outputs)
Data
Out
V
OL
tRAC
“H” or “L”
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
105
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRP
tRAS
V
tRCD
tRHCP
IH
RAS
V
IL
tRSH
tCAS
tCRP
tHPC
tCAS
tCRP
tCAS
tCP
V
IH
CAS
V
IL
tCSH
tRAH
tRAL
tCAH
tCAH
tASC
tASC
tASC
tCAH
tASR
V
IH
Address
Column 2
Column N
Row
Column 1
V
IL
tRAD
tRRH
tRCH
tRCS
V
IH
WE
OE
V
tCAC
tAA
tCPA
tCAC
tAA
tCPA
IL
tOES
tOEA
tOFF
V
OH
V
OL
tRAC
tAA
tCAC
tOEZ
tCOH
tCOH
tCLZ
V
I/O
IH
Data Out
1
Data Out
Data Out
N
(Output)
2
V
IL
WL5
“H” or “L”
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
106
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRP
tRAS
V
tRCD
tRHCP
IH
RAS
V
IL
tRSH
tCAS
tCRP
tHPC
tCAS
tCRP
tCAS
tCP
V
IH
CAS
V
IL
tCSH
tRAH
tRAL
tCAH
tASC
tASC
tASC
tCAH
tCAH
tASR
V
IH
Address
Column 2
Column N
Row
Column 1
V
IL
tRAD
tRRH
tRCH
tRCS
V
IH
WE
OE
tCAC
tAA
tCPA
CAC
t
V
IL
tAA
tCPA
tOES
tOEA
tOFF
tOEHC
tOEHC
V
OH
V
OL
tOEP
tOEZ
tOEP
tRAC
tAA
tCAC
tOEA
tOEA
tOEZ
tOEZ
tCLZ
V
I/O
IH
Data Out
1
Data Out
2
Data Out
N
(Output)
V
IL
WL6
“H” or “L”
Hyper Page Mode (EDO) Read Cycle (OE Control)
Semiconductor Group
107
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRP
tRAS
V
tRCD
tRHCP
IH
RAS
V
IL
tRSH
tCAS
tCRP
tHPC
tCAS
tCRP
tCAS
tCP
V
IH
CAS
V
IL
tCSH
tRAH
tRAL
tCAH
tASC
tASC
tASC
tCAH
tCAH
tASR
V
IH
Address
Column 2
Column N
Row
Column 1
V
IL
tRAD
tAA
tAA
tRRH
tRCH
tRCS
tRCH
tRCH
tRCS
tRCS
V
IH
WE
V
IL
tWPZ
tWPZ
tCAC
tCPA
tCAC
tCPA
tOES
tOEA
tOFF
V
OH
OE
V
OL
tRAC
tAA
tCAC
tOEZ
tWHZ
tWHZ
tCLZ
V
I/O
IH
Data Out
1
Data Out
2
Data Out
N
(Output)
V
IL
WL7
“H” or “L”
Hyper Page Mode (EDO) Read Cycle (WE Control)
Semiconductor Group
108
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRP
tRAS
V
tRCD
tRHCP
IH
RAS
V
IL
tCRP
tRSH
tCAS
tHPC
tCAS
tCRP
tCAS
tCP
V
IH
CAS
V
IL
tCSH
tRAL
tCAH
t
tASC
RAH tASC
tCAH
tASC
tCAH
tASR
V
IH
Row
Addr
Address
Column 1
Column 2
Column N
V
IL
tRAD
tRWL
tCWL
tCWL
tCWL
tWCH
tWP
tWCS
tWCS
tWCS
tWCH
tWP
tWCH
tWP
V
IH
WE
V
IL
V
OH
OE
V
OL
tDH
tDS
tDS
tDH
tDH
tDS
V
IH
Data In 1
Data In 2
Data In N
I/O (Input)
V
IL
“H” or “L”
WL8
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
109
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRP
tRAS
V
tRCD
IH
RAS
V
IL
tRSH
tCAS
tCRP
tHPC
tCAS
tCRP
tCAS
tCP
tCP
V
IH
CAS
V
IL
tCSH
tRAH
tRAL
tCAH
tCAH
tASC
tASC
tASC
tCAH
tASR
V
IH
Address
Column 2
Column N
Row
Column 1
V
IL
tRAD
tCWL
tCWL
tCWL
tRWL
tRCS
tRCS
tRCS
V
IH
WE
V
IL
tWP
tOEH
tWP
tWP
tOEH
tOEH
V
OH
OE
V
OL
tODD
tODD
tDS
tDH
tDS
tDS
tDH
tDH
tODD
V
I/O
(Input)
IH
Data In
1
Data In
2
Data In
N
V
IL
WL16
“H” or “L”
Hyper Page Mode (EDO) Late Write Cycle
Semiconductor Group
110
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
SAR
t
RP
t
RCP
t
EOH
WRL
t
WCL
t
t
PW
HD
t
t
SRH
t
DS
t
ARL
t
DO
t
ACS
t
WCD
t
WAD
PCWD
EOA
t
t
t
CA
PCA
LCZ
H
t
t
t
t
A
t
SAC
ZDC
EOH
t
t
t
WCL
t
HD
PW
t
t
SD
t
RPWC
RASP
ACS
t
t
DO
t
t
EOZ
t
WCD
t
WAD
PCWD
t
t
EOA
t
ACH
LCZ
PCA
t
t
t
A
t
ZDC
SAC
t
t
PC
t
WCL
t
EOH
t
PW
t
HD
t
SD
t
EOZ
t
DO
t
ACS
WCD
t
t
WAD
EOA
t
WRD
t
t
SCH
ACH
t
CA
LCZ
t
A
t
t
t
SAC
t
ZDO
t
ARC
ZDC
CRS
t
t
t
CRD
t
ARD
t
ARH
t
SAR
t
WL17
Hyper Page Mode (EDO) Read-Modify-Write Cycle
Semiconductor Group
111
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCRP
tRPC
V
IH
CAS
V
IL
tRAH
tASR
tASR
V
IH
Address
Row
Row
V
IL
V
OH
I/O
(Outputs)
HI-Z
V
OL
“H” or “L”
WL9
RAS Only Refresh Cycle
Semiconductor Group
112
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRP
tRP
tRAS
V
IH
RAS
CAS
V
IL
tRPC
tCP
tCSR
tCRP
tRPC
tCHR
V
IH
V
IL
tWRP
tWRH
V
IH
WE
OE
V
IL
tOEZ
V
IH
V
IL
tCDD
V
IH
I/O
(Inputs)
V
IL
tODD
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
“H” or “L”
WL10
CAS-before-RAS Refresh Cycle
Semiconductor Group
113
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRC
tRP
tRP
tRAS
tRAS
V
IH
RAS
V
IL
tRSH
tRCD
tCRP
tCHR
V
IH
CAS
V
tRAD
IL
tWRP
tASC
tASR
tRAH
tWRH
tCAH
tASR
V
IH
Column
Address
Row
Row
V
IL
tRRH
tRCS
V
IH
WE
OE
V
IL
tAA
tOEA
V
IH
V
IL
tDZC
tDZO
tCDD
tODD
V
IH
I/O
(Inputs)
V
IL
tCAC
tOFF
tCLZ
tOEZ
tRAC
V
OH
I/O
(Outputs)
Valid Data Out
HI-Z
V
OL
WL11
“H” or “L”
Hidden Refresh Read Cycle
Semiconductor Group
114
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRC
tRP
tRP
tRAS
V
tRAS
IH
RAS
V
IL
tRCD
tRSH
tCHR
tCRP
V
IH
CAS
tRAD
V
IL
tRAH
tASR
tASC
tCAH
tASR
V
IH
Address
Row
Column
Row
V
IL
tWCS
tWRP tWRH
tWCH
tWP
V
IH
WE
V
IL
tDS
tDH
V
IH
I/O
(Input)
Valid Data
V
IL
V
OH
I/O
(Output)
HI-Z
V
OL
“H” or “L”
WL12
Hidden Refresh Early Write Cycle
Semiconductor Group
115
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRP
tRASS
tRPS
V
IH
RAS
CAS
V
IL
tRPC
tCP
tCRP
tCHS
tCSR
V
IH
V
IL
tWRP
tWRH
V
IH
WE
OE
V
IL
V
IH
V
IL
tCDD
V
IH
I/O
(Inputs)
V
IL
tODD
tOEZ
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
WL13
“H” or “L”
Self Refresh (Sleep Mode)
Semiconductor Group
116
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRP
tRAS
tRP
V
IH
RAS
CAS
V
tRPC
IL
tCSR
tCP
tCHR
tCRP
tRPC
V
IH
V
IL
tRAH
tASR
V
IH
Address
WE
Row
V
IL
tWTS
tWTH
V
IH
V
IL
V
IH
OE
V
IL
tODD
V
I/O
(Inputs)
IH
HI-Z
V
IL
tCDD
tOEZ
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
“H” or “L”
WL15
Test Mode Entry Cycle
Semiconductor Group
117
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
t
RP
tRAS
Read Cycle:
RAS
V
IH
IL
V
tRSH
tCAS
tCP
tCHR
tCSR
CAS
V
IH
V
tRAL
IL
tASR
tASC tCAH
Column
tAA
V
IH
IL
Address
WE
Row
V
tWRP
tRRH
tRCH
V
IH
IL
tCAC
V
tWRH
tOEA
tRCS
V
IH
IL
OE
V
tCDD
tDZC
V
tODD
I/O
IH
IL
(Inputs)
V
tDZO
tOFF
tCLZ
tOEZ
Out
V
I/O
(Outputs)
OH
OL
Data
V
tWCS
tWRP
tRWL
tCWL
tWCH
Write Cycle:
WE
V
IH
IL
V
tWRH
V
V
IH
IL
OE
tDS
tDH
I/O
(Inputs)
V
IH
IL
Data In
V
I/O
(Outputs)
V
IH
HI-Z
V
IL
CAS-before-RAS Refresh Counter Test Cycle
Semiconductor Group
118
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Package Outlines
P-SOJ-34-1 (500 mil)
(Plastic Small Outline J-leaded Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
119
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
P-TSOPII-34-1 (500 mil)
(Plastic Thin Small Outline Package Type II
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
120
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