HYB3166160ATL-50 [INFINEON]
4M x 16-Bit Dynamic RAM; 4M ×16位动态RAM
| 型号： | HYB3166160ATL-50 |
| 厂家： | 
Infineon |
| 描述： | 4M x 16-Bit Dynamic RAM |
| 文件： | 总26页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4M x 16-Bit Dynamic RAM
( 8k, 4k & 2k Refresh)
HYB 3164160AT(L) -40/-50/-60
HYB 3165160AT(L) -40/-50/-60
HYB 3166160AT(L) -40/-50/-60
Advanced Information
• 4 194 304 words by 16-bit organization
• 0 to 70 °C operating temperature
• Fast Page Mode operation
• Performance:
-40
40
10
-50
50
13
25
90
35
-60
t
t
t
t
t
RAS access time
CAS access time
60
15
ns
ns
ns
ns
ns
RAC
CAC
AA
Access time from address 20
Read/write cycle time 75
Fast page mode cycle time 30
30
110
40
RC
PC
• Single + 3.3 V (± 0.3V) power supply
• Low power dissipation:
-40
-50
558
468
378
-60
HYB3166160AT(L)
HYB3165160AT(L)
HYB3164160AT(L)
900
756
612
396
324
270
mW
mW
mW
7.2 mW standby (TTL)
3.24 mW standby (MOS)
720 µW standby for L-version
• Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh (L-version only)
• 2 CAS / 1 WE byte control
• 8192 refresh cycles /128 ms , 13 R/ 9C addresses (HYB 3164160AT)
4096 refresh cycles / 64 ms , 12 R/ 10C addresses (HYB 3165160AT)
2048 refresh cycles / 32 ms , 11 R/ 11C addresses (HYB 3166160AT)
• 256 msec refresh period for L-versions
• Plastic Package:
P-TSOPII-50 400 mil
Semiconductor Group
1
6.97
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
This device is a 64 MBit dynamic RAM organized 4 194 304 by 16 bits. The device is fabricated on
an advanced second generation 64Mbit 0,35µm-CMOS silicon gate process technology. The circuit
and process design allow this device to achieve high performance and low power dissipation. This
DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or
LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)160AT to be packaged in a 400
mil wide TSOP-50 package. These packages provide high system bit densities and are compatible
with commonly used automatic testing and insertion equipment. The HYB3164(5/6)160ATL parts
(L-version) have a very low power „sleep mode“ supported by Self Refresh.
Ordering Information
Type
Ordering
Code
Package
Descriptions
8k-refresh versions:
HYB 3164160AT-40
HYB 3164160AT-50
HYB 3164160AT-60
HYB 3164160ATL-50
HYB 3164160ATL-60
4k-refresh versions:
HYB 3165160AT-40
HYB 3165160AT-50
HYB 3165160AT-60
HYB 3165160ATL-50
HYB 3165160ATL-60
2k-refresh versions:
HYB 3166160AT-40
HYB 3166160AT-50
HYB 3166160AT-60
HYB 3166160ATL-50
HYB 3166160ATL-60
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
400 mil
400 mil
400 mil
400 mil
400 mil
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
400 mil
400 mil
400 mil
400 mil
400 mil
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
400 mil
400 mil
400 mil
400 mil
400 mil
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
Semiconductor Group
2
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
Pin Configuration
P-TSOPII-50 (400 mil)
O
VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
N.C.
VCC
WE
1
2
3
4
5
6
7
8
9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
I/O16
I/O15
I/O14
I/O13
VSS
I/O12
I/O11
I/O10
I/O9
N.C.
VSS
L. CAS
UCAS
OE
N.C.
N.C.
A12/N.C. *
A11/N.C.**
A10
A9
A8
A7
A6
10
11
12
13
.
RAS
N.C.
N.C.
N.C.
N.C.
14
15
16
17
18
19
20
21
22
23
24
25
A0
A1
A2
A3
A4
A5
VCC
VSS
* Pin 33 is A12 for HYB 3164160AT(L) and N.C. for HYB 3165(6)160AT(L)
** Pin 32 is A11 for HYB 3164(5)160AT(L) and N.C. for HYB 3166160AT(L)
Pin Names
A0-A12
A0-A11
A0-A10
RAS
Address Inputs for 8k-refresh version HYB 3164160AT(L)
Address Inputs for 4k-refresh version HYB 3165160AT(L)
Address Inputs for 2k-refresh version HYB 3166160AT(L)
Row Address Strobe
OE
Output Enable
I/O1-I/O16
UCAS,LCAS
WE
Data Input/Output
Column Address Strobe
Read/Write Input
Vcc
Power Supply ( + 3.3V)
Vss
Ground
Semiconductor Group
3
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
TRUTH TABLE
FUNCTION
RAS LCAS UCAS
WE
OE
ROW
ADD
COL
ADD
I/O1-
I/O16
Standby
H
L
L
H - X
H - X
H
X
H
H
X
L
L
X
X
High Impedance
Data Out
Read:Word
Read:Lower Byte
L
L
ROW
ROW
COL
H
COL Lower Byte:Data Out
Upper-Byte:High-Z
Read:Upper Byte
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
X
X
X
ROW
ROW
ROW
ROW
COL
Lower Byte:High-Z
Upper Byte:Data Out
Write:Word
(Early-Write)
L
COL
Data In
Write:Lower Byte
(Early-Write)
L
H
L
COL Lower Byte:Data Out
Upper-Byte:High-Z
Write:Upper Byte
(Early Write)
H
L
L
COL
COL
COL
COL
COL
COL
COL
COL
Lower Byte:High-Z
Upper Byte:Data Out
Read-Modify-
Write
L
L
H - L
H
L - H ROW
Data Out, Data In
Fast Page Mode
Read (Word)
1st
Cycle
H - L
H - L
H - L
H - L
H - L
H - L
H - L
H - L
H - L
H - L
H - L
H - L
L
L
ROW
n/a
Data Out
Fast Page Mode
Read (Word)
2nd
Cycle
H
Data Out
Fast Page Mode
1st
L
X
X
ROW
n/a
Data In
Early Write(Word) Cycle
Fast Page Mode 2nd
Early Write(Word) Cycle
L
Data In
Fast Page Mode
RMW
1st
Cycle
H - L
H - L
L - H ROW
Data Out, Data In
Data Out, Data In
Fast Page Mode
RMW
2st
Cycle
L - H
n/a
RAS only refresh
L
H
L
H
L
X
H
X
X
ROW
X
n/a
n/a
High Impedance
High Impedance
CAS-before-RAS
refresh
H - L
Test Mode Entry
H - L
L
L
L
L
L
X
L
X
n/a
High Impedance
Data Out
Hidden Refresh
(Read)
L-H-
L
H
ROW
COL
Hidden Refresh
(Write)
L-H-
L
L
L
L
X
ROW
COL
Data In
Semiconductor Group
4
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
I/O16
I/O1 I/O2
WE
&
.
UCAS
LCAS
.
Data in
Buffer
Data out
Buffer
OE
No. 2 Clock
Generator
16
16
Column
Address
Buffer(9)
9
Column
Decoder
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Refresh
16
Sense Amplifier
I/O Gating
Controller
Refresh
Counter (13)
512
x16
13
A10
A11
A12
Row
Address
Buffers(13)
Row
Decoder
Memory Array
8192x512x16
13
13
8192
No. 1 Clock
Generator
RAS
Block Diagram for HYB 3164160AT(L)
Semiconductor Group
5
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
I/O16
I/O1 I/O2
WE
&
.
UCAS
LCAS
.
Data in
Buffer
Data out
Buffer
OE
No. 2 Clock
Generator
16
16
Column
Address
Buffer(10)
10
Column
Decoder
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Refresh
16
Sense Amplifier
I/O Gating
Controller
Refresh
Counter (12)
1024
x16
12
A10
A11
Row
Address
Buffers(12)
Row
Decoder
Memory Array
4096x1024x16
12
12
4096
No. 1 Clock
Generator
RAS
Block Diagram for HYB 3165160AT(L)
Semiconductor Group
6
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
I/O16
I/O1 I/O2
WE
&
.
UCAS
LCAS
.
Data in
Buffer
Data out
Buffer
OE
No. 2 Clock
Generator
16
16
Column
Address
Buffer(11)
11
Column
Decoder
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Refresh
16
Sense Amplifier
I/O Gating
Controller
Refresh
Counter (11)
2048
x16
11
A10
Row
Address
Buffers(11)
Row
Decoder
Memory Array
2048x2048x16
11
11
2048
No. 1 Clock
Generator
RAS
Block Diagram for HYB 3166160AT(L)
Semiconductor Group
7
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
Absolute Maximum Ratings
Operating temperature range..............................................................................................0 to 70 °C
Storage temperature range.........................................................................................– 55 to 150 °C
Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................-0.5V to 4.6 V
Power dissipation......................................................................................................................1.3 W
Data out current (short circuit)..................................................................................................50 mA
Note
Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
Unit Note
min.
max.
Vcc+0.3
0.8
Input high voltage
Input low voltage
VIH
VIL
2.0
V
V
V
1)
1)
– 0.3
2.4
Output high voltage (LVTTL)
VOH
–
Output „H“ level voltage (Iout = -2mA)
Output low voltage (LVTTL)
Output „L“level voltage (Iout = +2mA)
VOL
VOH
VOL
II(L)
–
0.4
V
Output high voltage (LVCMOS)
Output „H“ level voltage (Iout = -100uA)
Vcc-0.2 -
V
Ouput low voltage (LVCMOS)
Output „L“ level voltage (Iout = +100uA)
-
0.2
V
Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
– 2
– 2
2
2
µA
µA
Output leakage current
IO(L)
(DO is disabled, 0 V < Vout < Vcc )
Semiconductor Group
8
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
DC-Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter
Symbol
refresh version
2k 4k 8k
Unit Note
Operating Current
ICC1
-40 ns version
-50 ns version
-60 ns version
250
210
170
155
130
105
110
90
75
mA 2) 3) 4)
mA
mA
(RAS, CAS, address cycling: tRC = tRC min.)
Standby Current
(RAS=CAS= Vih)
ICC2
ICC3
2
2
2
mA
–
RASOnlyRefreshCurrent:
-
-40 ns version
-50ns version
-60 ns version
250
210
170
155
130
105
110
90
75
mA 2) 4)
mA
mA
(RAS cycling: CAS = VIH: tRC = tRC min.)
Fast Page Mode Current:
ICC4
-40 ns version
-50 ns version
-60 ns version
70
60
50
70
60
50
70
60
50
mA 2) 3) 4)
mA
mA
(RAS = VIL, CAS, address cycling: tPC=tPC min.)
Standby Current
(RAS=CAS= Vcc-0.2V)
ICC5
ICC5
ICC6
900
200
900
200
900
200
µA
µA
–
–
Standby Current (L-Version)
(RAS=CAS= Vcc-0.2V)
CAS Before RAS Refresh Current
-40 ns version
250
210
170
155
130
105
155
130
105
mA 2) 4)
mA
mA
-50 ns version
-60 ns version
(RAS, CAS cycling: tRC = tRC min.)
Self Refresh Current (L-version only)
ICC7
400
400
400
µA
(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
Semiconductor Group
9
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
AC64-2F
AC Characteristics (note: 6,7,8)
TA = 0 to 70 °C,VCC = 3.3 ± 0.3V
Symbol
Unit Note
Parameter
-40
-50
-60
min. max. min. max. min. max.
Common Parameters
Random read or write cycle time tRC
75
40
10
25
10
0
–
90
–
110
–
ns
RAS pulse width
tRAS
tCAS
tRP
100k 50
100k 13
100k 60
100k 15
100k ns
100k ns
CAS pulse width
RAS precharge time
–
30
10
0
–
40
10
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS precharge time
tCP
–
–
–
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay
RAS hold time
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tT
–
–
–
5
–
7
–
10
0
–
0
–
0
–
–
5
–
7
–
10
20
15
15
60
5
–
15
10
10
40
5
30
20
–
17
12
13
50
5
37
25
–
45
30
–
CAS hold time
–
–
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period for 8k-refresh
Refresh period for 4k-refresh
Refresh period for 2k-refresh
Refresh period for L-versions
–
–
–
7
1
30
128
64
32
256
1
30
128
64
32
256
1
30
tREF
tREF
tREF
tREF
–
–
–
128 ms
–
–
–
64
64
ms
ms
–
–
–
–
–
–
256 ms
Read Cycle
8, 9
8, 9
8, 10
8
Access time from RAS
Access time from CAS
tRAC
tCAC
–
40
10
20
10
–
–
50
13
25
13
–
–
60
15
30
15
–
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
Access time from column address tAA
–
–
–
OE access time
tOEA
–
–
–
Column address to RAS lead time tRAL
20
0
25
0
30
0
Read command setup time
Read command hold time
tRCS
tRCH
tRRH
–
–
–
11
11
0
–
0
–
0
–
Read command hold time
referenced to RAS
0
–
0
–
0
–
Semiconductor Group
10
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
AC64-2F
AC Characteristics (cont’d)(note: 6,7,8)
TA = 0 to 70 °C,VCC = 3.3 ± 0.3V
Symbol
Unit Note
Parameter
-40
-50
-60
min. max. min. max. min. max.
8
CAS to output in low-Z
tCLZ
tOFF
tOEZ
0
–
–
–
0
–
–
–
0
–
–
–
ns
ns
ns
12
12
Output buffer turn-off delay
10
10
13
13
15
15
Output buffer turn-off delay from
OE
13
14
14
Data to OE low delay
CAS high to data delay
OE high to data delay
tDZO
tCDD
tODD
0
–
–
–
0
–
–
–
0
–
–
–
ns
ns
ns
10
10
13
13
15
15
Write Cycle
Write command hold time
Write command pulse width
Write command setup time
tWCH
tWP
5
–
–
–
–
–
–
–
–
7
–
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
5
7
15
tWCS
0
0
Write command to RAS lead time tRWL
Write command to CAS lead time tCWL
10
10
0
13
13
0
15
15
0
16
16
13
Data setup time
tDS
Data hold time
tDH
5
7
10
0
CAS delay time from Din
tDZC
0
0
Read-Modify-Write Cycle
Read-write cycle time
RAS to WE delay time
CAS to WE delay time
tRWC
tRWD
tCWD
105
55
25
35
5
–
–
–
–
–
126
68
31
43
7
–
–
–
–
–
150
80
–
–
–
–
–
ns
ns
ns
ns
ns
15
15
15
35
Column address to WE delay time tAWD
50
OE command hold time
tOEH
10
Fast Page Mode Cycle
Fast page mode cycle time
tPC
30
–
–
35
–
–
40
–
–
ns
ns
8
Access time from CAS precharge tCPA
25
30
35
RAS pulse width
tRAS
40
25
200k 50
30
200k 60
35
200k ns
– ns
CAS precharge to RAS Delay
tRHPC
–
–
Semiconductor Group
11
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
AC64-2F
AC Characteristics (cont’d)(note: 6,7,8)
TA = 0 to 70 °C,VCC = 3.3 ± 0.3V
Symbol
Unit Note
Parameter
-40
-50
-60
min. max. min. max. min. max.
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle tPRWC
time
60
40
–
–
71
48
–
–
80
55
–
–
ns
ns
CAS precharge to WE
tCPWD
CAS-before-RAS Refresh Cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
5
5
0
5
5
–
–
–
–
–
5
5
0
5
5
–
–
–
–
–
5
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
10
0
RAS to CAS precharge time
Write to RAS precharge time
10
10
Write hold time referenced to RAS tWRH
Self Refresh Cycle (L-version only)
17
17
17
RAS pulse width
RAS precharge time
CAS hold time
tRASS
tRPS
100k –
100k –
100k –
ns
ns
ns
75
–
–
90
–
–
110
-50
–
–
tCHS
-50
-50
Capacitance
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A11,A12)
Input capacitance (RAS, CAS, WE, OE)
I/O capacitance (I/O1-I/O8)
CI1
CI2
CIO
–
–
–
5
7
7
pF
pF
pF
Semiconductor Group
12
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
Notes:
1) All voltages are referenced to VSS.
Vih may overshoot to Vcc + 2.0 V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse
width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less
during a fast page mode cycle ( tpc).
5) An initial pause of 100 µs is required after power-up followed by 8 RAS-only-refresh cycles, before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.
16) These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in Read-
Modify-Write cycles.
17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refresh in an evenly distributed manner over the refresh iterval using CBR refresh
cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh.
If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the
refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey
after exit from Self Refresh
Semiconductor Group
13
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCSH
tCRP
tRSH
tCAS
tRCD
V
IH
UCAS
LCAS
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
V
IH
Column
Row
Row
Address
WE
V
IL
tRCH
tRAH
tRCS
tRRH
V
IH
V
IL
tAA
tOEA
V
IH
OE
V
IL
tCDD
tDZC
tODD
tDZO
V
IH
I/O
(Inputs)
V
tCAC
tCLZ
IL
tOFF
tOEZ
V
OH
I/O
(Outputs)
Hi Z
Valid Data Out
Hi Z
V
OL
tRAC
WL1
“H” or “L”
Read Cycle
Semiconductor Group
14
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
UCAS
LCAS
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Row
Row
Column
Address
WE
V
IL
tCWL
tRAH
tWCS
V
tWP
IH
V
IL
tWCH
tRWL
V
IH
OE
V
IL
tDH
tDS
V
IH
I/O
(Inputs)
Valid Data In
V
IL
V
OH
I/O
(Outputs)
Hi Z
V
OL
WL2
“H” or “L”
Write Cycle (Early Write)
Semiconductor Group
15
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
UCAS
LCAS
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Row
Row
Column
Address
WE
V
IL
tCWL
tRWL
tWP
tRAH
V
IH
V
IL
tOEH
V
IH
OE
V
tODD
tDS
tOEZ
IL
tDH
tDZO
tDZC
V
IH
I/O
(Inputs)
Valid Data
V
IL
tCLZ
tOEA
V
OH
Hi-Z
Hi-Z
I/O
(Outputs)
V
OL
WL3
“H” or “L”
Write Cycle (OE Controlled Write)
Semiconductor Group
16
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRWC
tRAS
tRP
V
IH
RAS
tCSH
V
IL
tRSH
tCAS
tRCD
tCRP
V
IH
V
UCAS
LCAS
IL
tRAH
tCAH
tASR
tASC
tASR
V
IH
Address
Row
Column
Row
V
IL
tCWL
tRWL
tWP
tAWD
tRAD
tCWD
tRWD
V
IH
WE
OE
V
IL
tAA
tRCS
tOEH
tOEA
V
IH
V
IL
tDS
tDH
tDZO
tDZC
V
IH
Valid
Data in
I/O
(Inputs)
V
IL
tCLZ
tCAC
tODD
tOEZ
V
OH
I/O
(Outputs)
Data
Out
V
OL
tRAC
“H” or “L”
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
17
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRP
tRASP
V
IH
RAS
V
IL
tRHCP
tRSH
tCAS
tPC
tCAS
tCAS
tCP
tRCD
tCRP
V
IH
UCAS
LCAS
V
IL
tCSH
tCAH
tRAH
tCAH
tCAH
tASR
tASC
tASR
tASC
tASC
V
IH
Column
Column
Row
Row
Column
Address
V
IL
tRAD
tRCS
tRCH
tRCH
tRCS
tRCS
V
IH
WE
V
IL
tRRH
tCPA
tAA
tCPA
tAA
tOEA
tAA
tOEA
tOEA
V
IH
OE
V
IL
tDZC
tDZC
tDZO
tDZC
tCDD
tODD
tDZO
tDZO
tODD
tODD
V
IH
I/O
(Inputs)
V
IL
tCAC
tCLZ
tCAC
tOFF
tCAC
tOFF
tOFF
tRAC
tOEZ
tOEZ
tOEZ
tCLZ
tCLZ
V
OH
I/O
(Outputs)
Valid
Data Out
Valid
Data Out
Valid
Data Out
V
OL
“H” or “L”
FPM1
Fast Page Mode Read Cycle
Semiconductor Group
18
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRP
tRAS
V
IH
RAS
V
IL
tRSH
tCAS
tPC
tCAS
tRCD
tCP
tCAS
tCRP
V
IH
UCAS
LCAS
V
IL
tRAL
tCAH
tRAH
tCAH
tCAH
tASR
tASR
tASC
tASC
tASC
V
IH
Address
Column
Column
Row
Column
Column
V
IL
tCWL
tCWL
tWCH
tWP
tRAD
tWCS
tCWL
tWCH
tWP
tRWL
tWCS
tWCS
tWCH
tWP
V
IH
WE
V
IL
V
IH
OE
V
IL
tDH
tDH
tDH
tDS
tDS
tDS
V
IH
I/O
(Inputs)
Valid
Data In
Valid
Data In
Valid
Data In
V
IL
V
OH
I/O
(Outputs)
HI-Z
V
OL
“H” or “L”
FPM2
Fast Page Mode Early Write Cycle
Semiconductor Group
19
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
SAR
RP
t
t
P
RC
t
L
L
WR
WC
t
t
PW
HD
EOH
t
t
t
L
SD
D
t
H
S
AR
t
DO
EOZ
S
t
t
t
AC
t
D
W
D
WCD
t
WA
C
A
A
t
H
Z
PC
t
t
AC
PC
LC
AC
t
t
t
t
A
t
C
SAC
ZD
L
t
t
WC
t
EOH
HD
PW
t
t
t
C
W
SD
S
t
D
S
RA
RP
t
t
OD
AC
t
EOZ
t
D
t
D
D
W
WC
t
WA
t
H
Z
PC
EOA
t
t
AC
LC
t
t
A
A
t
PC
C
t
ZD
SAC
t
t
PC
t
WCL
t
PW
t
EOH
HD
t
t
SD
t
D
OEZ
t
DO
D
t
S
AC
WC
t
t
D
D
C
EOA
H
WA
WR
Z
t
t
H
t
AC
t
AC
LC
t
A
t
SC
t
t
O
SAC
t
ZD
t
C
C
S
D
ZD
AR
t
CR
t
t
CR
t
D
AR
H
t
AR
t
SAR
t
Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
20
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCRP
tRPC
V
IH
UCAS
LCAS
V
IL
tRAH
tASR
tASR
V
IH
Address
Row
Row
V
IL
V
OH
I/O
(Outputs)
HI-Z
V
OL
“H” or “L”
WL9
RAS-Only Refresh Cycle
Semiconductor Group
21
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRP
tRP
tRAS
V
IH
RAS
V
IL
tRPC
tCP
tCSR
tCRP
tRPC
tCHR
V
IH
UCAS
LCAS
V
IL
tWRP
tWRH
V
IH
WE
OE
V
IL
tOEZ
V
IH
V
IL
tCDD
V
IH
I/O
(Inputs)
V
IL
ODD
t
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
“H” or “L”
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
22
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRC
tRP
tRP
tRAS
tRAS
V
IH
RAS
V
IL
tRSH
tRCD
tCRP
tCHR
V
IH
UCAS
LCAS
V
tRAD
IL
tWRP
tASC
tASR
tRAH
tWRH
tCAH
tASR
V
IH
Column
Address
Row
Row
V
IL
tRRH
tRCS
V
IH
WE
OE
V
IL
tAA
tOEA
V
IH
V
IL
tDZC
tDZO
tCDD
tODD
V
IH
I/O
(Inputs)
V
IL
tCAC
tOFF
tCLZ
tOEZ
tRAC
V
OH
I/O
(Outputs)
Valid Data Out
HI-Z
V
OL
WL11
“H” or “L”
Hidden Refresh Cycle (Read)
Semiconductor Group
23
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRC
tRP
tRP
tRAS
V
tRAS
IH
RAS
V
IL
tRCD
tRSH
tCHR
tCRP
V
IH
UCAS
LCAS
V
tRAD
IL
tRAH
tASR
tASC
tCAH
tASR
V
IH
Address
WE
Row
Column
Row
V
IL
tWCS
tWRP tWRH
tWCH
tWP
V
IH
V
IL
tDS
tDH
V
IH
I/O
(Input)
Valid Data
V
IL
V
OH
I/O
(Output)
HI-Z
V
OL
“H” or “L”
WL12
Hidden Refresh Write Cycle
Semiconductor Group
24
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRP
tRASS
tRPS
V
IH
RAS
V
IL
tRPC
tCP
tCRP
tCHS
tCSR
V
IH
UCAS
LCAS
V
IL
tWRP
tWRH
V
IH
WE
OE
V
IL
V
IH
V
IL
tCDD
V
IH
I/O
(Inputs)
V
IL
tODD
tOEZ
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
WL13
“H” or “L”
CAS-before-RAS Self Refresh („Sleep Mode“)
Semiconductor Group
25
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
Package Outlines
Plastic Package P-TSOPII-50
(400 mil width, 0.8 mm lead pitch, thin small outline, SMD)
Semiconductor Group
26
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