HYB514175BJ-50 [INFINEON]
256k x 16-Bit EDO-DRAM; 256K ×16位EDO -DRAM
| 型号： | HYB514175BJ-50 |
| 厂家： | 
Infineon |
| 描述： | 256k x 16-Bit EDO-DRAM |
| 文件： | 总22页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256k × 16-Bit EDO-DRAM
HYB 514175BJ-50/-55/-60
Advanced Information
• 262 144 words by 16-bit organization
• 0 to 70 °C operating temperature
• Fast access and cycle time
• Low Power dissipation
max. 1100 mW active (-50 version)
max. 1045 mW active (-55 version)
max. 935 mW active (-60 version)
• RAS access time:
50 ns (-50 version)
55 ns (-55 version)
60 ns (-60 version)
• Standby power dissipation
11 mW standby (TTL)
5.5 mW max. standby (CMOS)
• CAS access time:
13 ns (-50 & -55 version)
15 ns (-60 version)
• Output unlatched at cycle end allows
two-dimensional chip selection
• Read, write, read-modify write,
CAS-before-RAS refresh, RAS-only
refresh, hidden-refresh and hyper page
(EDO) mode capability
• Cycle time:
89 ns (-50 version)
94 ns (-55 version)
104 ns (-60 version)
• 2 CAS/1 WE control
• Hyper page mode (EDO) cycle time
20 ns (-50 & -55 version)
• All inputs and outputs TTL-compatible
• 512 refresh cycles/16 ms
25 ns (-60 version)
• Plastic Packages:
• High data rate
P-SOJ-40-1 400 mil width
50 MHz (-50 & -55 version)
40 MHz (-60 version)
• Single + 5 V (± 10 %) supply with a built-in
V
BB generator
Semiconductor Group
1
1998-10-01
HYB 514175BJ/BJL-50/-55/-60
256k × 16 EDO-DRAM
The HYB 514175BJ is the new generation dynamic RAM organized as 262 144 words by 16-bit.
The HYB 514175BJ utilizes CMOS silicon gate process as well as advanced circuit techniques to
provide wide operation margins, both internally and for the system user. Multiplexed address inputs
permit the HYB 514175BJ to be packed in a standard plastic 400 mil wide P-SOJ-40-1 package.
This package size provides high system bit densities and is compatible with commonly used
automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 %)
power supply, direct interfacing with high performance logic device families such as Schottky TTL.
Ordering Information
Type
Ordering Code Package
Description
HYB 514175BJ-50
HYB 514175BJ-55
HYB 514175BJ-60
Q67100-Q2072 P-SOJ-40-1 400 mil
Q67100-Q2100 P-SOJ-40-1 400 mil
Q67100-Q2073 P-SOJ-40-1 400 mil
50 ns 256k × 16 EDO-DRAM
55 ns 256k × 16 EDO-DRAM
60 ns 256k × 16 EDO-DRAM
Truth Table
RAS
LCAS UCAS WE
OE
I/O1 - I/O8
I/O9 - I/O16
Operation
H
L
L
L
L
L
L
L
L
H
H
L
H
H
H
L
H
H
H
H
H
L
H
H
L
High-Z
High-Z
Dout
High-Z
High-Z
High-Z
Dout
Standby
Refresh
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
−
H
L
L
High-Z
Dout
L
L
Dout
L
H
L
H
H
H
H
Din
Don't care
Din
H
L
L
Don't care
Din
L
L
Din
L
L
H
High-Z
High-Z
Pin Names
A0 - A8
RAS
Address Inputs
Row Address Strobe
Column Address Strobe
Read/Write Input
Output Enable
UCAS, LCAS
WE
OE
I/O1 -I/O16
VCC
Data Input/Output
Power Supply (+ 5 V)
Ground (0 V)
VSS
N.C.
No Connection
Semiconductor Group
2
1998-10-01
HYB 514175BJ-50/-55/-60
256k × 16 EDO-DRAM
P-SOJ-40-1
V
V
SS
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
CC
I/O1
I/O2
I/O3
I/O4
I/O16
I/O15
I/O14
I/O13
V
V
CC
SS
I/O5
I/O6
I/O7
I/O8
N.C.
N.C.
WE
RAS
N.C.
A0
I/O12
I/O11
I/O10
9
10
11
12
13
14
15
16
31 I/O9
30
29
28
27
26
25
24
23
22
21
N.C.
LCAS
UCAS
OE
A8
A7
A6
A5
A4
A1 17
A2
A3
V
18
19
20
V
CC
SS
SPP02811
Pin Configuration
(top view)
Semiconductor Group
3
1998-10-01
HYB 514175BJ/BJL-50/-55/-60
256k × 16 EDO-DRAM
. . .
I/O1 I/O2
I/O16
.
.
.
Data In
Buffer
Data Out
Buffer
OE
16
WE
UCAS
LCAS
&
16
No.2 Clock
Generator
Column
Address
Buffers (9)
9
9
Column
Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
Refresh
Controller
16
Sense Amplifier
I/O Gating
Refresh
Counter (9)
512
x 16
9
.
.
.
Row
Address
Buffers (9)
9
9
Row
Decoder
Memory Array
512 x 512 x
512
16
.
.
.
No.1 Clock
Generator
RAS
V
Substrate Bias
Generator
CC
V
SS
SPB02827
Block Diagram
Semiconductor Group
4
1998-10-01
HYB 514175BJ-50/-55/-60
256k × 16 EDO-DRAM
Absolute Maximum Ratings
Operating temperature range ....................................................................................... 0 to + 70 °C
Storage temperature range.................................................................................... – 55 to + 150 °C
Input/output voltage ....................................................................................................... – 1 to + 6 V
Power supply voltage..................................................................................................... – 1 to + 6 V
Data out current (short circuit) ............................................................................................... 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 2 ns
Parameter
Symbol
Limit Values
min. max.
Unit Test
Condition
1
1
1
1
1
Input high voltage
VIH
VIL
2.4
– 1.0
2.4
–
V
CC + 0.5 V
Input low voltage
0.8
–
V
Output high voltage (IOUT = – 5.0 mA)
Output low voltage (IOUT = 4.2 mA)
VOH
VOL
II(L)
V
0.4
10
V
Input leakage current, any input
– 10
µA
(0 V < VIN < 7 V, all other inputs = 0 V)
1
Output leakage current
(DO is disabled, 0 V < VOUT < VCC)
IO(L)
ICC1
– 10
–
10
µA
Average VCC supply current
2, 3, 4
-50 version
-55 version
-60 version
200
190
170
mA
mA
Standby VCC supply current
(RAS = LCAS = UCAS = WE = VIH)
ICC2
ICC3
–
–
2
Average VCC supply current during
RAS-only refresh cycles
2, 4
-50 version
-55 version
-60 version
200
190
170
mA
mA
2, 3, 4
Average VCC supply current during
hyper page mode (EDO) operation
ICC4
–
-50 version
-55 version
-60 version
190
180
170
Semiconductor Group
5
1998-10-01
HYB 514175BJ/BJL-50/-55/-60
256k × 16 EDO-DRAM
DC Characteristics (cont’d)
TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
1
Standby VCC supply current
(RAS = LCAS = UCAS = WE = VCC – 0.2 V)
ICC5
ICC6
–
1
mA
2, 4
Average VCC supply current during
CAS-before-RAS refresh mode
-50 version
–
200
190
170
mA
-55 version
-60 version
Capacitance
TA = 0 to 70 °C; VCC = 5 V ± 10 %, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A8)
CI1
–
–
–
5
7
7
pF
pF
pF
Input capacitance (RAS, UCAS, LCAS, WE, OE) CI2
Output capacitance (l/O1 to l/O16)
CIO
5, 6
AC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 2 ns
Parameter
Symbol
Limit Values
-55
Unit Note
-50
-60
min. max. min. max. min. max.
Common Parameters
Random read or write cycle time
RAS precharge time
tRC
89
35
50
8
–
–
94
35
–
–
104 –
40
ns
ns
tRP
–
RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
10k 55
10k 60
10k 10
10k ns
10k ns
CAS pulse width
10k
–
8
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
0
0
–
0
–
ns
ns
ns
ns
ns
ns
8
–
8
–
10
0
–
0
–
0
–
–
8
–
8
–
10
14
12
–
12
10
37
25
12
10
43
30
45
30
Semiconductor Group
6
1998-10-01
HYB 514175BJ-50/-55/-60
256k × 16 EDO-DRAM
AC Characteristics (cont’d)5, 6
TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 2 ns
Parameter
Symbol
Limit Values
-55
min. max. min. max. min. max.
Unit Note
-50
-60
RAS hold time
tRSH
tCSH
tCRP
tT
13
40
5
–
13
45
5
–
15
50
5
–
ns
ns
ns
CAS hold time
–
–
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
–
–
–
7
1
50
16
1
50
16
1
50
16
ns
tREF
–
–
–
ms
Read Cycle
8, 9
Access time from RAS
Access time from CAS
Access time from column address
OE access time
tRAC
tCAC
tAA
–
50
13
25
13
–
–
55
13
25
13
–
–
60
15
30
15
–
ns
8, 9
–
–
–
ns
8, 10
–
–
–
ns
tOEA
tRAL
tRCS
tRCH
–
–
–
ns
ns
ns
Column address to RAS lead time
Read command setup time
Read command hold time
25
0
25
0
30
0
–
–
–
11
0
–
0
–
0
–
ns
11
Read command hold time ref. to RAS tRRH
CAS to output in low-Z
0
–
0
–
0
–
ns
8
tCLZ
0
–
0
–
0
–
ns
12
Output buffer turn-off delay from CAS tOFF
Output buffer turn-off delay from OE tOEZ
0
13
13
–
0
13
13
–
0
15
15
–
ns
12
0
0
0
ns
13
Data to OE low delay
CAS high to data delay
OE high to data delay
tDZO
tCDD
tODD
0
0
0
ns
14
10
10
–
10
10
–
13
13
–
ns
14
–
–
–
ns
Write Cycle
Write command hold time
Write command pulse width
Write command setup time
Write command to RAS lead time
Write command to CAS lead time
Data setup time
tWCH
tWP
8
–
–
–
–
–
–
–
–
8
–
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
–
ns
ns
8
8
15
tWCS
tRWL
tCWL
tDS
0
0
ns
13
13
0
13
13
0
15
15
0
ns
ns
16
ns
16
Data hold time
tDH
8
8
10
0
ns
13
Data to CAS low delay
tDZC
0
0
ns
Semiconductor Group
7
1998-10-01
HYB 514175BJ/BJL-50/-55/-60
256k × 16 EDO-DRAM
AC Characteristics (cont’d)5, 6
TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 2 ns
Parameter
Symbol
Limit Values
-55
Unit Note
-50
-60
min. max. min. max. min. max.
Read-Modify-Write Cycle
Read-write cycle time
tRWC
tRWD
tCWD
tAWD
tOEH
118 –
122 –
138 –
ns
15
RAS to WE delay time
64
27
39
10
–
–
–
–
69
27
39
10
–
–
–
–
77
32
47
13
–
–
–
–
ns
15
CAS to WE delay time
ns
15
Column address to WE delay time
OE command hold time
ns
ns
Hyper Page Mode (EDO) Cycle
Hyper page mode cycle time
CAS precharge time
tHPC
tCP
tCPA
tCOH
20
8
–
20
8
–
25
10
–
–
ns
ns
–
–
–
7
Access time from CAS precharge
Output data hold time
–
27
–
–
27
–
32
–
ns
5
5
5
ns
RAS pulse width in hyper page mode tRAS
RAS hold time from CAS precharge tRHCP
50
27
200k 55
200k 60
200k ns
–
27
–
32
–
ns
Hyper Page Mode (EDO) Read-Modify-Write Cycle
Hyper page mode read/write cycle
time
tPRWC
58
–
–
58
41
–
–
68
49
–
–
ns
ns
CAS precharge to WE delay time
tCPWD
41
CAS-before-RAS Refresh Cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
tWRH
5
–
–
–
–
–
5
–
–
–
–
–
5
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
10
5
10
5
10
5
RAS to CAS precharge time
Write to RAS precharge time
Write to RAS hold time
10
10
10
10
10
10
CAS-before-RAS Counter Test Cycle
CAS precharge time
tCPT
35
8
–
35
–
40
–
ns
Semiconductor Group
1998-10-01
HYB 514175BJ-50/-55/-60
256k × 16 EDO-DRAM
Notes
1. All voltages are referenced to VSS.
2. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
4. Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once
or less during a hyper page mode (EDO) cycle
5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of
8 RAS cycles are required.
6. AC measurements assume tT = 2 ns.
7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times
are also measured between VIH and VIL.
8. Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access
time is determined by the latter of tRAC, tCAC, tAA , tCPA , tOEA. tCAC is measured from tristate.
9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as
a reference point only. If tRCD is greater than the specified tRCD (MAX.) limit, then access time is
controlled by tCAC
.
10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as
a reference point only. If tRAD is greater than the specified tRAD (MAX.) limit, then access time is
controlled by tAA.
11.Either tRCH or tRRH must be satisfied for a read cycle.
12.tOFF (MAX.), tOEZ (MAX.) define the time at which the output achieves the open-circuit conditions and
are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or
CAS, whichever occurs last.
13.Either tDZC or tDZO must be satisfied.
14.Either tCDD or tODD must be satisfied.
15.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and
data out pin will remain open-circuit (high impedance) through the entire cycle; if
t
RWD > tRWD (MIN.), tCWD > tCWD (MIN.) and tAWD > tAWD (MIN.), the cycle is a read-write cycle and I/O will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the
condition of I/O (at access time) is indeterminated.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
Semiconductor Group
9
1998-10-01
HYB 514175BJ/BJL-50/-55/-60
256k × 16 EDO-DRAM
t RC
t RAS
t RP
VIH
VIL
RAS
t CSH
t RCD
t RSH
t CRP
VIH
VIL
t CAS
UCAS
LCAS
t RAD
t ASC
t RAL
t CAH
t ASR
Row
t ASR
VIH
VIL
Address
Column
Row
t RAH
t RCH
t RCS
t RRH
VIH
VIL
WE
OE
t AA
t OEA
VIH
VIL
t DZC
t CDD
t DZO
t ODD
VIH
VIL
I/O
(Inputs)
t OFF
t CAC
t CLZ
t OEZ
VOH
VOL
Hi Z
Hi Z
I/O
(Outputs)
Valid Data OUT
t RAC
"H" or "L"
SPT03043
Read Cycle
Semiconductor Group
10
1998-10-01
HYB 514175BJ-50/-55/-60
256k × 16 EDO-DRAM
t RC
t RAS
t RP
VIH
VIL
RAS
t CSH
t RCD
t RSH
t CRP
VIH
VIL
t CAS
UCAS
LCAS
t RAD
t ASC
t RAL
t CAH
t ASR
Row
t RAH
t ASR
VIH
VIL
Address
Column
Row
t CWL
t WCS
VIH
VIL
t WP
WE
OE
t WCH
t RWL
VIH
VIL
t DH
t DS
VIH
VIL
I/O
(Inputs)
Valid Data IN
VOH
VOL
Hi Z
I/O
(Outputs)
"H" or "L"
SPT03044
Write Cycle (Early Write)
Semiconductor Group
11
1998-10-01
HYB 514175BJ/BJL-50/-55/-60
256k × 16 EDO-DRAM
t RC
t RAS
t RP
VIH
VIL
RAS
t CSH
t RCD
t RSH
t CRP
VIH
VIL
t CAS
UCAS
LCAS
t RAD
t ASC
t RAL
t CAH
t ASR
Row
t RAH
t ASR
VIH
VIL
Address
Column
Row
t CWL
t RWL
t WP
VIH
VIL
WE
OE
t OEH
VIH
VIL
t ODD
t DZO
t DZC
t DH
tDS
VIH
VIL
I/O
(Inputs)
Valid Data
tOEZ
t CLZ
t OEA
VOH
VOL
Hi Z
Hi Z
I/O
(Outputs)
"H" or "L"
SPT03045
Write Cycle (OE Controlled Write)
Semiconductor Group
12
1998-10-01
HYB 514175BJ-50/-55/-60
256k × 16 EDO-DRAM
t RWC
t RAS
VIH
VIL
RAS
t CSH
t RP
t RSH
t CAS
t RCD
t CRP
VIH
VIL
UCAS
LCAS
t RAH
t CAH
t ASR
Row
t ASC
tASR
VIH
VIL
Address
Column
Row
t RAD
t CWL
t AWD
t CWD
t RWL
t WP
t RWD
VIH
VIL
WE
OE
t AA
t RCS
t OEA
t OEH
VIH
VIL
t DZC
t DS
t DH
tDZO
VIH
VIL
I/O
(Inputs)
Valid
Data IN
t ODD
t OEZ
t CAC
t CLZ
VOH
VOL
I/O
(Outputs)
Data
OUT
t RAC
"H" or "L"
SPT03046
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
13
1998-10-01
HYB 514175BJ/BJL-50/-55/-60
256k × 16 EDO-DRAM
tRAS
tRCD
tRHCP
VIH
VIL
RAS
tHPC
tRP
tCP
tRSH
tCRP
tCAS
tCAS
tCAS
tCRP
VIH
VIL
UCAS
LCAS
tCSH
tRAL
tCAH
tCAH
tRAH
tCAH
tASR
tASC
tASC
tASC
VIH
VIL
Address
WE
Row
tRAD
Column 1
Column 2
Column N
tRRH
tRCH
tRCS
VIH
VIL
tCAC
tAA
tCPA
tCAC
tAA
tCPA
tOES
tOEA
tOFF
VIH
VIL
OE
tRAC
tAA
tCAC
tCLZ
tCOH
tCOH
Data OUT 2
tOEZ
Data OUT N
VOH
VOL
I/O
(Output)
Data OUT 1
"H" or "L"
SPT03056
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
14
1998-10-01
HYB 514175BJ-50/-55/-60
256k × 16 EDO-DRAM
tRAS
tRCD
tRHCP
VIH
VIL
RAS
tHPC
tRP
tCP
t RSH
tCRP
tCAS
tCAS
tCAS
tCRP
VIH
VIL
UCAS
LCAS
tCSH
tRAL
tCAH
tRAH
tCAH
tCAH
tASR
tASC
tASC
tASC
VIH
VIL
Row
Address
Column 1
tCWL
Column 2
tCWL
Column N
Address
tRAD
tWCS
tRWL
tCWL
t WCS
t WCS
t WCH
t WP
t WCH
t WP
t WCH
t WP
VIH
VIL
WE
OE
VIH
VIL
tDH
tDH
tDH
tDS
tDS
tDS
VIH
VIL
I/O
(Input)
Data IN 1
Data IN 2
Data IN N
"H" or "L"
SPT03057
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
15
1998-10-01
HYB 514175BJ/BJL-50/-55/-60
256k × 16 EDO-DRAM
t RASP
VIH
VIL
RAS
tCSH
tRP
t CP
tPRWC
t RSH
tRCD
tCAS
tCAS
tCAS
tCRP
VIH
VIL
UCAS
LCAS
tRAD
tRAH
tRAL
tCAH
tCAH
tCAH
tASR
tASC
tASC
tASC
Column
tASR
Row
VIH
VIL
Address
Row
Column
tRWD
Column
tCPWD
tCWD
tCPWD
tCWD
tRWL
tCWL
tCWD
tCWL
tCWL
t OEH
tODD
tRCS
VIH
VIL
WE
t AWD
t AWD
t OEA
t AWD
t OEA
t AA
t WP
tWP
t WP
t OEA
t OEH
t OEH
VIH
VIL
OE
tCLZ
tCLZ
tCLZ
tDZC
tODD
tCPA
tCPA
tDZC
t ODD
tDZC
tDZO
VIH
VIL
I/O
(Inputs)
Data IN
Data IN
Data IN
tDH
tDH
tDH
tCAC
tCAC
tAA
tDS
tOEZ
tDS
tRAC
tAA
tDS
tOEZ
tOEZ
VOH
VOL
I/O
(Outputs)
Data
OUT
Data
OUT
Data
OUT
"H" or "L"
SPT03131
Hyper Page Mode (EDO) Late Write and Read-Modify-Write Cycles
Semiconductor Group
16
1998-10-01
HYB 514175BJ-50/-55/-60
256k × 16 EDO-DRAM
tRC
tRAS
tRP
VIH
VIL
RAS
tCRP
tRPC
VIH
VIL
UCAS
LCAS
tRAH
tASR
tASR
VIH
VIL
Address
Row
Row
VOH
VOL
Hi Z
I/O
(Outputs)
"H" or "L"
SPT03050
RAS-Only Refresh Cycle
Semiconductor Group
17
1998-10-01
HYB 514175BJ/BJL-50/-55/-60
256k × 16 EDO-DRAM
tRC
tRP
tRAS
tRP
VIH
VIL
RAS
tRPC
tCP
tCHR
tRPC
tCRP
tCSR
VIH
VIL
UCAS
LCAS
tWRH
tWRP
VIH
VIL
WE
OE
VIH
VIL
tODD
VIH
VIL
I/O
(Inputs)
tCDD
tOEZ
VOH
VOL
Hi Z
I/O
(Outputs)
tOFF
"H" or "L"
SPT03051
CAS-Before-RAS Refresh Cycle
Semiconductor Group
18
1998-10-01
HYB 514175BJ-50/-55/-60
256k × 16 EDO-DRAM
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH
VIL
RAS
tRCD
tRSH
tCHR
tCRP
VIH
VIL
UCAS
LCAS
tRAD
tASC
tRAH
tWRP
tASR
t WRH
tASR
tCAH
Column
VIH
VIL
Address
WE
Row
Row
tRCS
tRRH
VIH
VIL
tAA
tOEA
VIH
VIL
OE
tDZC
tCDD
tODD
tDZO
VIH
VIL
I/O
(Inputs)
tCAC
tCLZ
tRAC
tOFF
tOEZ
VOH
VOL
Hi Z
I/O
(Outputs)
Valid Data OUT
"H" or "L"
SPT03053
Hidden Refresh Cycle (Read)
Semiconductor Group
19
1998-10-01
HYB 514175BJ/BJL-50/-55/-60
256k × 16 EDO-DRAM
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
VIL
RAS
tRCD
tRSH
tCHR
tCRP
VIH
VIL
UCAS
LCAS
tRAD
tASC
tRAH
t ASR
t ASR
tCAH
Column
VIH
VIL
Address
Row
Row
tWCS
t WCH
t WP
t WRH
t WRP
VIH
VIL
WE
tDS
tDH
Valid Data
VIN
VIL
I/O
(Input)
VOH
VOL
Hi Z
I/O
(Output)
"H" or "L"
SPT03054
Hidden Refresh Cycle (Early Write)
Semiconductor Group
20
1998-10-01
HYB 514175BJ-50/-55/-60
256k × 16 EDO-DRAM
Read Cycle
tRAS
tRP
VIH
RAS
VIL
tCHR
tRSH
tCSR
tCP
VIH
tCAS
UCAS
LCAS
VIL
tRAL
tCAH
tASR
tASC
VIH
VIL
Address
WE
Column
tAA
Row
tWRP
tRRH
VIH
VIL
tCAC
tWRH
tRCS
tRCH
tOEA
VIH
VIL
OE
tCDD
tDZC
VIH
VIL
tODD
tOFF
tOEZ
I/O
(Inputs)
t DZO
tCLZ
VOH
VOL
I/O
(Outputs)
Data OUT
tWCS
tRWL
tCWL
tWCH
tWRP
Write Cycle
VIH
WE
VIL
tWRH
tDH
VIH
OE
VIL
tDS
VIH
I/O
Data IN
Hi Z
(Inputs)
VIL
VOH
I/O
(Outputs)
VOL
"H" or "L"
SPT03055
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
21
1998-10-01
HYB 514175BJ/BJL-50/-55/-60
256k × 16 EDO-DRAM
Package Outlines
Plastic Package, P-SOJ-40-1 (SMD)
(Plastic small outline J-leaded)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
1998-10-01
SMD = Surface Mounted Device
Semiconductor Group
22
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