HYM322030GS-70 [INFINEON]
2M x 32-Bit Dynamic RAM Module; 2M ×32位动态RAM模块型号: | HYM322030GS-70 |
厂家: | Infineon |
描述: | 2M x 32-Bit Dynamic RAM Module |
文件: | 总10页 (文件大小:81K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
2M x 32-Bit Dynamic RAM Module
HYM 322030S/GS-50/-60/-70
Advanced Information
• 2 097 152 words by 32-bit organization
• 1 memory bank
• Fast access and cycle time
50 ns access time
90 ns cycle time (-50 version)
60 ns access time
110 ns cycle time (-60 version)
70 ns access time
130 ns cycle time (-70 version)
• Fast page mode capability
35 ns cycle time (-50 version)
40 ns cycle time (-60 version)
45 ns cycle time (-70 version)
• Single + 5 V (± 10 %) supply
• Low power dissipation
max. 2640 mW active (-50 version)
max. 2420 mW active (-60 version)
max. 2200 mW active (-70 version)
CMOS – 22 mW standby
TTL
–44 mW standby
• CAS-before-RAS refresh
RAS-only-refresh
Hidden-refresh
• 4 decoupling capacitors mounted on substrate
• All inputs, outputs and clocks fully TTL compatible
• 72 pin Single in-Line Memory Module (L-SIM-72-9 ) with 20.32 mm (800 mil) height
• Utilizes four 2M × 8 -DRAMs in 400 mil SOJ packages
• 2048 refresh cycles / 32 ms with 11/10 addressing
• Optimized for use in byte-write non-parity applications
• Tin-Lead contact pads (S-version)
• Gold contact pads (GS - version)
Semicounductor Group
1
9.95
HYM 322030S/GS-50/-60/-70
2M × 32-Bit
The HYM 322030S/GS-50/-60/-70 is a 8 MByte DRAM module organized as 2 097 152 words by
32-bit in a 72-pin single-in-line package comprising four HYB 5117800BSJ 2M × 8 DRAMs in 400
mil wide SOJ-packages mounted together with four 0.2 µF ceramic decoupling capacitors on a PC
board.
Each HYB 5117800BSJ is described in the data sheet and is fully electrical tested and processed
according to SIEMENS standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 322030S/GS-60/-70 dictates the use of early write cycles.
Ordering Information
Type
Ordering Code
Package
Description
HYM 322030S-50
on request
L-SIM-72-9
DRAM Module
(access time 50 ns)
HYM 322030S-60
HYM 322030S-70
HYM 322030GS-50
HYM 322030GS-60
HYM 322030GS-70
Q67100-Q976
Q67100-Q977
on request
L-SIM-72-9
L-SIM-72-9
L-SIM-72-9
L-SIM-72-9
L-SIM-72-9
DRAM Module
(access time 60 ns)
DRAM Module
(access time 70 ns)
DRAM Module
(access time 50 ns)
Q67100-Q2018
Q67100-Q2019
DRAM Module
(access time 60 ns)
DRAM Module
(access time 70 ns)
Semiconductor Group
2
HYM 322030S/GS-50/-60/-70
2M × 32-Bit
Pin Configuration
Pin Names
VSS 1 DQ0
DQ16 3 DQ1
DQ17 5 DQ2
DQ18 7 DQ3
DQ19 9 VCC 10
N.C. 11 A0
2
4
6
8
A0R-A10R
A0C-A9C
DQ0-DQ31
CAS0 - CAS3
RAS0, RAS2
WE
Row Address Inputs
Column Address Inputs
Data Input/Output
Column Address Strobe
Row Address Strobe
Read/Write Input
Power (+ 5 V)
12
14
A1
A3
A5
13 A2
15 A4 16
17 A6 18
A10 19 DQ4 20
DQ20 21 DQ5 22
DQ21 23 DQ6 24
DQ22 25 DQ7 26
VCC
VSS
Ground
DQ23 27 A7
N.C. 29 VCC 30
A8 31 A9 32
N.C. 33 RAS2 34
N.C. 35 N.C. 36
28
PD
Presence Detect Pin
No Connection
N.C.
N.C. 37 N.C. 38
VSS 39 CAS0 40
CAS2 41 CAS3 42
CAS1 43 RAS0 44
N.C. 45 N.C. 46
WE
47 N.C. 48
Presence Detect Pins
DQ8 49 DQ24 50
DQ9 51 DQ25 52
DQ10 53 DQ26 54
DQ11 55 DQ27 56
DQ12 57 DQ28 58
VCC 59 DQ29 60
DQ13 61 DQ30 62
DQ14 63 DQ31 64
DQ15 65 N.C. 66
PD0 67 PD1 68
PD2 69 PD3 70
N.C. 71 VSS 72
-50
-60
-70
PD0
PD1
PD2
PD3
N.C.
N.C.
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
VSS
N.C.
Semiconductor Group
3
HYM 322030S/GS-50/-60/-70
2M × 32-Bit
RAS0
CAS0
CAS
RAS
D1
DQ0-DQ7
I/O1-I/O8
OE
CAS1
CAS
RAS
D2
DQ8-DQ15
I/O1-I/O8
OE
RAS2
CAS2
CAS
RAS
D3
DQ16-DQ23
I/O1-I/O8
OE
CAS3
CAS
RAS
D4
DQ24-DQ31
I/O1-I/O8
OE
A0R - A10R,
A0C - A9C
D1 - D4
D1 - D4
WE
VCC
VSS
C1 - C 4
Block Diagram
Semiconductor Group
4
HYM 322030S/GS-50/-60/-70
2M × 32-Bit
Absolute Maximum Ratings
Operation temperature range .........................................................................................0 to + 70 °C
Storage temperature range......................................................................................... – 55 to 125 °C
Input/output voltage ............................................................................–0.5V to min (Vcc+0.5, 7.0) V
Power supply voltage...................................................................................................... – 1 to + 7 V
Power dissipation..................................................................................................................... 4.2 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
TA = 0 to 70 °C, VCC = 5 V ± 10 %
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Vcc+0.5
0.8
1)
1)
1)
1)
1)
Input high voltage
VIH
VIL
2.4
– 0.5
2.4
–
V
Input low voltage
V
Output high voltage (IOUT = – 5 mA)
Output low voltage (IOUT = 4.2 mA)
VOH
VOL
II(L)
–
V
0.4
V
Input leakage current
– 10
10
µA
(0 V < VIN < 6.5 V, all other pins = 0 V)
1)
Output leakage current
(DO is disabled, 0 V < VOUT < 5.5 V)
IO(L)
ICC1
– 10
10
µA
Average VCC supply current
(RAS, CAS, address cycling, tRC = tRC min)
-50 version
2),3),4)
–
–
–
480
440
400
mA
mA
mA
-60 version
-70 version
Standby VCC supply current
(RAS = CAS = VIH)
ICC2
ICC3
–
8
mA
Average VCC supply current
during RAS only refresh cycles
(RAS cycling, CAS = VIH, tRC = tRC min)
-50 version
2), 4)
–
–
–
480
440
400
mA
mA
mA
-60 version
-70 version
Semiconductor Group
5
HYM 322030S/GS-50/-60/-70
2M × 32-Bit
DC Characteristics1) (cont’d)
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Average VCC supply current
during fast page mode
ICC4
(RAS = VIL, CAS, address cycling,
tPC = tPC min)
2), 3), 4)
-50 version
-60 version
-70 version
–
–
–
160
140
120
mA
mA
mA
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
ICC6
–
4
mA
Average VCC supply current
during CAS-before-RAS refresh mode
(RAS, CAS cycling, tRC = tRC min)
-50 version
2), 4)
–
–
–
480
440
400
mA
mA
mA
-60 version
-70 version
Capacitance
TA = 0 to 70 °C, VCC = 5 V ± 10 %, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
40
Input capacitance (A0 to A11)
Input capacitance (RAS0, RAS2)
Input capacitance (CAS0 - CAS3)
Input capacitance (WE)
CI1
CI2
CI3
CI4
CIO
–
–
–
–
–
pF
pF
pF
pF
pF
45
45
45
I/O capacitance
(DQ0-DQ31)
25
Semiconductor Group
6
HYM 322030S/GS-50/-60/-70
2M × 32-Bit
5)6)
16F
AC Characteristics
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns
Symbol
Unit Note
Parameter
Limit Values
-60
-50
-70
min. max. min. max. min. max.
common parameters
Random read or write cycle time tRC
90
30
50
13
0
–
110
40
60
15
0
–
130
50
70
20
0
–
ns
ns
ns
ns
ns
ns
ns
ns
RAS precharge time
RAS pulse width
tRP
–
–
–
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
10k
10k
–
10k
10k
–
10k
10k
–
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
8
–
10
0
–
10
0
–
0
–
–
–
10
18
13
–
15
20
15
–
15
20
15
–
37
25
45
30
50
35
RAS to column address delay
time
ns
RAS hold time
tRSH
tCSH
tCRP
tT
13
50
5
15
60
5
–
20
70
5
–
ns
ns
ns
CAS hold time
–
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
–
–
–
3
50
32
3
50
32
3
50
32
ns
7
tREF
–
–
–
ms
Read Cycle
Access time from RAS
Access time from CAS
tRAC
tCAC
–
50
13
25
–
–
60
15
30
–
–
70
20
35
–
ns 8, 9
ns 8, 9
ns 8,10
ns
–
–
–
Access time from column address tAA
Column address to RAS lead time tRAL
–
–
–
25
0
30
0
35
0
Read command setup time
Read command hold time
tRCS
tRCH
tRRH
–
–
–
ns
0
–
0
–
0
–
ns 11
ns 11
Read command hold time
referenced to RAS
0
–
0
–
0
–
CAS to output in low-Z
tCLZ
tOFF
0
0
–
0
0
–
0
0
–
ns
8
Output buffer turn-off delay
13
15
20
ns 12
Semiconductor Group
7
HYM 322030S/GS-50/-60/-70
2M × 32-Bit
5)6)
16F
AC Characteristics (cont’d)
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns
Symbol
Unit Note
Parameter
Limit Values
-60
-50
-70
min. max. min. max. min. max.
Early Write Cycle
Write command hold time
Write command pulse width
Write command setup time
tWCH
tWP
8
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
ns
8
ns
tWCS
0
ns 15
ns
Write command to RAS lead time tRWL
Write command to CAS lead time tCWL
13
13
0
15
15
0
20
20
0
ns
Data setup time
Data hold time
tDS
tDH
ns 16
ns 16
10
10
15
Fast Page Mode Cycle
Fast page mode cycle time
CAS precharge time
tPC
tCP
35
10
–
–
40
10
–
–
45
10
–
–
ns
ns
–
–
–
Access time from CAS precharge tCPA
30
35
40
ns
7
RAS pulse width
tRAS
50
30
200k 60
200k 70
200k ns
CAS precharge to RAS Delay
tRHPC
–
35
–
40
–
ns
CAS-before-RAS Refresh Cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
10
10
5
–
–
–
–
10
10
5
–
–
–
–
10
10
5
–
–
–
–
ns
ns
ns
ns
CAS hold time
RAS to CAS precharge time
Write to RAS precharge time
10
10
10
Semiconductor Group
8
HYM 322030S/GS-50/-60/-70
2M × 32-Bit
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less
during a fast page mode cycle (tPC).
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with a load equivalent to 2 TTL loads and 100 pF.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11)Either tRCH or tRRH must be satisfied for a read cycle.
12)tOFF (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to
output voltage levels
.
13)tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics
only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high
impedance) through the entire cycle.
14)These parameters are referenced to the CAS leading edge.
Semiconductor Group
9
HYM 322030S/GS-50/-60/-70
2M × 32-Bit
Package Outline
Dimensions in mm
GLS05789
Module Package L-SIM-72-9
(Single in-Line Memory Module)
Semiconductor Group
10
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