HYM324025S-50 [INFINEON]
4M x 32-Bit EDO-DRAM Module; 4M ×32位EDO -DRAM模块
| 型号： | HYM324025S-50 |
| 厂家： | 
Infineon |
| 描述： | 4M x 32-Bit EDO-DRAM Module |
| 文件： | 总10页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4M x 32-Bit EDO-DRAM Module
HYM 324025S/GS-50/-60
• 4 194 304 words by 32-bit organized SIMM modules
for PC main memory applications
• Fast access and cycle time
50 ns access time
84 ns cycle time (-50 version)
60 ns access time
104 ns cycle time (-60 version)
• Hyper page mode (EDO) capability
20 ns cycle time (-50 version)
25 ns cycle time (-60 version)
• Single + 5 V (± 10 %) supply
• Low power dissipation
max. 5280 mW active (HYM 324025S/GS-50)
max. 4840 mW active (HYM 324025S/GS-60)
CMOS – 44 mW standby
TTL
–88 mW standby
• CAS-before-RAS refresh
RAS-only-refresh
Hidden-refresh
• 8 decoupling capacitors mounted on substrate
• All inputs, outputs and clocks fully TTL compatible
• 72 pin Single in-Line Memory Module with 22.86 mm (900 mil) height
• Utilizes eight 4Mx4-DRAMs in 300mil wide SOJ packages
• 2048 refresh cycles / 32 ms
• Optimized for use in byte-write non-parity applications
• Tin-Lead contact pads (S - version)
• Gold contact pads (GS - version)
Semiconductor Group
1
9.96
HYM 324025S/GS-50/-60
4M x 32-Bit EDO-Module
The HYM 324025S/GS-50/-60 is a 16 MByte DRAM module organized as 4 194 304 words by
32-bit in a 72-pin single-in-line package comprising eight HYB 5117405BJ 4M x 4 DRAMs in 300
mil wide SOJ-packages mounted together with eight 0.2 µF ceramic decoupling capacitors on a PC
board.
Each HYB 5117405BJ is described in the data sheet and is fully electrical tested and processed
according to SIEMENS standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 324025S/GS-50/-60 dictates the use of early write cycles.
Ordering Information
Type
Ordering Code
Package
Description
HYM 324025S-50
Q67100-Q2156
L-SIM-72-12
EDO - DRAM Module
(access time 50 ns)
HYM 324025S-60
HYM 324025GS-50
HYM 324025GS-60
Q67100-Q2157
Q67100-Q2096
L-SIM-72-12
L-SIM-72-12
L-SIM-72-12
EDO - DRAM Module
(access time 60 ns)
EDO - DRAM Module
(access time 50 ns)
EDO - DRAM Module
(access time 60 ns)
Semiconductor Group
2
HYM 324025S/GS-50/-60
4M x 32-Bit EDO-Module
Pin Configuration
Pin Names
VSS 1 DQ0
DQ16 3 DQ1
DQ17 5 DQ2
DQ18 7 DQ3
2
4
6
8
A0-A10
Address Inputs for
HYM 324025S/GS
DQ19 9 VCC 10
DQ0-DQ31
CAS0 - CAS3
RAS0, RAS2
WE
Data Input/Output
Column Address Strobe
Row Address Strobe
Read/Write Input
Power (+ 5 V)
N.C. 11 A0
12
14
A1
A3
A5
13 A2
15 A4 16
17 A6 18
A10 19 DQ4 20
DQ20 21 DQ5 22
DQ21 23 DQ6 24
DQ22 25 DQ7 26
VCC
VSS
Ground
DQ23 27 A7
N.C. 29 VCC 30
A8 31 A9 32
28
PD
Presence Detect Pin
No Connection
N.C.
N.C. 33 RAS2 34
N.C. 35 N.C. 36
N.C. 37 N.C. 38
VSS 39 CAS0 40
CAS2 41 CAS3 42
CAS1 43 RAS0 44
N.C. 45 N.C. 46
WE
47 N.C. 48
Presence Detect Pins
DQ8 49 DQ24 50
DQ9 51 DQ25 52
DQ10 53 DQ26 54
DQ11 55 DQ27 56
DQ12 57 DQ28 58
VCC 59 DQ29 60
DQ13 61 DQ30 62
DQ14 63 DQ31 64
DQ15 65 N.C. 66
PD0 67 PD1 68
PD2 69 PD3 70
N.C. 71 VSS 72
-50
-60
PD0
PD1
PD2
PD3
VSS
N.C.
VSS
VSS
VSS
N.C.
N.C.
N.C.
Semiconductor Group
3
HYM 324025S/GS-50/-60
4M x 32-Bit EDO-Module
RAS0
CAS0
CAS RAS
I/O1-I/O4
OE
DQ0-DQ3
D0
CAS RAS
I/O1-I/O4
OE
DQ4-DQ7
CAS1
D1
CAS RAS
DQ8-DQ11
I/O1-I/O4
OE
D2
CAS RAS
I/O1-I/O4
OE
DQ12-DQ15
D3
RAS2
CAS2
CAS RAS
I/O1-I/O4
OE
DQ16-DQ19
DQ20-DQ23
D4
CAS RAS
I/O1-I/O4
OE
D5
CAS3
CAS RAS
I/O1-I/O4
OE
DQ24-DQ27
DQ28-DQ31
D6
CAS RAS
I/O1-I/O4
OE
D7
D0 - D7
D0 - D7
A0 - A10
WE
VCC
C0 - C7
VSS
Block Diagram
Semiconductor Group
4
HYM 324025S/GS-50/-60
4M x 32-Bit EDO-Module
Absolute Maximum Ratings
Operation temperature range ......................................................................................... 0 to + 70 °C
Storage temperature range......................................................................................... – 55 to 125 °C
Input/output voltage ............................................................................ –0.5V to min (Vcc+0.5, 7.0) V
Power supply voltage...................................................................................................... – 1 to + 7 V
Power dissipation................................................................................................................... 6.72 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
TA = 0 to 70 °C, VCC = 5 V ± 10 %
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Vcc+0.5
0.8
Input high voltage
VIH
VIL
2.4
– 0.5
2.4
–
V
1)
Input low voltage
V
1)
1)
1)
1)
Output high voltage (IOUT = – 5 mA)
Output low voltage (IOUT = 4.2 mA)
VOH
VOL
II(L)
–
V
0.4
V
Input leakage current
– 20
20
µA
(0 V < VIN < 6.5 V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V < VOUT < 5.5 V)
IO(L)
ICC1
– 10
10
µA
1)
Average VCC supply current
(RAS, CAS, address cycling, tRC = tRC min)
50 ns - Version
2) 3) 4)
–
–
960
880
mA
mA
60 ns - Version
Standby VCC supply current
(RAS = CAS = VIH)
ICC2
ICC3
–
16
mA
Average VCC supply current
during RAS only refresh cycles
(RAS cycling, CAS = VIH, tRC = tRC min)
50 ns - Version
2) 4)
–
–
960
880
mA
mA
60 ns - Version
DC Characteristics1) (contd’ )
Semiconductor Group
5
HYM 324025S/GS-50/-60
4M x 32-Bit EDO-Module
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Average VCC supply current
ICC4
during hyper page mode (EDO)
(RAS = VIL, CAS, address cycling,
tHPC = tHPC min)
2) 3) 4)
50 ns - Version
60 ns - Version
–
–
560
440
mA
mA
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
ICC6
–
8
mA
1)
Average VCC supply current
during CAS-before-RAS refresh mode
(RAS, CAS cycling, tRC = tRC min)
2) 4)
50 ns - Version
60 ns - Version
–
–
960
880
mA
mA
Capacitance
TA = 0 to 70 °C, VCC = 5 V ± 10 %, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
75
Input capacitance (A0 to A10,WE)
Input capacitance (RAS0, RAS2)
Input capacitance (CAS0 - CAS3)
CI1
CI2
CI3
CIO
–
–
–
–
pF
pF
pF
pF
45
25
I/O capacitance
(DQ0-DQ31)
15
Semiconductor Group
6
HYM 324025S/GS-50/-60
4M x 32-Bit EDO-Module
5)6)
AC Characteristics
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
-50 -60
min. max. min. max.
common parameters
Random read or write cycle time
RAS precharge time
tRC
84
30
50
8
–
104
40
60
10
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRP
–
–
RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tT
10k
10k
–
10k
10k
–
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
0
8
–
10
0
–
0
–
–
8
–
10
14
12
15
50
5
–
12
10
13
40
5
37
25
45
30
–
CAS hold time
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
–
–
1
50
32
1
50
32
ns
7
tREF
–
–
ms
Read Cycle
Access time from RAS
tRAC
tCAC
tAA
–
50
13
25
–
–
60
15
30
–
ns
ns
ns
ns
ns
ns
ns
8, 9
8, 9
8,10
Access time from CAS
–
–
Access time from column address
Column address to RAS lead time
Read command setup time
Read command hold time
–
–
tRAL
tRCS
tRCH
tRRH
25
0
30
0
–
–
0
–
0
–
11
11
Read command hold time referenced to
RAS
0
–
0
–
CAS to output in low-Z
tCLZ
tOFF
0
0
–
0
0
–
ns
ns
8
Output buffer turn-off delay
13
15
12
Semiconductor Group
7
HYM 324025S/GS-50/-60
4M x 32-Bit EDO-Module
5)6)
AC Characteristics (contd’ )
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
-50 -60
min. max. min. max.
Early Write Cycle
Write command hold time
Write command pulse width
Write command setup time
Write command to RAS lead time
Write command to CAS lead time
Data setup time
tWCH
tWP
8
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
ns
ns
8
tWCS
tRWL
tCWL
tDS
0
ns
ns
ns
ns
ns
13
13
13
0
15
15
0
14
14
Data hold time
tDH
8
10
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time
CAS precharge time
tHPC
tCP
20
8
–
25
10
–
–
ns
ns
ns
ns
–
–
Access time from CAS precharge
Output data hold time
tCPA
tCOH
tRAS
tRHCP
–
27
–
32
–
7
5
5
RAS pulse width in hyper page mode
CAS precharge to RAS Delay
50
27
200k 60
200k ns
–
32
–
ns
CAS before RAS Refresh Cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
tWRH
10
10
5
–
–
–
–
–
10
10
5
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
RAS to CAS precharge time
Write to RAS precharge time
Write hold time referenced to RAS
10
10
10
10
Semiconductor Group
8
HYM 324025S/GS-50/-60
4M x 32-Bit EDO-Module
Notes:
1) All voltages are referenced to VSS.
Vil may undershoot to -2.0 V for pulse width of less than or equal to 4 ns. Pulse width is measured at 50%
points with amplitude measured peak to the DC reference.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during
a hyper page mode (EDO) cycle.
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 2 ns.
7) VIH
and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
(min.)
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined
by the latter of tRAC, tCAC, tAA,tCPA . tCAC is measured from tristate.
.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point
only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC
.
10) Operation within the tRAD (max. limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
)
only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA
.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to
output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
13) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only.
If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance)
through the entire cycle.
14) These parameters are referenced to the CAS leading edge.
Semiconductor Group
9
HYM 324025S/GS-50/-60
4M x 32-Bit EDO-Module
Package Outline
107.95
101.19
3.38
5.28 max
+/- 0.05
1.27
R 1.57
+/- 0.05
2.03
6.35
6.35
+/- 0.05
95.25
+0.10
-0.08
1.27
Detail of Contacts
+/- 0.05
1.04
1.27
Tolerances : +/- 0.13 unless otherwise specified
GLS05835
Module Package, L-SIM-72-12
(Single in-Line Memory Module)
Semiconductor Group
10
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