HYR186420G-711 [INFINEON]
Rambus DRAM Module, 64MX18, CMOS, RIMM-184;
| 型号： | HYR186420G-711 |
| 厂家： | 
Infineon |
| 描述： | Rambus DRAM Module, 64MX18, CMOS, RIMM-184 动态存储器 |
| 文件： | 总14页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYR16xx30/HYR18xx20G
Rambus RIMM Modules
(with 128/144 Mb RDRAMs)
Direct RDRAM RIMM Modules
Perliminary Information
Rev. 0.9
Overview
Form Factor
The Direct Rambus™ RIMM™ module is a general
purpose high-performance memory subsystem suitable
for use in a broad range of applications including
computer memory, personal computers, workstations,
and other applications where high bandwidth and low
latency are required.
The Rambus RIMM modules are offered in a 184-pad
1mm edge connector pad pitch form factor suitable for
either 184 or 168 contact RIMM connectors. The RIMM
module is suitable for desktop and other system appli-
cations. Figure 1 shows an eight device Rambus RIMM
module without heat spreader.
The 128 MB Direct Rambus RIMM module consists of
eight 128Mb/ 144Mb Direct Rambus DRAM (Direct
RDRAM™) devices. These are extremely high-speed
CMOS DRAMs organized as 8M words by 16 or 18
bits. The use of Rambus Signaling Level (RSL) tech-
nology permits 600MHz to 800MHz transfer rates while
using conventional system and board design technolo-
gies. Direct RDRAM devices are capable of sustained
data transfers at 1.25 ns per two bytes (10ns per
sixteen bytes).
Features
n
n
n
High speed 800, 711 & 600 MHz RDRAM storage
184 edge connector pads with 1mm pad spacing
Maximum module PCB size: 133.5mm x 34.9mm x
1.37mm (5.21” x 1.36” x 0.05”)
n
Each RDRAM has 32 banks, for a total of
256banks on each 128MB module
The RDRAM architecture enables the highest
sustained bandwidth for multiple, simultaneous,
randomly addressed, memory transactions. The sepa-
rate control and data buses with independent row and
column control yield over 95% bus efficiency. The
RDRAM's 32-bank architecture supports up to four
simultaneous transactions per device.
n
n
n
n
n
Gold plated edge connector pad contacts
Serial Presence Detect (SPD) support
Operates from a 2.5 volt supply (±5%)
Low power and powerdown self refresh modes
Separate Row and Column buses for higher effi-
ciency
Last Modified on 7/13/99
1
HYR16xx30G/HYR18xx20G
Rambus RIMM Modules
Part Number Designators
I/O Freq.
MHz
# of
RDRAMs
RDRAM
density
Organization
Capacity
Part Designator
64MB/72MB:
32Mb x16
32Mb x16
32Mb x16
32Mb x16
32Mb x18
32Mb x18
32Mb x18
32Mb x18
96MB/108MB
48Mb x16
48Mb x16
48Mb x16
48Mb x16
48Mb x18
48Mb x18
48Mb x18
48Mb x18
128MB/144MB:
64Mb x16
64Mb x16
64Mb x16
64Mb x16
64Mb x18
64Mb x18
64Mb x18
64Mb x18
256MB/288MB:
128Mb x16
128Mb x16
128Mb x16
128Mb x16
128Mb x18
128Mb x18
128Mb x18
128Mb x18
64MB
64MB
64MB
64MB
72MB
72MB
72MB
72MB
600
711
800
800
600
711
800
800
HYR163230G-653
HYR163230G-745
HYR163230G-845
HYR163230G-840
HYR183220G-653
HYR183220G-745
HYR183220G-845
HYR183220G-840
4
4
4
4
4
4
4
4
128Mb
128Mb
128Mb
128Mb
144Mb
144Mb
144Mb
144Mb
96MB
96MB
600
711
800
800
600
711
800
800
HYR164830G-653
HYR164830G-745
HYR164830G-845
HYR164830G-840
HYR184820G-653
HYR184820G-745
HYR184820G-845
HYR184820G-840
6
6
6
6
6
6
6
6
128Mb
128Mb
128Mb
128Mb
144Mb
144Mb
144Mb
144Mb
96MB
96MB
108MB
108MB
108MB
108MB
128MB
128MB
128MB
128MB
144MB
144MB
144MB
144MB
600
711
800
800
600
711
800
800
HYR166430G-653
HYR166430G-711
HYR166430G-845
HYR166430G-840
HYR186420G-653
HYR186420G-711
HYR186420G-845
HYR186420G-840
8
8
8
8
8
8
8
8
128Mb
128Mb
128Mb
128Mb
144Mb
144Mb
144Mb
144Mb
256MB
256MB
256MB
256MB
288MB
288MB
288MB
288MB
600
711
800
800
600
711
800
800
HYR1612830G-653
HYR1612830G-745
HYR1612830G-845
HYR1612830G-840
HYR1812820G-653
HYR1812820G-745
HYR1812820G-845
HYR1812820G-840
16
16
16
16
16
16
16
16
128Mb
128Mb
128Mb
128Mb
144Mb
144Mb
144Mb
144Mb
Page 2
Last Modified on 7/13/99
HYR16xx30G/HYR18xx20G
Rambus RIMM Modules
Table 1: Module Pad Number and Signal Names
Pad
A1
Signal Name
Pad
B1
Signal Name
Pad
Signal Name
Pad
B47
Signal Name
Gnd
Gnd
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
NC
NC
A2
LDQA8
Gnd
B2
LDQA7
Gnd
NC
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
NC
A3
B3
NC
NC
A4
LDQA6
Gnd
B4
LDQA5
Gnd
NC
NC
A5
B5
Vref
Vref
A6
LDQA4
Gnd
B6
LDQA3
Gnd
Gnd
Gnd
A7
B7
SCL
SA0
A8
LDQA2
Gnd
B8
LDQA1
Gnd
Vdd
Vdd
A9
B9
SDA
SA1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
LDQA0
Gnd
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
LCFM
Gnd
SVdd
SWP
SVdd
SA2
LCTMN
Gnd
LCFMN
Gnd
Vdd
Vdd
RSCK
Gnd
RCMD
Gnd
LCTM
Gnd
NC
Gnd
RDQB7
Gnd
RDQB8
Gnd
NC
LROW2
Gnd
Gnd
RDQB5
Gnd
RDQB6
Gnd
LROW1
Gnd
LROW0
Gnd
RDQB3
Gnd
RDQB4
Gnd
LCOL4
Gnd
LCOL3
Gnd
RDQB1
Gnd
RDQB2
Gnd
LCOL2
Gnd
LCOL1
Gnd
RCOL0
Gnd
RDQB0
Gnd
LCOL0
Gnd
LDQB0
Gnd
RCOL2
Gnd
RCOL1
Gnd
LDQB1
Gnd
LDQB2
Gnd
RCOL4
Gnd
RCOL3
Gnd
LDQB3
Gnd
LDQB4
Gnd
RROW1
Gnd
RROW0
Gnd
LDQB5
Gnd
LDQB6
Gnd
NC
RROW2
Gnd
LDQB7
Gnd
LDQB8
Gnd
Gnd
RCTM
Gnd
NC
LSCK
Vcmos
SOUT
Vcmos
NC
LCMD
Vcmos
SIN
Gnd
RCTMN
Gnd
RCFMN
Gnd
Vcmos
NC
RDQA0
Gnd
RCFM
Gnd
Gnd
Gnd
RDQA2
Gnd
RDQA1
Gnd
NC
NC
Vdd
Vdd
RDQA4
Gnd
RDQA3
Gnd
Vdd
Vdd
NC
NC
RDQA6
Gnd
RDQA5
Gnd
NC
NC
NC
NC
RDQA8
Gnd
RDQA7
Gnd
NC
NC
Last Modified on 7/13/99
Page 3
HYR16xx30G/HYR18xx20G
Rambus RIMM Modules
Table 2: Module Connector Pad Description
Signal
Module Connector Pads
I/O
Type
Description
Gnd
A1, A3, A5, A7, A9, A11, A13, A15,
A17, A19, A21, A23, A25, A27, A29,
A31, A33, A39, A52, A60, A62, A64,
A66, A68, A70, A72, A74, A76, A78,
A80, A82, A84, A86, A88, A90, A92,
B1, B3, B5, B7, B9, B11, B13, B15,
B17, B19, B21, B23, B25, B27, B29,
B31, B33, B39, B52, B60, B62, B64,
B66, B68, B70, B72, B74, B76, B78,
B80, B82, B84, B86, B88, B90, B92
Ground reference for RDRAM core and interface. 72
PCB connector pads.
LCFM
B10
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
I
I
I
I
I
I
RSL
RSL
LCFMN
LCMD
B12
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity.
B34
Serial Command used to read from and write to the con-
trol registers. Also used for power management.
V
CMOS
LCOL4..
LCOL0
A20, B20, A22, B22, A24
Column bus. 5-bit bus containing control and address
information for column accesses.
RSL
LCTM
A14
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
RSL
RSL
LCTMN
A12
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
LDQA8..
LDQA0
A2, B2, A4, B4, A6, B6, A8, B8, A10
Data bus A. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. LDQA8 is
non-functional on modules with x16 RDRAM devices
I/O
I/O
RSL
LDQB8..
LDQB0
B32, A32, B30, A30, B28, A28, B26,
A26, B24
Data bus B. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. LDQB8 is
non-functional on modules with x16 RDRAM devices.
RSL
RSL
LROW2..
LROW0
B16, A18, B18
A34
Row bus. 3-bit bus containing control and address infor-
mation for row accesses.
I
I
LSCK
Serial Clock input. Clock source used to read from and
write to the RDRAM control registers.
V
CMOS
NC
A16, B14, A38, B38, A40, B40, A77,
B79
These pads are not connected. These 8 connector pads
are reserved for future use.
NC
A43, B43, A44, B44, A45, B45, A46,
B46, A47, B47, A48, B48, A49, B49,
A50, B50
These pads are not connected. These 16 connector pads
are reserved for future use. The 168 contact RIMM con-
nector does not connect to these PCB pads
RCFM
B83
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
I
I
RSL
RSL
RCFMN
B81
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity.
Page 4
Last Modified on 7/13/99
HYR16xx30G/HYR18xx20G
Rambus RIMM Modules
Signal
Module Connector Pads
I/O
I
Type
Description
RCMD
B59
Serial Command Input used to read from and write to
the control registers. Also used for power management.
V
CMOS
RCOL4..
RCOL0
A73, B73, A71, B71, A69
Column bus. 5-bit bus containing control and address
information for column accesses.
I
I
I
RSL
RCTM
A79
A81
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
RSL
RSL
RCTMN
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
RDQA8..
RDQA0
A91, B91, A89, B89, A87, B87, A85,
B85, A83
Data bus A. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. RDQA8 is
non-functional on modules with x16 RDRAM devices.
I/O
I/O
RSL
RDQB8..
RDQB0
B61, A61, B63, A63, B65, A65, B67,
A67, B69
Data bus B. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. RDQB8 is
non-functional on modules with x16 RDRAM devices.
RSL
RSL
RROW2.. B77, A75, B75
RROW0
Row bus. 3-bit bus containing control and address infor-
mation for row accesses.
I
I
RSCK
A59
Serial Clock input. Clock source used to read from and
write to the RDRAM control registers.
V
CMOS
SA0
SA1
SA2
SCL
SDA
SIN
B53
B55
B57
A53
A55
B36
Serial Presence Detect Address 0.
Serial Presence Detect Address 1.
Serial Presence Detect Address 2.
Serial Presence Detect Clock.
I
SV
DD
DD
DD
DD
DD
I
I
SV
SV
SV
SV
I
Serial Presence Detect Data (Open Collector I/ O).
I/O
Serial I/ O for reading from and writing to the control
registers. Attaches to SIO0 of the first RDRAM on the
module.
I/O
I/O
V
V
CMOS
CMOS
SOUT
A36
Serial I/ O for reading from and writing to the control
registers. Attaches to SIO1 of the last RDRAM on the
module.
SV
A56, B56
SPD Voltage. Used for signals SCL, SDA, SWE, SA0, SA1
and SA2.
DD
SWP
A57
Serial Presence Detect Write Protect (active high). When
low, the SPD can be written as well as read.
I
SV
DD
V
A35, B35, A37, B37
CMOS I/ O Voltage. Used for signals CMD, SCK, SIN,
SOUT.
CMOS
Vdd
Vref
A41, A42, A54, A58, B41, B42, B54,
B58
Supply voltage for the RDRAM core and interface logic.
A51, B51
Logic threshold reference voltage for RSL signals.
Last Modified on 7/13/99
Page 5
HYR16xx30G/HYR18xx20G
Rambus RIMM Modules
RIMM Module Functional Diagram
Vdd
2 per
RDRAM
0.1 µF
U1
SIO1
SIO0
SCK
CMD
VREF
Direct RDRAM (128/144Mb)
GND
Vref
1 per
2 RDRAMs
puls one
near
U2
SIO1
SIO0
SCK
CMD
VREF
Connector
Direct RDRAM (128/144Mb)
Direct RDRAM (128/144Mb)
0.1 µF
GND
VCMOS
SIO1
SIO0
SCK
CMD
VREF
1 per
2 RDRAMs
0.1 µF
U3
GND
.
.
.
SIO1
SIO0
SCK
CMD
VREF
UN
Direct RDRAM (128/144Mb)
Module
N
Capacity
64MB / 72MB
4
96MB / 108MB
128MB / 144MB
6
8
16
256MB/288MB
SVdd
Note 1: Rambus Channel signals form a loop through
the RIMM module, with the exception of the SIO
chain.
Note 2: See Serial Presence Detection Specification
for information on the SPD device and its contents.
Serial Presence Detect
Vcc
SVdd
SCL
SCL
A0
SDA
SDA
0.1µF
SWP
A1
Gnd
SA[0:2]
Page 6
Last Modified on 7/13/99
HYR16xx30G/HYR18xx20G
Rambus RIMM Modules
Table 3: Module Connector Pad Description
Signal
Module Connector Pads
I/O
Type
Description
Gnd
A1, A3, A5, A7, A9, A11, A13, A15,
A17, A19, A21, A23, A25, A27, A29,
A31, A33, A39, A52, A60, A62, A64,
A66, A68, A70, A72, A74, A76, A78,
A80, A82, A84, A86, A88, A90, A92,
B1, B3, B5, B7, B9, B11, B13, B15,
B17, B19, B21, B23, B25, B27, B29,
B31, B33, B39, B52, B60, B62, B64,
B66, B68, B70, B72, B74, B76, B78,
B80, B82, B84, B86, B88, B90, B92
Ground reference for RDRAM core and interface. 72
PCB connector pads.
LCFM
B10
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
I
I
I
I
I
I
RSL
RSL
LCFMN
LCMD
B12
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity.
B34
Serial Command used to read from and write to the con-
trol registers. Also used for power management.
V
CMOS
LCOL4..
LCOL0
A20, B20, A22, B22, A24
Column bus. 5-bit bus containing control and address
information for column accesses.
RSL
LCTM
A14
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
RSL
RSL
LCTMN
A12
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
LDQA8..
LDQA0
A2, B2, A4, B4, A6, B6, A8, B8, A10
Data bus A. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. LDQA8 is
non-functional on modules with x16 RDRAM devices
I/O
I/O
RSL
LDQB8..
LDQB0
B32, A32, B30, A30, B28, A28, B26,
A26, B24
Data bus B. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. LDQB8 is
non-functional on modules with x16 RDRAM devices.
RSL
RSL
LROW2..
LROW0
B16, A18, B18
A34
Row bus. 3-bit bus containing control and address infor-
mation for row accesses.
I
I
LSCK
Serial Clock input. Clock source used to read from and
write to the RDRAM control registers.
V
CMOS
NC
A16, B14, A38, B38, A40, B40, A77,
B79
These pads are not connected. These 8 connector pads
are reserved for future use.
NC
A43, B43, A44, B44, A45, B45, A46,
B46, A47, B47, A48, B48, A49, B49,
A50, B50
These pads are not connected. These 16 connector pads
are reserved for future use. The 168 contact RIMM con-
nector does not connect to these PCB pads
RCFM
B83
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
I
I
RSL
RSL
RCFMN
B81
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity.
Last Modified on 7/13/99
Page 7
HYR16xx30G/HYR18xx20G
Rambus RIMM Modules
Signal
Module Connector Pads
I/O
I
Type
Description
RCMD
B59
Serial Command Input used to read from and write to
the control registers. Also used for power management.
V
CMOS
RCOL4..
RCOL0
A73, B73, A71, B71, A69
Column bus. 5-bit bus containing control and address
information for column accesses.
I
I
I
RSL
RCTM
A79
A81
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
RSL
RSL
RCTMN
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
RDQA8..
RDQA0
A91, B91, A89, B89, A87, B87, A85,
B85, A83
Data bus A. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. RDQA8 is
non-functional on modules with x16 RDRAM devices.
I/O
I/O
RSL
RDQB8..
RDQB0
B61, A61, B63, A63, B65, A65, B67,
A67, B69
Data bus B. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. RDQB8 is
non-functional on modules with x16 RDRAM devices.
RSL
RSL
RROW2.. B77, A75, B75
RROW0
Row bus. 3-bit bus containing control and address infor-
mation for row accesses.
I
I
RSCK
A59
Serial Clock input. Clock source used to read from and
write to the RDRAM control registers.
V
CMOS
SA0
SA1
SA2
SCL
SDA
SIN
B53
B55
B57
A53
A55
B36
Serial Presence Detect Address 0.
Serial Presence Detect Address 1.
Serial Presence Detect Address 2.
Serial Presence Detect Clock.
I
SV
DD
DD
DD
DD
DD
I
I
SV
SV
SV
SV
I
Serial Presence Detect Data (Open Collector I/ O).
I/O
Serial I/ O for reading from and writing to the control
registers. Attaches to SIO0 of the first RDRAM on the
module.
I/O
I/O
V
V
CMOS
CMOS
SOUT
A36
Serial I/ O for reading from and writing to the control
registers. Attaches to SIO1 of the last RDRAM on the
module.
SV
A56, B56
SPD Voltage. Used for signals SCL, SDA, SWE, SA0, SA1
and SA2.
DD
SWP
A57
Serial Presence Detect Write Protect (active high). When
low, the SPD can be written as well as read.
I
SV
DD
V
A35, B35, A37, B37
CMOS I/ O Voltage. Used for signals CMD, SCK, SIN,
SOUT.
CMOS
Vdd
Vref
A41, A42, A54, A58, B41, B42, B54,
B58
Supply voltage for the RDRAM core and interface logic.
A51, B51
Logic threshold reference voltage for RSL signals.
Page 8
Last Modified on 7/13/99
HYR16xx30G/HYR18xx20G
Rambus RIMM Modules
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
V
Voltage applied to any RSL or CMOS signal pad with respect to
Gnd
- 0.3
V
V
+ 0.3
V
I,ABS
DD
V
Voltage on VDD with respect to Gnd
Storage temperature
- 0.5
- 50
+ 1.0
V
DD,ABS
STORE
DD
T
100
°C
DC Recommended Electrical Conditions
Symbol
Parameter and Conditions
Min
Max
Unit
V
V
Supply voltage
2.50 - 0.13
2.50 + 0.13
DD
V
CMOS I/ O power supply at pad for 2.5V controllers:
CMOS I/ O power supply at pad for 1.8V controllers:
2.5 - 0.13
1.8 - 0.1
2.5 + 0.25
1.8 + 0.2
V
V
CMOS
V
Reference voltage
1.4 - 0.2
1.4 + 0.2
V
V
REF
V
RSL input low voltage
RSL input high voltage
CMOS input low voltage
CMOS input high voltage
V
V
- 0.5
V
V
- 0.2
REF
IL
REF
V
+ 0.2
+ 0.5
REF
V
IH
REF
V
- 0.3
0.5V - 0.25
CMOS
V
IL,CMOS
V
0.5V
V
+ 0.25
V
+ 0.7
V
IH,CMOS
CMOS
CMOS
V
CMOS output low voltage @ I
= 1mA
0.3
V
OL,CMOS
OL,CMOS
V
CMOS output high voltage @ I
= -0.25mA
- 0.3
V
OH,CMOS
OH,CMOS
CMOS
a
a
a
a
I
V
current @ V
REF,MAX
-10 x no. RDRAMs
-10 x no. RDRAMs
-10.0
10 x no. RDRAMs
10 x no. RDRAMs
10.0
µA
µA
µA
REF
REF
I
CMOS input leakage current @ (0 ≤ V
CMOS input leakage current @ (0 ≤ V
≤ V
≤ V
)
)
SCK,CMD
CMOS
CMOS
DD
DD
I
SIN,SOUT
a. The table below shows the number of 128Mb or 144Mb RDRAM devices contained in a RIMM module of listed storage capacity.
RIMM Module Capacity:
64/72MB
96/108MB
128/144MB
256/288MB
Number of 128Mb or 144Mb RDRAM devices:
4
6
8
16
Last Modified on 7/13/99
Page 9
HYR16xx30G/HYR18xx20G
Rambus RIMM Modules
AC Electrical Specifications
Symbol
Parameter and Conditions
Min
Typ
Max
Unit
Z
Module Impedance
25.2
28
30.8
Ω
T
Propagation Delay, all RSL signals
-
See
Table
PD
ns
ps
ps
%
a
∆T
∆T
Propagation delay variation of RSL signals with respect to an average
-10
-100
10
PD
b
clock delay
Propagation delay variation of SCK and CMD signals with respect to an
100
PD-CMOS
b
average clock delay
V / V
Attenuation Limit
See
Table
α
IN
a
a
a
V
V
/ V
Forward crosstalk coefficient (300ps input rise time @ 20%-80%)
Backward crosstalk coefficient (300ps input rise time @ 20%-80%)
See
Table
XF
IN
%
/ V
See
Table
XB
IN
%
a. Table below lists parameters and specifications for different storage capacity RIMM modules that use 128Mb or 144Mb RDRAM devices.
b. Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN).
AC Electrical Specifications for RIMM Modules
RIMM Module Capacity:
No. of 128/144Mb RDRAMs:
64/72MB
4
96/108MB
6
128/144MB
8
256/288MB
16
Symbol
Unit
Parameter and Condition for -800 to-600
RIMM modules
Max
Max
Max
Max
Propagation Delay, all RSL signals -800
Propagation Delay, all RSL signals -600
Attenuation Limit -800
1.25
1.25
12
8
TBD
TBD
TBD
TBD
TBD
1.50
1.60
16
2.06
2.10
25
ns
ns
%
%
%
T
PD
V / V
α
IN
Attenuation Limit -600
10
21
Forward crosstalk coefficient (300ps input
rise time @ 20%-80%) -800
2
4
8
V
/ V
IN
XF
Forward crosstalk coefficient (300ps input
rise time @ 20%-80%) -600
2
TBD
TBD
TBD
4
8
%
%
%
Backward crosstalk coefficient (300ps input
rise time @ 20%-80%) -800
1.5
1.5
2.0
2.0
2.5
2.5
V
/ V
XB
IN
Backward crosstalk coefficient (300ps input
rise time @ 20%-80%) -600
DC Resistance Limit
DC Resistance Limit
0.6
0.6
TBD
TBD
0.8
1.2
1.2
Ω
Ω
R
DC
10.8
Page 10
Last Modified on 7/13/99
HYR16xx30G/HYR18xx20G
Rambus RIMM Modules
RIMM Module Current Profile
RIMM Module Capacity:
No. of 128/144Mb RDRAMs:
64/72MB
4
96/108MB
6
128/144MB
8
256/288MB
16
I
Unit
DD
a
RIMM module power conditions
Max
Max
Max
Max
I
I
I
One RDRAM in Read, balance in NAP
mode
587
TBD
604
637
mA
mA
mA
DD1
DD2
DD3
One RDRAM in Read, balance in
Standby mode, no commands
878
TBD
TBD
1282
1611
2090
2795
One RDRAM in Read, balance in
Active mode, no commands
1019
a. Specifications in this table are maximum guidelines. Actual power will depend on individual memory controller and usage pat-
terns.
Last Modified on 7/13/99
Page 11
HYR16xx30G/HYR18xx20G
Rambus RIMM Modules
A
B
E
C
C
Pad A-1
Pad A-92
D
Dimension
Description
Min
Nom
Max
Unit
A
B
C
D
E
F
PCB length
133.20
5.244
133.35
5.250
133.50
5.256
mm
in
PCB height
34.93
1.375
mm
in
Center-center pad width from pad A1 to A46, A47 to
A92, B1 to B46 or B47 to B92
45.00
1.770
mm
in
Spacing from PCB left edge to connector key notch
55.25
2.175
mm
in
Spacing from contact pad PCB edge to side edge
retainer notch
17.78
0.700
mm
in
PCB thickness
1.17
0.046
1.27
0.050
1.37
0.054
mm
in
G
Heat spreader thickness from PCB surface (one side) to
heat spreader top surface
3.00
0.118
mm
in
Figure 1: RIMM Module PCB Physical Description
Page 12
Last Modified on 7/13/99
HYR16xx30G/HYR18xx20G
Rambus RIMM Modules
a label is shown attached to the right-center side of the
RIMM module’s heat spreader. RIMM modules without
heat spreaders will have a similar label attached to the
lower right side of the RIMM module PCB. This label is
in addition to any vendor specific label or marking.
Information contained in this area is specific for the
RIMM module and provides RDRAM information
without requiring removal of the RIMM module’s heat
spreader.
Standard RIMM Module Marking
The RIMM modules available from RIMM module
manufacturers will be marked per Figure 2 below. This
industry standard marking will help OEMs and users
identify the Rambus RIMM modules when used in
specific system applications. This will assist OEMs or
users to specify and correctly verify if the correct RIMM
modules are installed in their systems. In the diagram,
A
C
E
B
D
Marked Text
Label Field
Description
Unit
A
B
C
Module Mem-
ory Capacity
Number of 8-bit or 9-bit MBytes of RDRAM
storage in RIMM module
128MB, 96MB,
64MB, 48MB, 32MB
MBytes
Number of
RDRAMs
Number of RDRAM devices contained in the
RIMM module
/ 16, / 12, / 8, / 6, / 4 RDRAM
devices
ECC Support
Indicates whether the RIMM module supports
8-bit (no ECC) or 9-bit (ECC) Bytes
blank = 8-bit Byte
ECC = 9-bit Byte
D
E
Reserved
Reserved for future use
blank
Memory Speed
Data transfer speed for RDRAM RIMM module 800, 711, 600
MHz
Figure 2: Standard RIMM Module Marking
Last Modified on 7/13/99
Page 13
HYR16xx30G/HYR18xx20G
Rambus RIMM Modules
Page 14
Last Modified on 7/13/99
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