HYS64D64020GU-8-X_技术文档

HYS64/72D32000GU / HYS64/72D64020GU

2.5 V 184-pin Unbuffered DDR-I SDRAM Modules

256MB & 512MB Modules

Preliminary Datasheet Rev. 0.9

• 184-pin Unbuffered 8-Byte Dual-In-Line

DDR-I SDRAM non-parity and ECC-Modules

for PC and Server main memory applications

• Auto Refresh (CBR) and Self Refresh

• All inputs and outputs SSTL_2 compatible

• Serial Presence Detect with E²PROM

• One bank 32M × 64, 32M x 72 and two bank

64M x 64, 64M × 72 organization

• Jedec standard MO-206a form factor:

133.35 mm × 31.75 mm × 4.00 mm

• JEDEC standard Double Data Rate

Synchronous DRAMs (DDR-I SDRAM)

Single + 2.5 V (± 0.2 V) power supply

• Jedec standard reference layout

• Gold plated contacts

• Built with 256Mbit DDR-I SDRAMs in 66-

Lead TSOPII package

• Programmable CAS Latency, Burst Length,

and Wrap Sequence (Sequential &

Interleave)

• Performance:

-7

-7.5

-8

Unit

Component Speed Grade

Module Speed Grade

PC266A PC266B PC200

PC2100 PC2100 PC1600

f_CK

Clock Frequency (max.) @ CL = 2.5

Clock Frequency (max.) @ CL = 2

143

133

100

125

100

MHz

The HYS64/72D000GU are industry standard 184-pin 8-byte Dual in-line Memory Modules

(DIMMs) organized as 32M × 64 and 64M × 64 for non-parity and 32M x 72 and 64M x 72 for ECC

main memory applications. The memory array is designed with Double Data Rate Synchronous

DRAMs (2.5V DDR-I). A variety of decoupling capacitors are mounted on the PC board. The DIMMs

feature serial presence detect based on a serial E²PROM device using the 2-pin I²C protocol. The

first 128 bytes are programmed with configuration data and the second 128 bytes are available to

the customer.

Preliminary Datasheet

1

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

Ordering Information

Type

Compliance Code

Description

SDRAM

Technology

PC266A:

one bank 256 MB Reg. DIMM

one bank 256 MB Reg. ECC-DIMM

two banks 512 MB Reg. DIMM

HYS64D32000GU-7

HYS72D32000GU-7

HYS64D64020GU-7

HYS72D64020GU-7

PC266B:

PC266A-20330-B1

PC266A-20330-A1

256 MBit

256 Mbit

256 MBit

two banks 512 MB Reg. ECC-DIMM 256 MBit

one bank 256 MB Reg. DIMM

one bank 256 MB Reg. ECC-DIMM

two banks 512 MB Reg. DIMM

HYS64D32000GU-7.5

HYS72D32000GU-7.5

HYS64D64020GU-7.5

HYS72D64020GU-7.5

PC200R:

PC266B-25330-B1

PC266B-25330-A1

256 MBit

256 Mbit

256 MBit

two banks 512 MB Reg. ECC-DIMM 256 MBit

one bank 256 MB Reg. DIMM

one bank 256 MB Reg. ECC-DIMM

two banks 512 MB Reg. DIMM

HYS64D32000GU-8

HYS72D32000GU-8

HYS64D64020GU-8

HYS72D64020GU-8

PC200-20220-B1

PC200-20220-A1

256 MBit

256 Mbit

256 MBit

two banks 512 MB Reg. ECC-DIMM 256 MBit

Note: All part numbers end with a place code (not shown), designating the silicon-die revision.

Reference information available on request.

Example: HYS 72D32000GU-8-A, indicating Rev.A die are used for SDRAM components.

Preliminary Datasheet

2

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

Pin Definitions and Functions

A0 - A12

BA0, BA1

DQ0 - DQ63

CB0 - CB7

RAS

Address Inputs

Bank Selects

S0, S1

V_DD

Chip Selects

Power (+ 2.5 V)

Ground

Data Input/Output

V_SS

Check Bits (x72 organization only) V_DDQ

I/O Driver power supply

VDD Indentification flag

I/O reference supply

Row Address Strobe

Column Address Strobe

Read/Write Input

V_DDID

V_REF

CAS

WE

V_DDSPD

Serial EEPROM power

supply

CKE0 - CKE1

DQS0 - DQS8

CLK0 - CLK2,

CLK0 - CLK2

DM0 - DM8

Clock Enable

SCL

Serial bus clock

Serial bus data line

slave address select

no connect

SDRAM low data strobes

SDRAM clock (positive lines)

SDRAM clock (negative lines)

SDRAM low data mask/

SDA

SA0 - SA2

NC

DQS9 - DQS17 high data strobes

Address Format

Density Organization Memory SDRAMs # of

# of row/bank/ Refresh Period Interval

Banks

SDRAMs columns bits

256 MB 32M x 64

256 MB 32M x 72

512 MB 64M × 64

512 MB 64M × 72

1

2

32M x 8

8

13/2/10

8k

64 ms 7.8 µs

9

16

18

Preliminary Datasheet

3

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

Pin Configuration

Frontside

Backside

PIN#

1

Symbol

VREF

DQ0

PIN#

48

Symbol

A0

PIN#

93

Symbol

VSS

PIN#

140

141

142

143

144

Symbol

NC / DM8/DQS17

A10

2

49

NC / CB2

VSS

94

DQ4

3

VSS

50

95

DQ5

NC / CB6

VDDQ

NC / CB7

KEY

4

DQ1

51

NC / CB3

BA1

96

VDDQ

DM0/DQS9

DQ6

5

DQS0

DQ2

52

97

6

KEY

98

7

VDD

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

99

DQ7

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

VSS

8

DQ3

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

VSS

DQ36

DQ37

VDD

9

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

NC

VSS

A13

DM4/DQS13

DQ38

DQ39

VSS

DQ8

VDDQ

DQ12

DQ13

DM1/DQS10

VDD

DQ9

BA0

DQS1

VDDQ

CLK1

VSS

DQ35

DQ40

VDDQ

WE

DQ44

RAS

DQ14

DQ15

CKE1

VDDQ

NC (BA2)

DQ20

A12

DQ45

VDDQ

S0

DQ41

CAS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

S1

DQS5

DQ42

DQ43

VDD

DM5/DQS14

VSS

DQ46

DQ47

NC

VSS

NC

DQ21

A11

DQ48

DQ49

VSS

VDDQ

DQ52

DQ53

NC

A9

DM2/DQS11

VDD

DQ18

A7

CLK2

VDDQ

DQS6

DQ50

DQ51

VSS

DQ22

A8

VDDQ

DQ19

A5

VDD

DQ23

VSS

DM6/DQS15

DQ54

DQ55

VDDQ

NC

DQ24

VSS

A6

DQ28

DQ29

VDDQ

DM3/DQS12

A3

DQ25

DQS3

A4

VDDID

DQ56

DQ57

VDD

DQ60

DQ61

VSS

VDD

DQ26

DQ27

A2

DQ30

VSS

DM7/DQS16

DQ62

DQ63

VDDQ

SA0

DQS7

DQS8

DQ59

VSS

DQ31

NC / CB4

NC / CB5

VDDQ

CK0

VSS

A1

NC / CB0

NC / CB1

VDD

NC

SA1

SDA

SA2

SCL

CK0

VDDSPD

NC / DQS8

VSS

Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“no-connects”) on x64 organised non-ECC

modules

Preliminary Datasheet

4

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

S0

DQS0

DQS4

DM4/DQS13

DM0/DQS9

DM

I/O7

S

DQS

S

DM

I/O 7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

D4

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

D0

DQS5

DQS1

DM5/DQS14

DM1/DQS10

DQS

DM

S

DQS

S

DM

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

DQ8

DQ9

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

D5

D1

DQ10

DQ1 1

DQ12

DQ13

DQ14

DQ15

I/O3

I/O2

DQS6

DM6/DQS15

DQS2

DM2/DQS11

DM

S

DQS

S

DQS

DM

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

DQ16

I/O7

D6

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

D2

DQS3

DM3/DQS12

DQS7

DM7/DQS16

DM

S

DQS

S

DM

DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

DQ24

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

D7

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

D3

* Clock Wiring

Clock

Input

SDRAMs

Serial PD

A1

2 SDRAMs

3 SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

SDA

SCL

A0

SA0

A2

* Wire per Clock Loading

Table/Wiring Diagrams

SA1

SA2

BA0, BA1: SDRAMs D0 - D7

A0- A12: SDRAMs D0 - D7

BA0 - BA1

A0 - A12

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections

RAS

RAS : SDRAMs D0 - D7

V

DDQ

D0 - D7

CAS

CKE0

WE

CAS : SDRAMs D0 - D7

CKE: SDRAMs D0 - D7

WE : SDRAMs D0 - D7

V

DD

VREF

D0 - D7

V

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

SS

V

DDID

Block Diagram: One Bank 32M × 64 DDR-I SDRAM DIMM Module

HYS64D32000GU using x8 organized SDRAMs on Raw Card Version B

Preliminary Datasheet

5

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

S1

S0

DQS4

DM4/DQS13

DQS0

DM0/DQS9

DM

I/O0

DM

I/O7

DQS

S

DQS

S

DQS

DM

I/O 7

S

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

DQ0

DQ1

DQ2

DQ3

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

D12

D4

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

D0

D8

DQ4

DQ5

DQ6

DQ7

DQS5

DM5/DQS14

DQS1

DM1/DQS10

DM

S

DQS

S

DM

S

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

DQ8

DQ9

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

D5

D13

D9

D1

DQ10

DQ1 1

DQ12

DQ13

DQ14

DQ15

I/O4

I/O5

I/O3

I/O2

DQS6

DM6/DQS15

DQS2

DM2/DQS11

S

DM

S

DM

DQS

S

DQS

DM

I/O0

S

DM

I/O7

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

DQ16

D14

D6

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

D10

D2

DQS7

DM7/DQS16

DQS3

DM3/DQS12

S

DM

S

DM

DQS

DM

S

DQS

DM

S

DQS

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

DQ56

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

DQ24

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

D15

D7

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

D3

D11

* Clock Wiring

Clock

Input

SDRAMs

BA0, BA1: SDRAMs D0, D15

A0- A12: SDRAMs D0 - D15

BA0, BA1

A0 - A12

Serial PD

A1

4 SDRAMs

6 SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

SDA

SCL

V

DDQ

A0

SA0

A2

D0 - D15

* Wire per Clock Loading

Table/Wiring Diagrams

V

DD

SA1

SA2

VREF

D0 - D15

Notes:

V

SS

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

V

DDID

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

CKE1

CKE: SDRAMs D8 - D15

RAS : SDRAMs D0 - D15

RAS

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

CAS

CKE0

WE

CAS : SDRAMs D0 - D15

CKE: SDRAMs D0 - D7

WE : SDRAMs D0 - D15

Block Diagram: Two Bank 64M × 64 DDR-I SDRAM DIMM Modules

HYS64D64020GU using x8 Organized SDRAMs on Raw Card Version A

Preliminary Datasheet

6

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

S0

DQS0

DQS4

DM4/DQS13

DM0/DQS9

DM

I/O7

DQS

S

DQS

S

DM

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 7

I/O 6

I/O 1

I/O 0

I/O5

I/O4

I/O3

I/O2

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

D4

D0

DQS5

DQS1

DM5/DQS14

DM1/DQS10

DQS

DM

S

DQS

S

DM

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

DQ8

DQ9

D5

D1

DQ10

DQ1 1

DQ12

DQ13

DQ14

DQ15

I/O3

I/O2

DQS6

DM6/DQS15

DQS2

DM2/DQS11

S

DM

DQS

S

DM

I/O7

DQS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

DQ16

D6

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

D2

DQS3

DM3/DQS12

DQS7

DM7/DQS16

S

DM

DQS

S

DM

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ24

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

D7

DQ25

DQ26

DQ27

D3

DQ28

DQ29

DQ30

DQ31

DQS8

DM8/DQS17

Serial PD

A1

S

DM

DQ24

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

D8

SDA

SCL

A0

SA0

A2

SA2

SA1

BA0, BA1

A0 - A12

BA0, BA1: SDRAMs D0 - D8

A0 - A12: SDRAMs D0 - D8

* Clock Wiring

Clock

Input

SDRAMs

RAS

RAS : SDRAMs D0 - D8

V

DDQ

3 SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

D0 - D8

CAS

CKE0

WE

CAS : SDRAMs D0 - D8

CKE: SDRAMs D0 - D8

WE : SDRAMs D0 - D8

V

DD

VREF

D0 - D8

* Wire per Clock Loading

Table/Wiring Diagrams

V

SS

V

DDID

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

Block Diagram: One Bank 32M × 72 DDR-I SDRAM DIMM Module

HYS72D32000GU using x8 organized SDRAMs on Raw Card Version B

Preliminary Datasheet

7

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

S1

S0

DQS4

DM4/DQS13

DQS0

DM0/DQS9

DM

I/O7

DQS

DM

I/O0

DQS

S

DQS

S

DQS

DM

I/O 7

DM

S

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

DQ0

DQ1

DQ2

DQ3

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

D13

D4

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

D9

D0

DQ4

DQ5

DQ6

DQ7

DQS5

DM5/DQS14

DQS1

DM1/DQS10

DM

S

DQS

S

DM

S

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

DQ8

DQ9

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

D14

D5

D10

D1

DQ10

DQ1 1

DQ12

DQ13

DQ14

DQ15

I/O4

I/O5

I/O3

I/O 2

DQS6

DQS2

DM2/DQS11

DM6/DQS15

DM

S

DM

S

DQS

S

DQS

DM

I/O0

S

DM

I/O 7

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

DQ16

D15

D6

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D11

D2

DQS7

DQS3

DM3/DQS12

DM7/DQS16

S

DM

S

DM

DQS

DM

S

DM

S

DQS

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

DQ56

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

DQ24

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

D16

D7

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

D1 2

D3

DQS8

DM8/DQS17

DM

S

DM

S

DQS

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

DQ24

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

D3

D12

* Clock Wiring

Clock

Input

SDRAMs

BA0, BA1

A0 - A12

BA0, BA1: SDRAMs D0 - D17

A0 - A12: SDRAMs D0 - D17

Serial PD

A1

6 SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

SDA

SCL

V

DDQ

A0

SA0

A2

D0 - D17

* Wire per Clock Loading

Table/Wiring Diagrams

V

DD

SA1

SA2

VREF

D0 - D17

Notes:

V

SS

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

V

DDID

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

CKE1

CKE: SDRAMs D9 - D17

RAS : SDRAMs D0 - D17

RAS

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

CAS

CKE0

WE

CAS : SDRAMs D0 - D17

CKE: SDRAMs D0 - D8

WE : SDRAMs D0 - D17

Block Diagram: Two Bank 64M × 72 DDR-I SDRAM DIMM Modules

HYS72D64020GU using x8 Organized SDRAMs on Raw Card Version A

Preliminary Datasheet

8

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

6 D R AM L oads

4 DRAM L oa ds

2 DRAM L oads

3 DR AM L oad s

Clock Net Wiring

Capacitance (target, not verified)

T_A= 0 to 70 °C; V_DD= 2.5 V ± 0.2 V, f = 1 MHz

Parameter

Symbol

Limit Values (max.)

Unit

One Bank

modules

Two Bank

Modules

Input Capacitance

C_IN

tbd.

pF

(all inputs except CLK,CLK & CKE)

Input Capacitance (CLK, CLK )

Input Capacitance (CKE)

C_CLK

C_CKE

C_IO

tbd.

pF

Input/Output Capacitance

(DQ0 - DQ63, CB0 - CB7)

Input Capacitance (SCL, SA0 - 2)

Input/Output Capacitance (SDA)

C_SC

C_SD

8

pF

Preliminary Datasheet

9

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

Supply Voltage Levels

Parameter

Symbol

Limit Values

Unit Notes

min.

2.3

nom.

2.5

max.

2.7

Device Supply Voltage

Output Supply Voltage

Input Reference Voltage

V_DD

V

–

1)

V_DDQ

V_REF

V_TT

2.3

2.5

2.7

2)

3)

1.15

1.25

1.35

Termination Voltage

V

_REF– 0.04 V_REF

V_REF+ 0.04

1)

Under all conditions, V_DDQmust be less than or equal to V_DD

Peak to peak AC noise on V_REFmay not exceed ± 2% V_{REF (DC)}. V_REFis also expected to track noise variations

in V_DDQ

_TTof the transmitting device must track V_REFof the receiving device.

.

2)

.

3)

V

DC Operating Conditions (SSTL_2 Inputs)

(V_DDQ= 2.5 V, T_A= 70 °C, Voltage Referenced to V_SS)

Parameter

Symbol

Limit Values

max.

Unit

Notes

min.

V

1)

DC Input Logic High

DC Input Logic Low

Input Leakage Current

V_{IH (DC)}

V_{IL (DC)}

I_IL

_REF+ 0.18

V

5

_DDQ+ 0.3

V

– 0.30

– 5

_REF– 0.18

V

–

2)

µA

2)

Output Leakage Current

I_OL

– 5

5

1)

The relationship between the V_DDQof the driving device and the V_REFof the receiving device is what determines

noise margins. However, in the case of V_{IH (max)}(input overdrive), it is the V_DDQof the receiving device that is

referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2

outputs (such as a translator), and therefore no V_DDQsupply voltage connection, inputs must tolerate input

overdrive to 3.0 V (High corner V_DDQ+ 300 mV).

2)

For any pin under test input of 0 V ≤ V_IN≤ V_DDQ+ 0.3 V.

Operating, Standby and Refresh Currents (for reference only)

(values apply to one SDRAM component and do not include register and PLL)

(T_A= 0 to +70 °C, V_DD= 2.5 V ± 0.2 V)

Parameter

Symbol Test Condition

Speed

Unit Notes

– 7

– 7.5 – 8

1), 2), 3)

Operating Current

I_CC1

1 bank operation

CAS Latency = 2

100 90

70

mA

t_RC= t_RC(min), t_CK= min.

Active-Precharge

command without burst

operation

1)

Precharge Standby

Current in Power Down

Mode

I_CC2P

CKE ≤ V_IL(max)

_CK= min.,

CS = V_IH(min)

,

20

mA

t

Preliminary Datasheet

10

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

Operating, Standby and Refresh Currents (cont’d)(for reference only)

(values apply to one SDRAM component and do not include register and PLL)

(T_A= 0 to +70 °C, V_DD= 2.5 V ± 0.2 V)

Parameter

Symbol Test Condition

Speed

Unit Notes

– 7

– 7.5 – 8

1), 3)

Precharge Standby

Current in Non-Power

Down Mode

I_CC2N

CKE ≥ V_IH(min)

_CK= min.,

CS = V_{IH (min)}

CKE ≤ V_IL(max)

_CK= min.

CKE ≥ V_IH(min)

_CK= min.,

CS = V_{IH (min)}

_CK= min.,

,

50

45

40

mA

t

1)

No Operating Current

(Active state: 4 bank)

I_CC3P

I_CC3N

,

30

65

30

60

30

55

mA

t

1), 3)

,

mA

t

1), 2), 3)

Operating Current

(Burst Mode)

I_CC4

t

140 120 100 mA

Read/Write command

cycling,

Multiple banks active,

gapless data, BL = 4

1), 4), 5)

1), 4)

Auto (CBR) Refresh

Current

I_CC5

I_CC6

t_CK= min., t_RC= t_RFC(min)155 135 110 mA

CBR command cycling

Self Refresh Current

CKE ≤ 0.2 V

1

mA

1)

These parameters depend on the cycle rate and are measured with the cycle determined by the minimum

value of t_CKand t_RC

.

2)

3)

4)

5)

The specified values are obtained with the output open.

Input signals are changed once during three clock cycles.

8192 refresh cycles in 64 ms.

Minimum cycle time during Auto Refresh operation (t_REF) is greater than minimum cycle time for Read/Write

operation.

Preliminary Datasheet

11

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

AC Characteristics (for reference only)

(values apply to the SDRAM component and do not include register, PLL, or card wiring)

(T_A= 0 to + 70 °C, V_DD= 2.5 V ± 0.2 V)

Parameter

Symbol

-7

-7.5

-8

Unit

Notes

PC266A

PC266B

PC200

min.

max.

min.

max.

min.

max.

DQ Output Access Time from CK/ t_AC

CK

– 0.75

+ 0.75

– 0.75

+ 0.75

– 0.8

+ 0.8

ns

–

DQS Output access Time from CK/ t_DQSCK

CK

– 0.75

+ 0.75

– 0.75

+ 0.75

– 0.8

+ 0.8

CLK High Level Width

CLK Low Level Width

t_CH

t_CL

t_CK

0.45

7.5

7

0.55

20

–

0.45

10

0.55

20

–

0.45

10

8

0.55

20

–

*tCK

ns

–

1)

Clock Period

CL = 2

CL = 2.5

CL = 3

7.5

ns

–

7

7.5

8

ns

DQ and DM Input Hold Time

DQ and DM Input Setup Time

t_DH

0.5

1.75

0.5

0.6

2

ns

t_DS

–

0.5

–

ns

DQ and DM Input Pulse Width

(for each input)

t_DIPW

–

1.75

–

ns

Data-Out High-impedance from CK/ t_HZ

CK

– 0.75

+ 0.75

– 0.75

+ 0.75

– 0.8

+ 0.8

ns

–

Data-Out Low-impedance from CK/ t_LZ

CK

DQS-DQ Skew

t_DQSQ

–

+ 0.5

–

+ 0.5

–

+ 0.6

–

ns

–

2)

QH Data-Out Hold Time from DQS t_QH

tHP-0.75

0.75

tHP-0.75

0.75

tHP-1.0

0.75

ns

Write Command to First DQS

Latching Transition

1.25

*t_CK

–

t_DQSS

DQS Input Valid Time

t_DSL,H

t_MRD

0.4

15

0.6

–

0.4

15

0.6

–

0.4

16

0.6

–

*t_CK

–

Mode Register/Extended Mode

Register Set Cycle Time

ns

Write Preamble Setup Time

DQS Hold Time from CK/CK

Write Postamble

t_WPRES

t_WPREH

t_WPST

t_IS

0

–

0

–

0

–

ns

–

0.25

0.4

0.9

0.4

45

–

0.25

0.4

0.9

0.4

45

–

0.25

0.4

1.2

0.9

0.4

50

–

*t_CK

ns

0.6

–

0.6

–

0.6

–

3)

Input Setup Time (LVTTL inputs)

Input Hold Time (LVTTL inputs)

Read Preamble

3)

t_IH

–

ns

t_RPRE

t_RPST

t_RAS

1.1

0.6

120K

–

1.1

0.6

120k

–

1.1

0.6

120K

–

*t_CK

ns

–

Read Postamble

Row Active Time

Row Cycle Time R/W Operation t_RC

Auto Refresh t_RFC

t_RCD

t_RP

Row Activate to Row Activate Delay t_RRD

65

70

ns

–

1)

75

–

75

–

80

–

ns

RAS to CAS Delay

Row Precharge Time

20

–

20

–

20

–

ns

–

20

–

20

–

20

–

ns

15

–

15

–

15

–

ns

Write Recovery Time

t_WR

15

–

15

–

15

–

ns

Preliminary Datasheet

12

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

AC Characteristics (cont’d)(for reference only)

(values apply to the SDRAM component and do not include register, PLL, or card wiring)

(T_A= 0 to + 70 °C, V_DD= 2.5 V ± 0.2 V)

Parameter

Symbol

-7

-7.5

-8

Unit

Notes

PC266A

PC266B

PC200

min.

max.

min.

max.

min.

max.

Auto Precharge Write Recovery +

Precharge Time

t_DAL

35

–

35

–

35

–

ns

–

Internal Write to Read Command

Delay

t_WTR

1

–

1

–

1

–

*t_CK

Power Down Entry Time

Power Down Exit Time

t_PDENT

t_PDEX

t_SREX

t_REF

t_{IS + 1 CLK 2 CLK +}t_IS

–

t_{IS + 1 CLK 2 CLK +}t_ISns

–

Self Refresh Exit Time

200

–

200

–

200

–

Cycles

µs

Average Periodic Refresh Intercal

7.8

CLK Transition Time

t_T

0.5

–

0.5

–

ns

1)

Minimum Auto Refresh cycle time is greater than minimum cycle time during normal Read or Write operation.

t_HPis the lesser of t_CLand T_CH

These parameters guarantee device timing, but they are not necessarily tested on each device

they may be guaranteed by design or tester correlation

2)

3)

t_IS/ t_IH=0.9ns for PC266 are measured with command / address input slew rate of > 1.0V/ns

for command / address input slew rate of > 0.5V/ns and < 1.0V/ns t_IS/ t_IH= 1.0ns should be guaranteed by design

for PC200 t_IS/ t_IH= 1.2ns command / address input slew rate of 1.0V/ns is assumed

slew rate is measured between V_OH(AC) and V_OL(AC)

CK / CK slew rates are assumed to be > 1.0V/ns

Pulse width for command / address signals to be properly sampled at rising edges of clock shall be a minimum of 2.2ns

Environmental Parameters

Symbol

Parameter

Rating

Units

Notes

T_OPR

H_OPR

T_STG

H_STG

Operating Temperature (ambient)

Operating Humidity (relative)

0 to +55

^oC

%

10 to 90

-50 to +100

5 to 95

1)

2)

Storage Temperature

^oC

%

Storage Humidity (without condensation)

Barometric Pressure (operating and storage)

105 to 69

K Pascal

¹⁾stresses greater than those listed may cause permanent damage to the device. Device functional operation at or above these conditions is not implied.

²⁾up to 3000 m (9850 ft)

Preliminary Datasheet

13

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

Package Outlines

Simplified Mechanical Drawing

(for details see JEDEC document MO-206a)

DDR-I Unbuffered DIMM Modules

133,35

128,93

N/A

for

x64

92

2,3

2,5

B

64,77

49,53

93

PIN 184

N/A

for

x64

Detail A:

Detail B:

6,62

1,8

2,175

Preliminary Datasheet

14

5.00

HYS64/72D32000GU / HYS64/72D64020GU

Unbuffered DDR-I SDRAM-Modules

Change List

9.5.2000

Rev.0.9

First target revision

Preliminary Datasheet

15

5.00


型号：	HYS64D64020GU-8-X
厂家：	Infineon
描述：	DDR DRAM Module, 64MX64, 0.8ns, CMOS, DIMM-184 动态存储器双倍数据速率
文件：	总15页 (文件大小：164K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYS64D64020GU-8-X [INFINEON]

相关型号：

HYS64D64020HBDL

HYS64D64020HBDL-5-B

HYS64D64020HBDL-5-C

HYS64D64020HBDL-5-C

HYS64D64020HBDL-6-B

HYS64D64020HBDL-6-C

HYS64D64020HBDL-6-C

HYS64D64020HDL-5-B

HYS64D64020HDL-5-C

HYS64D64020HDL-6-B

HYS64D64020HDL-6-C

HYS64D64020HU-8-B