HYS64V16220GU-8B [INFINEON]
3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module; 3.3 V 8M ×64 /72- 1位银行SDRAM模块3.3 V 16M ×64 /72- 2位银行SDRAM模块
| 型号： | HYS64V16220GU-8B |
| 厂家： | 
Infineon |
| 描述： | 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module |
| 文件： | 总17页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 V 8M × 64/72-Bit 1 Bank SDRAM Module
3.3 V 16M × 64/72-Bit 2 Bank SDRAM Module
HYS 64/72V8200GU
HYS 64/72V16220GU
168 pin unbuffered DIMM Modules
• 168 Pin PC100-compatible unbuffered 8 Byte Dual-In-Line SDRAM Modules
for PC main memory applications
• 1 bank 8M × 64, 8M × 72 and 2 bank 16M × 64, 16M × 72 organization
• Optimized for byte-write non-parity or ECC applications
• JEDEC standard Synchronous DRAMs (SDRAM)
• Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification
• SDRAM Performance
-8
100
6
-8B
100
6
-10
66
8
Units
MHz
ns
fCK Clock frequency (max.)
tAC Clock access time
• Programmed Latencies
Product Speed
CL
2
tRCD tRP
-8
PC100
2
2
2
2
3
2
-8B
-10
PC100
PC66
3
2
• Single + 3.3 V (± 0.3 V ) power supply
• Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Utilizes 8M × 8 SDRAMs in TSOPII-54 packages
• 4096 refresh cycles every 64 ms
• 133.35 mm × 31.75 mm × 4.00 mm card size with gold contact pads
Semiconductor Group
1
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
The HYS 64(72)8200 and HYS 64(72)16220 are industry standard 168-pin 8-byte Dual in-line
Memory Modules (DIMMs) which are organized as 8M × 64, 8M × 72 in 1 bank and 16M × 64 and
16M × 72 in two banks high speed memory arrays designed with 64M Synchronous DRAMs
(SDRAMs) for non-parity and ECC applications. The DIMMs use -8 and -8B speed sort
8M 8 SDRAM devices in TSOP-54 packages to meet the PC100 requirement. Modules which use
-10 parts are suitable for PC66 applications only. Decoupling capacitors are mounted on the PC
board. The PC board design is according to INTEL’s PC SDRAM Rev. 1.0 module specification.
The DIMMs have a serial presence detect, implemented with a serial E2PROM using the two pin I2C
protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are
available to the end user.
All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm
long footprint, with 1.25“ ( 31.75 mm) height.
Ordering Information
Type
Ordering Code Package
Descriptions
Module
Height
HYS 64V8200GU-8
HYS 72V8200GU-8
PC100-222-620 L-DIM-168-30 100 MHz 8M × 64 1 bank
1.25“
1.25“
1.25“
1.25“
1.25“
1.25“
1.25“
1.25“
1.25“
1.25“
SDRAM module
PC100-222-620 L-DIM-168-30 100 MHz 8M × 72 1 bank
SDRAM module
HYS 64V16220GU-8 PC100-222-620 L-DIM-168-30 100 MHz 16M × 64 2 bank
SDRAM module
HYS 72V16220GU-8 PC100-222-620 L-DIM-168-30 100 MHz 16M × 72 2 bank
SDRAM module
HYS 64V8200GU-8B PC100-323-620 L-DIM-168-30 100 MHz 8M × 64 1 bank
SDRAM module
HYS 64V16220GU-8B PC100-323-620 L-DIM-168-30 100 MHz 16M × 64 2 bank
SDRAM module
HYS 64V8200GU-10 PC66-222-920 L-DIM-168-30 66 MHz 8M × 64 1 bank
SDRAM module
HYS 72V8200GU-10 PC66-222-920 L-DIM-168-30 66 MHz 8M × 72 1 bank
SDRAM module
HYS 64V16220GU-10 PC66-222-920 L-DIM-168-30 66 MHz 16M × 64 2 bank
SDRAM module
HYS 72V16220GU-10 PC66-222-920 L-DIM-168-30 66 MHz 16M × 72 2 bank
SDRAM module
Semiconductor Group
2
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
Pin Names
A0 - A11
Address Inputs
Bank Selects
CLK0 - CLK3 Clock Input
BA0, BA1
DQMB0 -
DQMB7
Data Mask
DQ0 - DQ63
CB0 - CB7
Data Input/Output
CS0 - CS3
Chip Select
Check Bits (× 72
VCC
Power (+ 3.3 Volt)
organization only)
RAS
Row Address Strobe
Column Address Strobe
Read/Write Input
VSS
Ground
CAS
SCL
SDA
N.C.
Clock for Presence Detect
Serial Data Out for Presence Detect
No Connection
WE
CKE0, CKE1
Clock Enable
Address Format
Part Number
Rows Columns Bank
Select
Refresh Period
Interval
8M × 64 HYS 64V8200GU
8M × 72 HYS 72V8200GU
12
12
9
9
9
9
2
2
2
2
4k
4k
4k
4k
64 ms
64 ms
64 ms
64 ms
15.6 µs
15.6 µs
15.6 µs
15.6 µs
16M × 64 HYS 64V16220GU 12
16M × 72 HYS 72V16220GU 12
Semiconductor Group
3
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
Pin Configuration
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
1
43
85
127
VSS
VSS
VSS
VSS
2
3
4
5
6
DQ0
DQ1
DQ2
DQ3
VCC
44
45
46
47
48
DU
86
87
88
89
90
DQ32
DQ33
DQ34
DQ35
VCC
128
129
130
131
132
CKE0
CS3
CS2
DQMB2
DQMB3
DU
DQMB6
DQMB7
NC
7
DQ4
49
91
DQ36
133
VCC
VCC
8
DQ5
DQ6
DQ7
DQ8
VSS
50
51
52
53
54
NC
92
93
94
95
96
DQ37
DQ38
DQ39
DQ40
VSS
134
135
136
137
138
NC
9
NC
NC
10
11
12
NC (CB2)
NC (CB3)
VSS
CB6
CB7
VSS
13
14
15
16
17
DQ9
DQ10
DQ11
DQ12
DQ13
55
56
57
58
59
DQ16
DQ17
DQ18
DQ19
VCC
97
DQ41
DQ42
DQ43
DQ44
DQ45
139
140
141
142
143
DQ48
DQ49
DQ50
DQ51
VCC
98
99
100
101
18
60
DQ20
102
144
DQ52
VCC
VCC
19
20
21
22
DQ14
61
62
63
64
NC
103
104
105
106
DQ46
145
146
147
148
NC
DQ15
DU
DQ47
DU
NC (CB0)
NC (CB1)
CKE1
VSS
NC (CB4)
NC (CB5)
NC
VSS
DQ53
23
65
DQ21
107
149
VSS
VSS
24
25
26
NC
66
67
68
DQ22
DQ23
VSS
108
109
110
NC
150
151
152
DQ54
DQ55
VSS
NC
NC
VCC
VCC
27
28
29
30
31
WE
69
70
71
72
73
DQ24
DQ25
DQ26
DQ27
VCC
111
112
113
114
115
CAS
DQMB4
DQMB5
CS1
153
154
155
156
157
DQ56
DQ57
DQ58
DQ59
VCC
DQMB0
DQMB1
CS0
DU
RAS
32
74
DQ28
116
158
DQ60
VSS
A0
A2
A4
A6
VSS
A1
A3
A5
A7
33
34
35
36
75
76
77
78
DQ29
DQ30
DQ31
VSS
117
118
119
120
159
160
161
162
DQ61
DQ62
DQ63
VSS
37
38
39
40
A8
79
80
81
82
CLK2
NC
121
122
123
124
A9
163
164
165
166
CLK3
NC
A10
BA1
VCC
BA0
A11
VCC
WP
SA0
SDA
SA1
41
42
83
84
SCL
125
126
CLK1
167
168
SA2
VCC
CLK0
NC
VCC
VCC
Note: Pinnames in brackets are for the x72 ECC versions
Semiconductor Group
4
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
WE
CS0
CS
DQM
WE
CS
DQM
WE
DQMB0
DQ(7:0)
DQMB4
DQ0-DQ7
DQ(39:32)
DQ0-DQ7
D0
D4
CS
DQM
WE
CS
DQM
WE
DQMB1
DQMB5
DQ(15:8)
DQ0-DQ7
DQ(47:40)
DQ0-DQ7
D1
D5
CS
WE
DQM
CB(7:0)
CS2
DQ0-DQ7
D8
CS
DQM
WE
CS
DQM
WE
DQMB2
DQMB6
DQ(23:16)
DQ0-DQ7
DQ(55:48)
DQ0-DQ7
D2
D6
CS
DQM
WE
CS
DQM
WE
DQMB3
DQMB7
DQ(31:24)
DQ0-DQ7
DQ(63:56)
DQ0-DQ7
D3
D7
A0-A11, BA0, BA1
VCC
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
E2PROM (256 word x 8 Bit)
SA0
SA0
SA1
SA2
SCL
SA1
SA2
SCL
SDA
WP
C0-C15, (C16, C17)
VSS
47 k
Ω
RAS
CAS
CKE0
Clock Wiring
16 M x 64
16 M x 72
5 SDRAM
CLK0
4 SDRAM + 3.3 pF
Termination
CLK1
CLK2
CLK3
Termination
4 SDRAM + 3.3 pF
Termination
4 SDRAM + 3.3 pF
Termination
Note: D8 is only used in the x72 ECC version.
SPB03958
Block Diagram for 8M × 64/72 SDRAM DIMM Modules (HYS 64/72V8200GU)
Semiconductor Group
5
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
CS1
CS0
CS
CS
CS
CS
DQMB0
DQ(7:0)
DQM
DQM
DQMB4
DQM
DQM
DQ0-DQ7
DQ0-DQ7
DQ(39:32)
DQ0-DQ7
DQ0-DQ7
D0
D1
D8
D9
D4
D5
D12
D13
CS
CS
CS
CS
DQMB1
DQM
DQM
DQMB5
DQM
DQM
DQ(15:8)
DQ0-DQ7
DQ0-DQ7
DQ(47:40)
DQ0-DQ7
DQ0-DQ7
CS
CS
DQM
DQM
DQ0-DQ7
CB(7:0)
DQ0-DQ7
D16
D17
CS3
CS2
CS
CS
CS
CS
DQMB2
DQM
DQM
DQMB6
DQM
DQM
DQ(23:16)
DQ0-DQ7
DQ0-DQ7
DQ(55:48)
DQ0-DQ7
DQ0-DQ7
D2
D3
D10
D11
D6
D7
D14
D15
CS
CS
CS
CS
DQMB3
DQM
DQM
DQMB7
DQM
DQM
DQ(31:24)
DQ0-DQ7
DQ0-DQ7
DQ(63:56)
DQ0-DQ7
DQ0-DQ7
A0-A11, BA0, BA1
VDD
D0-D15, (D16, D17)
D0-D15, (D16, D17)
D0-D7, (D8)
E2PROM (256 word x 8 Bit)
SA0
SA0
SA1
SA2
SCL
SA1
SA2
SCL
SDA
WP
C0-C31, (C32...C35)
VSS
47 k
Ω
RAS, CAS, WE
CKE0
D0-D15, (D16, D17)
D0-D7, (D16)
Clock Wiring
16 M x 64
VDD
10 k
16 M x 72
5 SDRAM
5 SDRAM
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
Ω
CLK0
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
CLK1
CLK2
CLK3
CKE1
D9-D15, (D17)
SPB03769
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ω except otherwise noted.
Block Diagram for 16M × 64/72 SDRAM DIMM Modules (HYS 64/72V1620GU)
Semiconductor Group
6
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
max.
Unit
min.
2.0
Input high voltage
VIH
VIL
V
CC + 0.3
V
Input low voltage
– 0.5
2.4
0.8
–
V
Output high voltage (IOUT = – 2.0 mA)
Output low voltage (IOUT = 2.0 mA)
VOH
VOL
II(L)
V
–
0.4
40
V
Input leakage current, any input
– 40
µA
(0 V < VIN < 3.6 V, all other inputs = 0 V)
Output leakage current
IO(L)
– 40
40
µA
(DQ is disabled, 0 V < VOUT < VCC)
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
max. max.
Unit
max.
max.
8M×64 8M×72 16M×64 16M×72
Input capacitance
CI1
45
55
70
80
pF
(A0 to A11, BA0, BA1, RAS, CAS, WE)
Input capacitance (CS0 - CS3)
Input capacitance (CLK0 - CLK3)
Input capacitance (CKE0, CKE1)
CI2
25
35
35
13
10
25
38
38
13
10
25
35
35
20
15
30
38
38
20
15
pF
pF
pF
pF
pF
CICL
CI3
Input capacitance (DQMB0 - DQMB7) CI4
Input/Output capacitance
(DQ0 - DQ63, CB0 - CB7)
CIO
Input Capacitance (SCL, SA0 - 2)
Input/Output capacitance
CSC
CSD
8
8
8
8
pF
pF
10
10
10
10
Semiconductor Group
7
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
Operating Currents
TA = 0 to 70 °C, VDD = 3.3 V ± 0.3 V 1
Recommended Operating Conditions unless otherwise noted
Parameter & Test Condition
Symb.
-8/-8B -10
max.
Unit Note
1
Operating Current
ICC1
110
75
mA
t
RC = tRC(MIN.), tCK = tCK(MIN.)
Outputs open Burst length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner to maximize
gapless data access
1
t
t
t
t
CK = min.
Precharged Standby Current in
Power Down Mode
ICC2P
2
2
mA
1
CK = infinity
CK = min.
ICC2PS
ICC2N
ICC2NS
1
1
mA
CS = VIH(MIN.), CKE ≤ VIL(MAX.)
1
Precharged Standby Current in
Non-power Down Mode
35
5
30
5
mA
1
CK = infinity
CS = VIH(MIN.), CKE ≥ VIH(MIN.)
1
CKE ≥ VIH(MIN.)
CKE ≤ VIL(MAX.)
No operating current
ICC3N
ICC3P
ICC4
45
8
40
8
mA
1
t
CK = min., CS = VIH(MIN.),
mA
active state (max. 4 banks)
1, 2
Burst operating current
–
–
70
130
1
50
90
1
mA
t
CK = min.,
Read command cycling
1
Auto refresh current
ICC5
mA
t
CK = min.,
Auto Refresh command cycling
1
Self refresh current
standard version ICC6
mA
Self Refresh Mode, CKE = 0.2 V
Semiconductor Group
8
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
AC Characteristics 3, 4
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
Unit Note
-8
-8B
-10
PC100-222 PC100-323
PC66
min. max. min. max. min. max.
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
tCK
fCK
tAC
10
10
–
–
10
12
–
–
10
15
–
–
ns
ns
System Frequency
CAS Latency = 3
CAS Latency = 2
–
–
100
100
–
–
100
83
–
–
100
66
MHz
MHz
Clock Access Time
CAS Latency = 3
CAS Latency = 2
4, 5
–
–
6
6
–
–
6
7
–
–
8
9
ns
ns
6
Clock High Pulse Width
Clock Low Pulse Width
Input Setup Time
tCH
3
–
–
–
–
–
3
–
–
–
–
–
3.5
3.5
3
–
–
–
–
–
ns
6
tCL
3
3
ns
7
tCS
2
2
ns
7
Input Hold Time
tCH
1
1
1
ns
8
CKE Setup Time
tCKSP
2.5
2.5
3
ns
(Power down mode)
9
CKE Setup Time
(Self Refresh Exit)
tCKSR
tT
8
1
–
–
10
1
–
–
8
1
–
–
ns
Transition Time
(rise and fall)
ns
Common Parameters
RAS to CAS delay
Precharge Time
tRCD
tRP
tRAS
tRC
tRRD
tCCD
20
20
50
70
16
1
–
–
20
30
–
–
30
30
–
–
ns
ns
Active Command Period
Cycle Time
100k 60
100k 70
100k ns
–
–
–
80
20
1
–
–
–
80
20
1
–
–
–
ns
Bank to Bank Delay Time
ns
CAS to CAS Delay Time
(same bank)
CLK
Semiconductor Group
9
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
AC Characteristics (cont’d)3, 4
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
Unit Note
-8
-8B
-10
PC100-222 PC100-323
PC66
min. max. min. max. min. max.
Refresh Cycle
8
Refresh Period
(4096 cycles)
tREF
–
64
–
–
64
–
–
64
–
ms
9
Self Refresh Exit Time
tSREX
10
10
10
ns
Read Cycle
4
Data Out Hold Time
tOH
3
0
3
–
–
–
8
2
3
0
3
–
–
3
0
3
–
–
ns
Data Out to Low Impedance tLZ
Data Out to High Impedance tHZ
–
–
ns
10
10
2
10
2
ns
DQM Data Out Disable
Latency
tDQZ
CLK
Write Cycle
Data input to Precharge
(write recovery)
tDPL
2
–
2
–
2
–
CLK
Data In to Active/Refresh
DQM Write Mask Latency
tDAL
5
0
–
–
5
0
–
–
5
0
–
–
CLK
CLK
tDQW
Semiconductor Group
10
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
Notes
1. The specified values are valid when addresses are changed no more than once during tCK(MIN.)
and when No Operation commands are registered on every rising clock edge during tRC(MIN.)
.
Values are shown per module bank.
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(MIN.)
.
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume
tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1V/ns edge rate
between 0.8 V and 2.0 V.
.
tCH
2.4 V
0.4 V
CLOCK
tT
tCL
tHOLD
tSETUP
INPUT
1.4 V
I/O
tAC
tAC
50 pF
tLZ
tOH
Measurement conditions for
AC and tOH
OUTPUT
1.4 V
t
tHZ
SPT03404
5. If clock rising time is longer than 1ns, a time (tT/2 – 0.5) ns has to be added to this parameter.
6. Rated at 1.5 V
7. If tT is longen than 1 ns, a time (tT – 1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up“ the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
10.Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
Semiconductor Group
11
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
A serial presence detect storage device - E2PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E2PROM device during module
production using a serial presence detect protocol (I2C synchronous 2-wire bus).
SPD-Table for PC100 Modules
Byte# Description
SPD
Hex
Entry
Value
8M×64 8M×64 8M×72 16M×64 16M×64 16M×72
-8
-8B
-8
-8
-8B
-8
0
1
Number of SPD
bytes
128
80
08
04
80
80
08
04
80
08
80
08
04
80
08
Total bytes in Serial 256
PD
08
2
3
Memory Type
SDRAM
04
04
04
Number of Row
Addresses
12
0C
0C
0C
0C
0C
0C
(without BS bits)
4
Number of Column
Addresses
9
09
09
09
09
09
09
(for 8M × 8
SDRAMs)
5
Number of DIMM
Banks
1/2
01
01
01
02
02
02
6
7
Module Data Width 64/72
40
00
40
00
48
00
40
00
40
00
48
00
Module Data Width
(cont’d)
0
8
Module Interface
Levels
LVTTL
01
A0
60
01
A0
60
01
A0
60
01
A0
60
01
A0
60
01
A0
60
9
SDRAM Cycle Time 10.0 ns
at CL= 3
10
SDRAM Access
time from Clock at
CL = 3
6.0 ns
11
12
Dimm Config
(Error Det/Corr.)
none/ECC 00
00
80
02
80
00
80
00
80
02
80
Refresh Rate/Type Self
Refresh15.
80
6 µs
13
14
SDRAM width,
Primary
× 8
08
00
08
00
08
08
08
00
08
00
08
08
Error Checking
n/a /× 8
SDRAM data width
Semiconductor Group
12
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
SPD-Table for PC100 Modules (cont’d)
Byte# Description
SPD
Hex
Entry
Value
8M×64 8M×64 8M×72 16M×64 16M×64 16M×72
-8
-8B
-8
-8
-8B
-8
15
Minimum clock
delay for back-to-
back random
t
CCD = 1
01
01
01
01
01
01
CLK
column address
16
17
18
Burst Length
supported
1, 2, 4, 8 & 8F
full page
8F
04
06
8F
04
06
8F
04
06
8F
04
06
8F
04
06
Number of SDRAM
banks
4
04
Supported CAS
Latencies
CAS
06
latency =
2 & 3
19
20
21
CS Latencies
WE Latencies
CS
latency = 0
01
01
00
01
01
00
01
01
00
01
01
00
01
01
00
01
01
00
Write
latency = 0
SDRAM DIMM
non
module attributes
buffered/
non reg.
22
23
SDRAM Device
Attributes: General 10%
V
CC tol ±
06
A0
06
06
A0
06
A0
06
06
A0
Min. Clock Cycle
Time at CAS
Latency = 2
10.0/12.0
ns
C0
C0
24
25
26
Max. data access
time from Clock for
CL = 2
6.0/7.0 ns 60
70
FF
FF
60
FF
FF
60
FF
FF
60
FF
FF
60
FF
FF
Minimum Clock
Cycle Time at
CL = 1
not
supported
FF
FF
Maximum Data
Access Time from
Clock at CL = 1
not
supported
27
28
Minimum Row
Precharge Time
20/30 ns
16/20 ns
14
10
1E
14
14
10
14
10
1E
14
14
10
Minimum Row
Active to Row
Active delay tRRD
Semiconductor Group
13
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
SPD-Table for PC100 Modules (cont’d)
Byte# Description
SPD
Hex
Entry
Value
8M×64 8M×64 8M×72 16M×64 16M×64 16M×72
-8
-8B
-8
-8
-8B
-8
29
30
31
32
33
34
35
Minimum RAS to
CAS delay tRCD
20 ns
14
14
14
14
2D
10
20
10
20
10
FF
14
14
2D
10
20
10
20
10
FF
Minimum RAS
pulse width tRAS
45 ns
2D
10
20
10
20
10
FF
2D
10
20
10
20
10
FF
2D
10
20
10
20
10
FF
2D
10
20
10
20
10
FF
Module Bank
Density (per bank)
64 MByte
SDRAM input setup 2 ns
time
SDRAM input hold
time
1 ns
SDRAM data input 2 ns
hold time
SDRAM data input 1 ns
setup time
62-61 Superset
information (may
–
be used in future)
62
63
SPD Revision
Revision
1.2
12
12
16
XX
12
12
12
17
XX
12
Checksum for
bytes 0 - 62
–
D8
XX
EA
XX
D9
XX
EB
XX
64-
125
Manufacturers
information
–
(optional)
(FFH if not used)
126
127
Frequency
Specification
100 MHz
64
AF
FF
64
64
AF
FF
64
FF
FF
64
FD
FF
64
FF
FF
100 MHz support
details
–
–
AD
FF
128+ Unused storage
locations
Semiconductor Group
14
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
SPD-Table for PC66 Modules
Byte# Description
SPD Entry Value
Hex
8M×64 8M×72 16M×64 16M×72
-10
-10
-10
-10
0
1
2
3
Number of SPD bytes
Total bytes in Serial PD
Memory Type
128
80
80
80
08
04
80
08
04
256
08
04
0C
08
04
0C
SDRAM
Number of Row Addresses 12
(without BS bits)
0C
0C
4
Number of Column
Addresses
9
09
09
09
09
(for x8 SDRAM)
5
6
7
8
9
Number of DIMM Banks
Module Data Width
1/2
01
40
00
01
A0
01
48
00
01
A0
02
40
00
01
A0
02
48
00
01
A0
64/72
0
Module Data Width (cont’d)
Module Interface Levels
LVTTL
10.0 ns
SDRAM Cycle Time at
CL = 3
10
11
12
SDRAM Access time from
Clock at C L= 3
8.0 ns
80
00
80
80
02
80
80
00
80
80
02
80
Dimm Config
(Error Det/Corr.)
none/ECC
Refresh Rate/Type
Self Refresh
15.6 µs
13
14
SDRAMwidth,Primary
×8
08
00
08
08
08
00
08
08
Error Checking SDRAM
data width
n/a/×8
15
Minimum clock delay for
back-to-back random
column address
t
CCD = 1 CLK
01
01
01
01
16
17
18
19
20
21
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
1, 2, 4, 8 & full page 8F
04
CAS latency = 2 & 3 06
8F
04
06
01
01
00
8F
04
06
01
01
00
8F
04
06
01
01
00
4
CS latency = 0
01
01
00
WE Latencies
Write latency = 0
SDRAM DIMM module
attributes
non buffered/
non reg.
Semiconductor Group
15
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
SPD-Table for PC66 Modules (cont’d)
Byte# Description
SPD Entry Value
Hex
8M×64 8M×72 16M×64 16M×72
-10
-10
-10
-10
22
23
24
25
26
27
28
29
30
31
SDRAM Device Attributes:
General
V
CC tol ± 10%
06
06
06
F0
90
06
F0
90
Min. Clock Cycle Time at
CAS Latency = 2
15.0 ns
F0
90
FF
FF
1E
14
1E
2D
10
F0
90
FF
FF
1E
14
1E
2D
10
Max. data access time from 9.0 ns
Clock for CL= 2
Minimum Clock Cycle Time not supported
at CL = 1
FF
FF
1E
14
1E
2D
10
FF
FF
1E
14
1E
2D
10
Maximum Data Access
Time from Clock at CL = 1
not supported
Minimum Row Precharge
Time
30 ns
Minimum Row Active to
Row Active delay tRRD
20 ns
Minimum RAS to CAS delay 30 ns
tRCD
Minimum RAS pulse width
tRAS
45 ns
Module Bank Density (per
bank)
64 MByte
32
33
34
35
SDRAM input setup time
SDRAM input hold time
3 ns
1 ns
30
10
30
10
30
10
30
10
30
10
30
10
30
10
30
10
SDRAM data input hold time 3 ns
SDRAM data input setup
time
1 ns
62-61 Superset information
(may be used in future)
FF
FF
FF
FF
62
63
SPD Revision
Revision 1.2
12
B0
XX
12
12
B1
XX
12
Checksum for bytes 0 - 62
C2
XX
C3
XX
64-
125
Manufacturers information
(optional)
(FFH if not used)
126
127
Frequency Specification
Details
66 MHz
66
AF
FF
66
AF
FF
66
FF
FF
66
FF
FF
128+ Unused storage locations
Semiconductor Group
16
1998-08-01
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
Package Outlines
L-DIM-168-30
SDRAM DIMM Module Package
133.35
127.35
4
*)
1
10
11
6.35
40
41
6.35
84
1.27±
0.1
3
1.27
42.18
91 x 1.27 = 115.57
124 125
2
85 94
95
168
*)
R1.27+0.1
3 min.
2.26
Detail of Contacts
*) on ECC modules only
1±
0.05
1.27
GLD09159
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
1998-08-01
SMD = Surface Mounted Device
Semiconductor Group
17
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