HYS64V64220GU-8-C [INFINEON]

Synchronous DRAM Module, 64MX64, 6ns, CMOS, DIMM-168;


型号：	HYS64V64220GU-8-C
厂家：	Infineon
描述：	Synchronous DRAM Module, 64MX64, 6ns, CMOS, DIMM-168 动态存储器内存集成电路
文件：	总23页 (文件大小：216K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYS 64/72V64220GU

SDRAM-Modules

3.3 V 64M × 64/72-Bit SDRAM Modules

168-pin Unbuffered DIMM Modules

• 168-pin unbuffered 8 Byte Dual-In-Line

SDRAM Modules for PC main memory

applications

• Single + 3.3 V (± 0.3 V) power supply

• Programmable CAS Latency, Burst Length,

and Wrap Sequence (Sequential &

Interleave)

• PC100 and PC133 versions

• Two bank 64M × 64 and 64M × 72

• Auto Refresh (CBR) and Self Refresh

• Decoupling capacitors mounted on substrate

• All inputs and outputs are LVTTL compatible

• Serial Presence Detect with E²PROM

organization

• Optimized for byte-write non-parity or ECC

applications

• Fully PC board layout compatible to INTEL’s

Rev. 1.0 module specification

• Uses Infineon 256 Mbit SDRAM components

in 32M × 8 organization and TSOPII-54

packages

• JEDEC standard Synchronous DRAMs

(SDRAM

• Gold contact pad, card size:

• Programmed Latencies:

133.35 mm × 31.75 mm × 4.00 mm

Product Speed

CL t_RCD

t_RP

-7.5

-8

PC133

PC100

-8A

-8B

• SDRAM Performance:

-7.5

-8

-8A

PC100

100

-8B

PC100

100

Unit

PC133

133

PC100

100

f_CK

t_AC

Clock Frequency (max.)

Clock Access time

MHz

5.4

The HYS 64V64220GU and HYS 72V64220GU are industry standard 168-pin 8-byte Dual in-line

Memory Modules (DIMMs) which are organized as 64M × 64 and 64M × 72 in two banks high speed

memory arrays designed with 256M Synchronous DRAMs (SDRAMs) for non-parity and ECC

applications. The DIMMs use 7-5 speed sorted 256 Mbit Synchronous DRAMs (SDRAMs) to meet

the PC133-333 requirements and -8, -8A and -8B components for the standard PC100 applications.

Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s

PC100 module specification. The DIMMs have a serial presence detect, implemented with a serial

E²PROM using the 2-pin I²C protocol. The first 128 bytes are utilized by the DIMM manufacturer

and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high

performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25“ (31.75 mm) height.

Data Book

3.00

HYS 64/72V64220GU

SDRAM-Modules

Ordering Information

Type

Code

Package

Descriptions

Module

Height

HYS 64V64220GU-7.5-A PC133-333-520 L-DIM-168-30 PC133 64M × 64 2 bank 1.25“

HYS 64V64220GU-7.5-C SDRAM module

HYS 72V64220GU-7.5-A PC133-333-520 L-DIM-168-30 PC133 64M × 72 2 bank 1.25“

HYS 72V64220GU-7.5-C

SDRAM module

HYS 64V64220GU-8-A

HYS 64V64220GU-8-C

PC100-222-620 L-DIM-168-30 PC100 64M × 64 2 bank 1.25“

SDRAM module

HYS 72V64220GU-8-A

HYS 72V64220GU-8-C

PC100-222-620 L-DIM-168-30 PC100 64M × 72 2 bank 1.25“

SDRAM module

HYS 64V64220GU-8A-A PC100-222-620 L-DIM-168-30 PC100 64M × 64 2 bank 1.25“

SDRAM module

HYS 72V64220GU-8A-A PC100-222-620 L-DIM-168-30 PC100 64M × 72 2 bank 1.25“

SDRAM module

HYS 64V64220GU-8B-A PC100-323-620 L-DIM-168-30 PC100 64M × 64 2 bank 1.25“

SDRAM module

HYS 72V64220GU-8B-A PC100-323-620 L-DIM-168-30 PC100 64M × 72 2 bank 1.25“

SDRAM module

Note: All part numbers end with a place code, designating the die revision. Consult factory for

current revision. Example: HYS 64V64220GU-8-A, indicating Rev.A dies are used for

SDRAM components.

Data Book

3.00

HYS 64/72V64220GU

SDRAM-Modules

Pin Definitions and Functions

A0 - A12

Address Inputs

Bank Selects

CLK0 - CLK3

Clock Input

BA0, BA1

DQMB0 - DQMB7 Data Mask

DQ0 - DQ63 Data Input/Output

CS0 - CS3

Chip Select

CB0 - CB7

RAS

Check Bits (x72 organization only) V_DD

Power (+ 3.3 V)

Ground

Row Address Strobe

Column Address Strobe

Read/Write Input

V_SS

CAS

SCL

SDA

Clock for Presence Detect

Serial Data Out for

Presence Detect

CKE0, CKE1 Clock Enable

N.C./DU

No Connection

Address Format

Part Number

Rows Columns Bank Select Refresh Period Interval

64M × 64/72 HYS64/72V64220GU 13

64 ms 7.8 µs

Pin Configuration

PIN# Symbol

V_SS

100

101

102

V_SS

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

V_SS

DQ0

DQ1

DQ2

DQ3

V_DD

DQ32

DQ33

DQ34

DQ35

V_DD

CKE0

CS3

CS2

DQMB2

DQMB3

DQMB6

DQMB7

N.C.

DQ4

DQ5

DQ6

DQ7

DQ8

V_SS

V_DD

DQ36

DQ37

DQ38

DQ39

DQ40

V_SS

V_DD

N.C.

N.C. (CB2)

N.C. (CB3)

V_SS

CB6

CB7

V_SS

DQ9

DQ10

DQ11

DQ12

DQ13

V_DD

DQ16

DQ17

DQ18

DQ19

V_DD

DQ41

DQ42

DQ43

DQ44

DQ45

V_DD

DQ48

DQ49

DQ50

DQ51

V_DD

DQ20

DQ52

Data Book

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HYS 64/72V64220GU

SDRAM-Modules

Pin Configuration (cont’d)

PIN# Symbol PIN# Symbol

PIN# Symbol

DQ14

DQ15

N.C. (CB0)

N.C. (CB1)

V_SS

N.C.

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

DQ46

DQ47

N.C. (CB4)

N.C. (CB5)

V_SS

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

N.C.

CKE1

V_SS

N.C.

V_SS

DQ21

DQ22

DQ23

V_SS

DQ53

DQ54

DQ55

V_SS

N.C.

V_DD

N.C.

V_DD

DQ24

DQ25

DQ26

DQ27

V_DD

CAS

DQMB4

DQMB5

CS1

DQ56

DQ57

DQ58

DQ59

V_DD

DQMB0

DQMB1

CS0

RAS

V_SS

DQ28

DQ29

DQ30

DQ31

V_SS

DQ60

DQ61

DQ62

DQ63

V_SS

CLK2

N.C.

CLK3

N.C.

SA0

A10

BA0

BA1

A11

V_DD

SDA

SCL

V_DD

SA1

V_DD

CLK1

A12

SA2

CLK0

V_DD

Note: Pin names in paranthese are for the x72 ECC versions; example: Pin 106 = (CB5)

Data Book

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HYS 64/72V64220GU

SDRAM-Modules

CS1

CS0

DQMB0

DQ(7:0)

DQM

DQMB4

DQM

DQ0-DQ7

DQ(39:32)

DQ0-DQ7

D12

D13

DQMB1

DQM

DQMB5

DQM

DQ(15:8)

DQ0-DQ7

DQ(47:40)

DQ0-DQ7

DQM

DQ0-DQ7

CB(7:0)

DQ0-DQ7

D16

D17

CS3

CS2

DQMB2

DQM

DQMB6

DQM

DQ(23:16)

DQ0-DQ7

DQ(55:48)

DQ0-DQ7

D10

D11

D14

D15

DQMB3

DQM

DQMB7

DQM

DQ(31:24)

DQ0-DQ7

DQ(63:56)

DQ0-DQ7

A0-A12, BA0, BA1

V_DD

D0-D15, (D16, D17)

E²PROM (256 Word x 8 Bit)

SA0

SA1

SA2

SCL

SA1

SA2

SCL

SDA

C0-C31, (C32...C35)

V_SS

D0-D7, (D8)

47 k

Ω

RAS, CAS, WE

CKE0

D0-D15, (D16, D17)

Clock Wiring

64 M x 64

D0-D7, (D16)

D9-D15, (D17)

V_DD

10 k

64 M x 72

5 SDRAM

4 SDRAM + 3.3 pF

Ω

CLK0

4 SDRAM + 3.3 pF

CLK1

CLK2

CLK3

CKE1

Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ω except otherwise noted.

SPB03971

Block Diagram: 64M × 64/72 Two Bank SDRAM DIMM Modules

Data Book

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HYS 64/72V64220GU

SDRAM-Modules

DC Characteristics

T_A= 0 to 70 °C; V_SS= 0 V; V_DD,V_DDQ= 3.3 V ± 0.3 V

Parameter

Symbol

Limit Values

max.

Unit

min.

2.0

Input High Voltage

V_IH

V_IL

_DD+ 0.3

Input Low Voltage

– 0.5

2.4

0.8

–

Output High Voltage (I_OUT= – 4.0 mA)

Output Low Voltage (I_OUT= 4.0 mA)

V_OH

V_OL

I_I(L)

–

0.4

Input Leakage Current, any input

– 40

µA

(0 V < V_IN< 3.6 V, all other inputs = 0 V)

Output Leakage Current

I_O(L)

– 40

µA

(DQ is disabled, 0 V < V_OUT< V_DD)

Capacitance

T_A= 0 to 70 °C; V_DD= 3.3 V ± 0.3 V, f = 1 MHz

Parameter

Symbol

Limit Values

max.

Unit

max.

64M × 64

64M × 72

Input Capacitance

C_I1

105

144

(A0 to A11, BA0, BA1, RAS, CAS, WE)

Input Capacitance (CS0 - CS3)

Input Capacitance (CLK0 - CLK3)

Input Capacitance (CKE0, CKE1)

Input Capacitance (DQMB0 - DQMB7)

C_I2

C_ICL

C_I3

C_I4

C_IO

Input/Output Capacitance

(DQ0 - DQ63, CB0 - CB7)

Input Capacitance (SCL, SA0-2)

Input/Output Capacitance

C_SC

C_SD

Data Book

3.00

HYS 64/72V64220GU

SDRAM-Modules

Operating Currents per SDRAM Component ¹⁾

T_A= 0 to 70 ^oC, V_DD= 3.3 V ± 0.3 V

(Recommended Operating Conditions unless otherwise noted)

Parameter

Test

Symbol -7.5 -8/-8A/-8B Unit Note

Condition

max.

Operating current

–

I_CC1

270 210

t_RC= t_RC(MIN.), t_CK= t_CK(MIN.)

Outputs open, Burst Length = 4, CL = 3

All banks operated in random access,

all banks operated in ping-pong manner

to maximize gapless data access

Precharge stand-by current

in Power Down Mode

_CK= min.

I_CC2P

CS = V_IH(MIN.), CKE ≤ V_IL(MAX.)

Precharge Stand-by Current

in Non-Power Down Mode

I_CC2N

CS = V_{IH (MIN.)}, CKE ≥ V_IH(MIN.)

No operating current

CKE ≥ V_IH(MIN.)I_CC3N

CKE ≤ V_IL(MAX.)I_CC3P

t_CK= min., CS = V_IH(MIN.),

active state (max. 4 banks)

1), 2)

Burst operating current

–

I_CC4

I_CC5

I_CC6

270 210

240 240

2.5 2.5

t_CK= min.,

Read command cycling

Auto refresh current

t_CK= min.,

Auto Refresh command cycling

Self refresh current

Self Refresh Mode, CKE = 0.2 V

Data Book

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HYS 64/72V64220GU

SDRAM-Modules

3), 4)

AC Characteristics

T_A= 0 to 70 °C; V_SS= 0 V; V_DD= 3.3 V ± 0.3 V, t_T= 1 ns

Parameter

Symbol

Limit Values

Unit Note

-7.5

-8

PC133-333

PC100-222

min.

max.

min.

max.

Clock

Clock Cycle Time

t_CK

–

CAS Latency = 3

CAS Latency = 2

7.5

–

System Frequency

f_CK

–

CAS Latency = 3

CAS Latency = 2

–

133

–

100

MHz

for HYS64/72V64220GU-7.5-A

for HYS64/72V64220GU-7.5-C

–

100

–

100

MHz *)

4), 5)

Clock Access Time

CAS Latency = 3

CAS Latency = 2

t_AC

–

5.4

–

Clock High Pulse Width

Clock Low Pulse Width

t_CH

t_CL

2.5

–

Setup and Hold Times

Input Setup Time

t_CS

t_CH

t_SB

1.5

0.8

–

Input Hold Time

Power Down Mode Entry Time

CLK

Power Down Mode Exit Setup Time t_PDE

CLK

Mode Register Setup Time

Transition Time (rise and fall)

t_RSC

t_T

CLK

–

Common Parameters

RAS to CAS Delay

Precharge Time

t_RCD

t_RP

t_RAS

t_RC

67.5

–

Active Command Period

Cycle Time

100k

–

Bank to Bank Delay Time

t_RRD

CAS to CAS Delay Time (same bank) t_CCD

CLK

Data Book

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HYS 64/72V64220GU

SDRAM-Modules

AC Characteristics (cont’d) ^{3), 4)}

T_A= 0 to 70 °C; V_SS= 0 V; V_DD= 3.3 V ± 0.3 V, t_T= 1 ns

Parameter

Symbol

Limit Values

Unit Note

-7.5

-8

PC133-333

PC100-222

min.

max.

min.

max.

Refresh Cycle

Refresh Period (8192 cycles)

Self Refresh Exit Time

t_REF

–

10)

t_SREX

CLK

Read Cycle

Data Out Hold Time

t_OH

t_LZ

–

Data Out to Low Impedance

Data Out to High Impedance

DQM Data Out Disable Latency

–

11)

t_HZ

t_DQZ

CLK

–

Write Cycle

Data Input to Precharge

(write recovery)

t_WR

–

CLK

–

DQM Write Mask Latency

t_DQW

Data Book

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HYS 64/72V64220GU

SDRAM-Modules

3), 4)

AC Characteristics

T_A= 0 to 70 °C; V_SS= 0 V; V_DD= 3.3 V ± 0.3 V, t_T= 1 ns

Parameter

Symbol

Limit Values

Unit Note

-8A

-8B

PC100-322

PC100-323

min.

max.

min.

max.

Clock and Access Time

Clock Cycle Time

CAS Latency = 3

CAS Latency = 2

t_CK

f_CK

t_AC

–

System Frequency

CAS Latency = 3

CAS Latency = 2

–

MHz

–

100

–

100

MHz

4), 5)

Access Time from Clock

CAS Latency = 3

–

CAS Latency = 2

Clock High Pulse Width

Clock Low Pulse Width

t_CH

t_CL

–

Setup and Hold Parameters

Input Setup Time

t_IS

–

Input Hold Time

t_IH

t_SB

Power Down Mode Entry Time

CLK

Power Down Mode Exit Setup Time t_PDE

CLK

Mode Register Setup Time

Transition Time (rise and fall)

t_RSC

t_T

CLK

–

Common Parameters

Row to Column Delay Time

Row Precharge Time

Row Active Time

t_RCD

t_RP

t_RAS

t_RC

–

100k

Row Cycle Time

–

Activate (a) to Activate (b) Command t_RRD

Period

CAS(a) to CAS(b) Command Period t_CCD

–

CLK

–

Data Book

3.00

HYS 64/72V64220GU

SDRAM-Modules

AC Characteristics (cont’d) ^{3), 4)}

T_A= 0 to 70 °C; V_SS= 0 V; V_DD= 3.3 V ± 0.3 V, t_T= 1 ns

Parameter

Symbol

Limit Values

Unit Note

-8A

-8B

PC100-322

PC100-323

min.

max.

min.

max.

Refresh Cycle

Refresh Period (8192 cycles)

Self Refresh Exit Time

t_REF

–

10)

t_SREX

CLK

Read Cycle

Data Out Hold Time

t_OH

t_LZ

–

Data Out to Low Impedance Time

Data Out to High Impedance Time

DQM Data Out Disable Latency

–

11)

t_HZ

t_DQZ

CLK

–

Write Cycle

Data Input to Precharge

(write recovery)

t_WR

–

CLK

–

DQM Write Mask Latency

t_DQW

Notes

1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7.5

modules and at 100 Mhz for -8 modules. Input signals are changed once during t_CK, except for

_CC6and for standby currents when t_CK= infinity. All values are shown per memory component.

2. These parameters are measured with continuous data stream during read access and all DQ

toggling. CL = 3 and BL = 4 assumed and the V_DDQcurrent is excluded.

3. All AC characteristics are shown on SDRAM component level.

An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must

be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation

can begin.

4. AC timing tests have V_IL= 0.4 V and V_IH= 2.4 V with the timing referenced to the 1.4 V crossover

point. The transition time is measured between V_IHand V_IL. All AC measurements assume

t_T= 1 ns with the AC output load circuit show. Specified t_ACand t_OHparameters are measured

with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate

between 0.8 V and 2.0 V.

5. If clock rising time is longer than 1 ns, a time (t_T/2 – 0.5) ns must be added to this parameter.

6. Rated at 1.4 V

Data Book

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HYS 64/72V64220GU

SDRAM-Modules

7. If t_Tis longer than 1 ns, a time (t_T– 1) ns has to be added to this parameter.

8. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)

commands must be given to “wake-up” the device.

9. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal

is assumed latched on the next cycle.

10.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after

CKE returns high. Self-Refresh Exit is not complete until a time period equal to t_RCis satisfied

after the Self Refresh Exit command is registered.

11.This is referenced to the time at which the output achieves the open circuit condition, not to

output voltage levels.

t_CH

2.4 V

0.4 V

CLOCK

t_T

t_CL

t_HOLD

t_SETUP

INPUT

1.4 V

t_AC

I/O

t_LZ

t_OH

50 pF

OUTPUT

1.4 V

Measurement conditions for

_ACand t_OH

t_HZ

SPT03404

Note: *) 256MByte PC133 modules with place code “-C” indicating Rev. C dies are used as memory

components are fully PC100 2-2-2 backwards compatible, where PC133 modules with place code

“-A” operates as PC100 3-2-2 on a 100 Mhz memory bus.

A serial presence detect storage device - E²PROM - is assembled onto the module. Information

about the module configuration, speed, etc. is written into the E²PROM device during module

production using a serial presence detect protocol (I²C synchronous 2-wire bus).

Data Book

3.00

HYS 64/72V64220GU

SDRAM-Modules

SPD-Table for PC133 Modules

Byte# Description

SPD Entry Value

Hex

64M × 64 64M × 72

-7.5

Number of SPD Bytes

Total Bytes in Serial PD

Memory Type

128

256

SDRAM

Number of Row Addresses (without BS

bits)

Number of Column Addresses

Number of DIMM Banks

Module Data Width

64/72

Module Data Width (cont’d)

Module Interface Levels

SDRAM Cycle Time at CL = 3

LVTTL

7.5 ns

SDRAM Access Time from Clock at CL = 3 5.4 ns

DIMM Config

none/ECC

Refresh Rate/Type

Self-Refresh, 7.8 µs

SDRAM Width, Primary

Error Checking SDRAM Data Width

Minimum Clock Delay for Back-to-Back

Random Column Address

Burst Length Supported

Number of SDRAM Banks

Supported CAS Latencies

CS Latencies

n/a/x8

t_CCD= 1 CLK

1, 2, 4 & 8

CAS latency = 2 & 3 06

CS latency = 0

WE Latencies

Write latency = 0

SDRAM DIMM Module Attributes

SDRAM Device Attributes: General

non buffered/non reg. 00

_DDtol +/– 10%

Min. Clock Cycle Time at CAS Latency = 2 12.0 ns

for HYS64//72V64220GU-7.5-A

Min. Clock Cycle Time at CAS Latency = 2 10.0 ns

for HYS64//72V64220GU-7.5-C

Max. Data Access Time from Clock for

CL = 2

6.0 ns

Minimum Clock Cycle Time at CL = 1

not supported

Maximum Data Access Time from Clock at not supported

CL = 1

Minimum Row Precharge Time

20 ns

Minimum Row Active to Row Active Delay 15

t_RRD

Minimum RAS to CAS Delay t_RCD

Minimum RAS Pulse Width t_RAS

20 ns

45 ns

Data Book

3.00

HYS 64/72V64220GU

SDRAM-Modules

SPD-Table for PC133 Modules (cont’d)

Byte# Description

SPD Entry Value

Hex

64M × 64 64M × 72

-7.5

Module Bank Density (per bank)

SDRAM Input Setup Time

256 MByte

1.5 ns

0.8 ns

1.5 ns

0.8 ns

–

SDRAM Input Hold Time

SDRAM Data Input Hold Time

SDRAM Data Input Setup Time

36-61 Superset Information (may be used in

future)

SPD Revision

Revision 1.2

–

Checksum for Bytes 0 - 62

for HYS64/72V64220GU-7.5-A

Checksum for Bytes 0 - 62

for HYS64/72V64220GU-7.5-C

–

64-125 Manufacturers Information

(FF_Hif not used)

126

127

Frequency Specification

100 MHz Support Details

for HYS64/72V64220GU-7.5-A

for HYS64/72V64220GU-7.5-C

Unused Storage Locations

–

128+

Data Book

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HYS 64/72V64220GU

SDRAM-Modules

SPD-Table for PC100 Modules

Byte# Description

SPD Entry

Value

Hex

Number of SPD Bytes

Total Bytes in Serial PD

Memory Type

128

256

SDRAM

Number of Row Addresses

(without BS bits)

Number of Column Addresses 10

Number of DIMM Banks

Module Data Width

64/72

Module Data Width (cont’d)

Module Interface Levels

LVTTL

SDRAM Cycle Time at CL = 3 10.0 ns

SDRAM Access Time from

Clock at CL = 3

6.0 ns

DIMM Config

none/ECC

Self-Refresh,

7.8 µs

Refresh Rate/Type

SDRAM Width, Primary

Error Checking SDRAM Data n/a/x8

Width

Minimum Clock Delay for

Back-to-Back Random

Column Address

_CCD= 1 CLK

Burst Length Supported

Number of SDRAM Banks

Supported CAS Latencies

1, 2, 4 & 8

CAS latency = 2 06

& 3

CS Latencies

CS latency = 0

WE Latencies

Write latency = 0 01

nonbuffered/non 00

reg.

SDRAM DIMM Module

Attributes

SDRAM Device Attributes:

General

_DDtol +/– 10% 0E

Min. Clock Cycle Time at CAS 10.0/15.0 ns

Latency = 2

Max. Data Access Time from 6.0/7.0 ns

Clock for CL = 2

Minimum Clock Cycle Time at not supported

CL = 1

Data Book

3.00

HYS 64/72V64220GU

SDRAM-Modules

SPD-Table for PC100 Modules

Byte# Description

SPD Entry

Value

Hex

Maximum Data Access Time not supported

from Clock at CL = 1

Minimum Row Precharge

Time

20/30 ns

Minimum Row Active to Row 16/20 ns

Active Delay t_RRD

Minimum RAS to CAS Delay 20 ns

t_RCD

Minimum RAS Pulse Width

t_RAS

50/60 ns

Module Bank Density (per

bank)

256 MByte

SDRAM Input Setup Time

SDRAM Input Hold Time

SDRAM Data Input Setup

Time

2 ns

1 ns

2 ns

SDRAM Data Input Hold Time 1 ns

36-61 Superset Information (may be –

used in future)

SPD Revision

Revision 1.2

Checksum for Bytes 0 - 62

–

64-125 Manufacturers Information

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126

Frequency Specification

100 MHz Support Details

Unused Storage Locations

100 MHz

127

–

128+

Data Book

3.00

HYS 64/72V64220GU

SDRAM-Modules

Package Outlines

L-DIM-168-30

SDRAM DIMM Module Package

HYS 64/72V64220GU

133.35

127.35

6.35

1.27^±

0.1

1.27

42.18

91 x 1.27 = 115.57

124 125

85 94

168

R1.27^+0.1

3 min.

2.26

Detail of Contacts

*) on ECC modules only

1^±

0.05

1.27

GLD09159

Data Book

3.00

CODES FOR DIE REVISION

ON COMPONENTS AND DIMM MODULES

Introduction of Module Partnumber Extensions

and “functional label”

NEW MODULE LABELS WITH INFINEON LOGO

MP TM, May. 2000

Rev. 1.3

Weidlich, MP TM

Memory Products Division

Always a step ahead

Weidlich, HL MP TM

Aprl99MODULE_LABEL_generic.DOC/2

Component Partnumber, Die Rev. Indicators, Module Partnumber Extensions

for INFINEON SDRAM COMPONENTS & MODULE PRODUCTS:

64M-SDRAM:

Generation

Die Rev. Indicator

Component Partnumber

Module Partnumber

Extension

(for new module labels)

S24

S20

S19

S17

S17N

“A”

“B”

“C”

“D

HYB39S64xxxAT-x

HYB39S64xxxBT-x

HYB39S64xxxCT-x

HYB39S64xxxDT-x

HYB39S64xxxET-x

-A

-B

-C

-D

-E

“E”

256M-SDRAM:

S20

S19

S17

S14

“A”

“B”

“C2”

“D

HYB39S256xxxT-x

HYB39S256xxxAT-x

HYB39S256xxxCT-x

HYB39S256xxxDT-x

-A

-B

-C2

-D

**)

*) since the Baunumbers are allready fixed, we have to live with this inconsistancy

**) starting with Step DD3D

128M-SDRAM:

S17

“C2”

HYB39S128xxxCT-x

“C2”

*) starting with Step DD2B

Memory Products Division

Always a step ahead

Weidlich, HL MP TM

Aprl99MODULE_LABEL_generic.DOC/3

Component Partnumber, Die Rev. Indicators, Module Partnumber Extensions

for INFINEON SDRAM COMPONENTS & MODULE PRODUCTS (cont’d):

256M-DDR-SDRAM:

D17 (ASTC)

D17 (WOS)

D14

none

“A”

“B”

HYB25D256xxxT-x

HYB25D256xxxAT-x

HYB25D256xxxBT-x

none

“A”

“B”

Memory Products Division

Always a step ahead

Weidlich, HL MP TM

Aprl99MODULE_LABEL_generic.DOC/4

What is the partnumber and the partnumber extension ?

· The current partnumbers for SDRAM modules do not show any indicator for the die

revision of the SDRAM components.

· A partnumber extension has been added to indicate the die revision of the used

components on the SDRAM modules

· The partnumber extensions consists of 3 digits, beginning with a “dash” and two

alphanumerics, the “die revision indicator”.

· The nomenclature of the die shrink indicator can be seen in the next foil for all

SDRAM products.

· On all INFINEON SDRAM DIMM module datasheets the following note on page 2

has been added:

“All part numbers end with a place code (not shown), designating the die revision. Consult factory for current

revision. Example: HYS72V16220GU-7.5-B, indicating Rev.B dies are used for SDRAM components.”

Example:

HYS72V16220GU-7.5 –B

Partnumber

Extension

Partnumbe

Memory Products Division

Always a step ahead

Weidlich, HL MP TM

Aprl99MODULE_LABEL_generic.DOC/5

NEW LABELS (starting from Nov.’99)

64M-SDRAM BASED MODULES

IDENTIFICATION OF DIE SHRINKS, PCB BOARD REVISION & MANUFACTURER

Example:

HYS72V16220GU-8-B 16Mx72 SDRAM

B22xxxxxxx

Assembled in Germany

128MB, SYNC, 100 MHz, CL2, ECC

PC100-222-620

“Functional Label

Module Manufacturer

2 = SIEMENS EWK

5 = SMART (UK)

4 = OPTOSYS

6 = SMART (USA)

7 = STATSYM

8 = EEMS

A = CELESTICA

S = DRESDEN

V = PORTO

R = Regensburg

W= White OAK

Designstep of 64M SDRAM:

A = S24

PCB board revision:

1 = first

B = S20

C = S19

D = S17

2 =second etc.

9 = KINGSTON

Memory Products Division

Always a step ahead

Weidlich, HL MP TM

Aprl99MODULE_LABEL_generic.DOC/6

NEW 256Mbit based SDRAM MODULE LABELS:

EXAMPLE : 512MByte unbuffered PC100 CL 323 DIMM Module based on S20 256Mbit SDRAM

HYS72V64220GU-8B-A 64Mx72 SDRAM

New labels

A2299201222

Assembled in Germany

512MB, SYNC, 100 MHz, CL3, ECC

PC100-323-620

“Functional Label

Module Manufacturer

Designstep of 256M SDRAM:

A = S20

PCB board revision:

1 = first

2 = SIEMENS EWK

5 = SMART (UK)

4 = OPTOSYS

6 = SMART (USA)

7 = STATSYM

8 = EEMS

A = CELESTICA

S = DRESDEN

V = PORTO

R = Regensburg

W= White OAK

B = S19

C = S17

D = S15

2 =second etc.

9 = KINGSTON

Memory Products Division

Always a step ahead

Weidlich, HL MP TM

Aprl99MODULE_LABEL_generic.DOC/7

HYS64V64220GU-8-C [INFINEON]

相关型号：

HYS64V64220GU-8-C2

HYS64V64220GU-8A

HYS64V64220GU-8A-A

HYS64V64220GU-8B

HYS64V64220GU-8B-A

HYS64V8000GCD-8

HYS64V8000GCDL-8

HYS64V8000GD-8

HYS64V8000GDL-10

HYS64V8000GDL-8

HYS64V8000GU

HYS64V8000GU-10