HYS72D64300HBR-6-B [INFINEON]
DDR DRAM Module, 64MX72, 0.7ns, CMOS, DIMM-184;
| 型号： | HYS72D64300HBR-6-B |
| 厂家： | 
Infineon |
| 描述： | DDR DRAM Module, 64MX72, 0.7ns, CMOS, DIMM-184 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总48页 (文件大小：1197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.1, Apr. 2004
HYS72D32300GBR–[5/6/7]–B
HYS72D643[00/20]GBR–[5/6/7]–B
HYS72D128320GBR–[5/6/7]–B
184 - Pin Registered Double Data Rate SDRAM
Modules
Reg DIMM
DDR SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
Edition 2004-04
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, Rev. 1.1, Apr. 2004
HYS72D32300GBR–[5/6/7]–B
HYS72D643[00/20]GBR–[5/6/7]–B
HYS72D128320GBR–[5/6/7]–B
184 - Pin Registered Double Data Rate SDRAM
Modules
Reg DIMM
DDR SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
HYS72D32300GBR–[5/6/7]–B HYS72D643[00/20]GBR–[5/6/7]–B HYS72D128320GBR–[5/6/7]–B
HYS72D643[00/20]GBR–[5/6/7]–B HYS72D128320GBR–[5/6/7]–B
Revision History:
Rev. 1.1
2004-04
Previous Version:
Rev. 1.0
2003-12
Page
21,22
Subjects (major changes since last revision)
Registerd and PLL current added
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc.mp@infineon.com
Template: mp_a4_v2.2_2003-10-07.fm
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4
5
6
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Data Sheet
5
Rev. 1.1, 2004-04
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Overview
1
Overview
1.1
Features
•
184-Pin Registered 8-Byte Dual-In-Line
DDR SDRAM Module for “1U” PC, Workstation and Server main memory applications
One rank 32M × 72, 64M × 72 and two ranks 64M × 72, 128M × 72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V (± 0.2 V) power
supply and a single + 2.6 V (± 0.1 V) power supply for DDR400
Built with 256-Mbit DDR-I SDRAMs in P-TFBGA-60-1 packages
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
•
•
•
•
•
•
•
•
•
All inputs and outputs SSTL_2 compatible
Re-drive for all input signals using register and PLL devices.
Serial Presence Detect with E2PROM
Low Profile Modules form factor:
128.95 mm × 28.58 mm × 4.00 mm
133.35 mm × 30.48 mm (1.2”) × 4.00 mm (6.80 mm with stacked components)
JEDEC standard reference layout for one rank 256MB and 512MB, two ranks 512MB and 1GByte:
PC2700 Registered DIMM Raw Cards A,B,C,D
•
•
Gold plated contacts
Table 1
Performance
Part Number Speed Code
Speed Grade Component
Module
-5
–6
-7
Unit
—
DDR400B
PC3200-3033
200
DDR333B
PC2700–2533
166
DDR266A
PC2100-2033
—
max. Clock
Frequency
@CL3
@CL2.5
@CL2
fCK3
–
MHz
MHz
MHz
fCK2.5
fCK2
166
166
143
133
133
133
1.2
Description
The HYS72D[32/64/128]3[00/20]GBR are low profile versions of the standard Registered DIMM modules with
less/equal 1.2” inch (30.48 mm) height for 1U Server Applications. The Low Profile DIMM versions are available
as 32M × 72 (256MB), 64M × 72 (512MB) and 128M × 72 (1 GB).
The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors
are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using
the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
available to the customer.
Data Sheet
6
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Overview
Table 2
Type
Ordering Information
Compliance Code
Description
SDRAM Technology
PC3200 (CL = 3, tRP = tRCD = 3 at tCK = 5ns)
HYS72D32300GBR–5–B PC3200R-30330-A
one rank 256 MB Registered 256 Mbit (×8)
DIMM
HYS72D64300GBR–5–B PC3200R-30330-C
HYS72D64320GBR–5–B PC3200R-30330-B
HYS72D128320GBR–5–B PC3200R-30331-D
one rank 512 MB Registered 256 Mbit (×4)
DIMM
two ranks 512 MB Registered 256 Mbit (×8)
DIMM
two ranks 1 GB Registered
DIMM
256 Mbit (×4)
PC2700 (CL = 2.5, tRP = tRCD = 3 at tCK = 6ns)
HYS72D32300GBR–6–B PC2700R-25330-A
one rank 256 MB Registered 256 Mbit (×8)
DIMM
HYS72D64300GBR–6–B PC2700R-25330-C
HYS72D64320GBR–6–B PC2700R-25330-B
HYS72D128320GBR–6–B PC2700R-25330-D
one rank 512 MB Registered 256 Mbit (×4)
DIMM
two ranks 512 MB Registered 256 Mbit (×8)
DIMM
two ranks 1 GB Registered
DIMM
256 Mbit (×4)
PC2100 (CL = 2, tRP = tRCD = 3 at tCK = 7.5ns)
HYS72D32300GBR–7–B PC2100R-20330-A
one rank 256 MB Registered 256 Mbit (×8)
DIMM
HYS72D64300GBR–7–B PC2100R-20330-C
HYS72D64320GBR–7–B PC2100R-20330-B
HYS72D128320GBR–7–B PC2100R-20330-D
one rank 512 MB Registered 256 Mbit (×4)
DIMM
two ranks 512 MB Registered 256 Mbit (×8)
DIMM
two ranks 1 GB Registered
DIMM
256 Mbit (×4)
Note: All “product type” end with a place code designating the silicon-die revision. Reference information available
on request. Example: HYS72D64300GR-5-B, indicating rev. C dies are used for SDRAM components. The
“compliance code” is printed on the module labels describing the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “20330” means CAS latency of 2.0 clocks, RCD1) latency of
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
2
Pin Configuration
The pin configuration of the Registered DDR SDRAM Table 3
DIMM is listed by function in Table 3 (184 pins). The
abbreviations used in columns Pin and Buffer Type are
explained in Table 4 and Table 5 respectively. The pin
Pin Configuration of RDIMM (cont’d)
Buffer Function
Type Type
Pin# Name Pin
125 A6
I
I
I
I
I
I
I
I
SSTL Address Bus 11:0
numbering is depicted in Figure 1.
29
122 A8
27 A9
A7
SSTL
SSTL
Table 3
Pin Configuration of RDIMM
SSTL
Pin# Name Pin
Buffer Function
Type Type
141 A10
AP
SSTL
Clock Signals
137 CK0
SSTL
I
I
I
I
SSTL Clock Signal
118 A11
115 A12
SSTL
138 CK0
SSTL Complement Clock
SSTL Clock Enable Rank 0
SSTL Clock Enable Rank 1
Note: 2-rank module
SSTL Address Signal 12
21
CKE0
Note: Module based on
256 Mbit or larger
dies
111 CKE1
NC
NC
I
–
Note: 128 Mbit based
module
NC
NC
SSTL Note: 1-rank module
Control Signals
167 A13
SSTL Address Signal 13
157 S0
158 S1
I
I
SSTL Chip Select of Rank 0
SSTL Chip Select of Rank 1
Note: 2-ranks module
Note: 1 Gbit based
module
NC
NC
–
Note: Module based on
512 Mbit or
NC
NC
–
Note: 1-rank module
smaller dies
154 RAS
I
I
SSTL Row Address Strobe
65
CAS
SSTL Column Address
Strobe
63
10
WE
I
SSTL Write Enable
RESET I
LV-
Register Reset
CMOS Forces registered
inputs low
Note: For detailed
description of the
Power Up and
Power
Management see
the Application
Note at the end of
data sheet
Address Signals
59
52
48
43
41
BA0
BA1
A0
I
I
I
I
I
I
I
I
SSTL Bank Address Bus
1:0
SSTL
SSTL Address Bus 11:0
A1
SSTL
A2
SSTL
130 A3
SSTL
37
32
A4
A5
SSTL
SSTL Address Bus 11:0
Data Sheet
8
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
Table 3
Pin Configuration of RDIMM (cont’d)
Table 3
Pin Configuration of RDIMM (cont’d)
Pin# Name Pin
Buffer Function
Pin# Name Pin
Buffer Function
Type Type
Type Type
Data Signals
150 DQ38 I/O
151 DQ39 I/O
SSTL Data Bus 63:0
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL Data Bus 63:0
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
4
61
64
68
69
DQ40 I/O
DQ41 I/O
DQ42 I/O
DQ43 I/O
SSTL
6
SSTL
8
SSTL
94
95
98
99
12
13
19
20
SSTL
153 DQ44 I/O
155 DQ45 I/O
161 DQ46 I/O
162 DQ47 I/O
SSTL
SSTL
SSTL
SSTL
72
73
79
80
DQ48 I/O
DQ49 I/O
DQ50 I/O
DQ51 I/O
SSTL
DQ10 I/O
DQ11 I/O
SSTL
SSTL
105 DQ12 I/O
106 DQ13 I/O
109 DQ14 I/O
110 DQ15 I/O
SSTL
165 DQ52 I/O
166 DQ53 I/O
170 DQ54 I/O
171 DQ55 I/O
SSTL
SSTL
SSTL
23
24
28
31
DQ16 I/O
DQ17 I/O
DQ18 I/O
DQ19 I/O
SSTL
83
84
87
88
DQ56 I/O
DQ57 I/O
DQ58 I/O
DQ59 I/O
SSTL
SSTL
SSTL
114 DQ20 I/O
117 DQ21 I/O
121 DQ22 I/O
123 DQ23 I/O
SSTL
174 DQ60 I/O
175 DQ61 I/O
178 DQ62 I/O
179 DQ63 I/O
SSTL
SSTL
SSTL
33
35
39
40
DQ24 I/O
DQ25 I/O
DQ26 I/O
DQ27 I/O
SSTL
44
45
49
51
CB0
CB1
CB2
CB3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL Check Bits 7:0
SSTL
SSTL
126 DQ28 I/O
127 DQ29 I/O
131 DQ30 I/O
133 DQ31 I/O
SSTL
134 CB4
135 CB5
142 CB6
144 CB7
SSTL
SSTL
SSTL
53
55
57
60
DQ32 I/O
DQ33 I/O
DQ34 I/O
DQ35 I/O
SSTL
5
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
DQS5 I/O
SSTL Data Strobes 8:0
Note: See block
diagram for
14
25
36
56
67
SSTL
SSTL
SSTL
SSTL
SSTL
corresponding
DQ signals
146 DQ36 I/O
147 DQ37 I/O
Data Sheet
9
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
Table 3
Pin# Name Pin
Type Type
Pin Configuration of RDIMM (cont’d)
Table 3
Pin Configuration of RDIMM (cont’d)
Buffer Function
Pin# Name Pin
Buffer Function
Type Type
78
86
47
97
DQS6 I/O
DQS7 I/O
DQS8 I/O
SSTL Data Strobes 8:0
SSTL
EEPROM
92
91
SCL
SDA
I
CMOS Serial Bus Clock
SSTL
I/O
OD
Serial Bus Data
DM0
DQS9 I/O
107 DM1
DQS10 I/O
I
SSTL Data Mask 0
Note: ×8 based module
SSTL Data Strobe 9
Note: ×4 based module
SSTL Data Mask 1
Note: ×8 based module
SSTL Data Strobe 10
Note: ×4 based module
SSTL Data Mask 2
Note: ×8 based module
SSTL Data Strobe 11
Note: ×4 based module
SSTL Data Mask 3
Note: ×8 based module
SSTL Data Strobe 12
Note: ×4 based module
SSTL Data Mask 4
Note: ×8 based module
SSTL Data Strobe 13
Note: ×4 based module
SSTL Data Mask 5
Note: ×8 based module
SSTL Data Strobe 14
Note: ×4 based module
SSTL Data Mask 6
Note: ×8 based module
SSTL Data Strobe 15
Note: ×4 based module
SSTL Data Mask 7
Note: ×8 based module
SSTL Data Strobe 16
Note: ×4 based module
SSTL Data Mask 8
Note: ×8 based module
SSTL Data Strobe 17
Note: ×4 based module
181 SA0
182 SA1
183 SA2
I
I
I
CMOS Slave Address Select
Bus 2:0
CMOS
CMOS
Power Supplies
VREF AI
184 VDDSPD PWR –
I
1
–
I/O Reference Voltage
EEPROM Power
Supply
15, VDDQ
22,
30,
54,
62,
PWR –
I/O Driver Power
Supply
119 DM2
I
DQS11 I/O
77,
96,
129 DM3
I
104,
112,
128,
136,
143,
156,
164,
172,
180
DQS12 I/O
149 DM4
I
DQS13 I/O
7,
VDD
PWR –
Power Supply
159 DM5
I
38,
46,
70,
85,
108,
120,
148,
168
DQS14 I/O
169 DM6
I
DQS15 I/O
177 DM7
I
DQS16 I/O
140 DM8
I
DQS17 I/O
Data Sheet
10
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
Table 3
Pin# Name Pin
Type Type
Pin Configuration of RDIMM (cont’d)
Table 4
Abbreviations for Pin Type
Buffer Function
Abbreviation Description
I
Standard input-only pin. Digital levels.
3,
VSS
GND
–
Ground Plane
O
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
11,
18,
26,
I/O
AI
34,
42,
50,
58,
PWR
GND
NU
NC
Power
Ground
Not Usable (JEDEC Standard)
Not Connected (JEDEC Standard)
66,
74,
81,
89,
Table 5
Abbreviations for Buffer Type
Abbreviation Description
93,
100,
116,
124,
132,
139,
145,
152,
160,
176
SSTL
Serial Stub Terminalted Logic (SSTL2)
LV-CMOS
CMOS
OD
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding pin has 2
operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.
Other Pins
82
VDDID
O
OD
VDD Identification
Note: Pin in tristate,
indicating VDD
and VDDQ nets
connected on
PCB
9,
NC
NC
–
Not connected
16,
17,
Pins not connected on
Infineon RDIMM’s
71,
75,
76,
90,
101,
102,
103,
113,
163,
173
Data Sheet
11
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
Front View
Standard Height
PIN 1
PIN 52
PIN 53
PIN 92
Back View
PIN 93
PIN 144
PIN 145
PIN 184
Front View
1U Height
PIN 1
PIN 52
PIN 53
PIN 92
Back View
PIN 93
PIN 144
PIN 145
PIN 184
Figure 1
PCB with Pin Connector
Data Sheet
12
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
Table 6
Density
Address Format
Organization Memory
Ranks
SDRAMs # of
SDRAMs
# of
Refresh Period Interval
row/bank/
columns
bits
256 MB
512 MB
512 MB
1 GB
32M x 72
64M × 72
64M × 72
128M × 72
1
1
2
2
32M ×8
64M ×4
32M ×8
64M ×4
9
13 / 2 / 10
13 / 2 / 11
13 / 2 / 10
13 / 2 / 11
8K
8K
8K
8K
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
18
18
36
Data Sheet
13
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
RS0
DQS0
DQS4
DM4/DQS13
DM0/DQS9
DM
CS DQS
D4
DQS
CS
D0
DM
I/O 0
I/O 0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DQS1
DM1/DQS10
DM5/DQS14
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
CS
D5
DQS
CS
D1
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS6
DQS2
DM2/DQS11
DM6/DQS15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D6
DM
CS DQS
D2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
DQ16
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3/DQS12
DQS7
DM7/DQS16
CS
D7
DM
DQS
CS DQS
D3
DM
I/O 0
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
DQ24
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
V
EEPROM
D0 - D8
DDSPD
DM8/DQS17
Serial PD
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D8
DQS
V
V
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DD, DDQ
VREF
D0 - D8
D0 - D8
SDA
SCL
A0
SA0 SA1
A1 A2
V
V
SS
D0 - D8
SA2
DDID
Strap: see Note 4
CS0
RS0 -> CS : SDRAMs D0-D8
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8
R
E
G
I
S
T
E
R
Notes:
BA0-BA1
A0-A12
RAS
1. DQ-to-I/O wiring may be changed within a byte.
RA0-RA12 -> A0-A12: SDRAMs D0 - D8
RRAS -> RAS : SDRAMs D0 - D8
RCAS -> CAS : SDRAMs D0 - D8
RCKE0 -> CKE: SDRAMs D0 - D8
RWE -> WE: SDRAMs D0 - D8
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
CAS
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
CKE0
WE
STRAP OUT (OPEN): VDD = VDDQ
5. SDRAM placement alternates between the back
and front of the DIMM.
CK0, CK 0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
PCK
PCK
RESET
Figure 2
Block Diagram: One Rank 32M × 72 DDR SDRAM DIMM Module (32M×8 components)
HYS72D32300GBR on Raw Card A
Data Sheet
14
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
RS1
RS0
DQS4
DQS0
DM0/DQS9
DM4/DQS13
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D4
DM
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
CS
D0
CS
D9
DQS
I/O 0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
DQ0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D13
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS5
DQS1
DM1/DQS10
DM5/DQS14
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
CS
D5
CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
CS
D1
DM
CS
I/O 0
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
DQ8
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D14
DQ9
D10
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS6
DQS2
DM2/DQS11
DM6/DQS15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D15
DM
CS DQS
D11
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D2
DQ48
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS7
DM7/DQS16
DQS3
DM3/DQS12
CS
D7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D3
DM
CS
DQS
DQ56
I/O 0
DQ24
DQ57
DQ58
DQ59
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D16
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D12
DQ60
DQ61
DQ62
DQ63
DQS8
Serial PD
V
EEPROM
D0 - D17
DDSPD
DM8/DQS17
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D8
CS DQS
D17
SDA
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
SCL
V
V
A0
SA0 SA1
A1 A2
DD, DDQ
VREF
D0 - D17
D0 - D17
SA2
V
V
SS
DDID
Strap: see Note 4
CK0, CK 0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
CS0
CS1
BA0-BA1
A0-A12
RAS
CAS
CKE0
CKE1
WE
RS0 -> CS : SDRAM D0-D8
RS1 -> CS : SDRAM D9-D17
R
E
G
I
S
T
E
R
Notes:
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17
RA0-RA12 -> A0-A12: SDRAMs D0 - D17
RRAS -> RAS : SDRAMs D0 - D17
RCAS -> CAS : SDRAMs D0 - D17
RCKE0 -> CKE: SDRAMs D0 - D8
RCKE1 -> CKE: SDRAMs D9 - D17
RWE -> WE: SDRAMs D0 - D17
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDDQ
PCK
PCK
RESET
5. SDRAM placement alternates between the back
and front of the DIMM.
Figure 3
Block Diagram: Two Ranks 64M × 72 DDR-I SDRAM DIMM Module (32M×8 components)
HYS 72D64320GBR on Raw Card B
Data Sheet
15
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
VSS
RS0B
RS0A
DQS0
DM0/DQS9
DM
DQS
CS
D0
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D9
DM
DQ0
DQ1
DQ2
DQ3
DQ4
I/O 0
I/O 1
I/O 2
I/O 3
DQ5
DQ6
DQ7
DQS1
DQS2
DQS3
DM1/DQS10
DM
DM
DM
CS
D1
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQS
CS
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ13
DQ14
DQ15
D10
DQ10
DQ11
DM2/DQS11
DQS
DQS
CS
CS
D2
DM
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
D11
DM3/DQS12
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D3
DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
D12
DQS4
DM4/DQS13
V
EEPROM
D0 - D17
DDSPD
DQS
DM
DM
DQS
CS
CS
D4
DQ32
DQ33
DQ34
DQ35
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
V
V
D13
DD, DDQ
VREF
D0 - D17
D0 - D17
V
DQS5
DQS6
SS
DM5/DQS14
DQS
CS DM
D14
DQS
CS DM
D5
V
DDID
Strap: see Note 4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Serial PD
DM6/DQS15
CS DM
D15
DQS
CS DM
D6
DQS
SDA
DQ48
DQ49
DQ50
DQ51
I/O 0
I/O 1
I/O 2
I/O 3
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
SCL
A0
SA0 SA1 SA2
A1 A2
DQS7
DQS8
DM7/DQS16
DM
DM
DM
DM
CS
DQS
CS
D7
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
D16
Notes:
1. DQ-to-I/O wiring may be changed within a byte.
DM8/DQS17
2. DQ/DQS/DM/CKE/S relationships must be
DQS
CS
D8
CS
DQS
maintained as shown.
I/O 0
I/O 1
I/O 2
I/O 3
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
D17
STRAP OUT (OPEN): VDD = VDDQ
5. SDRAM placement alternates between the back
and front of the DIMM.
CS0
RS 0 -> CS : SDRAMs D0-D17
R
E
G
I
S
T
E
R
BA0-BA1
A0-A11,A12
RAS
CAS
CKE0
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17
RA0-RA11,RA12 -> A0-A11,A12: SDRAMs D0 - D17
RRAS -> RAS : SDRAMs D0 - D17
RCAS -> CAS : SDRAMs D0 - D17
RCKE0A -> CKE: SDRAMs D0 - D8
RCKEB -> CKE: SDRAMs D9 - D17
RWE -> WE: SDRAMs D0 - D17
CK0, CK 0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
WE
PCK
PCK
RESET
Figure 4
Block Diagram: One Rank 64M × 72 DDR-I SDRAM DIMM Modules (64M×4 components)
HYS72D64300GBR on Raw Card C
Data Sheet
16
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
VSS
RS1
RS0
DQS0
DM0/DQS9
DM
DM
DQS
I/O 0
CS
D0
DQS
I/O 3
CS
D18
DQS
I/O 0
DQS
I/O 0
CS
D9
DM
CS
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 2
I/O 1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D27
DQS1
DQS2
DQS3
DM1/DQS10
DM
DM
CS
D1
DM
CS
DM
DQS
DQS
DQS
CS
DQS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ8
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
D19
D10
D28
DQ10
DQ11
DM2/DQS11
DM
DM
DQS
DQS
I/O 0
DQS
CS
DQS
CS
CS
D2
CS
DM
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 1
I/O 2
I/O 3
D11
D29
D20
DM3/DQS12
DM
DM
CS
CS
DQS
CS
D3
DQS
I/O 0
CS
DQS
DM
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D12
D30
D21
DQS4
DM4/DQS13
DQS
DQS
DM
DM
DQS
DQS
I/O 0
CS
DM
CS DM
D31
CS
D4
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D22
D13
DQS5
DQS6
DQS7
DM5/DQS14
DQS
DQS
CS DM
D14
CS DM
D32
DQS
CS DM
D5
DQS
I/O 0
CS DM
D23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 1
I/O 2
I/O 3
DM6/DQS15
CS DM
D15
CS DM
D33
DQS
CS DM
D6
DQS
I/O 0
CS DM
D24
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
DM7/DQS16
DM
CS
DM
CS
DQS
DM
DM
CS
D7
DQS
I/O 0
CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D25
D16
D34
DQS8
DM8/DQS17
DM
CS
DM
CS
DM
DM
DQS
CS
D8
DQS
I/O 0
CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D26
D17
D35
V
DDSPD
VDDQ
VDD
Serial PD
D0-D35
CK0, CK0 --------- PLL*
Serial PD
* Wire per Clock Loading Table/Wiring Diagrams
SCL
SDA
D0-D35
D0-D35
D0-D35
VREF
VSS
A0 A1 A2
WP
S0
S1
RSO -> CS : SDRAMs D0-D17
R
RS1 -> CS: SDRAMs D18-D35
E
SA0 SA1 SA2
VDDID
Strap: see Note 4
BA0-BA1
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D35
RA0-RA12 -> A0-A12: SDRAMs D0- D35
RRAS -> RAS: SDRAMs D0-D35
G
I
Notes:
1. DQ-to-I/O wiring may be changed within a byte.
A0-A12
RAS
S
T
E
R
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ/DQS resistors should be 22 Ohms.
CAS
RCAS -> CAS: SDRAMs D0-D35
4. VDDID strap connections (for memory device VDD, VDDQ):
CKE0
CKE1
RCKE0 -> CKE: SDRAMs D0-D17
RCKE1 -> CKE: SDRAMs D18-D35
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ
.
RWE -> WE: SDRAMs D0-D35
WE
5. Address and control resistors should be 22 Ohms.
6. Each Chip Select and CKE pair alternate between decks for ther-
mal enhancement.
PCK
PCK
RESET
Figure 5
Block Diagram: Two Ranks 128M × 72 DDR SDRAM DIMM Modules (64M×4 components)
HYS72D128320GBR on Raw Card D
Data Sheet
17
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 7
Absolute Maximum Ratings
Parameter
Symbol
Values
typ.
–
Unit Note/ Test
Condition
min.
VIN, VOUT –0.5
max.
Voltage on I/O pins relative to VSS
VDDQ
+
V
–
0.5
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
VIN
–0.5
–0.5
–0.5
0
–
+3.6
+3.6
+3.6
+70
+150
–
V
–
–
–
–
–
–
–
VDD
VDDQ
TA
–
V
–
V
–
°C
°C
W
mA
TSTG
PD
-55
–
–
Power dissipation (per SDRAM component)
Short circuit output current
2.0
50
IOUT
–
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 8
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Values
Typ.
Unit Note/Test Condition 1)
Min.
2.3
2.5
2.3
2.5
Max.
2.7
2.7
2.7
2.7
3.6
0
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
EEPROM supply voltage
VDD
2.5
2.6
2.5
2.6
2.5
V
V
V
V
V
V
fCK ≤ 166 MHz
CK > 166 MHz 2)
fCK ≤ 166 MHz 3)
CK > 166 MHz 2)3)
VDD
f
VDDQ
VDDQ
f
VDDSPD 2.3
—
—
Supply Voltage, I/O Supply VSS,
0
Voltage
VSSQ
VREF
VTT
4)
5)
Input Reference Voltage
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ
V
I/O Termination Voltage
(System)
V
REF – 0.04
V
REF + 0.04 V
8)
8)
8)
Input High (Logic1) Voltage VIH(DC)
Input Low (Logic0) Voltage VIL(DC)
V
REF + 0.15
V
V
V
DDQ + 0.3
V
–0.3
REF – 0.15 V
Input Voltage Level,
CK and CK Inputs
VIN(DC) –0.3
DDQ + 0.3
DDQ + 0.6
V
8)6)
7)
Input Differential Voltage, VID(DC) 0.36
CK and CK Inputs
V
V
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio
0.71
1.4
—
Data Sheet
18
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Table 8
Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter
Symbol
Values
Typ.
Unit Note/Test Condition 1)
Min.
Max.
Input Leakage Current
Output Leakage Current
II
–2
2
µA Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 8)9)
IOZ
IOH
IOL
–5
5
µA DQs are disabled;
0 V ≤ VOUT ≤ VDDQ
Output High Current,
Normal Strength Driver
—
–16.2
—
mA
V
OUT = 1.95 V
Output Low
16.2
mA
V
OUT = 0.35 V
Current, Normal Strength
Driver
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF
.
.
.
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per DDR SDRAM component
Data Sheet
19
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Table 9
IDD Specifications
Unit Note/ Test
Conditions5)
256 MB
×72
512 MB
×72
512 MB
×72
1 GByte
×72
1 Rank
–5
1 Rank
–5
2 Ranks
–5
2 Ranks
–5
typ.
max.
1960
2005
725
typ.
max.
3040
3130
806
typ.
max.
2599
2644
806
typ.
max.
4318
4408
968
1)4)
IDD0
1690
1825
698
2500
2770
752
2284
2419
752
3688
3958
860
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1)3)4)
2)4)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
2)4)
1076
878
1139
932
1508
1112
986
1634
1220
1094
1994
3490
3508
4390
698
1508
1112
986
1634
1220
1094
1994
2824
2833
3274
698
2372
1580
1328
3020
4318
4318
4948
694.4
6388
2624
1796
1544
3344
4768
4786
5668
752
2)4)
2)4)
815
869
2)4)
1238
2005
2005
2320
656.6
3040
1319
2185
2194
2635
671
1832
3130
3130
3760
669.2
5200
1832
2599
2599
2914
669.2
3634
1)3)4)
1)4)
1)4)
2)4)
IDD6
1)3)4)5)
IDD7
3310
5740
3949
7018
1) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
n * IDD×[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
2 * n * IDD×[component] for single two bank modules (n: number of components per module bank)
3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
4) Module IDD is calculated on the basis of component IDD and includes Register and PLL
5) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
Data Sheet
20
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Table 10
IDD Specifications
Unit Note/ Test
Conditions5)
256 MB
×72
512 MB
×72
512 MB
×72
1 GB
×72
1 Rank
–6
1Ranks
–6
2 Ranks
–6
2 Ranks
–6
typ.
1495
1630
484
max.
1720
1810
511
typ.
max.
2710
2890
592
typ.
max.
2305
2395
592
typ.
max.
3880
4060
754
1)4)
IDD0
2260
2530
538
2035
2170
538
3340
3610
646
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1)3)4)
2)4)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
2)4)
835
925
1240
875
1420
934
1240
875
1420
934
2050
1319
1078
2590
3790
4060
4393
484
2410
1438
1186
2770
4420
4510
5320
520
2)4)
652
682
2)4)
592
619
754
808
754
808
2)4)
970
1015
1990
2035
2440
453
1510
2710
2980
3313
457
1600
3250
3340
4150
475
1510
2260
2395
2562
457
1600
2575
2620
3025
475
1)3)4)
1)4)
1720
1855
2022
444
1)4)
2)4)
IDD6
1)3)4)5)
IDD7
2600
3160
4470
5590
3140
3745
5550
6760
1) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
n * IDD×[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
2 * n * IDD×[component] for single two bank modules (n: number of components per module bank)
3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
4) Module IDD is calculated on the basis of component IDD and includes Register and PLL
5) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
Data Sheet
21
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Table 11
IDD Specifications
Unit Note/ Test
Conditions5)
256 MB
×72
512 MB
×72
512 MB
×72
1 GB
×72
1 Rank
–7
1 Rank
–7
2 Ranks
–7
2 Ranks
–7
typ.
1263
1398
426
max.
1488
1578
448
typ.
max.
2388
2568
520
typ.
max.
1983
2073
520
typ.
max.
3378
3558
664
1)4)
IDD0
1938
2208
475
1713
1848
475
2838
3108
574
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1)3)4)
2)4)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
2)4)
691
736
1006
736
1096
826
1006
736
1096
826
1636
1096
916
1816
1276
1024
2356
3648
3828
4818
466
2)4)
556
601
2)4)
511
538
646
700
646
700
2)4)
826
871
1276
2298
2478
3018
403
1366
2658
2838
3828
421
1276
1893
1983
2253
403
1366
2118
2208
2703
421
2176
3198
3378
3918
430
1)3)4)
1)4)
1443
1533
1803
390
1623
1713
2208
399
1)4)
2)4)
IDD6
1)3)4)5)
IDD7
2128
2613
3668
4638
2578
3108
4568
5628
1) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
n * IDD×[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
2 * n * IDD×[component] for single two bank modules (n: number of components per module bank)
3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
4) Module IDD is calculated on the basis of component IDD and includes Register and PLL
5) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
Data Sheet
22
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
3.2
AC Characteristics
Table 12
AC Timing - Absolute Specifications –5/–6/–7
Parameter
Symbol
–5
–6
–7
Unit Note/ Test
Condition 1)
DDR400B
DDR333
DDR266A
Min. Max.
Min.
Max.
Min.
Max.
2)3)4)5)
DQ output access time from
CK/CK
tAC
–0.7
+0.7
–0.7
+0.7
–0.75 +0.75 ns
2)3)4)5)
DQS output access time from tDQSCK
–0.6
+0.6
–0.6
+0.6
–0.75 +0.75 ns
CK/CK
2)3)4)5)
2)3)4)5)
2)3)4)5)
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
tCH
tCL
tHP
tCK
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
min. (tCL, tCH)
min. (tCL, tCH) min. (tCL, tCH) ns
5
6
8
—
—
12
12
—
—
—
—
—
12
12
—
—
—
ns
ns
ns
ns
ns
ns
CL = 3.0 2)3)4)5)
CL = 2.5 2)3)4)5)
CL = 2.0 2)3)4)5)
12
6
7.5
7.5
0.5
0.5
2.2
7.5
0.4
0.4
2.2
12
—
—
—
7.5
0.45
0.45
2.2
2)3)4)5)
DQ and DM input hold time
tDH
2)3)4)5)
DQ and DM input setup time tDS
2)3)4)5)6)
Control and Addr. input pulse tIPW
width (each input)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
DQ and DM input pulse width tDIPW
(each input)
1.75
—
—
1.75
—
—
1.75
—
—
ns
Data-out high-impedance time tHZ
from CK/CK
+0.7
+0.7
1.25
+0.4
+0.7
+0.7
1.25
+0.4
+0.75 ns
Data-out low-impedance time tLZ
from CK/CK
–0.7
0.72
—
–0.7
0.75
—
–0.75 +0.75 ns
Write command to 1st DQS
latching transition
tDQSS
tDQSQ
0.75
—
1.25
+0.5
tCK
DQS-DQ skew (DQS and
associated DQ signals)
ns
TFBGA 2)3)4)5)
Data hold skew factor
tQHS
tQH
—
+0.5
—
—
+0.55
—
+0.75 ns
TFBGA 2)3)4)5)
2)3)4)5)
DQ/DQS output hold time
tHP
tQHS
tDQSL,H 0.35
–
tHP
tQHS
–
tHP
tQHS
–
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
DQS input low (high) pulse
width (write cycle)
—
—
—
—
0.35
—
—
—
—
0.35
—
—
—
—
tCK
tCK
tCK
tCK
DQS falling edge to CK setup tDSS
time (write cycle)
0.2
0.2
2
0.2
0.2
2
0.2
0.2
2
DQS falling edge hold time
from CK (write cycle)
tDSH
tMRD
Mode register set command
cycle time
2)3)4)5)8)
2)3)4)5)9)
2)3)4)5)
Write preamble setup time
Write postamble
tWPRES
tWPST
tWPRE
0
—
0
—
0
—
ns
0.4
0.25
0.6
—
0.4
0.25
0.6
—
0.4
0.25
0.6
—
tCK
tCK
Write preamble
Data Sheet
23
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Table 12
AC Timing - Absolute Specifications –5/–6/–7 (cont’d)
Parameter
Symbol
–5
–6
–7
Unit Note/ Test
Condition 1)
DDR400B
DDR333
DDR266A
Min. Max.
Min.
Max.
Min.
Max.
Address and control input
setup time
tIS
0.6
0.7
0.6
0.7
—
0.75
—
0.9
1.0
0.9
1.0
—
—
—
—
ns
ns
ns
ns
fast slew rate
3)4)5)6)10)
—
0.8
—
—
—
slow slew rate
3)4)5)6)10)
Address and control input hold tIH
time
0.75
0.8
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
40
1.1
0.6
0.9
0.4
1.1
0.6
0.90
0.4
1.1
0.6
tCK
tCK
Active to Precharge command tRAS
70E+3 42
60
70E+3 45
70E+3 ns
Active to Active/Auto-refresh tRC
55
—
65
—
ns
command period
2)3)4)5)
Auto-refresh to Active/Auto-
refresh command period
tRFC
65
72
—
75
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
Active to Read or Write delay tRCD
Precharge command period tRP
15
15
—
—
18
18
—
—
20
20
—
—
ns
ns
ns
Active to Autoprecharge delay tRAP
t
RCD or
t
RCDor
tRCDor —
tRASmin
tRASmin
tRASmin
2)3)4)5)
Active bank A to Active bank B tRRD
command
10
—
—
12
—
—
15
—
—
ns
2)3)4)5)
Write recovery time
tWR
15
—
15
—
15
—
ns
2)3)4)5)11)
Auto precharge write recovery tDAL
+ precharge time
tCK
2)3)4)5)
Internal write to read
command delay
tWTR
tXSNR
tXSRD
tREFI
2
—
—
—
7.8
1
—
—
—
7.8
1
—
—
tCK
ns
tCK
µs
2)3)4)5)
Exit self-refresh to non-read
command
75
200
—
75
200
—
75
200
—
2)3)4)5)
Exit self-refresh to read
command
—
2)3)4)5)12)
Average Periodic Refresh
Interval
7.8
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Data Sheet
24
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac)
.
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
25
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
4
SPD Contents
Table 13
SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5
1 GByte
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
2 Ranks
1 Rank
Label Code
PC3200R–30331 PC3200R–30330 PC3200R–30330 PC3200R–30330
Jedec SPD Revision Rev 1.0
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Byte#
Description
HEX
0
Programmed SPD
Bytes in E2PROM
80
1
2
3
4
5
Total number of Bytes 08
in E2PROM
08
07
0D
0B
01
08
07
0D
0A
02
08
07
0D
0A
01
Memory Type (DDR = 07
07h)
Number of Row
Addresses
0D
0B
02
Number of Column
Addresses
Number of DIMM
Ranks
6
7
8
Data Width (LSB)
Data Width (MSB)
48
00
04
48
00
04
48
00
04
48
00
04
Interface Voltage
Levels
9
tCK @ CLmax (Byte
18) [ns]
50
50
02
50
50
02
50
50
02
50
50
02
10
11
tAC SDRAM @
CLmax (Byte 18) [ns]
Error Correction
Support
12
13
Refresh Rate
82
04
82
04
82
08
82
08
Primary SDRAM
Width
14
15
Error Checking
SDRAM Width
04
01
04
01
08
01
08
01
tCCD [cycles]
Data Sheet
26
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
Table 13
SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5
1 GByte
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
2 Ranks
1 Rank
Label Code
PC3200R–30331 PC3200R–30330 PC3200R–30330 PC3200R–30330
Jedec SPD Revision Rev 1.0
Rev 0.0
HEX
0E
Rev 0.0
HEX
Rev 0.0
HEX
0E
Byte#
Description
HEX
16
Burst Length
Supported
0E
0E
17
Number of Banks on 04
SDRAM Device
04
04
04
18
19
20
21
22
23
CAS Latency
CS Latency
1C
01
02
26
1C
01
02
26
C1
60
1C
01
02
26
C1
60
1C
01
02
26
C1
60
Write Latency
DIMM Attributes
Component Attributes C0
tCK @ CLmax -0.5
(Byte 18) [ns]
60
24
25
26
tAC SDRAM @
CLmax -0.5 [ns]
50
50
75
50
50
75
50
50
75
50
tCK @ CLmax -1 (Byte 75
18) [ns]
tAC SDRAM @
CLmax -1 [ns]
50
27
28
29
30
31
tRPmin [ns]
3C
28
3C
28
80
3C
28
3C
28
80
3C
28
3C
28
40
3C
28
3C
28
40
tRRDmin [ns]
tRCDmin [ns]
tRASmin [ns]
Module Density per
Rank
32
33
34
35
tAS, tCS [ns]
tAH, TCH [ns]
tDS [ns]
60
60
40
40
00
37
60
60
40
40
00
37
60
60
40
40
00
37
60
60
40
40
00
37
tDH [ns]
36 - 40 not used
41
tRCmin [ns]
Data Sheet
27
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
Table 13
SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5
1 GByte
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
2 Ranks
1 Rank
Label Code
PC3200R–30331 PC3200R–30330 PC3200R–30330 PC3200R–30330
Jedec SPD Revision Rev 1.0
Rev 0.0
HEX
41
Rev 0.0
HEX
41
Rev 0.0
HEX
41
Byte#
42
Description
tRFCmin [ns]
tCKmax [ns]
HEX
41
28
28
50
00
01
00
10
43
28
28
28
44
tDQSQmax [ns]
tQHSmax [ns]
not used
28
28
28
45
50
50
50
46
00
00
00
47
DIMM PCB Height
00
00
00
48 - 61 not used
00
00
00
62
63
SPD Revision
00
00
00
Checksum of Byte 0- 5F
4E
16
15
62
64
65
66
67
68
69
70
71
72
JEDEC ID Code of
Infineon (1)
C1
49
4E
46
49
4E
45
4F
C1
49
4E
46
49
4E
45
4F
xx
C1
49
4E
46
49
4E
45
4F
xx
C1
49
4E
46
49
4E
45
4F
xx
JEDEC ID Code of
Infineon (2)
JEDEC ID Code of
Infineon (3)
JEDEC ID Code of
Infineon (4)
JEDEC ID Code of
Infineon (5)
JEDEC ID Code of
Infineon (6)
JEDEC ID Code of
Infineon (7)
JEDEC ID Code of
Infineon (8)
Module Manufacturer xx
Location
73
74
Part Number, Char 1 37
Part Number, Char 2 32
37
32
37
32
37
32
Data Sheet
28
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
Table 13
SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5
1 GByte
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
2 Ranks
1 Rank
Label Code
Jedec SPD Revision Rev 1.0
Description HEX
PC3200R–30331 PC3200R–30330 PC3200R–30330 PC3200R–30330
Rev 0.0
HEX
44
Rev 0.0
HEX
44
Rev 0.0
HEX
44
Byte#
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Part Number, Char 3 44
Part Number, Char 4 31
Part Number, Char 5 32
Part Number, Char 6 38
Part Number, Char 7 33
Part Number, Char 8 32
Part Number, Char 9 30
Part Number, Char 10 47
Part Number, Char 11 42
Part Number, Char 12 52
Part Number, Char 13 37
Part Number, Char 14 42
Part Number, Char 15 20
Part Number, Char 16 20
Part Number, Char 17 20
Part Number, Char 18 20
Module Revision Code xx
36
36
33
34
34
32
33
33
33
30
32
30
30
30
30
47
47
47
42
42
42
52
52
52
35
35
35
42
42
42
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
xx
xx
xx
Test Program
Revision Code
xx
xx
xx
xx
93
94
95
96
97
Module Manufacturing xx
Date Year
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
Module Manufacturing xx
Date Week
Module Serial Number xx
(1)
Module Serial Number xx
(2)
Module Serial Number xx
(3)
Data Sheet
29
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
Table 13
SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5
1 GByte
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
2 Ranks
1 Rank
Label Code
Jedec SPD Revision Rev 1.0
Description HEX
PC3200R–30331 PC3200R–30330 PC3200R–30330 PC3200R–30330
Rev 0.0
HEX
xx
Rev 0.0
HEX
xx
Rev 0.0
HEX
xx
Byte#
98
Module Serial Number xx
(4)
99 - 127 not used
00
00
00
00
Table 14
SPD Codes for HYS72D128320GBR–6–B, HYS72D64300GBR–[6/7]–B, HYS72D64320GBR–6–B
and HYS72D32300GBR–6–B
1 GByte
×72
512 MB
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R–
25330
PC2700R–
25330
PC2100R–
20330
PC2700R–
25330
PC2700R–
25330
Jedec SPD
Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
ProgrammedSPD 80
Bytes in E2PROM
80
80
80
80
1
2
Total number of
Bytes in E2PROM
08
08
07
08
07
08
07
08
07
Memory Type
(DDR = 07h)
07
Data Sheet
30
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
Table 14
SPD Codes for HYS72D128320GBR–6–B, HYS72D64300GBR–[6/7]–B, HYS72D64320GBR–6–B
and HYS72D32300GBR–6–B
1 GByte
×72
512 MB
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R–
25330
PC2700R–
25330
PC2100R–
20330
PC2700R–
25330
PC2700R–
25330
Jedec SPD
Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
3
Number of Row
Addresses
0D
0D
0D
0D
0D
4
5
Number of
Column
Addresses
0B
0B
01
0B
01
0A
02
0A
01
Number of DIMM 02
Ranks
6
7
8
Data Width (LSB) 48
Data Width (MSB) 00
48
00
04
48
00
04
48
00
04
48
00
04
Interface Voltage 04
Levels
9
tCK @ CLmax
(Byte 18) [ns]
60
60
70
70
75
60
70
60
70
10
tAC SDRAM @
CLmax (Byte 18)
[ns]
70
11
Error Correction
Support
02
82
02
02
02
02
12
13
Refresh Rate
82
04
82
04
82
08
82
08
Primary SDRAM 04
Width
14
Error Checking
SDRAM Width
04
04
04
08
08
15
16
tCCD [cycles]
01
0E
01
0E
01
0E
01
0E
01
0E
Burst Length
Supported
17
Number of Banks 04
on SDRAM
04
04
04
04
Device
Data Sheet
31
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
Table 14
SPD Codes for HYS72D128320GBR–6–B, HYS72D64300GBR–[6/7]–B, HYS72D64320GBR–6–B
and HYS72D32300GBR–6–B
1 GByte
×72
512 MB
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R–
25330
PC2700R–
25330
PC2100R–
20330
PC2700R–
25330
PC2700R–
25330
Jedec SPD
Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
18
Description
CAS Latency
CS Latency
HEX
0C
01
HEX
0C
01
HEX
0C
01
HEX
0C
01
HEX
0C
01
19
20
Write Latency
DIMM Attributes
02
02
02
02
02
21
26
26
26
26
26
22
Component
Attributes
C0
C0
C0
C0
C0
23
24
25
26
tCK @ CLmax -
0.5 (Byte 18) [ns]
75
70
75
70
00
00
75
75
00
00
75
70
00
00
75
70
00
00
tAC SDRAM @
CLmax -0.5 [ns]
tCK @ CLmax -1 00
(Byte 18) [ns]
tAC SDRAM @
CLmax -1 [ns]
00
27
28
29
30
31
tRPmin [ns]
48
30
48
2A
80
48
30
48
2A
80
50
3C
50
2D
80
48
30
48
2A
40
48
30
48
2A
40
tRRDmin [ns]
tRCDmin [ns]
tRASmin [ns]
Module Density
per Rank
32
33
34
35
tAS, tCS [ns]
tAH, TCH [ns]
tDS [ns]
75
75
45
45
00
3C
48
75
75
45
45
00
3C
48
90
90
50
50
00
41
4B
75
75
45
45
00
3C
48
75
75
45
45
00
3C
48
tDH [ns]
36 - 40 not used
41
42
tRCmin [ns]
tRFCmin [ns]
Data Sheet
32
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
Table 14
SPD Codes for HYS72D128320GBR–6–B, HYS72D64300GBR–[6/7]–B, HYS72D64320GBR–6–B
and HYS72D32300GBR–6–B
1 GByte
×72
512 MB
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R–
25330
PC2700R–
25330
PC2100R–
20330
PC2700R–
25330
PC2700R–
25330
Jedec SPD
Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
43
Description
tCKmax [ns]
tDQSQmax [ns]
tQHSmax [ns]
not used
HEX
30
HEX
30
28
50
00
00
00
00
47
HEX
30
32
75
00
00
00
00
03
HEX
30
28
50
00
00
00
00
0F
HEX
30
44
28
28
45
50
50
46
00
00
47
DIMM PCB Height 00
00
48 - 61 not used
00
00
00
62
63
SPD Revision
00
Checksum of Byte 48
0-62
0E
64
65
66
67
68
69
70
71
72
JEDEC ID Code C1
of Infineon (1)
C1
49
4E
46
49
4E
45
4F
xx
C1
49
4E
46
49
4E
45
4F
xx
C1
49
4E
46
49
4E
45
4F
xx
C1
49
4E
46
49
4E
45
4F
xx
JEDEC ID Code 49
of Infineon (2)
JEDEC ID Code 4E
of Infineon (3)
JEDEC ID Code 46
of Infineon (4)
JEDEC ID Code 49
of Infineon (5)
JEDEC ID Code 4E
of Infineon (6)
JEDEC ID Code 45
of Infineon (7)
JEDEC ID Code 4F
of Infineon (8)
Module
xx
Manufacturer
Location
Data Sheet
33
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
Table 14
SPD Codes for HYS72D128320GBR–6–B, HYS72D64300GBR–[6/7]–B, HYS72D64320GBR–6–B
and HYS72D32300GBR–6–B
1 GByte
×72
512 MB
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R–
25330
PC2700R–
25330
PC2100R–
20330
PC2700R–
25330
PC2700R–
25330
Jedec SPD
Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
73
Part Number,
Char 1
37
37
37
37
37
74
75
76
77
78
79
80
81
82
83
84
85
86
Part Number,
Char 2
32
44
31
32
38
33
32
30
47
42
52
36
42
32
44
36
34
33
30
30
47
42
52
36
42
20
32
44
36
34
33
30
30
47
42
52
37
42
20
32
44
36
34
33
32
30
47
42
52
36
42
20
32
44
33
32
33
30
30
47
42
52
36
42
20
Part Number,
Char 3
Part Number,
Char 4
Part Number,
Char 5
Part Number,
Char 6
Part Number,
Char 7
Part Number,
Char 8
Part Number,
Char 9
Part Number,
Char 10
Part Number,
Char 11
Part Number,
Char 12
Part Number,
Char 13
Part Number,
Char 14
Data Sheet
34
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
Table 14
SPD Codes for HYS72D128320GBR–6–B, HYS72D64300GBR–[6/7]–B, HYS72D64320GBR–6–B
and HYS72D32300GBR–6–B
1 GByte
×72
512 MB
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R–
25330
PC2700R–
25330
PC2100R–
20330
PC2700R–
25330
PC2700R–
25330
Jedec SPD
Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
87
Part Number,
Char 15
20
20
20
20
20
88
89
90
91
92
93
Part Number,
Char 16
20
20
20
20
20
20
xx
xx
xx
20
20
20
xx
xx
xx
20
20
20
xx
xx
xx
20
20
20
xx
xx
xx
Part Number,
Char 17
Part Number,
Char 18
Module Revision xx
Code
Test Program
Revision Code
xx
Module
xx
Manufacturing
Date Year
94
Module
xx
xx
xx
xx
xx
Manufacturing
Date Week
95
96
97
98
Module Serial
Number (1)
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
Module Serial
Number (2)
Module Serial
Number (3)
Module Serial
Number (4)
99 - 127 not used
Data Sheet
35
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
Table 15
SPD Codes for HYS72D[64/128]320GBR–7–B and HYS72D32300GBR–7–B
1 GByte
×72
512 MB
×72
256 MB
×72
2 Ranks
2 Ranks
1 Rank
Label Code
PC2100R–
20330
PC2100R–
20330
PC2100R–
20330
Jedec SPD Revision
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Byte#
0
Description
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
Data Width (LSB)
1
08
08
08
2
07
07
07
3
0D
0B
02
0D
0A
02
0D
0A
01
4
5
6
48
48
48
7
Data Width (MSB)
00
00
00
8
Interface Voltage Levels
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
04
04
04
9
70
70
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
75
75
02
02
02
82
82
82
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
04
08
08
04
08
08
01
01
01
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
0E
04
0E
04
0E
04
0C
01
0C
01
0C
01
CS Latency
Write Latency
02
02
02
DIMM Attributes
26
26
26
Component Attributes
C0
75
C0
75
C0
75
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
75
75
75
00
00
00
Data Sheet
36
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
Table 15
SPD Codes for HYS72D[64/128]320GBR–7–B and HYS72D32300GBR–7–B
1 GByte
×72
512 MB
×72
256 MB
×72
2 Ranks
2 Ranks
1 Rank
Label Code
PC2100R–
20330
PC2100R–
20330
PC2100R–
20330
Jedec SPD Revision
Description
Rev 0.0
HEX
00
Rev 0.0
HEX
00
Rev 0.0
HEX
00
Byte#
26
tAC SDRAM @ CLmax -1 [ns]
tRPmin [ns]
27
50
50
50
28
tRRDmin [ns]
3C
50
3C
50
3C
50
29
tRCDmin [ns]
30
tRASmin [ns]
2D
80
2D
40
2D
40
31
Module Density per Rank
tAS, tCS [ns]
32
90
90
90
33
tAH, TCH [ns]
90
90
90
34
tDS [ns]
50
50
50
35
tDH [ns]
50
50
50
36 - 40 not used
00
00
00
41
42
43
44
45
46
47
tRCmin [ns]
41
41
41
tRFCmin [ns]
tCKmax [ns]
4B
30
4B
30
4B
30
tDQSQmax [ns]
tQHSmax [ns]
not used
32
32
32
75
75
75
00
00
00
DIMM PCB Height
00
00
00
48 - 61 not used
00
00
00
62
63
64
65
66
67
68
69
SPD Revision
00
00
00
Checksum of Byte 0-62
04
CB
C1
49
CA
C1
49
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2)
JEDEC ID Code of Infineon (3)
JEDEC ID Code of Infineon (4)
JEDEC ID Code of Infineon (5)
JEDEC ID Code of Infineon (6)
C1
49
4E
46
4E
46
4E
46
49
49
49
4E
4E
4E
Data Sheet
37
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
Table 15
SPD Codes for HYS72D[64/128]320GBR–7–B and HYS72D32300GBR–7–B
1 GByte
×72
512 MB
×72
256 MB
×72
2 Ranks
2 Ranks
1 Rank
Label Code
PC2100R–
20330
PC2100R–
20330
PC2100R–
20330
Jedec SPD Revision
Description
Rev 0.0
HEX
45
4F
xx
Rev 0.0
HEX
45
4F
xx
Rev 0.0
HEX
45
4F
xx
Byte#
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
JEDEC ID Code of Infineon (7)
JEDEC ID Code of Infineon (8)
Module Manufacturer Location
Part Number, Char 1
37
32
44
31
32
38
33
32
30
47
42
52
37
42
20
20
20
20
xx
37
32
44
36
34
33
32
30
47
42
52
37
42
20
20
20
20
20
xx
37
32
44
33
32
33
30
30
47
42
52
37
42
20
20
20
20
20
xx
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1)
Module Serial Number (2)
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
Data Sheet
38
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
Table 15
SPD Codes for HYS72D[64/128]320GBR–7–B and HYS72D32300GBR–7–B
1 GByte
×72
512 MB
×72
256 MB
×72
2 Ranks
2 Ranks
1 Rank
Label Code
PC2100R–
20330
PC2100R–
20330
PC2100R–
20330
Jedec SPD Revision
Description
Rev 0.0
HEX
xx
Rev 0.0
HEX
xx
Rev 0.0
HEX
xx
Byte#
97
Module Serial Number (3)
Module Serial Number (4)
98
xx
xx
xx
99 - 127 not used
00
00
00
Data Sheet
39
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Package Outlines
5
Package Outlines
133.35
128.95
0.15
A B C
2.64 MAX.
A
1
2.5
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
Burr max. 0.4 allowed
Figure 6
Package Outlines Raw Card A L-DIM 184-21
Data Sheet
40
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Package Outlines
133.35
128.95
0.15
A B C
4 MAX.
A
1
2.5
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
Burr max. 0.4 allowed
Figure 7
Package Outlines Raw Card B L-DIM 184-23
Data Sheet
41
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Package Outlines
133.35
128.95
0.15
A B C
4 MAX.
A
1
2.5
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
Burr max. 0.4 allowed
Figure 8
Package Outline Raw Card C L-DIM 184-22
Data Sheet
42
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Package Outlines
133.35
128.95
0.15
A B C
4 MAX.
A
1
2.5
92
B
C
6.62
2.175
±0.1
ø0.1
A B C
0.4
6.35
±0.1
1.27
64.77
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
Burr max. 0.4 allowed
Figure 9
Package Outline Raw card D L-DIM 184-24
Data Sheet
43
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Application Note
6
Application Note
Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item
1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and
to minimize power consumption during low power mode. One feature is externally controlled via a system-
generated RESET signal; the second is based on module detection of the input clocks. These enhancements
permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations
and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked
Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other SDRAM
inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low level, all the
register outputs are forced to a low level, and all differential register input receivers are powered down, resulting
in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as
an asynchronous signal according to the attached details. Using this function also permits the system and DIMM
clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh
mode.
Table 16
RESET Truth Table
Register Inputs
Register
Outputs
RESET
CK
CK
Data in (D)
Data out (Q)
H
H
H
H
Rising
Rising
L or H
High Z
Falling
Falling
L or H
High Z
H
L
H
L
X
X
Qo
Illegal input
conditions
L
X or Hi-Z
X or Hi-Z
X or Hi-Z
L
X: Don’t care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are
maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low
maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until
activated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz
or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating
frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual
detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made
High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less than
1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied
inactive on the DIMM.
This application note describes the required and optional system sequences associated with the DDR Registered
DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2-
bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control
CKE to one physical DIMM bank through the use of the RESET pin.
Data Sheet
44
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Application Note
Power-Up Sequence with RESET — Required
1. The system sets RESET at a valid low level.
This is the preferred default state during power-up. This input condition forces all register outputs to a low state
independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level
at the DDR SDRAMs.
2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR
SDRAMs.
3. Stabilization of Clocks to the SDRAM
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,
the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a
stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 µsec prior to
SDRAM operation.
4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would
be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be
consistent with the state of the register outputs.
5. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs
must remain stable).
6. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows their clock receivers, data input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-
pproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) — Optional
Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down
and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.
Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption
(RESET low deactivates register CK and CK, data input receivers, and data output drivers).
1. 1. The system applies Self Refresh entry command.
(CKE→Low, CS→Low, RAS → Low, CAS→ Low, WE→ High)
Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares— with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the registerm
inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-level
at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a
specific clock edge is not required.
3. The system turns off clock inputs to the DIMM. (Optional)
a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
Data Sheet
45
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Application Note
inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the
register (t (INACT). The deactivate time defines the time in which the clocks and the control and address
signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM
documentation.
b.The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which
the clocks and the control and the address signals must maintain valid levels after RESET low has been
applied. It is highly recommended that CKE continue to remain low during this operation.
4. The DIMM is in lowest power Self Refresh mode.
Self Refresh Exit (RESET low, clocks powered off) — Optional
1. Stabilization of Clocks to the SDRAM.
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,
the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds.
2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this
would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs, to
be consistent with the state of the register outputs.
3. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
RESET timing relationship to a specific clock edge is not required (during this period, register inputs must
remain stable).
4. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) — Optional
Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this
is an alternate operating mode for these DIMMs.
1. 1. System enters Self Refresh entry command.
(CKE→ Low, CS→ Low, RAS→ Low, CAS→ Low, WE→ High)
Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares — with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the data and clock
register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs.
3. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes
the time in which the clocks and the control and the address signals must maintain valid levels after RESET
low has been applied. It is highly recommended that CKE continue to remain low during the operation.
4. The DIMM is in a low power, Self Refresh mode.
Data Sheet
46
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Application Note
Self Refresh Exit (RESET low, clocks running) — Optional
1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector). CKE must be maintained low and all other inputs should be driven to a known state. In general
these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’
command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this
would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be
consistent with the state of the register outputs.
2. The system switches RESET to a logic 'high' level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain
stable).
3. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE
outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation
time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept
an input signal, is t (ACT ) as specified in the register and DIMM documentation.
4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) — Optional
As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification
explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) — Not Permissible
In order to maintain a valid low level on the register output, it is required that either the clocks be running and the
system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the
sequence defined in this application note. In the case where RESET remains high and the clocks are powered off,
the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM
state will result.
Data Sheet
47
Rev. 1.1, 2004-04
10102003-01E2-HPA8
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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