HYS72D64320GBR-5-C [INFINEON]
184-Pin Registered Double Data Rate SDRAM Module; 184引脚均录得双数据速率SDRAM模块
| 型号： | HYS72D64320GBR-5-C |
| 厂家： | 
Infineon |
| 描述： | 184-Pin Registered Double Data Rate SDRAM Module |
| 文件： | 总38页 (文件大小：1085K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.0, Mar. 2004
HYS72D32300GBR–[5/6]–C
HYS72D64300GBR–[5/6]–C
HYS72D64320GBR–[5/6]–C
HYS72D128320GBR–6–C
184-Pin Registered Double Data Rate SDRAM Module
Reg DIMM
DDR SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
Edition 2004-03
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, Rev. 1.0, Mar. 2004
HYS72D32300GBR–[5/6]–C
HYS72D64300GBR–[5/6]–C
HYS72D64320GBR–[5/6]–C
HYS72D128320GBR–6–C
184-Pin Registered Double Data Rate SDRAM Module
Reg DIMM
DDR SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
HYS72D32300GBR–[5/6]–C HYS72D64300GBR–[5/6]–C HYS72D64320GBR–[5/6]–C HYS72D128320GBR–
6–CHYS72D64300GBR–[5/6]–C HYS72D64320GBR–[5/6]–C
Revision History:
Rev. 1.0
2004-03
Previous Version:
Rev. 0.5
Page
20,21
8,22
Subjects (major changes since last revision)
Idd values updated
editorial changes
24,27
Changed SPD Code Byte 99 - 127 to FF
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc.mp@infineon.com
Template: mp_a4_v2.2_2003-10-07.fm
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
6
7
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Data Sheet
5
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Overview
1
Overview
1.1
Features
•
184-Pin Registered 8-Byte Dual-In-Line
DDR SDRAM Module for “1U” PC, Workstation and Server main memory applications
One rank 32 M × 72 and 64M × 72 and two ranks 64 M ×72 and 128 M ×72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V (± 0.2 V) power
supply and + 2.6 V (± 0.1 V) power supply for DDR400
Built with 256-Mbit DDR SDRAMs in P-TFBGA-60-1 packages
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
•
•
•
•
•
•
•
•
•
All inputs and outputs SSTL_2 compatible
Re-drive for all input signals using register and PLL devices.
Serial Presence Detect with E2PROM
Low Profile Modules form factor:
133.35 mm × 28.58 mm × 4.00 mm / 2.64 mm and for 1GB 133.35 mm × 30.48 mm (1.2”)× 4.00 mm
JEDEC standard reference layout for one rank 256 MB, 512 MB and two ranks 512 MB, 1 GB:
PC2700 and PC3200 Registered DIMM Raw Cards A,B,C,D
Gold plated contacts
•
•
Table 1
Performance
Part Number Speed Code
–5
–6
Unit
—
Speed Grade
Component
Module
@CL3
DDR400B
PC3200–3033
200
DDR333B
PC2700–2533
166
—
max. Clock Frequency
fCK3
MHz
MHz
MHz
@CL2.5
@CL2
fCK2.5
fCK2
166
166
133
133
1.2
Description
The HYS72D[128/64/32][300/320]GBR–[5/6]–C and HYS72D64320GBR–5–C are low profile versions of the
standard Registered DIMM modules suitable for 1U Server Applications. The Low Profile DIMM versions are
available as 32 M ×72 (256 MB), 64 M ×72 (512 MB) and 128 M ×72 (1 GB)
The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors
are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using
the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
available to the customer.
Data Sheet
6
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Overview
Table 2
Type
Ordering Information
Compliance Code
Description
SDRAM
Technology
PC3200 (CL = 3.0)
HYS72D32300GBR–5–C PC3200R–30330–A0 1 Rank 256 MB Registered DIMM ECC
HYS72D64300GBR–5–C PC3200R–30330–C0 1 Rank 512 MB Registered DIMM ECC
HYS72D64320GBR–5–C PC3200R–30330–B0 2 Ranks 512 MB Registered DIMM ECC
256 Mbit (×8)
256 Mbit (×4)
256 Mbit (×8)
PC2700 (CL = 2.5, tRP = tRCD = 3 at tCK = 6ns)
HYS72D32300GBR–6–C PC2700R–25330–A0 1 Rank 256 MB Registered DIMM ECC
HYS72D64300GBR–6–C PC2700R–25330–C0 1 Rank 512 MB Registered DIMM ECC
HYS72D64320GBR–6–C PC2700R–25330–B0 2 Ranks 512 MB Registered DIMM ECC
HYS72D128320GBR–6–C PC2700R–25330–D0 2 Ranks 1 GB Registered DIMM ECC
256 Mbit (×8)
256 Mbit (×4)
256 Mbit (×8)
256 Mbit (×4)
Data Sheet
7
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Pin Configuration
2
Pin Configuration
The pin configuration of the Registered DDR SDRAM Table 3
DIMM is listed by function in Table 3 (184 pins). The
abbreviations used in columns Pin and Buffer Type are
explained in Table 4 and Table 5 respectively. The pin
Pin Configuration of RDIMM (cont’d)
Buffer Function
Type Type
Pin# Name Pin
125 A6
I
I
I
I
I
I
I
I
SSTL Address Bus 11:0
numbering is depicted in Figure 1.
29
122 A8
27 A9
A7
SSTL
SSTL
Table 3
Pin Configuration of RDIMM
SSTL
Pin# Name Pin
Buffer Function
Type Type
141 A10
AP
SSTL
Clock Signals
137 CK0
SSTL
I
I
I
I
SSTL Clock Signal
118 A11
115 A12
SSTL
138 CK0
SSTL Complement Clock
SSTL Clock Enable Rank 0
SSTL Clock Enable Rank 1
Note:2-rank module
SSTL Address Signal 12
21
CKE0
Note:Module based on
256 Mbit or larger
dies
111 CKE1
NC
NC
I
–
Note:128 Mbit based
module
NC
NC
SSTL Note:1-rank module
Control Signals
167 A13
SSTL Address Signal 13
157 S0
158 S1
I
I
SSTL Chip Select of Rank 0
SSTL Chip Select of Rank 1
Note:2-ranks module
Note:1 Gbit
module
based
NC
NC
–
Note:Module based on
NC
NC
–
Note:1-rank module
512 Mbit
or
smaller dies
154 RAS
I
I
SSTL Row Address Strobe
65
CAS
SSTL Column Address
Strobe
63
10
WE
I
SSTL Write Enable
RESET I
LV-
Register Reset
CMOS Forces registered
inputs low
Note:For
detailed
description of the
Power Up and
Power
Management see
the
Application
Note at the end of
data sheet
Address Signals
59
52
48
43
41
BA0
BA1
A0
I
I
I
I
I
I
I
I
SSTL Bank Address Bus
1:0
SSTL
SSTL Address Bus 11:0
A1
SSTL
A2
SSTL
130 A3
SSTL
37
32
A4
A5
SSTL
SSTL Address Bus 11:0
Data Sheet
8
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Pin Configuration
Table 3
Pin Configuration of RDIMM (cont’d)
Table 3
Pin Configuration of RDIMM (cont’d)
Pin# Name Pin
Buffer Function
Pin# Name Pin
Buffer Function
Type Type
Type Type
Data Signals
150 DQ38 I/O
151 DQ39 I/O
SSTL Data Bus 63:0
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL Data Bus 63:0
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
4
61
64
68
69
DQ40 I/O
DQ41 I/O
DQ42 I/O
DQ43 I/O
SSTL
6
SSTL
8
SSTL
94
95
98
99
12
13
19
20
SSTL
153 DQ44 I/O
155 DQ45 I/O
161 DQ46 I/O
162 DQ47 I/O
SSTL
SSTL
SSTL
SSTL
72
73
79
80
DQ48 I/O
DQ49 I/O
DQ50 I/O
DQ51 I/O
SSTL
DQ10 I/O
DQ11 I/O
SSTL
SSTL
105 DQ12 I/O
106 DQ13 I/O
109 DQ14 I/O
110 DQ15 I/O
SSTL
165 DQ52 I/O
166 DQ53 I/O
170 DQ54 I/O
171 DQ55 I/O
SSTL
SSTL
SSTL
23
24
28
31
DQ16 I/O
DQ17 I/O
DQ18 I/O
DQ19 I/O
SSTL
83
84
87
88
DQ56 I/O
DQ57 I/O
DQ58 I/O
DQ59 I/O
SSTL
SSTL
SSTL
114 DQ20 I/O
117 DQ21 I/O
121 DQ22 I/O
123 DQ23 I/O
SSTL
174 DQ60 I/O
175 DQ61 I/O
178 DQ62 I/O
179 DQ63 I/O
SSTL
SSTL
SSTL
33
35
39
40
DQ24 I/O
DQ25 I/O
DQ26 I/O
DQ27 I/O
SSTL
44
45
49
51
CB0
CB1
CB2
CB3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL Check Bits 7:0
SSTL
SSTL
126 DQ28 I/O
127 DQ29 I/O
131 DQ30 I/O
133 DQ31 I/O
SSTL
134 CB4
135 CB5
142 CB6
144 CB7
SSTL
SSTL
SSTL
53
55
57
60
DQ32 I/O
DQ33 I/O
DQ34 I/O
DQ35 I/O
SSTL
5
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
DQS5 I/O
SSTL Data Strobes 8:0
Note:See
diagram
block
for
14
25
36
56
67
SSTL
SSTL
SSTL
SSTL
SSTL
corresponding
DQ signals
146 DQ36 I/O
147 DQ37 I/O
Data Sheet
9
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Pin Configuration
Table 3
Pin# Name Pin
Type Type
Pin Configuration of RDIMM (cont’d)
Table 3
Pin Configuration of RDIMM (cont’d)
Buffer Function
Pin# Name Pin
Buffer Function
Type Type
78
86
47
97
DQS6 I/O
DQS7 I/O
DQS8 I/O
SSTL Data Strobes 8:0
SSTL
EEPROM
92
91
SCL
SDA
I
CMOS Serial Bus Clock
SSTL
I/O
OD
Serial Bus Data
DM0
DQS9 I/O
107 DM1
DQS10 I/O
I
SSTL Data Mask 0
Note:×8 based module
SSTL Data Strobe 9
Note:×4 based module
SSTL Data Mask 1
Note:×8 based module
SSTL Data Strobe 10
Note:×4 based module
SSTL Data Mask 2
Note:×8 based module
SSTL Data Strobe 11
Note:×4 based module
SSTL Data Mask 3
Note:×8 based module
SSTL Data Strobe 12
Note:×4 based module
SSTL Data Mask 4
Note:×8 based module
SSTL Data Strobe 13
Note:×4 based module
SSTL Data Mask 5
Note:×8 based module
SSTL Data Strobe 14
Note:×4 based module
SSTL Data Mask 6
Note:×8 based module
SSTL Data Strobe 15
Note:×4 based module
SSTL Data Mask 7
Note:×8 based module
SSTL Data Strobe 16
Note:×4 based module
SSTL Data Mask 8
Note:×8 based module
SSTL Data Strobe 17
Note:×4 based module
181 SA0
182 SA1
183 SA2
I
I
I
CMOS Slave Address Select
Bus 2:0
CMOS
CMOS
Power Supplies
AI
184 VDDSPD PWR –
I
1
VREF
–
I/O Reference Voltage
EEPROM Power
Supply
15, VDDQ
22,
30,
54,
62,
PWR –
I/O Driver Power
Supply
119 DM2
I
DQS11 I/O
77,
96,
129 DM3
I
104,
112,
128,
136,
143,
156,
164,
172,
180
DQS12 I/O
149 DM4
I
DQS13 I/O
7,
VDD
PWR –
Power Supply
159 DM5
I
38,
46,
70,
85,
108,
120,
148,
168
DQS14 I/O
169 DM6
I
DQS15 I/O
177 DM7
I
DQS16 I/O
140 DM8
I
DQS17 I/O
Data Sheet
10
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Pin Configuration
Table 3
Pin# Name Pin
Type Type
Pin Configuration of RDIMM (cont’d)
Table 4
Abbreviations for Pin Type
Buffer Function
Abbreviation Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
3,
VSS
GND
–
Ground Plane
O
11,
I/O
AI
I/O is a bidirectional input/output signal.
Input. Analog levels.
18,
26,
34,
42,
50,
58,
PWR
GND
NU
NC
Power
Ground
Not Usable (JEDEC Standard)
Not Connected (JEDEC Standard)
66,
74,
81,
89,
Table 5
Abbreviations for Buffer Type
Abbreviation Description
93,
100,
116,
124,
132,
139,
145,
152,
160,
176
SSTL
Serial Stub Terminalted Logic (SSTL2)
LV-CMOS
CMOS
OD
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding pin has 2
operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.
Other Pins
82
VDDID
O
OD
V
DD Identification
Note:Pin in tristate,
indicating VDD
and VDDQ nets
connected
PCB
on
9,
NC
NC
–
Not connected
16,
17,
Pins not connected on
Infineon RDIMM’s
71,
75,
76,
90,
101,
102,
103,
113,
163,
173
Data Sheet
11
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Pin Configuration
VREF - Pin 001
DQS0 - Pin 005
NC - Pin 009
DQ09 - Pin 013
NC - Pin 017
CKE0 - Pin 021
DQS2 - Pin 025
A7 - Pin 029
DQ24 - Pin 033
A4 - Pin 037
Pin 002 - DQ00
Pin 004 - DQ01
Pin 006 - DQ02
Pin 008 - DQ03
Pin 010 - RESET
Pin 012 - DQ08
Pin 014 - DQS1
Pin 016 - NC
V
V
SS - Pin 003
DD - Pin 007
V
SS - Pin 011
V
DDQ - Pin 015
DQ10 - Pin 019
DQ16 - Pin 023
A9 - Pin 027
Pin 018 - VSS
Pin 020 - DQ11
Pin 022 - VDDQ
Pin 024 - DQ17
Pin 026 - VSS
Pin 028 - DQ18
Pin 030 - VDDQ
DQ19 - Pin 031
DQ25 - Pin 035
DQ26 - Pin 039
Pin 032 - A5
VSS
VDD
Pin 034 -
Pin 038 -
Pin 036 - DQS3
Pin 040 - DQ27
A2 - Pin 041
CB01 - Pin 045
CB02 - Pin 049
DQ32 - Pin 053
DQ34 - Pin 057
DQ40 - Pin 061
CAS - Pin 065
DQ43 - Pin 069
DQ49 - Pin 073
VDDQ - Pin 077
Pin 042 - VSS
VDD
A1 - Pin 043
DQS8 - Pin 047
CB03 - Pin 051
DQ33 - Pin 055
BA0 - Pin 059
WE - Pin 063
DQS5 - Pin 067
NC - Pin 071
Pin 044 - CB00
Pin 048 - A0
Pin 046 -
Pin 050 - VSS
Pin 054 - VDDQ
Pin 058 - VSS
Pin 062 - VDDQ
Pin 066 - VSS
Pin 052 - BA1
Pin 056 - DQS4
Pin 060 - DQ35
Pin 064 - DQ41
Pin 068 - DQ42
Pin 072 - DQ48
Pin 076 - NC
Pin 080 - DQ51
Pin 084 - DQ57
Pin 088 - DQ59
Pin 092 - SCL
VDD
Pin 070 -
Pin 074 - VSS
Pin 078 - DQS6
VDDID
Pin 082 -
NC - Pin 075
DQ50 - Pin 079
DQ56 - Pin 083
DQ58 - Pin 087
SDA - Pin 091
DQ05 - Pin 095
DQ07 - Pin 099
NC - Pin 103
V
SS - Pin 081
V
DD - Pin 085
Pin 086 - DQS7
Pin 090 - NC
Pin 094 - DQ04
Pin 098 - DQ06
Pin 102 - NC
Pin 106 - DQ13
Pin 110 - DQ15
Pin 114 - DQ20
Pin 118 - A11
Pin 122 - A8
Pin 126 - DQ28
Pin 130 - A3
Pin 134 - DQ04
Pin 138 - CK0
Pin 142 - CB06
Pin 146 - DQ36
Pin 150 - DQ38
Pin 154 - RAS
Pin 158 - S1 /NC
Pin 162 - DQ47
Pin 166 - DQ53
Pin 170 - DQ54
Pin 174 - DQ60
Pin 178 - DQ62
Pin 182 - SA1
V
V
SS - Pin 089
SS - Pin 093
VDDQ
VSS
VDDQ
VDD
VDDQ
VSS
VDD
VSS
VDDQ
VSS
Pin 096 -
Pin 100 -
Pin 104 -
Pin 108 -
Pin 112 -
Pin 116 -
Pin 120 -
Pin 124 -
Pin 128 -
Pin 132 -
Pin 136 -
DM00/DQS9 - Pin 097
NC - Pin 101
DQ12 - Pin 105
DQ14 - Pin 109
NC - Pin 113
DQ21 - Pin 117
DQ22 - Pin 121
A6 - Pin 125
DM1/DQS10 - Pin 107
CKE1/NC - Pin 111
A12/NC - Pin 115
DM2/DQS11 - Pin 119
DQ23 - Pin 123
DQ29 - Pin 127
DQ30 - Pin 131
CB5 - Pin 135
DM3/DQS12 - Pin 129
DQ31 - Pin 133
CK0 - Pin 137
VDDQ
V
SS - Pin 139
Pin 140 - DM8/DQS17
Pin 144 - CB07
A10/AP - Pin 141
V
DDQ - Pin 143
DQ37 - Pin 147
DQ39 - Pin 151
DQ45 - Pin 155
DM5/DQS14 - Pin 159
NC - Pin 163
V
SS - Pin 145
VDD
VSS
VDDQ
VSS
VDDQ
VDD
VDDQ
VSS
VDDQ
Pin 148 -
Pin 152 -
Pin 156 -
Pin 160 -
Pin 164 -
Pin 168 -
Pin 172 -
Pin 176 -
Pin 180 -
DM4/DQS13 - Pin 149
DQ44 - Pin 153
S0 - Pin 157
DQ46 - Pin 161
DQ52 - Pin 165
DM6/DQS15 - Pin 169
NC - Pin 173
A13/NC - Pin 167
DQ55 - Pin 171
DQ61 - Pin 175
DQ63 - Pin 179
SA2 - Pin 183
DM7/DQS16 - Pin 177
SA0 - Pin 181
Pin 184 - VDDSPD
MPPD0020
Figure 1
Table 6
Pin Configuration 184 Pins, Reg
Address Table
Density Organization Memory SDRAMs # of SDRAMs # of row/rank/ Refresh Period Interval
Ranks
columns bits
256 MB 32 M ×72
512 MB 64 M ×72
1
1
32 M ×8
64 M ×4
9
18
13 / 2 / 10
13 / 2 / 11
8 K
8 K
64 ms 7.8 µs
64 ms 7.8 µs
Data Sheet
12
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Pin Configuration
Table 6
Address Table
Density Organization Memory SDRAMs # of SDRAMs # of row/rank/ Refresh Period Interval
Ranks
columns bits
512 MB 64 M ×72
2
2
32 M ×8
64 M ×4
18
36
13 / 2 / 10
13 / 2 / 11
8 K
8 K
64 ms 7.8 µs
64 ms 7.8 µs
1 GB
128 M ×72
CK0
CK0
S0
PCK
PCK
PLL
RS0
CS: SDRAMs D0- D8
CKE0
RCKE0
RBA0 - RBA1
RA0-RAn
RRAS
CKE: SDRAMs D0 - D8
BA0 - BA1: SDRAMs D0 - D8
A0 - An: SDRAMs D0 - D8
RAS: SDRAMs D0 - D8
CAS: SDRAMs D0 - D8
WE: SDRAMs D0 - D8
R
E
G
I
BA0 - BA1
A0 - An
RAS
CAS
RCAS
S
T
E
R
WE
RWE
PCK
PCK
RESET
S0
D3
D6
D0
D1
D2
DM0/DQS9
DQS0
DQ0
DM CS
DQS
I/O 0
DM3/DQS12
DQS3
DQ24
DM CS
DQS
I/O 0
DM6/DQS15
DQS6
DQ48
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ1
DQ25
I/O 1
DQ49
I/O 1
DQ2
DQ26
I/O 2
DQ50
I/O 2
DQ3
DQ27
I/O 3
DQ51
I/O 3
DQ4
I/O 4
DQ28
I/O 4
DQ52
DQ5
DQ29
I/O 5
DQ53
I/O 5
DQ6
DQ30
I/O 6
DQ54
I/O 6
DQ7
I/O 7
DQ31
I/O 7
DQ55
D4
D5
D7
D8
DM1/DQS10
DQS1
DQ8
DM CS
DQS
I/O 0
DM4/DQS13
DQS4
DQ32
DM CS
DQS
I/O 0
DM7/DQS16
DQS7
DQ56
DM CS
DQS
I/O 0
DQ9
I/O 1
DQ33
I/O 1
DQ57
I/O 1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
DQ34
I/O 2
DQ58
I/O 2
I/O 3
DQ35
I/O 3
DQ59
I/O 3
I/O 4
DQ36
I/O 4
DQ60
I/O 4
I/O 5
DQ37
I/O 5
DQ61
I/O 5
I/O 6
DQ38
I/O 6
DQ62
I/O 6
I/O 7
DQ39
I/O 7
DQ63
I/O 7
DM2/DQS11
DQS2
DQ16
DM CS
DQS
I/O 0
DM5/DQS14
DQS5
DQ40
DM CS
DQS
I/O 0
DM8/DQS17
DQS8
CB0
DM CS
DQS
I/O 0
DQ17
I/O 1
DQ41
I/O 1
CB1
I/O 1
DQ18
I/O 2
DQ42
I/O 2
CB2
I/O 2
DQ19
I/O 3
DQ43
I/O 3
CB3
I/O 3
DQ20
I/O 4
DQ44
I/O 4
CB4
I/O 4
DQ21
I/O 5
DQ45
I/O 5
CB5
I/O 5
DQ22
I/O 6
DQ46
I/O 6
CB6
I/O 6
DQ23
I/O 7
DQ47
I/O 7
CB7
I/O 7
E0
VDD,SPD
V
DD: SPD EEPROM E0
DD/VDDQ: SDRAMs D0 - D8
REF: SDRAMs D0 - D8
SS: SDRAMs D0 - D8
SCL
SAD
SA0
SA1
SA2
VSS
SCL
SAD
A0
V
DD/VDDQ
V
V
V
VREF
A1
VSS
A2
VDDID
WP
Strap: see Note 1
MPBD1101
Figure 2
Notes
Block Diagram Raw Card A ×72 1 Rank ×8, ECC
3. BAn, An, RAS, CAS, WE resistors are 22 ohms
± 5%
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 ohms ± 5%
Data Sheet
13
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Pin Configuration
CK0
CK0
PCK
PCK
PLL
S0
CKE0
S1
RS0
R
E
G
I
RCKE0
RS1
CKE: SDRAMs D0 - D8
CKE1
BA0 - BA1
A0 - An
RAS
RCKE1
RBA0 - RBA1
RA0 - RAn
RRAS
CKE: SDRAMs D9 - D17
BA0 - BA1: SDRAMs D0 - D17
A0 - An: SDRAMs D0 - D17
RAS: SDRAMs D0 - D17
CAS: SDRAMs D0 - D17
WE: SDRAMs D0 - D17
S
T
E
R
E0
SCL
SAD
SA0
SA1
SA2
VSS
SCL
SAD
A0
CAS
RCAS
WE
RWE
A1
PCK
A2
PCK
WP
RESET
S0
S1
D0
D1
D2
D3
D9
D4
D5
D6
D7
D8
D13
CS
CS
CS
CS
CS
DM
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
DM0/DQS9
DQS0
DQ0
DM4/DQS13
DM
DM
DM
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
DQ1
I/O 1
DQ2
I/O 2
DQ3
I/O 3
DQ4
I/O 4
DQ5
I/O 5
DQ6
I/O 6
DQ7
I/O 7
D10
D11
D12
D14
D15
D16
D17
CS
DM
DM5/DQS14
DQS5
DQ40
DM
DM
DM
DM1/DQS10
DQS1
DQ8
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
DQ41
I/O 1
DQ9
DQ42
I/O 2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ43
I/O 3
DQ44
I/O 4
DQ45
I/O 5
DQ46
I/O 6
DQ47
I/O 7
CS
DM
DM2/DQS11
DQS2
DQ16
DM6/DQS15
DQS6
DQ48
DM
DM
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
DQ17
DQ49
I/O 1
DQ18
DQ50
I/O 2
DQ19
DQ51
I/O 3
DQ20
DQ52
I/O 4
DQ21
DQ53
I/O 5
DQ22
DQ54
I/O 6
DQ23
DQ55
I/O 7
CS
DM
DM7/DQS16
DQS7
DQ56
DM
DM
DM
DM3/DQS12
DQS3
DQ24
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
DQ57
I/O 1
DQ25
DQ58
I/O 2
DQ26
DQ59
I/O 3
DQ27
DQ60
I/O 4
DQ28
DQ61
I/O 5
DQ29
DQ62
I/O 6
DQ30
DQ63
I/O 7
DQ31
DM8/DQS17
DQS8
CB0
DM
DM
VDD,SPD
V
V
V
V
DD: SPD EEPROM E0
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
V
DD/VDDQ
DD/VDDQ: SDRAMs D0 - D17
REF: SDRAMs D0 - D17
SS: SDRAMs D0 - D17
VREF
CB1
CB2
VSS
CB3
VDDID
DM: SDRAMs D0 - D17
CB4
CB5
Strap: see Note 1
CB6
CB7
MPBD1401
Figure 3
Notes
Block Diagram Raw Card B ×72, 2Ranks ×8, ECC
3. BAn, An, RAS, CAS, WE resistors are 22 ohms
±5%
4. For Wire per Clock Loading please see Figure:
“Diferential Clock Net Wiring“
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 ohms ±5%
Data Sheet
14
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Pin Configuration
CK0
CK0
PCK
PCK
PLL
S0
CKE0
BA0 - BA1
A0 - An
RAS
RS0
CS: SDRAMs D0- D17
RCKE0
RBA0 - RBA1
RA0 - RAn
RRAS
CKE: SDRAMs D0 - D17
BA0 - BA1: SDRAMs D0 - D17
A0 - An: SDRAMs D0 - D17
RAS: SDRAMs D0 - D17
CAS: SDRAMs D0 - D17
WE: SDRAMs D0 - D17
R
E
G
I
CAS
RCAS
S
T
E
R
WE
RWE
PCK
PCK
RESET
RS0
D0
D1
D2
D3
D4
D5
D6
CS
D12
D13
D14
D15
D16
D17
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
DQS0
DQ0
DQ1
DQ2
DQ3
DQS
DQS6
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS12
DQ28
DQ29
DQ30
DQ31
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ48
DQ49
DQ50
DQ51
I/O 0
I/O 1
I/O 2
I/O 3
D7
CS
DQS1
DQ8
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS7
DQ56
DQ57
DQ58
DQ59
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS13
DQ36
DQ37
DQ38
DQ39
DQ9
DQ10
DQ11
D8
CS
DQS2
DQ16
DQ17
DQ18
DQ19
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS8
CB0
CB1
CB2
CB3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS14
DQ44
DQ45
DQ46
DQ47
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D9
CS
DQS3
DQ24
DQ25
DQ26
DQ27
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS9
DQ4
DQ5
DQ6
DQ7
DQS15
DQ52
DQ53
DQ54
DQ55
D10
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS10
DQ12
DQ13
DQ14
DQ15
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS16
DQ60
DQ61
DQ62
DQ63
DQS4
DQ32
DQ33
DQ34
DQ35
D11
CS
DQS11
DQ20
DQ21
DQ22
DQ23
DQS17
CB4
DQS5
DQ40
DQ41
DQ42
DQ43
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CB5
CB6
CB7
E0
VDD,SPD
SCL
SAD
SA0
SA1
SA2
VSS
SCL
SAD
A0
V
V
V
V
DD: SPD EEPROM E0
V
DD/VDDQ
VREF
DD/VDDQ: SDRAMs D0 - D17
REF: SDRAMs D0 - D17
SS: SDRAMs D0 - D17
A1
VSS
VDDID
A2
WP
Strap: see Note 1
MPBD1501
Figure 4
Notes
Block Diagram Raw Card C ×72 1 Rank ×4, ECC
3. BAn, An, RAS, CAS, WE resistors are 22 ohms
± 5%
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 ohms ± 5%
Data Sheet
15
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Pin Configuration
CK0
CK0
PCK
PCK
VDD,SPD
PLL
V
V
V
V
DD: SPD EEPROM E0
DD/VDDQ: SDRAMs D0 - D35
REF: SDRAMs D0 - D35
SS: SDRAMs D0 - D35
V
DD/VDDQ
S0
CKE0
S1
RS0
VREF
R
E
G
I
RCKE0
RS1
VSS
VDDID
CKE1
BA0 - BA1
A0 - An
RAS
RCKE1
RBA0 - RBA1
RA0-RAn
RRAS
DM: SDRAMs D0 - D35
BA0 - BA1: SDRAMs D0 - D35
A0 - An: SDRAMs D0 - D35
RAS: SDRAMs D0 - D35
CAS: SDRAMs D0 - D35
WE: SDRAMs D0 - D35
Strap: see Note 1
S
T
E
R
E0
SCL
SAD
SA0
SA1
SA2
VSS
SCL
SAD
A0
CAS
RCAS
WE
RWE
A1
PCK
A2
PCK
WP
RESET
RS0
RCKE0
RS1
RCKE1
D6
D4
D5
D7
CKE CS
CKE CS
CKE CS
CKE CS
DQS0
DQ0
DQ1
DQ2
DQ3
DQS7
DQ56
DQ57
DQ58
DQ59
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
D2
D0
D1
D3
CKE CS
CKE CS
CKE CS
CKE CS
DQS6
DQ48
DQ49
DQ50
DQ51
DQS1
DQ8
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ10
DQ11
D12
D8
D14
D13
D9
D15
D11
D23
D19
D27
D31
D35
CKE CS
CKE CS
CKE CS
CKE CS
DQS10
DQ12
DQ13
DQ14
DQ15
DQS15
DQ52
DQ53
DQ54
DQ55
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D10
D22
D18
D26
D30
D34
CKE CS
CKE CS
CKE CS
CKE CS
DQS9
DQ4
DQ5
DQ6
DQ7
DQS16
DQ60
DQ61
DQ62
DQ63
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D20
D16
D24
D28
D32
D21
D17
D25
D28
D33
CKE CS
CKE CS
CKE CS
CKE CS
DQS11
DQ20
DQ21
DQ22
DQ23
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS14
DQ44
DQ45
DQ46
DQ47
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
CKE CS
CKE CS
CKE CS
DQS2
DQ16
DQ17
DQ18
DQ19
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS5
DQ40
DQ41
DQ42
DQ43
CKE CS
CKE CS
CKE CS
CKE CS
DQS3
DQ24
DQ25
DQ26
DQ27
DQS4
DQ32
DQ33
DQ34
DQ35
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
CKE CS
CKE CS
CKE CS
DQS17
CB4
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS8
CB0
CB1
CB2
CB3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CB5
CB6
CB7
CKE CS
CKE CS
CKE CS
CKE CS
DQS12
DQ28
DQ29
DQ30
DQ31
DQS13
DQ36
DQ37
DQ38
DQ39
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
MPBD1061
Figure 5
Notes
Block Diagram Raw Card D ×72 2 Ranks ×4, ECC
3. BAn, An, RAS, CAS, WE resistors are 22 ohms
±
5%
4. For Wire per Clock Loading please see Figure
“Differental Clock Net Wiring“
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 18 ohms ± 5%
Data Sheet
16
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 7
Absolute Maximum Ratings
Parameter
Symbol
Values
typ.
Unit Note/ Test
Condition
min.
VIN, VOUT –0.5
max.
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
–
V
DDQ +0.5
V
–
–
–
–
–
–
–
–
VIN
–1
–1
–1
0
–
+3.6
+3.6
+3.6
+70
+150
–
V
VDD
VDDQ
TA
–
V
–
V
–
°C
°C
W
mA
TSTG
PD
-55
–
–
Power dissipation (per SDRAM component)
Short circuit output current
1
IOUT
–
50
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 8
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Values
Typ.
Unit Note/Test Condition 1)
Min.
2.3
2.5
2.3
2.5
Max.
2.7
2.7
2.7
2.7
3.6
0
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
EEPROM supply voltage
VDD
2.5
2.6
2.5
2.6
2.5
V
V
V
V
V
V
fCK ≤ 166 MHz
CK > 166 MHz 2)
fCK ≤ 166 MHz 3)
CK > 166 MHz 2)3)
VDD
f
VDDQ
VDDQ
f
VDDSPD 2.3
—
—
Supply Voltage, I/O Supply VSS,
0
Voltage
VSSQ
VREF
VTT
4)
5)
Input Reference Voltage
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ
V
I/O Termination Voltage
(System)
V
REF – 0.04
V
REF + 0.04 V
8)
8)
8)
Input High (Logic1) Voltage VIH(DC)
Input Low (Logic0) Voltage VIL(DC)
V
REF + 0.15
V
V
V
DDQ + 0.3
V
–0.3
REF – 0.15 V
Input Voltage Level,
CK and CK Inputs
VIN(DC) –0.3
DDQ + 0.3
DDQ + 0.6
V
8)6)
7)
Input Differential Voltage, VID(DC) 0.36
CK and CK Inputs
V
V
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio
0.71
1.4
—
Data Sheet
17
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Electrical Characteristics
Table 8
Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter
Symbol
Values
Typ.
Unit Note/Test Condition 1)
Min.
Max.
Input Leakage Current
Output Leakage Current
II
–2
2
µA Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 8)9)
IOZ
IOH
IOL
–5
5
µA DQs are disabled;
0 V ≤ VOUT ≤ VDDQ
Output High Current,
Normal Strength Driver
—
–16.2
—
mA
V
OUT = 1.95 V
Output Low
16.2
mA
V
OUT = 0.35 V
Current, Normal Strength
Driver
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF
.
.
.
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per DDR SDRAM component
Data Sheet
18
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
4
Current Specification and Conditions
Table 9
IDD Conditions
Parameter
Symbol
Operating Current 0
IDD0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
IDD1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
IDD2F
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN
;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current
IDD2Q
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX
.
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
IDD3N
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
;
Operating Current Read
IDD4R
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
Operating Current Write
IDD4W
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
IDD5
IDD6
IDD7
t
RC = tRFCMIN, burst refresh
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
Data Sheet
19
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
Table 10
IDD Specification for PC3200
Unit
Note/ Test Conditions1) 2)
256 MB
×72
512 MB
×72
512 MB
×72
1 Rank
–5
1 Rank
–5
2 Ranks
–5
Symbol
IDD0
Typ.
1510
1600
680
Max.
1690
1780
689
Typ.
2140
2320
716
Max.
2500
2680
734
Typ.
1852
1942
788
Max.
2095
2185
824
3)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)4)
5)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
5)
914
968
1184
1004
878
1292
1148
968
1184
1004
878
1292
1148
968
5)
824
896
5)
761
806
5)
986
1049
1780
1825
2590
670
1328
2410
2500
3400
669
1454
2680
2770
4300
694
1328
1987
2032
2482
669
1454
2185
2230
2995
694
3)4)
3)
1645
1690
2140
657
3)
5)
IDD6
3)4)
IDD7
2770
3130
4660
5380
3112
3535
1) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
2) Module IDD is calculated on the basis of component IDD and includes Register an PLL
3) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
n * IDD×[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
5) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
2 * n * IDD×[component] for single two bank modules (n: number of components per module bank)
Data Sheet
20
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
Table 11
IDD Specification for PC2700
Unit Note/ Test Conditions1) 2)
256 MB
×72
512 MB
×72
512 MB
×72
1 GB
×72
1 Rank
–6
1 Rank
–6
2 Ranks
–6
2 Ranks
–6
Symbol Typ.
Max. Typ.
Max. Typ.
Max. Typ.
Max.
3)
IDD0
1270 1405 1810 2080 1558 1747 2386 2764 mA
1360 1495 1990 2260 1648 1837 2566 2944 mA
3)4)
5)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
466
655
583
529
718
475
700
646
565
772
502
880
736
628
520
970
862
700
574
880
736
628
610
970
862
700
718
790
mA
5)
1330 1510 mA
1042 1294 mA
5)
5)
826
970
mA
5)
1006 1114 1006 1114 1582 1798 mA
3)4)
3)
1360 1495 1990 2260 1648 1837 2566 2944 mA
1405 1540 2080 2350 1693 1882 2656 3034 mA
1810 2170 2890 3610 2098 2512 3466 4294 mA
3)
5)
IDD6
443
455
455
480
455
480
480
531
mA
3)4)
IDD7
2350 2665 3970 4600 2638 3007 4546 5284 mA
1) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
2) Module IDD is calculated on the basis of component IDD and includes Register an PLL
3) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
n * IDD×[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
5) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
2 * n * IDD×[component] for single two bank modules (n: number of components per module bank)
Data Sheet
21
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
4.1
AC Characteristics
Table 12
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol –5
DDR400B
–6
Unit Note/ Test
Condition 1)
DDR333
Min.
–0.5
–0.6
0.45
0.45
Max.
+0.5
+0.6
0.55
0.55
Min. Max.
–0.7 +0.7
–0.6 +0.6
0.45 0.55
0.45 0.55
2)3)4)5)
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
ns
2)3)4)5)
tDQSCK
tCH
ns
2)3)4)5)
tCK
2)3)4)5)
CK low-level width
tCL
tCK
2)3)4)5)
Clock Half Period
tHP
min. (tCL, tCH)
min. (tCL, tCH) ns
Clock cycle time
tCK
5
8
6
12
12
12
ns
ns
ns
CL = 3.0
2)3)4)5)
6
12
12
6
CL = 2.5
2)3)4)5)
7.5
7.5
CL = 2.0
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)6)
DQ and DM input hold time
DQ and DM input setup time
tDH
tDS
0.4
0.4
2.2
—
—
—
0.45
0.45
2.2
—
—
—
ns
ns
ns
Control and Addr. input pulse width (each
input)
tIPW
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
DQ and DM input pulse width (each input)
Data-out high-impedance time from CK/CK
Data-out low-impedance time from CK/CK
tDIPW
tHZ
1.75
—
—
1.75
—
ns
ns
ns
tCK
+0.7
+0.7
1.25
+0.40
–0.7 +0.7
–0.7 +0.7
0.75 1.25
tLZ
–0.7
0.72
—
Write command to 1st DQS latching transition tDQSS
DQS-DQ skew (DQS and associated DQ
signals)
tDQSQ
—
+0.40 ns
TFBGA 2)3)4)5)
Data hold skew factor
tQHS
tQH
—
+0.50
—
+0.50 ns
ns
TFBGA 2)3)4)5)
2)3)4)5)
DQ/DQS output hold time
tHP –tQHS
2)3)4)5)
2)3)4)5)
2)3)4)5)
DQS input low (high) pulse width (write cycle) tDQSL,H 0.35
—
—
—
0.35
0.2
—
—
—
tCK
tCK
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
0.2
DQS falling edge hold time from CK (write
cycle)
tDSH
0.2
2)3)4)5)
Mode register set command cycle time
Write preamble setup time
Write postamble
tMRD
2
—
2
0
—
—
tCK
ns
2)3)4)5)8)
2)3)4)5)9)
2)3)4)5)
tWPRES
tWPST
tWPRE
tIS
0
—
0.40
0.25
0.6
0.60
—
0.40 0.60
tCK
tCK
ns
Write preamble
0.25
0.75
—
—
Address and control input setup time
—
fast slew rate
3)4)5)6)10)
0.7
0.6
0.7
—
—
—
0.8
—
—
—
ns
ns
ns
slow slew
rate3)4)5)6)10)
Address and control input hold time
tIH
0.75
0.8
fast slew rate
3)4)5)6)10)
slow slew
rate3)4)5)6)10)
Data Sheet
22
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
Table 12
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol –5
DDR400B
–6
Unit Note/ Test
Condition 1)
DDR333
Min. Max.
Min.
0.9
0.40
40
Max.
1.1
2)3)4)5)
Read preamble
tRPRE
tRPST
tRAS
0.9
1.1
tCK
2)3)4)5)
Read postamble
0.60
0.40 0.60
tCK
2)3)4)5)
Active to Precharge command
70E+3 42
70E+3 ns
2)3)4)5)
2)3)4)5)
Active to Active/Auto-refresh command period tRC
55
—
—
60
72
—
—
ns
ns
Auto-refresh to Active/Auto-refresh command tRFC
70
period
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B command
Write recovery time
tRCD
tRP
15
15
—
—
18
18
—
—
ns
ns
ns
ns
ns
tCK
tRAP
tRRD
tWR
tRCD or tRASmin
10
15
—
—
12
15
—
—
Auto precharge write recovery + precharge
time
tDAL
(tWR/tCK)+(tRP/tCK)
2)3)4)5)
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
tWTR
tXSNR
tXSRD
tREFI
2
—
—
—
7.8
1
—
—
—
7.8
tCK
ns
tCK
µs
2)3)4)5)
75
200
—
75
200
—
2)3)4)5)
2)3)4)5)12)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VIH(ac) and VIL(ac)
.
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
23
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
SPD Contents
5
SPD Contents
Table 13
SPD Codes for HYS72D[128/64/32][300/320]GBR–5–C
512 MB
×72
512 MB
×72
256 MB
×72
1 Rank
2 Ranks
1 Rank
Label Code
PC3200R–30331 PC3200R–30331 PC3200R–30331
Jedec SPD Revision
Description
Rev 1.0
HEX
80
Rev 1.0
HEX
80
Rev 1.0
HEX
80
Byte#
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
Data Width (LSB)
1
08
08
08
2
07
07
07
3
0D
0B
01
0D
0A
02
0D
0A
01
4
5
6
48
48
48
7
Data Width (MSB)
00
00
00
8
Interface Voltage Levels
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
04
04
04
9
50
50
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
50
50
02
02
02
82
82
82
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
04
08
08
04
08
08
01
01
01
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
0E
04
0E
04
0E
04
1C
01
1C
01
1C
01
CS Latency
Write Latency
02
02
02
DIMM Attributes
26
26
26
Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
C1
60
C1
60
C1
60
50
50
50
75
75
75
Data Sheet
24
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
SPD Contents
Table 13
SPD Codes for HYS72D[128/64/32][300/320]GBR–5–C
512 MB
×72
512 MB
×72
256 MB
×72
1 Rank
2 Ranks
1 Rank
Label Code
PC3200R–30331 PC3200R–30331 PC3200R–30331
Jedec SPD Revision
Description
Rev 1.0
HEX
50
Rev 1.0
HEX
50
Rev 1.0
HEX
50
Byte#
26
tAC SDRAM @ CLmax -1 [ns]
tRPmin [ns]
27
3C
28
3C
28
3C
28
28
tRRDmin [ns]
29
tRCDmin [ns]
3C
28
3C
28
3C
28
30
tRASmin [ns]
31
Module Density per Rank
tAS, tCS [ns]
80
40
40
32
60
60
60
33
tAH, TCH [ns]
60
60
60
34
tDS [ns]
40
40
40
35
tDH [ns]
40
40
40
36 - 40
41
not used
00
00
00
tRCmin [ns]
37
37
37
42
tRFCmin [ns]
41
41
41
43
tCKmax [ns]
28
28
28
44
tDQSQmax [ns]
tQHSmax [ns]
28
28
28
45
50
50
50
46
not used
00
00
00
47
DIMM PCB Height
not used
01
01
01
48 - 61
62
00
00
00
SPD Revision
10
10
10
63
Checksum of Byte 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2 - 8)
Module Manufacturer Location
Part Number, Char 1
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
5F
C1
00
27
26
64
C1
00
C1
00
65 - 71
72
xx
xx
xx
73
37
37
37
74
32
32
32
75
44
44
44
76
36
36
33
Data Sheet
25
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
SPD Contents
Table 13
SPD Codes for HYS72D[128/64/32][300/320]GBR–5–C
512 MB
×72
512 MB
×72
256 MB
×72
1 Rank
2 Ranks
1 Rank
Label Code
PC3200R–30331 PC3200R–30331 PC3200R–30331
Jedec SPD Revision
Description
Rev 1.0
HEX
34
Rev 1.0
HEX
34
Rev 1.0
HEX
32
Byte#
77
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1 - 4)
78
33
33
33
79
30
32
30
80
30
30
30
81
47
47
47
82
42
42
42
83
52
52
52
84
35
35
35
85
43
43
43
86
20
20
20
87
20
20
20
88
20
20
20
89
20
20
20
90
20
20
20
91
xx
xx
xx
92
xx
xx
xx
93
xx
xx
xx
94
xx
xx
xx
95 - 98
xx
xx
xx
99 - 127 Blank
FF
FF
FF
Data Sheet
26
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
SPD Contents
Table 14
SPD Codes for HYS72D[128/64/32][300/320]GBR–6–C
1 GByte
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R– PC2700R– PC2700R–
PC2700R–
25330
25330
Rev 0.0
HEX
80
25330
Rev 0.0
HEX
80
25330
Rev 0.0
HEX
80
Jedec SPD Revision
Rev 0.0
HEX
80
Byte#
0
Description
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
Data Width (LSB)
1
08
08
08
08
2
07
07
07
07
3
0D
0B
02
0D
0B
01
0D
0A
02
0D
0A
01
4
5
6
48
48
48
48
7
Data Width (MSB)
00
00
00
00
8
Interface Voltage Levels
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
04
04
04
04
9
60
60
60
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
70
70
70
70
02
02
02
02
82
82
82
82
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
04
04
08
08
04
04
08
08
01
01
01
01
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
0E
04
0E
04
0E
04
0E
04
0C
01
0C
01
0C
01
0C
01
CS Latency
Write Latency
02
02
02
02
DIMM Attributes
26
26
26
26
Component Attributes
C1
75
C1
75
C1
75
C1
75
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
70
70
70
70
00
00
00
00
Data Sheet
27
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
SPD Contents
Table 14
SPD Codes for HYS72D[128/64/32][300/320]GBR–6–C
1 GByte
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R– PC2700R– PC2700R–
PC2700R–
25330
25330
Rev 0.0
HEX
00
25330
Rev 0.0
HEX
00
25330
Rev 0.0
HEX
00
Jedec SPD Revision
Description
Rev 0.0
HEX
00
Byte#
26
tAC SDRAM @ CLmax -1 [ns]
tRPmin [ns]
27
48
48
48
48
28
tRRDmin [ns]
30
30
30
30
29
tRCDmin [ns]
48
48
48
48
30
tRASmin [ns]
2A
80
2A
80
2A
40
2A
40
31
Module Density per Rank
tAS, tCS [ns]
32
75
75
75
75
33
tAH, TCH [ns]
75
75
75
75
34
tDS [ns]
45
45
45
45
35
tDH [ns]
45
45
45
45
36 - 40 not used
00
00
00
00
41
42
43
44
45
46
47
tRCmin [ns]
3C
48
3C
48
3C
48
3C
48
tRFCmin [ns]
tCKmax [ns]
30
30
30
30
tDQSQmax [ns]
tQHSmax [ns]
not used
28
28
28
28
50
50
50
50
00
00
00
00
DIMM PCB Height
00
00
00
00
48 - 61 not used
00
00
00
00
62
63
64
SPD Revision
00
00
00
00
Checksum of Byte 0-62
49
48
10
0F
C1
00
JEDEC ID Code of Infineon (1)
C1
00
C1
00
C1
00
65 - 71 JEDEC ID Code of Infineon (2 - 8)
72
73
74
75
Module Manufacturer Location
Part Number, Char 1
xx
xx
xx
xx
37
37
37
37
Part Number, Char 2
32
32
32
32
Part Number, Char 3
44
44
44
44
Data Sheet
28
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
SPD Contents
Table 14
SPD Codes for HYS72D[128/64/32][300/320]GBR–6–C
1 GByte
×72
512 MB
×72
512 MB
×72
256 MB
×72
2 Ranks
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R– PC2700R– PC2700R–
PC2700R–
25330
25330
Rev 0.0
HEX
31
25330
Rev 0.0
HEX
36
25330
Rev 0.0
HEX
36
Jedec SPD Revision
Description
Rev 0.0
HEX
33
Byte#
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
32
34
34
32
38
33
33
33
33
30
32
30
32
30
30
30
30
47
47
47
47
42
42
42
42
52
52
52
52
36
36
36
36
43
43
43
43
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
95 - 98 Module Serial Number (1 - 4)
99 -127 Blank
xx
xx
xx
xx
FF
FF
FF0
FF
Data Sheet
29
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Package Outlines
6
Package Outlines
133.35
128.95
0.15
A B C
2.64 MAX.
A
1
2.5
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
Burr max. 0.4 allowed
L-DIMM-184-021
Rev. 1.0, 2004-03
Figure 6
Package Outlines – Raw Card A HYS72D32300GBR–[5/6]–C (1 Rank × 8)
Data Sheet
30
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Package Outlines
133.35
128.95
0.15
A B C
4 MAX.
A
1
2.5
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
Burr max. 0.4 allowed
L-DIMM-184-22-2
Figure 7
Package Outlines – Raw Card C HYS72D64300GBR–[5/6]–C (1 Rank × 4)
Data Sheet
31
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Package Outlines
133.35
128.95
0.15
A B C
4 MAX.
A
1
2.5
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
Burr max. 0.4 allowed
L-DIMM-184-23
Figure 8
Package Outlines – Raw Card B HYS72D64320GBR–[5/6]–C (2 Ranks ×8)
Data Sheet
32
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Package Outlines
133.35
128.95
0.15
A B C
4 MAX.
A
1
2.5
92
B
C
6.62
2.175
±0.1
ø0.1
A B C
0.4
6.35
±0.1
1.27
64.77
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
L-DIMM-184-24-3
Burr max. 0.4 allowed
Figure 9
Package Outlines – Raw Card D HYS72D128320GBR–[5/6]–C (2 Ranks ×4)
Data Sheet
33
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Application Note
7
Application Note
Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item
1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and
to minimize power consumption during low power mode. One feature is externally controlled via a system-
generated RESET signal; the second is based on module detection of the input clocks. These enhancements
permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations
and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked
Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other SDRAM
inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low level, all the
register outputs are forced to a low level, and all differential register input receivers are powered down, resulting
in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as
an asynchronous signal according to the attached details. Using this function also permits the system and DIMM
clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh
mode.
Table 15
RESET Truth Table
Register Inputs
Register
Outputs
RESET
CK
CK
Data in (D)
Data out (Q)
H
H
H
H
Rising
Rising
L or H
Falling
Falling
L or H
High Z
H
L
H
L
X
X
Qo
High Z
Illegal input
conditions
L
X or Hi-Z
X or Hi-Z
X or Hi-Z
L
X: Don’t care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are
maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low
maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until
activated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz
or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating
frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual
detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made
High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less than
1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied
inactive on the DIMM.
This application note describes the required and optional system sequences associated with the DDR Registered
DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2-
bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control
CKE to one physical DIMM bank through the use of the RESET pin.
Data Sheet
34
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Application Note
Power-Up Sequence with RESET — Required
1. The system sets RESET at a valid low level.
This is the preferred default state during power-up. This input condition forces all register outputs to a low state
independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level
at the DDR SDRAMs.
2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR
SDRAMs.
3. Stabilization of Clocks to the SDRAM
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,
the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a
stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 µsec prior to
SDRAM operation.
4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would
be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be
consistent with the state of the register outputs.
5. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs
must remain stable).
6. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows their clock receivers, data input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-
pproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) — Optional
Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down
and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.
Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption
(RESET low deactivates register CK and CK, data input receivers, and data output drivers).
1. 1. The system applies Self Refresh entry command.
(CKE→Low, CS→Low, RAS → Low, CAS→ Low, WE→ High)
Note:Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares— with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the registerm
inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-level
at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a
specific clock edge is not required.
3. The system turns off clock inputs to the DIMM. (Optional)
a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
Data Sheet
35
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Application Note
inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the
register (t (INACT). The deactivate time defines the time in which the clocks and the control and address
signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM
documentation.
b.The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which
the clocks and the control and the address signals must maintain valid levels after RESET low has been
applied. It is highly recommended that CKE continue to remain low during this operation.
4. The DIMM is in lowest power Self Refresh mode.
Self Refresh Exit (RESET low, clocks powered off) — Optional
1. Stabilization of Clocks to the SDRAM.
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,
the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds.
2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this
would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs, to
be consistent with the state of the register outputs.
3. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
RESET timing relationship to a specific clock edge is not required (during this period, register inputs must
remain stable).
4. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) — Optional
Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this
is an alternate operating mode for these DIMMs.
1. 1. System enters Self Refresh entry command.
(CKE→ Low, CS→ Low, RAS→ Low, CAS→ Low, WE→ High)
Note:Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares — with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the data and clock
register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs.
3. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes
the time in which the clocks and the control and the address signals must maintain valid levels after RESET
low has been applied. It is highly recommended that CKE continue to remain low during the operation.
4. The DIMM is in a low power, Self Refresh mode.
Data Sheet
36
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Application Note
Self Refresh Exit (RESET low, clocks running) — Optional
1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector). CKE must be maintained low and all other inputs should be driven to a known state. In general
these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’
command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this
would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be
consistent with the state of the register outputs.
2. The system switches RESET to a logic 'high' level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain
stable).
3. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE
outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation
time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept
an input signal, is t (ACT ) as specified in the register and DIMM documentation.
4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) — Optional
As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification
explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) — Not Permissible
In order to maintain a valid low level on the register output, it is required that either the clocks be running and the
system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the
sequence defined in this application note. In the case where RESET remains high and the clocks are powered off,
the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM
state will result.
Data Sheet
37
Rev. 1.0, 2004-03
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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