HYS72T128000HF-3-A_技术文档

Data Sheet, Rev. 0.9, Apr. 2005

HYS72T64000HF–[3.7/3]–A

HYS72T1280[00/20]HF–[3.7/3]–A

HYS72T256020HF–[3.7/3]–A

240-Pin Fully- Buffered DDR2 SDRAM Modules

DDR2 SDRAM

FB-DIMM SDRAM

RoHS Compliant

Green Product

High-Speed Differential Point-to-Point Link

Interface at 1.5 V

Memory Products

N e v e r s t o p t h i n k i n g .

Edition 2005-04

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

HYS72T64000HF–[3.7/3]–A HYS72T1280[00/20]HF–[3.7/3]–A HYS72T256020HF–[3.7/3]–A

Preliminary

Revision History: 2005-04, Rev. 0.9

Previous Version: 0.8

Page

28

Subjects (major changes since last revision)

updated Table 13

29

updated Table 14

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

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Template: mp_a4_s_rev312 / 3 / 2005-03-18

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Table of Contents

1

1.1

1.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2

3

4

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

FB-DIMM Input/Output Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5

5.1

5.2

5.2.1

5.2.2

5.2.3

5.3

5.4

5.5

5.5.1

5.5.2

5.5.3

5.5.4

5.6

Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Advanced Memory Buffer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Advanced Memory Buffer Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Advanced Memory Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Transparent Mode for DRAM Test Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Advanced Memory Buffer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DDR2 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Channel Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Peak Theoretical Channel Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Hot-add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Hot-remove . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Hot-replace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.7

5.8

6

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7

8

9

Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

ICC/IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Termination Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10

10.1

High-Speed Differential Point-to-Point Link Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Differential Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Transition Density in Transmitted Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Jitter and Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

De-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Electrical Idle (EI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

High Speed Serial Link Reference Clocks (SCK, SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Spread Spectrum Clocking (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Reference Clock Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Differential Transmitter Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Differential Receiver Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Receiver Input Compliance Eye Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10.1.1

10.1.2

10.1.3

10.1.4

10.1.5

10.2

10.3

10.4

10.5

10.6

10.6.1

11

11.1

11.1.1

11.2

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

Channel Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

RESET Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Inband Control ‘Signals’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Channel Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Firmware Transition Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

AMB Internal State Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Disable State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Training State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Testing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Data Sheet

4

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

11.2.6

11.2.7

Polling State 43

Config State 43

12.3.3

Simultaneous Read and Write Data

Transfers 51

12.3.4

DRAM Bus Segment Restrictions 51

12

Channel Protocol 44

12.1

12.1.1

12.1.2

12.1.3

12.1.3.1

12.1.3.2

12.1.4

12.1.4.1

12.1.4.2

12.1.4.3

12.1.4.4

12.1.4.5

12.1.4.6

12.1.4.7

12.1.4.8

Southbound Frames 44

13

Reliability, Availability and Serviceability

52

Overview 52

Example Error Flows 52

Command Error Flow 52

Normal Southbound Frames 44

Fail-over Southbound Frames 44

Command Frame Format 44

Command Frame with Data Format 44

Command+Wdata Frame Format 44

Southbound Commands 44

DRAM Commands 44

13.1

13.2

13.2.1

13.2.2

13.2.3

13.3

Write Data Error Flow 52

Read Error Flow 52

Overview of Error Protection, Detection,

Correction, and Logging 53

Error Protection and Detection Methods 54

CRC Logic Used on Normal Southbound

Frames 54

Fail-over Southbound Frames 54

Write and Read Data ECC Error Protection

54

Southbound Error Handling at the AMB 54

Exiting Command Error State 54

Northbound Error Handling at the AMB 55

Error Logging 55

Fail-over Mode Operation 55

Fail-over Mode Operation on Southbound

Lanes 55

Channel Commands 45

CKE Control Commands 45

Soft Channel Reset Command 45

Sync Command 46

13.4

13.4.1

NOP Frame 46

13.4.2

13.4.3

Command Delivery Timing 46

Concurrent Command Delivery Rules

46

13.5

13.5.1

13.6

13.7

13.8

12.1.4.9

12.2

Command Encoding 47

Northbound CRC Modes 47

Northbound Idle Frame 48

Northbound Alert Frame 48

Northbound Data Frames 48

14-bit Lane Northbound Data Frame 48

13-bit Lane Fail-over Northbound Data

Frame 48

12.2.1

12.2.2

12.2.3

12.2.3.1

12.2.3.2

13.8.1

13.8.2

Fail-over Mode Operation on Northbound

Lanes 55

12.2.3.3

12.2.3.4

13-bit Lane Northbound Data Frame 48

13-bit Lane Fail-Over Northbound Data

Frame 48

13.9

13.10

13.11

AMB Pass-through Functionality 55

Memory Initialization 56

Thermal Trip Sensor 56

12.2.3.5

12-bit Lane Northbound Data Frame

(Non-ECC Mode) 49

Northbound Register Data Frame 49

Northbound Status Frame 49

DRAM Memory Timing 49

Read Timing 49

14

15

16

SPD Codes 57

Package Outline 68

12.2.3.6

12.2.3.7

12.3

12.3.1

12.3.2

DDR2 Nomencature (Component &

Modules) 73

DDR2 Component 73

16.1

Write Timing 50

12.3.2.1

Write Data FIFO 51

Data Sheet

5

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

Preliminary

240-Pin Fully- Buffered DDR2 SDRAM Modules

DDR2 SDRAM

HYS72T64000HF–[3.7/3]–A

HYS72T1280[00/20]HF–[3.7/3]–A

HYS72T256020HF–[3.7/3]–A

1

Overview

This chapter describes the main characteristics of the 240-Pin Fully- Buffered DDR2 SDRAM Modules product

family.

1.1

Features

•

240-pin Fully Buffered ECC Dual-In-Line

DDR2 SDRAM Module for PC, Workstation and

Server main memory applications.

One rank 64Mb x 72, 128Mb x 72 and two ranks

128Mbx72, 256Mb x 72 memory array.

JEDEC Standard Double Data Rate 2

Synchronous DRAMs (DDR2 SDRAMs) with 1.8 V

(± 0.1 V) power supply.

Built with 512Mb DDR2 SDRAMs in 60-ball FBGA

Chipsize Packages.

Re-drive and re-sync of all address, command,

clock and data signals using AMB (Advanced

Memory Buffer).

High-Speed Differential Point-to-Point Link

Interface at 1.5 V (Jedec standard pending).

Host Interface and AMB component industry

standard compliant.

Supports SMBus protocol interface for access to

the AMB configuration registers.

•

Detects errors on the channel and reports them to

the host memory controller.

•

Automatic DDR2 DRAM Bus Calibration.

Automatic Channel Calibration.

•

Full Host Control of the DDR2 DRAMs.

Over-Temperature Detection and Alert.

Hot Add-on and Hot Remove Capability.

MBIST and IBIST Test Functions.

Transparent Mode for DRAM Test Support.

Low profile: 133.35mm x 30,35mm

•

240 Pin gold plated card connector with 1.00mm

contact centers (JEDEC standard pending).

Based on JEDEC standard reference card designs

(Jedec standard pending).

•

SPD (Serial Presence Detect) with 256 Byte serial

E²PROM.Performance:

RoHS Compliant Products¹⁾

Table 1

Performance

Speed Grade Indicator

-3.7

-3

Unit

DDR2 DRAM Speed Grade

DDR2-533C 4-4-4

DDR2-667D 4-4-4

FB-DIMM Speed Grade

PC2-4200F

PC2-5300F

FB-DIMM Peak Channel Throughput

FB-DIMM Link Transfer Rate

6.4

3.2

8.0

4.0

GByte/s

GT/s

1.2

Description

This document describes the electrical and mechanical Modules (DDR2 SDRAM FB-DIMMs). Fully Buffered

features of Infineon’s 240-pin, PC2-4200F, PC2- DIMMs use commodity DRAMs isolated from the

5300F, ECC type, Fully Buffered Double-Data-Rate memory channel behind a buffer on the DIMM. They

Two Synchronous DRAM Dual In-Line Memory are intended for use as main memory when installed in

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and

electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the

Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium,

polybrominated biphenyls and polybrominated biphenyl ethers.

Data Sheet

6

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Overview

systems such as servers and workstations. PC2-4200, The Advanced Memory Buffer also allows buffering of

PC2-5300 refers to the DIMM naming convention memory traffic to support large memory capacities. All

indicating the DDR2 SDRAMs running at 266, 333 MHz memory control for the DRAM resides in the host,

clock speed and offering 4200, 5300 MB/s peak including memory request initiation, timing, refresh,

bandwidth. FB-DIMM features a novel architecture scrubbing, sparing, configuration access, and power

including the Advanced Memory Buffer. This single management. The Advanced Memory Buffer interface

chip component, located in the center of each DIMM, is responsible for handling channel and memory

acts as a repeater and buffer for all signals and requests to and from the local DIMM and for forwarding

commands which are exchanged between the host requests to other DIMMs on the memory channel. Fully

controller and the DDR2 SDRAMs including data in- Buffered DIMM provides a high memory bandwidth,

and output. The AMB communicates with the host large capacity channel solution that has a narrow host

controller and / or the adjacent DIMMs on a system interface. The maximum memory capacity is 288 DDR2

board using an Industry Standard High-Speed SDRAM devices per channel or 8 DIMMs.

Differential Point-to-Point Link Interface at 1.5 V.

Table 2

Ordering Information (Pb-free components and assembly)

Type & Partnumber¹⁾

Compliance Code²⁾

Description

SDRAM

Technology

PC2-4200F (DDR2-533):

HYS72T64000HF-3.7-A

HYS72T128020HF-3.7-A

HYS72T128000HF-3.7-A

HYS72T256020HF-3.7-A

PC2-5300F (DDR2-667):

HYS72T64000HF-3-A

HYS72T128020HF-3-A

HYS72T128000HF-3-A

HYS72T256020HF-3-A

PC2-4200F-44410-A

PC2-4200F-44410-B

PC2-4200F-44410-C

PC2-4200F-44410-H

one rank 512 MB FB-DIMM

two ranks 1024 MB FB-DIMM

one rank 1024 MB FB-DIMM

two ranks 2048 MB FB-DIMM

512 Mbit (x8)

512 Mbit (x4)

PC2-5300F-44410-A

PC2-5300F-44410-B

PC2-5300F-44410-C

PC2-5300F-44410-H

one rank 512 MB FB-DIMM

two ranks 1024 MB FB-DIMM

one rank 1024 MB FB-DIMM

two ranks 2048 MB FB-DIMM

512 Mbit (x8)

512 Mbit (x4)

1) All product types end with a place code, designating the silicon die revision. Example: HYS 72T64000HF-3.7-A, indicating

Rev. A dice are used for DDR2 SDRAM components. To learn more on INFINEON DDR2 module and component

nomenclature see section 8 of this datasheet.

2) The Compliance Code is printed on the module label and describes the speed grade, e.g. “PC2-4200F-444-10-C”, where

4200F means Fully Buffered DIMM with 4.26 GB/sec Module Bandwidth and “444-10” means CAS latency = 4, t_rcdlatency

= 4 and t_rplatency = 4 using JEDEC SPD Revision 1.0 and assembled on Raw Card “C”.

Data Sheet

7

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Pin Configuration

2

Pin Configuration

The pin configuration of the DDR2 SDRAM DIMM is listed by function in Table 3 (240 pins). The abbreviations

used in columns Pin and Buffer Type are explained in Table 5 and Table 4 respectively. The pin numbering is

depicted in Figure 1.

Table 3

Pin#

Pin Configuration of FB-DIMM

Name

Type

Buffer

Type

Function

Clock Signals

228

229

SCK

I

HSDL_15 System Clock Input, positive line

HSDL_15 System Clock Input, negative line

Control Signals

17

RESET

I

LV-CMOS AMB reset signal

Northbound

22

25

28

31

34

37

51

54

57

60

63

66

48

40

23

26

29

32

35

38

52

55

58

61

64

67

49

41

PN0

PN1

PN2

PN3

PN4

PN5

PN6

PN7

PN8

PN9

PN10

PN11

PN12

PN13

PN0

PN1

PN2

PN3

PN4

PN5

PN6

PN7

PN8

PN9

PN10

PN11

PN12

PN13

O

HSDL_15 Primary Northbound Data, positive

lines

HSDL_15

HSDL_15 Primary Northbound Data, negative

lines

HSDL_15

Data Sheet

8

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Pin Configuration

Table 3

Pin#

Pin Configuration of FB-DIMM (cont’d)

Name

Type

Buffer

Type

HSDL_15 Secondary Northbound Data,

HSDL_15

Function

142

145

148

151

154

157

171

174

177

180

183

186

168

160

143

146

149

152

155

158

172

175

178

181

184

187

169

161

Southbound

70

SN0

SN1

SN2

SN3

SN4

SN5

SN6

SN7

SN8

SN9

SN10

SN11

SN12

SN13

SN0

SN1

SN2

SN3

SN4

SN5

SN6

SN7

SN8

SN9

SN10

SN11

SN12

SN13

I

positive lines

HSDL_15 Secondary Northbound Data,

positive lines

HSDL_15

HSDL_15 Secondary Northbound Data,

negative lines

HSDL_15

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PS8

PS9

I

HSDL_15 Primary Southbound Data, positive

lines

73

76

79

82

93

96

99

102

90

HSDL_15

Data Sheet

9

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Pin Configuration

Table 3

Pin#

Pin Configuration of FB-DIMM (cont’d)

Name

Type

Buffer

Type

HSDL_15 Primary Southbound Data, negative

Function

71

74

77

80

83

94

97

100

103

91

190

193

196

199

202

213

216

219

222

210

191

194

197

200

203

214

217

220

223

211

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PS8

PS9

SS0

SS1

SS2

SS3

SS4

SS5

SS6

SS7

SS8

SS9

SS0

SS1

SS2

SS3

SS4

SS5

SS6

SS7

SS8

SS9

I

lines

HSDL_15

I

O

HSDL_15 Secondary Southbound data,

positive lines

HSDL_15

HSDL_15 Secondary Southbound data,

positive lines

HSDL_15

HSDL_15 Secondary Southbound data,

negative lines

HSDL_15

EEPROM

120

119

239

240

SCL

SDA

SA0

SA1

SA2

I

CMOS

OD

CMOS

Serial Bus Clock

Serial Bus Data

Serial Address Select Bus 2:0

I/O

I

118

Power Supplies

238

9,10,12,13,129,130,132,133

V_DDSPD

V_CC

PWR

–

EEPROM Power Supply

AMB Core Power / Channel Interface

Power

Data Sheet

10

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Pin Configuration

Table 3

Pin#

Pin Configuration of FB-DIMM (cont’d)

Name

Type

Buffer

Type

Function

15,117,135,237

V_TT

PWR

–

Address/Command/Clock

Termination Power

1,2,3,5,6,7,108,109,111,112,113, V_DD

115,116,121,122,123,125,126,

127,231,232,233,235,236

PWR

–

Power Supply

4,8,11,14,18,21,24,27,30,33,36,

39,42,43,46,47,50,53,56,59,62,

65,68,69,72,75,78,81,84,85,88,

89,92,95,98,101,104,107,110,

114,124,128,131,134,138,141,

144,147,150,153,156,159,162,

163,166,167,170,173,176,179,

182,185,188,189,192,195,198,

201,204,205,208,209,212,215,

218,221,224,227,230,234

V_SS

GND

Ground Plane

Other Pins

19,20,44,45,86,87,105,106,139,

140,164,165,206,207,225,226

NC

–

Not connected

Pins not connected on Infineon FB-

DIMM’s

136

16

VID0

VID1

–

Voltage ID

Note: These Pins must be unconnected

for DDR2-based Fully Buffered

DIMMs VID[0] is V_DDvalue:

OPEN = 1.8 V, GND = 1.5 V;

VID[1] is V_CCvalue: OPEN = 1.5

V, GND = 1.2 V

137

Test

AI

–

VREF

Note: Pin must be unconnected for

normal operation

Table 4

Abbreviations for Buffer Type

Description

Abbreviation

HSDL_15

LV-CMOS

CMOS

High-Speed Differential Point-to-Point Link Interface at 1.5 V

Low Voltage CMOS

CMOS Levels

OD

Open Drain. The corresponding pin has 2 operational states, active low and

tristate, and allows multiple devices to share as a wire-OR.

Data Sheet

11

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Table 5

Pin Configuration

Abbreviations for Pin Type

Abbreviation

Description

I

O

Standard input-only pin. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

Ground

Not Usable

Not Connected

I/O

AI

PWR

GND

NU

NC

Data Sheet

12

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Pin Configuration

6

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0.ꢅ 0IN ꢁꢄꢈ

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0IN ꢂꢅꢉ 6₃₃

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0IN ꢂꢅꢊ 3.ꢊ

6₃₃0IN ꢁꢄꢉ

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0.ꢊ 0IN ꢁꢄꢊ

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0.ꢆ 0IN ꢁꢉꢁ

0IN ꢂꢊꢁ 3.ꢆ

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6₃₃0IN ꢁꢉꢇ

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03ꢇ ꢀ 0IN ꢁꢅꢅ

03ꢃ ꢀ 0IN ꢁꢅꢆ

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03ꢁ 0IN ꢁꢅꢁ

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0IN ꢂꢆꢃ ꢀ 33ꢂ

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0IN ꢂꢆꢅ ꢀ 33ꢇ

0IN ꢂꢆꢆ ꢀ 33ꢃ

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6₃₃0IN ꢁꢅꢊ

0IN ꢂꢆꢊ 6₃₃

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03ꢃ 0IN ꢁꢊꢁ

0IN ꢇꢁꢁ 33ꢃ

0IN ꢁꢊꢂ

0IN ꢇꢁꢂ

6₃₃

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0IN ꢁꢊꢄ

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ꢀ 6₃₃

0IN ꢇꢁꢃ ꢀ 33ꢈ

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0IN ꢇꢁꢇ 33ꢈ

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6₃₃0IN ꢁꢊꢈ

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0IN ꢁꢊꢆ

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ꢀ 6₃₃

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ꢀ 6₃₃

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0IN ꢇꢁꢉ .#

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0IN ꢇꢁꢊ 6₃₃

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6₃₃0IN ꢁꢊꢊ

6₃₃

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03ꢆ 0IN ꢁꢆꢁ

03ꢆ ꢀ 0IN ꢁꢆꢂ

03ꢄ ꢀ 0IN ꢁꢆꢃ

6₃₃ꢀ 0IN ꢁꢆꢄ

03ꢉ ꢀ 0IN ꢁꢆꢅ

0IN ꢇꢂꢂ ꢀ 33ꢆ

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6₃₃0IN ꢁꢆꢊ

0IN ꢇꢂꢊ 6₃₃

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0IN ꢇꢂꢆ

03ꢅ ꢀ

6₃₃ꢀ 0IN ꢂꢁꢂ

0IN ꢂꢁꢃ

ꢀ 33ꢅ

0IN ꢇꢇꢂ ꢀ 6₃₃

0IN ꢇꢇꢃ

ꢀ

03ꢅ 0IN ꢂꢁꢁ

0IN ꢇꢇꢁ 33ꢅ

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03ꢊ ꢀ

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0IN ꢂꢁꢅ

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0IN ꢇꢇꢈ 6₃₃

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0IN ꢇꢇꢊ 3#+

.# 0IN ꢂꢁꢉ

6₃₃

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ꢀ 6₃₃

ꢀ

6_$$0IN ꢂꢁꢊ

6_$$ꢀ 0IN ꢂꢁꢆ

6_$$ꢀ 0IN ꢂꢂꢂ

6_$$ꢀ 0IN ꢂꢂꢃ

6_$$ꢀ 0IN ꢂꢂꢄ

0IN ꢇꢇꢆ ꢀ 3#+

0IN ꢇꢃꢂ ꢀ 6_$$

0IN ꢇꢃꢃ ꢀ 6_$$

0IN ꢇꢃꢄ ꢀ 6_$$

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6₃₃0IN ꢂꢂꢁ

0IN ꢇꢃꢁ 6₃₃

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6_$$0IN ꢂꢂꢇ

0IN ꢇꢃꢇ 6_$$

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6₃₃0IN ꢂꢂꢈ

0IN ꢇꢃꢈ 6₃₃

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6_$$0IN ꢂꢂꢉ

0IN ꢇꢃꢉ 6_$$

0IN ꢂꢂꢅ

0IN ꢇꢃꢅ

6₄₄

ꢀ

6₄₄

ꢀ

3!ꢇ 0IN ꢂꢂꢊ

0IN ꢇꢃꢊ 6$$30$

0IN ꢇꢈꢁ 3!ꢂ

3$! ꢀ 0IN ꢂꢂꢆ

0IN ꢇꢃꢆ 3!ꢁ

-004ꢁꢂꢆꢁ

ꢀ

3#, 0IN ꢂꢇꢁ

Figure 1

Pin Configuration for FBDIMM (240 pin)

Data Sheet

13

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

FB-DIMM Input/Output Functional Description

3

FB-DIMM Input/Output Functional Description

Table 6

Symbol

FB-DIMM Input/Output Functional Description

Type Polarity Function

Channel Signals

SCK, SCK

Input

Differential System Clock Input

PN[13:0], PN[13:0] Output Differential Primary Northbound Data

PS[9:0], PS[9:0]

SN[13:0], SN[13:0] Input

Input

Differential Primary Southbound Data

Differential Secondary Northbound Data

SS[9:0], SS[9:0]

SMB Bus Signals

SA[2:0]

Output Differential Secondary Southbound Data

Input

I/O

—

SPD Address, also used to select the DIMM number in the AMB

SPD Data. A resistor must be connected from the SDA bus line to

VDDSPD on the system planar to act as a pull-up.

SDA

SCL

Input

—

SPD Clock

Miscellaneous Signals

RESET

VID[1:0]

TEST

Input

Analog + 0.9 V

Active Low AMB Reset Signal

Voltage ID. Both pins shall be NC in case of V_DD= 1.8 V, V_CC= 1.5 V

—

DRAM V_REFMargin Test. Do not connect on the system planar.

Power / Ground

V_DD

V_CC

Supply + 1.8 V

Supply + 1.5 V

Supply + 3.3 V

DDR2 DRAM Power

AMB Core Power

SPD Power

V_DDSPD

Data Sheet

14

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Block Diagrams

4

Block Diagrams

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6_$$ꢊ6_$$1ꢌ 3$2!-S $ꢀ ꢋ $ꢈꢍ!-"

6_2%&ꢌ 3$2!-S $ꢀ ꢋ $ꢈ

6₃₃ꢌ 3$2!-S $ꢀ ꢋ $ꢈ

#3

$13

#3

$13

$13ꢄ

$13ꢃꢇ

$13ꢁ

$13ꢃꢃ

$13

6₃₃

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$1ꢆꢈ

$1ꢆꢂ

$1ꢇꢀ

$1ꢇꢃ

$1ꢇꢁ

$1ꢇꢉ

$1ꢇꢆ

$1ꢇꢇ

$1ꢃꢄ

$1ꢃꢅ

$1ꢃꢈ

$1ꢃꢂ

$1ꢁꢀ

$1ꢁꢃ

$1ꢁꢁ

$1ꢁꢉ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

)ꢊ/ ꢉ

0.ꢀꢋ0.ꢃꢉ

03ꢀꢋ03ꢂ

3.ꢀꢋ3.ꢃꢉ

33ꢀꢋ33ꢂ

!-"

)ꢊ/ ꢆ

)ꢊ/ ꢇ

)ꢊ/ ꢄ

)ꢊ/ ꢅ

$1ꢀꢋ$1ꢄꢉ

#"ꢀꢋ#"ꢅ

$13ꢀꢋ$13ꢃꢅ

$13ꢀꢋ$13ꢈ

3ꢀ

#+%ꢀ

#3ꢌ 3$2!-S $ꢀꢋ$ꢈ

#+%ꢌ 3$2!-S $ꢀꢋ$ꢈ

#3

$13

#3

$13

$13ꢉ

$13ꢃꢁ

$13ꢅ

$13ꢃꢄ

$13

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

3#,

3$!

3!ꢀꢋ3!ꢁ

/$4

/$4ꢌ 3$2!-S $ꢀꢋ$ꢈ

"!ꢀꢋ"!Nꢌ 3$2!-S $ꢀꢋ$ꢈ

!ꢀꢋ!Nꢌ 3$2!-S $ꢀꢋ$ꢈ

2!3ꢌ 3$2!-S $ꢀꢋ$ꢈ

#!3ꢌ 3$2!-S $ꢀꢋ$ꢈ

7%ꢌ 3$2!-S $ꢀꢋ$ꢈ

#+ꢊ#+ꢌ 3$2!- $ꢀꢋ$ꢈ

"!ꢀꢋ"!ꢁ

!ꢀꢋ!N

2!3

$1ꢁꢆ

$1ꢁꢇ

$1ꢁꢄ

$1ꢁꢅ

$1ꢁꢈ

$1ꢁꢂ

$1ꢉꢀ

$1ꢉꢃ

$1ꢇꢄ

$1ꢇꢅ

$1ꢇꢈ

$1ꢇꢂ

$1ꢄꢀ

$1ꢄꢃ

$1ꢄꢁ

$1ꢄꢉ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

2%3%4

#!3

)ꢊ/ ꢉ

7%

)ꢊ/ ꢆ

3#+ꢊ3#+

#+ꢊ#+

)ꢊ/ ꢇ

)ꢊ/ ꢄ

)ꢊ/ ꢅ

-0"4ꢀꢁꢂꢀ

Figure 2

Block Diagram Raw Card A FB-DIMM ECC (x72, 1Rank, x8)

Notes

2. There are two physical copies of each address,

command, control, clock

3. All address, command, control, clock have

termination resitors to V_TT

1. DQ to I/O wiring may be changed within a byte

Data Sheet

15

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Block Diagrams

6₄₄

6_##

4ERMINATORS

!-"

6_$$ꢊ6_$$1

6_2%&

6_$$ꢊ6_$$1ꢌ 3$2!-S $ꢀ ꢋ $ꢂꢇꢍ!-"

6_2%&ꢌ 3$2!-S $ꢀ ꢋ $ꢂꢇ

6_$$ꢍ30$

6₃₃

6_$$ꢌ 30$ꢍ !-"

6₃₃ꢌ 3$2!-S $ꢀ ꢋ $ꢂꢇ

6₃₃

6₃₃ꢌ 3$2!-S $ꢀ ꢋ $ꢂꢇ

0.ꢀꢋ0.ꢂꢁ

03ꢀꢋ03ꢉ

$1ꢀꢋ$1ꢆꢁ

#"ꢀꢋ#"ꢇ

$13ꢀꢋ$13ꢂꢇ

$13ꢀꢋ$13ꢈ

3#,

3.ꢀꢋ3.ꢂꢁ

3ꢀ

3ꢂ

!-"

3.ꢀꢋ3.ꢂꢁ

33ꢀꢋ33ꢉ

3ꢀ

$ꢀ

$ꢂ

$ꢃ

$ꢁ

$ꢄ

$ꢉ

#3

#3ꢌ 3$2!-S $ꢀꢋ$ꢈ

$13ꢀ

$13ꢉ

$13

#+%ꢀ

3ꢂ

#+%ꢌ 3$2!-S $ꢀꢋ$ꢈ

#3ꢌ 3$2!-S $ꢉꢋ$ꢂꢇ

#+%ꢌ 3$2!-S $ꢉꢋ$ꢂꢇ

/$4ꢌ 3$2!-S $ꢀꢋ$ꢂꢇ

"!ꢀꢋ"!Nꢌ 3$2!-S $ꢀꢋ$ꢂꢇ

!ꢀꢋ!Nꢌ 3$2!-S $ꢀꢋ$ꢂꢇ

2!3ꢌ 3$2!-S $ꢀꢋ$ꢂꢇ

#!3ꢌ 3$2!-S $ꢀꢋ$ꢂꢇ

7%ꢌ 3$2!-S $ꢀꢋ$ꢂꢇ

#+ꢊ#+ꢌ 3$2!- $ꢀꢋ$ꢂꢇ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

#+%ꢂ

/$4

$1ꢀ

$1ꢂ

$1ꢃ

$1ꢁ

$1ꢄ

$1ꢅ

$1ꢆ

$1ꢇ

3$!

3!ꢀꢋ3!ꢃ

"!ꢀꢋ"!ꢃ

!ꢀꢋ!N

2!3

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

2%3%4

#!3

)ꢊ/ ꢄ

7%

)ꢊ/ ꢅ

3#+ꢊ3#+

#+ꢊ#+

)ꢊ/ ꢆ

)ꢊ/ ꢇ

$ꢂꢀ

#3

$ꢅ

$ꢆ

$ꢇ

$ꢈ

$ꢂꢄ

$ꢂꢅ

$ꢂꢆ

$ꢂꢇ

#3

$13

#3

$13ꢂ

$13ꢂꢀ

$13

$13ꢅ

$13ꢂꢄ

$13

%ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

3#,

3$!

!ꢀ

3#,

.5ꢊ2$13

3$!

$1ꢈ

$1ꢉ

)ꢊ/ ꢀ

3!ꢀ

$1ꢄꢀ

$1ꢄꢂ

$1ꢄꢃ

$1ꢄꢁ

$1ꢄꢄ

$1ꢄꢅ

$1ꢄꢆ

$1ꢄꢇ

)ꢊ/ ꢂ

3!ꢂ

)ꢊ/ ꢂ

!ꢂ

$1ꢂꢀ

$1ꢂꢂ

$1ꢂꢃ

$1ꢂꢁ

$1ꢂꢄ

$1ꢂꢅ

)ꢊ/ ꢃ

3!ꢃ

)ꢊ/ ꢃ

!ꢃ

70

)ꢊ/ ꢁ

6₃₃

)ꢊ/ ꢄ

)ꢊ/ ꢅ

)ꢊ/ ꢆ

)ꢊ/ ꢇ

)ꢊ/ ꢄ

)ꢊ/ ꢅ

)ꢊ/ ꢆ

)ꢊ/ ꢇ

$ꢂꢂ

#3

$13

#3

$13

#3

$13

$13ꢃ

$13ꢂꢂ

$13

$13ꢆ

$13ꢂꢅ

$13

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$1ꢂꢆ

$1ꢂꢇ

$1ꢂꢈ

$1ꢂꢉ

$1ꢃꢀ

$1ꢃꢂ

$1ꢃꢃ

$1ꢃꢁ

$1ꢄꢈ

$1ꢄꢉ

$1ꢅꢀ

$1ꢅꢂ

$1ꢅꢃ

$1ꢅꢁ

$1ꢅꢄ

$1ꢅꢅ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

)ꢊ/ ꢄ

)ꢊ/ ꢅ

)ꢊ/ ꢆ

)ꢊ/ ꢇ

$ꢂꢃ

#3

$13

#3

$13

#3

$13

$13ꢁ

$13ꢂꢃ

$13

$13ꢇ

$13ꢂꢆ

$13

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$1ꢃꢄ

$1ꢃꢅ

$1ꢃꢆ

$1ꢃꢇ

$1ꢃꢈ

$1ꢃꢉ

$1ꢁꢀ

$1ꢁꢂ

$1ꢅꢆ

$1ꢅꢇ

$1ꢅꢈ

$1ꢅꢉ

$1ꢆꢀ

$1ꢆꢂ

$1ꢆꢃ

$1ꢆꢁ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

)ꢊ/ ꢄ

)ꢊ/ ꢅ

)ꢊ/ ꢆ

)ꢊ/ ꢇ

$ꢂꢁ

#3

$13

#3

$13

#3

$13

$13ꢄ

$13ꢂꢁ

$13

$13ꢈ

$13ꢂꢇ

$13

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$1ꢁꢃ

$1ꢁꢁ

$1ꢁꢄ

$1ꢁꢅ

$1ꢁꢆ

$1ꢁꢇ

$1ꢁꢈ

$1ꢁꢉ

#"ꢀ

#"ꢂ

#"ꢃ

#"ꢁ

#"ꢄ

#"ꢅ

#"ꢆ

#"ꢇ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

)ꢊ/ ꢄ

)ꢊ/ ꢅ

)ꢊ/ ꢆ

)ꢊ/ ꢇ

-0"4ꢀꢁꢀꢀ

Figure 3

Block Diagram Raw Card B FB-DIMM ECC (x72, 2Ranks, x8)

Notes

2. There are two physical copies of each address,

command, control and clock

3. All address, command, control, clock have

termination resitors to V_TT

1. DQ to I/O wiring may be changed within a byte

Data Sheet

16

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Block Diagrams

3ꢀ

$ꢂꢄ

$ꢀ

$ꢂ

$ꢃ

$ꢁ

$ꢄ

$ꢅ

$ꢆ

$ꢇ

#3

$13

#3

$13ꢂꢄ

$1ꢄꢄ

$1ꢄꢅ

$1ꢄꢆ

$1ꢄꢇ

6₃₃

$13ꢀ

$1ꢀ

$1ꢂ

$1ꢃ

$1ꢁ

6₃₃

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$13ꢇ

$1ꢅꢆ

$1ꢅꢇ

$1ꢅꢈ

$1ꢅꢉ

6₃₃

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$ꢈ

$ꢂꢅ

#3

$13ꢂ

$1ꢈ

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$13ꢂꢅ

$1ꢅꢃ

$1ꢅꢁ

$1ꢅꢄ

$1ꢅꢅ

6₃₃

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$13ꢈ

#"ꢀ

#"ꢂ

#"ꢃ

#"ꢁ

6₃₃

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$1ꢉ

$1ꢂꢀ

$1ꢂꢂ

6₃₃

$ꢉ

$ꢂꢆ

#3

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$13ꢉ

$1ꢄ

$1ꢅ

$1ꢆ

$1ꢇ

6₃₃

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$13ꢂꢆ

$1ꢆꢀ

$1ꢆꢂ

$1ꢆꢃ

$1ꢆꢁ

6₃₃

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$13ꢃ

$1ꢂꢆ

$1ꢂꢇ

$1ꢂꢈ

$1ꢂꢉ

6₃₃

$ꢂꢀ

$ꢂꢂ

$ꢂꢃ

$ꢂꢁ

$ꢂꢇ

%ꢀ

#3

3#,

3$!

!ꢀ

3#,

3$!

3!ꢀ

3!ꢂ

3!ꢃ

6₃₃

$13ꢁ

$1ꢃꢄ

$1ꢃꢅ

$1ꢃꢆ

$1ꢃꢇ

6₃₃

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$13ꢂꢀ

$1ꢂꢃ

$1ꢂꢁ

$1ꢂꢄ

$1ꢂꢅ

6₃₃

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$13ꢂꢇ

#"ꢄ

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

!ꢂ

#"ꢅ

!ꢃ

70

#"ꢆ

#"ꢇ

6₃₃

0.ꢀꢍ0.ꢂꢁ

03ꢀꢍ03ꢉ

3.ꢀꢍ3.ꢂꢁ

33ꢀꢍ33ꢉ

!-"

$13ꢄ

$1ꢁꢃ

$1ꢁꢁ

$1ꢁꢄ

$1ꢁꢅ

6₃₃

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$13ꢂꢂ

$1ꢃꢀ

$1ꢃꢂ

$1ꢃꢃ

$1ꢃꢁ

6₃₃

$1ꢀꢍ$1ꢆꢁ

#"ꢀꢍ#"ꢇ

$13ꢀꢍ$13ꢂꢇ

3ꢀ

#+%ꢀ

#3ꢋ 3$2!-S $ꢀꢍ$ꢂꢇ

#+%ꢋ 3$2!-S $ꢀꢍ$ꢂꢇ

3#,

3$!

3!ꢀꢍ3!ꢃ

/$4

/$4ꢋ 3$2!-S $ꢀꢍ$ꢂꢇ

"!ꢀꢍ"!Nꢋ 3$2!-S $ꢀꢍ$ꢂꢇ

!ꢀꢍ!Nꢋ 3$2!-S $ꢀꢍ$ꢂꢇ

2!3ꢋ 3$2!-S $ꢀꢍ$ꢂꢇ

#!3ꢋ 3$2!-S $ꢀꢍ$ꢂꢇ

7%ꢋ 3$2!-S $ꢀꢍ$ꢂꢇ

#+ꢊ#+ꢋ 3$2!- $ꢀꢍ$ꢂꢇ

$13ꢅ

$1ꢄꢀ

$1ꢄꢂ

$1ꢄꢃ

$1ꢄꢁ

6₃₃

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$13ꢂꢃ

$1ꢃꢈ

$1ꢃꢉ

$1ꢁꢀ

$1ꢁꢂ

6₃₃

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

"!ꢀꢍ"!ꢃ

!ꢀꢍ!N

2!3

2%3%4

#!3

7%

3#+ꢊ3#+

#+ꢊ#+

6₄₄

6_##

4ERMINATORS

!-"

$13ꢆ

$1ꢄꢈ

$1ꢄꢉ

$1ꢅꢀ

$1ꢅꢂ

6₃₃

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

$13ꢂꢁ

$1ꢁꢆ

$1ꢁꢇ

$1ꢁꢈ

$1ꢁꢉ

6₃₃

$13

)ꢊ/ ꢀ

)ꢊ/ ꢂ

)ꢊ/ ꢃ

)ꢊ/ ꢁ

$-

6_$$ꢌ30$

6_$$ꢊ6_$$1

6_2%&

6_$$ꢋ 30$ꢌ !-"

6_$$ꢊ6_$$1ꢋ 3$2!-S $ꢀ ꢍ $ꢂꢇꢌ!-"

6_2%&ꢋ 3$2!-S $ꢀ ꢍ $ꢂꢇ

6₃₃

6₃₃ꢋ 3$2!-S $ꢀ ꢍ $ꢂꢇ

-0"4ꢀꢁꢂꢀ

Figure 4

Block Diagram Raw Card C FB-DIMM ECC (×72, 1Rank, ×4)

Notes

2. There are two physical copies of each address,

command, control and clock

3. All address, command, control, clock have

termination resitors to V_TT

1. DQ to I/O wiring may be changed within a nibble

Data Sheet

17

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Block Diagrams

%ꢀ

0.ꢀꢋ0.ꢃꢁ

03ꢀꢋ03ꢆ

6₄₄

3.ꢀꢋ3.ꢃꢁ

33ꢀꢋ33ꢆ

03ꢀꢋ03ꢆ

33ꢀꢋ33ꢆ

!-"

3#,

3$!

!ꢀ

3#,

3$!

3!ꢀ

3!ꢃ

3!ꢂ

6₃₃

$1ꢀꢋ$1ꢇꢁ

#"ꢀꢋ#"ꢈ

$13ꢀꢋ$13ꢃꢈ

3#,

3ꢀ

#3ꢌ 3$2!-S $ꢀꢋ$ꢃꢈ

#+%ꢌ 3$2!-S $ꢀꢋ$ꢃꢈ

#3ꢌ 3$2!-S $ꢃꢄꢋ$ꢁꢊ

#+%ꢌ 3$2!-S $ꢃꢄꢋ$ꢁꢊ

/$4ꢌ 3$2!-S $ꢀꢋ$ꢁꢊ

"!ꢀꢋ"!Nꢌ 3$2!-S $ꢀꢋ$ꢁꢊ

!ꢀꢋ!Nꢌ 3$2!-S $ꢀꢋ$ꢁꢊ

2!3ꢌ 3$2!-S $ꢀꢋ$ꢁꢊ

#!3ꢌ 3$2!-S $ꢀꢋ$ꢁꢊ

7%ꢌ 3$2!-S $ꢀꢋ$ꢁꢊ

#+ꢅ#+ꢌ 3$2!- $ꢀꢋ$ꢁꢊ

#+%ꢀ

3ꢃ

4ERMINATORS

!ꢃ

#+%ꢃ

/$4

6_##

!ꢂ

70

!-"

6_$$ꢍ30$

6_$$ꢅ6_$$1

6_2%&

3$!

3!ꢀꢋ3!ꢂ

"!ꢀꢋ"!ꢂ

!ꢀꢋ!N

2!3

6_$$ꢌ 30$ꢍ !-"

6_$$ꢅ6_$$1ꢌ 3$2!-S $ꢀ ꢋ $ꢁꢊꢍ!-"

6_2%&ꢌ 3$2!-S $ꢀ ꢋ $ꢁꢊ

2%3%4

#!3

7%

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Figure 5

Block Diagram Raw Card H FB-DIMM ECC (×72, 2Ranks, ×4)

Notes

3. There are four physical copies of each clock

4. All address, command, control, clock have

termination resitors to V_TT

1. DQ to I/O wiring may be changed within a nibble

2. There are two physical copies of each address,

command and control

Data Sheet

18

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Basic Functionality

5

Basic Functionality

5.1

Advanced Memory Buffer Overview

The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol

Specification (Jedec standard pending).

5.2

Advanced Memory Buffer Functionality

5.2.1

Advanced Memory Buffer

The Advanced Memory Buffer will perform the following

FB-DIMM channel functions:

•

Detects errors on the channel and reports them to

the host memory controller.

Support the FB-DIMM configuration register set as

defined in the register chapters.

•

Supports channel initialization procedures as

defined in the initialization chapter of the FB-DIMM

Architecture and Protocol Specification to align the

clocks and the frame boundaries, verify channel

connectivity, and identify AMB DIMM position.

Supports the forwarding of southbound and

northbound frames, servicing requests directed to a

specific AMB or DIMM, as defined in the protocol

chapter, and merging the return data into the

northbound frames.

Acts as DRAM memory buffer for all read, write, and

configuration accesses addressed to the DIMM.

Provides a read buffer FIFO and a write buffer

FIFO.

•

Supports an SMBus protocol interface for access to

the AMB configuration registers.

Provides logic to support MEMBIST and IBIST

Design for Test functions.

Provides a register interface for the thermal sensor

and status indicator.

•

If the AMB resides on the last DIMM in the channel,

the AMB initializes northbound frames.

Functions as a repeater to extend the maximum

length of FB-DIMM Links.

5.2.2

Transparent Mode for DRAM Test Support

In this mode, the Advanced Memory Buffer will provide

lower speed tester access to DRAM pins through the

FB-DIMM I/O pins. This allows the tester to send an

arbitrary test pattern to the DRAMs. Transparent mode

only supports a maximum DRAM frequency equivalent

to DDR2 400. Transparent mode functionality:

•

Reconfigures FB-DIMM inputs from differential high

speed link receivers to two single ended lower

speed receivers (~200 MHz)

These inputs directly control DDR2

Command/Address and input data that is replicated

to all DRAMs

Uses low speed direct drive FB-DIMM outputs to

bypass high speed Parallel/Serial circuitry and

provide test results back to tester

5.2.3

DDR2 SDRAM

•

Supports DDR2 at speeds of 533, 667 MT/s

Supports 512Mb devices in x4 and x8

configurations

•

72-bit DDR2 SDRAM memory array

Data Sheet

19

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Basic Functionality

5.3

Advanced Memory Buffer Block Diagram

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Figure 6

Block Diagram Advanced Memory Buffer FBDIMM ECC

Note:Figure is a conceptual Block Diagram of the Advanced Memory Bufferis data flow and clock domains.

Data Sheet

20

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Basic Functionality

5.4

Interfaces

Figure 7 illustrates the Advanced Memory Buffer and host memory controller or an adjacent FB-DIMM. The

all of its interfaces. They consist of two FB-DIMM links, DDR2 channel supports direct connection to the DDR2

one DDR2 channel and an SMBus interface. Each FB- SDRAMs on a Fully Buffered DIMM.

DIMM link connects the Advanced Memory Buffer to a

-EMORY )NTERFACE

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Figure 7

Block Diagram Advanced Memory Buffer Interface

Interface Topology

The FB-DIMM channel uses a daisy-chain topology to drives the data to the next DIMM until the last DIMM

provide expansion from a single DIMM per channel to receives the data. The last DIMM in the chain initiates

up to 8 DIMMs per channel. The host sends data on the the transmission of data in the direction of the host

southbound link to the first DIMM where it is received (a.k.a. northbound). On the northbound data path each

and redriven to the second DIMM. On the southbound DIMM receives the data and re-drives the data to the

data path each DIMM receives the data and again re- next DIMM until the host is reached.

(OST

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.OURTHBOUND

!-"

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-0"4ꢀꢁꢂꢀ

Figure 8

Block Diagram FBDIMM Channel Soutbound and Northbound Paths

Data Sheet

21

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Basic Functionality

5.5

High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces

The Advanced Memory Buffer supports one FB-DIMM multiplexes in any read return data or status

Channel consisting of two bidirectional link interfaces information that is generated internally. Data and

using highspeed differential point-to-point electrical commands sent to the DRAMs travel southbound on 10

signaling. The southbound input link is 10 lanes wide primary differential signal line pairs. Data received from

and carries commands and write data from the host the DRAMs and status information travel northbound

memory controller or the adjacent DIMM in the host on 14 primary differential pairs. Data and commands

direction. The southbound output link forwards this sent to the adjacent DIMM upstream are repeated and

same data to the next FB-DIMM. The northbound input travel further southbound on 10 secondary differential

link is 14 lanes wide and carries read return data or pairs. Data and status information received from the

status information from the next FB-DIMM in the chain adjacent DIMM upstream travel further northbound on

back towards the host. The northbound output link 14 secondary differential pairs.

forwards this information back towards the host and

5.5.1

DDR2 Channel

The DDR2 channel on the Advanced Memory Buffer delays between read data/check-bit strobe lanes on a

supports direct connection to DDR2 SDRAMs. The given channel can differ. Each strobe can be calibrated

DDR2 channel supports two ranks of eight banks with by hardware state machines using write/read trial and

16 row/column request, 64 data, and eight check-bit error. Hardware aligns the read data and check-bits to

signals. There are two copies of address and command a single core clock. The Advanced Memory Buffer

signals to support DIMM routing and electrical provides four copies of the command clock phase

requirements. Four transfer bursts are driven on the references (CLK[3:0]) and write data/check-bit strobes

data and check-bit lines at 800 MHz. Propagation (DQSs) for each DRAM nibble.

5.5.2

SMBus Slave Interface

The Advanced Memory Buffer supports an SMBus Memory Buffer may be a requirement to boot and to set

interface to allow system access to configuration link strength, frequency and other parameters needed

registers independent of the FB-DIMM link. The to insure robust configurations. It is also required for

Advanced Memory Buffer will never be a master on the diagnostic support when the link is down. The SMBus

SMBus, only a slave. Serial SMBus data transfer is address straps located on the DIMM connector are

supported at 100 kHz. SMBus access to the Advanced used by the unique ID.

5.5.3

Channel Latency

FB-DIMM channel latency is measured from the time a based on the point-to-point interconnection of buffer

read request is driven on the FB-DIMM channel pins to components between DIMMs, memory requests are

the time when the first 16 bytes (2nd chunk) of read required to travel through N-1 buffers before reaching

completion data is sampled by the memory controller. the Nth buffer. The result is that a 4 DIMM channel

When not using the Variable Read Latency capability, configuration will have greater idle read latency

the latency for a specific DIMM on a channel is always compared to a 1 DIMM channel configuration. The

equal to the latency for any other DIMM on that Variable Read Latency capability can be used to

channel. However, the latency for each DIMM in a reduce latency for DIMMs closer to the host. The idle

specific configuration with some number of DIMMs latencies listed in this section are representative of

installed may not be equal to the latency for each FB- what might be achieved in typical AMB designs. Actual

DIMM in a configuration with some different number of implementations with latencies less than the values

DIMMs installed. As more DIMMs are added to the listed will have higher application performance and vice

channel, additional latency is required to read from versa.

each DIMM on the channel. Because the channel is

Data Sheet

22

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Basic Functionality

5.5.4

Peak Theoretical Channel Throughput

An FB-DIMM channel transfers read completion data command clock. A DRAM burst of 8 transfers from a

on the Northbound data connection. 144 bits of data single channel, or a burst of 4 from two lock-step

are transferred for every Northbound data frame. This channels provides a total of 72 bytes of data (64 bytes

matches the 18-byte data transfer of an ECC DDR plus 8 bytes ECC). When the frame rate matches the

DRAM in a single DRAM command clock. A DRAM DRAM command clock, the Southbound command and

burst of 8 from a single channel or a DRAM burst of four data connection will exhibit one half the peak

from two lockstepped channels provides a total of 72 theoretical throughput of a single DRAM channel. For

bytes of data (64 bytes plus 8 bytes ECC). The FB- example, when using DDR2 533 DRAMs, the peak

DIMM frame rate matches the DRAM command clock theoretical bandwidth of the Southbound command and

because of the fixed 6:1 ratio of the FB-DIMM channel data connection is 2.133 GB/sec. The total peak

clock to the DRAM command clock. Therefore, the theoretical throughput for a single FB-DIMM channel is

Northbound data connection will exhibit the same peak defined as the sum of the peak theoretical throughput

theoretical throughput as a single DRAM channel. For of the Northbound data connection and the

example, when using DDR2 533 DRAMs, the peak Southbound command and data connection. When the

theoretical bandwidth of the Northbound data frame rate matches the DRAM command clock, this is

connection is 4.267 GB/sec. Write data is transferred equal to 1.5 times the peak theoretical throughput of a

on the Southbound command and data connection, via single DRAM channel. For example, when using DDR2

Command+Wdata frames. 72 bits of data are 533 DRAMs, the peak theoretical throughput of a single

transferred for every Command+Wdata frame. Two DDR2-533 channel would be 4.267 GB/sec, while the

Command+Wdata frames match the 18-byte data peak theoretical throughput of the entire FB-DIMM

transfer of an ECC DDR DRAM in a single DRAM PC4200F channel would be 6.4GB/sec.

5.6

Hot-add

The FB-DIMM channel does not provide a mechanism controller to initialize the newly added DIMM(s) and

to automatically detect and report the addition of a new perform a Hot-Add Reset to bring them into the channel

DIMM south of the currently active last DIMM. It is timing domain. It should be noted that the power to the

assumed the system will be notified through some DIMM socket must be removed before a “hot-add”

means of the addition of one or more new DIMMs so DIMM is inserted or removed. Applying or removing the

that specific commands can be sent to the host power to a DIMM socket is a system platform function.

5.7

Hot-remove

In order to accomplish removal of DIMMs the host must appropriate outputs are disabled the system can

perform a Fast Reset sequence targeted at the last coordinate the procedure to remove power in

DIMM that will be retained on the channel. The Fast preparation for physical removal of the DIMM if needed.

Reset re-establish the appropriate last DIMM so that It should be noted that the power to the DIMM socket

the Southbound Tx outputs of the last active DIMM and must be removed before a “hot-add” DIMM is inserted

the Southbound and Northbound outputs of the DIMMs or removed. Applying or removing the power to a DIMM

beyond the last active DIMM are disabled. Once the socket is a system platform function.

5.8

Hot-replace

Hot replace of DIMM is accomplished through combining the Hot-Remove and Hot-Add process.

Data Sheet

23

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Electrical Characteristics

6

Electrical Characteristics

6.1

Operating Conditions

Table 7

Absolute Maximum Ratings

Symbol Parameter

Values

Unit Note

Min

Max

1)

V_IN,

V_OUT

Voltage on any pin relative to –0.3

V_SS

Voltage on V_CCpin relative to –0,3

V_SS

Voltage on V_DDpin relative to –0.5

V_SS

Voltage on V_TTpin relative to –0.5

V_SS

1.75

2.3

V

1)

V_CC

V_DD

V_TT

V

2.3

V

T_STG

Storage Temperature

–55

+100

°C

1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

Table 8

Operating Temperature Range

Symbol Parameter

Values

Unit Note

Min

0

Max

+95

1)2)3)4)

T_CASE

DRAM Component Case

°C

Temperature Range

1)

AMB Component Case

Temperature Range

0

+110

°C

1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2) Within the DRAM Component Case Temperature range all DRAM specification will be supported.

3) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below

85C case temperature before initiating self-refresh operation.

4) Above 85C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.

Table 9

Supply Voltage Levels and DC Operating Conditions

Parameter

Symbol

Limit Values

Unit

Notes

min.

1.46

1.7

nom.

1.5

1.8

max.

1.45

1.9

AMB Supply Voltage

DRAM Supply Voltage

V_CC

V_DD

V

Data Sheet

24

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Electrical Characteristics

Table 9

Supply Voltage Levels and DC Operating Conditions

Parameter

Symbol

Limit Values

Unit

Notes

min.

0.48 × VDD

nom.

0.50 × VDD

max.

0.52 × VDD

3.6

VDDSPD

0.8

—

+0.5

+90

+5

Termination Voltage

V_TT

V

EEPROM Supply Voltage

DC Input Logic High(SPD)

DC Input Logic Low(SPD)

V_DDSPD

V_IH(DC)

V_IL(DC)

3.0

2.1

—

1.0

—

3.3

—

V

µΑ

1)

2)

1)

2)

3)

DC Input Logic High(RESET) V_IH(DC)

DC Input Logic Low(RESET)

Leakage Current (RESET)

Leakage Current (Link)

V_IL(DC)

I_L

–90

–5

µΑ

1) applies for SMB and SPD Bus Signals

2) applies for AMB CMOS Signal RESET

3) for all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications

Table 10

Parameter

Timing Parameters

Symbol

Min.

Typ.

Max.

4

Units Notes

EI Assertion Pass-Thru Timing t_{EI Propagate}t

clks

—

EI Deassertion Pass-Thru

Timing

EI Assertion Duration

FBD Cmd to DDR Clk out that

latches Cmd

t_EID

Bitlock

clks

2

1)2)

3)

t_EI

100

clks

ns

8.1

FBD Cmd to DDR Write

DDR Read to FBD (last DIMM)

Resample Pass-Thru time

ResynchPass-Thru time

Bit Lock Interval

TBD

5.0

1.075

2.075

ns

frames

4)

1)

t_BitLock

t_FrameLock

119

154

Frame Lock Interval

1) Defined in FB-DIMM Architecture and Protocol Spec

2) Clocks defined as core clocks = 2x SCK input

3) @ DDR2-667 - measured from beginning of frame at southbound input to DDR clock output that latches the first command

of a frame to the DRAMs

4) @ DDR2-667 - measured from latest DQS input to AMB to start of matching data frame at northbound FB-DIMM outputs

Data Sheet

25

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Electrical Characteristics

Table 11

Environmental Parameters

Parameter

Operating Temperature

Symbol

T_OPR

H_OPR

T_STG

H_STG

P_BAR

Rating

Units

Notes

1)

See Note

10 to 90

-50 to +100

5 to 95

3050

14240

2)

Operating Humidity (relative)

Storage Temperature

Storage Humidity (without condensation)

Barometric pressure (operating)

Barometric pressure (storage)

%

°C

%

m

1) The designer must meet the case temperature specifications for individual module components.

2) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and the device

funcional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

Data Sheet

26

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Current Specification and Conditions

7

Current Specification and Conditions

Table 12

I_DDMeasurement Conditions

Parameter

Idle Current, single or last DIMM

L0 state, idle (0 BW)

Symbol

I_{CC_Idle_0}

I_{DD_Idle_0}

Primary channel enabled, Secondary channel disabled

CKE high. Command and address lines stable.

DRAM clock active

Idle Current, first DIMM

L0 state, idle (0 BW)

I_{CC_Idle_1}

I_{DD_Idle_1}

Primary and Secondary channels enabled.

CKE high. Command and address lines stable.

DRAM clock active

Idle Current, DRAM power down

_.L0 state, idle (0 BW)

I_{CC_Idle_2}

I_{DD_Idle_2}

Primary and Secondary channels enabled.

CKE high. Command and address lines floated.

DRAM clock active, ODT and CKE driven low.

DRAM is in Precharge Power Down Mode

Active Power

I_{CC_Active_1}

I_{DD_Active_1}

L0 state

50% DRAM BW, 67% read, 33% write.

Primary and Secondary channels enabled.

DRAM clock active, CKE high.

Active Power, data pass through

L0 state

I_{CC_Active_2}

I_{DD_Active_2}

50% DRAM BW to downstream DIMM, 67% read, 33% write.

Primary and Secondary channels enabled.

CKE high. Command and address lines stable.

DRAM clock active.

Channel Standby

I_{CC_LOs}

Average power over 42 frames where the channel enters and exits L0s I_{DD_LOs}

DRAMs Idle (0 BW).

CKE low. Command and address lines floated.

Dram clocks active, ODE and CKE driven low.

DRAM is in Precharge Power Down Mode

Training

I_{CC_Training}

I_{DD_Training}

Primary and Secondary channels enabled.

100% toggle on all channels lanes.

DRAMs idle (0 BW).

CKE high. Command and address lines stable.

DRAM clock active.

Notes

1. Primary channel Drive strength at 100 % with De-emphasis at -6.5 dB

2. Secondary channel drive strength at 60 % with De-emphasis at -3 dB when enabled.

Data Sheet

27

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

ICC/IDD Conditions

3. Address and Data fields provide a 50 % toggle rate on DRAM data and link lanes.

4. Burst Length = 4.

5. 10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM).

6. Modeled with 27 Ω termination for command, address, and clocks, and 47 Ω termination for control.

7. Termination is referenced to V_TT= V_DD/ 2.

8

ICC/IDD Conditions

In the following tabel you can finde the Measurement Conditions and Power Supply Currents

Table 13 I_CC/I_DDSpecification for HYS72T[64/128/256]xxxHF-3-A

Product Type

Unit Note

Speed Grade

PC2-5300F PC2-5300F PC2-5300F PC2-5300F PC2-5300F

4-4-4

Max.

1.7

0.4

3.3

2.5

0.4

4.5

2.3

0.05

3.5

3.3

0.9

6.6

2.6

0.4

4.6

1.1

0.05

1.7

4-4-4

Max.

1.7

0.8

4

2.5

0.8

5.2

2.3

0.09

3.6

3.3

1.7

8

2.6

0.8

5.3

1.1

0.09

1.8

3.9

0.8

7.3

4-4-4

Max.

1.7

0.8

4

4-4-4

Max.

1.7

1.5

5.3

2.5

1.5

6.5

2.3

0.18

3.8

3.3

2.6

9.6

2.6

1.5

6.6

1.1

0.18

2

4-4-4

Max.

1.7

1.5

5.3

2.5

1.5

6.5

2.3

0.18

3.8

3.3

2.6

9.6

2.6

1.5

6.6

1.1

0.18

2

Symbol

I_{CC_Idle_0}

I_{DD_Idle_0}

P_{Idle_0}

I_{CC_Idle_1}

I_{DD_Idle_1}

P_{Idle_1}

I_{CC_Idle_2}

I_{DD_Idle_2}

P_{Idle_2}

I_{CC_Active_1}

I_{DD_Active_1}

P_{Active_1}

I_{CC_Active_2}

I_{DD_Active_2}

P_{Active_2}

I_{CC_LOs}

A

W

A

W

A

W

A

W

A

W

A

W

A

V_CC= 1.5V

V_CC= 1.8V

Total power

V_CC= 1.5V

V_CC= 1.8V

Total power

V_CC= 1.5V

V_CC= 1.8V

Total power

2.5

0.8

5.2

2.3

0.09

3.6

3.3

1.3

7.3

2.6

0.8

5.3

1.1

0.09

1.8

3.9

0.8

7.3

V_CC= 1.5V

1)

V = 1.8V

CC

Total power

V_CC= 1.5V

V_CC= 1.8V

Total power

V_CC= 1.5V

V_CC= 1.8V

Total power

V_CC= 1.5V

V_CC= 1.8V

Total power

I_{DD_Los}

P_LOs

I_{CC_Training}

I_{DD_Training}

P_{_Training}

3.9

0.4

6.6

3.9

1.5

8.6

3.9

1.5

8.6

W

1) For 1 Rank modules: n × 0.5 × (2/3 × I_DD4R+ 1/3 × I_DD4W+ I_DD3N) For 2 Rank modules: n × 0.5 × (2/3 × I_DD4R+ 1/3

× I_DD4W+ I_DD3N)+ n × I_DD3Nwhere n = number of components/rank

Data Sheet

28

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

ICC/IDD Conditions

Table 14

I_CC/I_DDSpecification for HYS72T[64/129/256]xxxHF-3.7-A

Product Type

Unit Note

Speed Grade PC2-4200F

PC2-4200F

Symbol

Max.

I_{CC_Idle_0}

1.6

A

V_CC=

1.5V

I_{DD_Idle_0}

P_{Idle_0}

0.3

2.9

2.3

0.3

4

0.6

3.5

2.3

0.6

4.5

2.2

0.09

3.5

3.1

1.2

6.8

2.5

0.6

4.8

1

0.6

3.5

2.3

0.6

4.5

2.2

0.09

3.5

3.1

1

1.1

4.4

2.3

1.1

5.4

2.2

0.17

3.6

3.1

2

1.1

4.4

2.3

1.1

5.4

2.2

0.17

3.6

3.1

2

A

V_CC=

1.8V

W

A

Total

power

I_{CC_Idle_1}

I_{DD_Idle_1}

P_{Idle_1}

V_CC=

1.5V

A

V_CC=

1.8V

W

A

Total

power

I_{CC_Idle_2}

I_{DD_Idle_2}

P_{Idle_2}

2.2

0.05

3.4

3.1

0.6

5.7

2.5

0.3

4.3

1

V_CC=

1.5V

A

V_CC=

1.8V

W

A

Total

power

I_{CC_Active_1}

I_{DD_Active_1}

P_{Active_1}

I_{CC_Active_2}

I_{DD_Active_2}

P_{Active_2}

I_{CC_LOs}

V_CC=

1.5V

1)

A

V =

CC

1.8V

6.5

2.5

0.6

4.8

1

8.3

2.5

1.1

5.7

1

8.3

2.5

1.1

5.7

1

W

A

Total

power

V_CC=

1.5V

A

V_CC=

1.8V

W

A

Total

power

V_CC=

1.5V

I_{DD_Los}

0.05

0.09

0.17

A

V_CC=

1.8V

Data Sheet

29

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

Termination Current

Table 14

I_CC/I_DDSpecification for HYS72T[64/129/256]xxxHF-3.7-A

Product Type

Unit Note

Speed Grade PC2-4200F

PC2-4200F

Symbol

Max.

P_LOs

1.6

1.7

1.8

W

A

Total

power

I_{CC_Training}

I_{DD_Training}

P_{_Training}

3.7

0.3

6.1

3.7

0.6

6.6

3.7

0.6

6.6

3.7

1.1

7.5

3.7

1.1

7.5

V_CC=

1.5V

A

V_CC=

1.8V

W

Total

power

1) For 1 Rank modules: n × 0.5 × (2/3 × I_DD4R+ 1/3 × I_DD4W+ I_DD3N) For 2 Rank modules: n × 0.5 × (2/3 × I_DD4R+ 1/3

× I_DD4W+ I_DD3N)+ n × I_DD3Nwhere n = number of components/rank

9

Termination Current

Internal signals are terminated on the DIMM through address and clocks and 47 ohm for control. The VTT

resistors to an external power supply VTT = VDD / 2. power supply must be able to source and sink these

Modeled with 27 Ohm termination for command, currents:

Table 15

V_TTCurrents

Description

Symbol

I_TT1

I_TT2

Typ.

500

Max.

700

Unit

mA

Idle Current, DRAM Power Down (conditions TBD)

Active Power, 50% DRAM BW (conditions TBD)

Power Partitioning

Power dissipation of AMB (V_CC.AMB) plus power conditions which may be different from the actual

dissipation of DRAMs (V_DD.DRAM) plus termination application. Actual system power consumption is a

power (V_TT= 0.9 V) have to be added up to obtain the mixture of the above depending on access pattern,

total power consumption of the FB-DIMM. The above number of DIMMs, number of Ranks per DIMM and

numbers are given for specific standardized test duty factor of each rank and DIMM on the channel.

Data Sheet

30

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

High-Speed Differential Point-to-Point Link Interface

10

High-Speed Differential Point-to-Point Link Interface

The following specifications define the High-Speed them into a serialized bit-stream. This FB-DIMM link is

Differential Point-to-Point Signaling Link for FB- being specified to operate from 3.2 to 4.8 Gb/s. The

DIMMD, operating at the AMB supply voltage of 1.5 V specifications are defined for three distinct bit-rates of

that is provided at the DIMM connector. The link operation: 3.2 Gb/s (PC2-4200F), 4.0 Gb/s (PC2-

consists of a transmitter and a receiver and the 5300F) and 4.8 Gb/s (PC2-6400F). The link utilizes a

interconnect in between them. The transmitter sends derived clock approach and transmitter de-emphasis to

serialized bits into a lane and the receiver accepts the compensate for channel loss characteristics.

electrical signals of the serialized bits and transforms

10.1

Differential Signaling

A Differential Signal is defined by taking the voltage (VDIFF = VD+ - VD-). The Common Mode Voltage

difference between two conductors. In this (VCM) is defined as the average or mean voltage

specification, a differential signal or differential pair is present on the same differential pair (VCM = [VD++

comprised of a voltage on a positive conductor, VD+, VD-]/2). This documentís electrical specifications often

and a negative conductor, VD-. The differential voltage refer to peak-to-peak measurements or peak

(VDIFF) is defined as the difference of the positive measurements, which are defined by the following 5

conductor voltage and the negative conductor voltage equations:

1. VDIFFp-p = (2*max|VD+ - VD-|) (This applies to a symmetric differential swing)

2. VDIFFp-p = (max|VD+ - VD-| {VD+ > VD-} + max|VD+ - VD-| {VD+ < VD-}) (This applies to an asymmetric

differential swing.)

3. VDIFFp = (max|VD+ - VD-|) (This applies to a symmetric differential swing)

4. VDIFFp = (max|VD+ - VD-| {VD+ > VD-}) or (max|VD+ - VD-| {VD+ < VD-}) which ever is greater (This applies

to an asymmetric differential swing.)

5. VCMp = (max|VD+ + VD-|/2)

Note: The maximum value is calculated on a per unit kHz. AC is defined as all frequency components at or

interval evaluation. The maximum function as above Fdc = 30 kHz. These definitions pertain to all

described is implicit for all peak-to-peak and peak voltage and current specifications. An example

equations throughout the rest of this chapter, and thus waveform is shown in Figure 1-2. In this waveform the

a max function will not appear in any following differential peak-peak signal is approximately 0.6 V, the

representations of these equations. In this section, DC differential peak signal is approximately 0.3 V and the

is defined as all frequency components below Fdc = 30 common mode is approximately 0.25 V.

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Figure 9

Sample Differental Signal FB-DIMMUnit Interval (UI)

31

Data Sheet

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

High-Speed Differential Point-to-Point Link Interface

Average time interval between voltage transitions of a intentional frequency modulation of the source clock

signal. This is the same as the period of the FB-DIMM negligible. The UI will be different depending on the

link bit-rate clock. Given a <...1010...> between voltage data rate of operation. UI=312.5ps (PC2-4200F),

transitions, over a time interval long enough to make all UI=250ps (PC2-5300F), UI=208ps (PC2-6400F).

10.1.1

Transition Density in Transmitted Signals

The FB-DIMM link doesn’t prescribe encoding. Density_min is: 6 transitions per 512 bits: FB-DIMM at

However the link bit stream needs to maintain a 3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s. The prescribed

minimum transition density. The transition density is minimum is required to enable phase tracking of the

defined as the number of transitions that occurs either received data by the receiver while at the same time

from 0 to 1 or from 1 to 0 within any bit stream of a minimize the overhead requirements.

prescribed length. The minimum prescribed Transition-

10.1.2

Jitter and Bit Error Rate

Jitter is defined as the deviation in the edges of a approximated as Gaussian and can be used to

sequence of data bits from their ideal timing positions. estimate the bit error rate (BER) of the link. In this

This deviation can be in phase, period or duty cycle. document the allocation to random jitter and

Jitter is further categorized into random jitter and deterministic jitter has not been separately specified.

deterministic jitter. The total jitter is the convolution of The total jitter must support a maximum BER of 10 -16.

the probability density for all the independent jitter The methods for measuring BER compliance are still

sources. The random jitter magnitude can be being evaluated.

10.1.3

De-Emphasis

De-emphasis is the engineering term used to describe interference (ISI) due to the difference in loss across

the technique of utilizing a voltage swing reduction of the frequency band where the main energy of the

non-transition bits. Figure 1-3 shows an example of a transmitted bit patterns is located. De-emphasis must

de-emphasized differential signal. De-emphasis is be implemented when multiple bits of the same polarity

different from pre-emphasis in that non-transition bits are output in succession. Subsequent bits are driven at

are reduced in voltage as opposed to an increase in a differential voltage level below the first bit and

voltage swing for transition bits with pre-emphasis. De- individual bits are always driven at the full voltage level,

emphasis is included to minimize Inter-symbol for normal operation.

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Figure 10 De-Emphasis

10.1.4

Electrical Idle (EI)

The condition when both conductors of a differential primarily used in power saving and inactive states (i.e.

pair are at 0 volt (grounded) level. Electrical idle is DISABLE).

Data Sheet

32

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

High-Speed Differential Point-to-Point Link Interface

10.1.5

Reference Clock

The reference clock network consists of the clock the chips at both ends of the link. The reference clock

generator and the clock buffer that drives the PLL of signal meets the High-Speed Current Steering Logic

any front-end transmitter or receiver. The same (HCSL) specification.

reference clock shall be transmitted to the front-end of

10.2

High Speed Serial Link Reference Clocks (SCK, SCK)

To reduce jitter and allow for future silicon fabrication Logic) clocks are used. The nominal single-ended

process changes, HCSL (High-Speed Current Steering swing for each clock is 0 to 0.7 V.

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Figure 11 Differental Reference Clock Waveform

The reference clock frequency is 1/24 of the link data reference clock is unspecified. However, in order to

rate, e.g. 166.67 MHz for a data rate of 4.0Gb/s. The limit the jitter difference between TX and RX there is an

reference clock pair is routed point-to-point to each upper limit for the phase difference between data and

DIMM on the system board. The FB-DIMM channel reference clock at the RX, called the transport delay,

utilizes mesochronous clocking, i.e. the phase T1).

relationship between TX reference clock and RX

10.3

Spread Spectrum Clocking (SSC)

Spread Spectrum Clock (SSC) with up to -0.5% down a modulation rate in the range between 30 kHz and 33

spread in frequency shall be supported. The frequency kHz. The modulation profile of SSC shall be able to

of the clock and therefore bit rate can be modulated provide optimal or close to optimal EMI reduction.

from 0% to -0.5% of the nominal data rate/frequency, at Typical profiles include Triangular or Hershey profile.

10.4

Reference Clock Input Specifications

Table 16

Parameter

Reference Clock Input Specifications

Symbol

Values

Min.

133.33

Unit

Notes

Max.

200.00

700

1)2)

3)

Reference clock frequency

Rise time, Fall time

f_SCK

T_sck-rise

T_sck-fall

MHz

psec

175

Voltage high

Voltage low

V_SCK-high

V_SCK-low

V_Cross-abs

V_Cross-rel

T_{SCK-Rise-Fall-Match}

T_{SCK-Dutycycle}

I_{I_CK}

660

-150

250

850

mV

4)

Absolute crossing point

Relative crossing point

% mismatch between rise and fall times

Duty cycle of referance clock

Clock leakage current

Clock input capacitance

550

5)4)

Calculated Calculated

-

40

-10

0.5

10

60

10

2

%

uA

pF

6)7)

7)

C_{I_CK}

Data Sheet

33

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

High-Speed Differential Point-to-Point Link Interface

Table 16

Parameter

Reference Clock Input Specifications

Symbol

Values

Min.

-0.25

Unit

Notes

Max.

0.25

5

8)

Clock input capacitance delta

Transport delay

C_{I_CK(D)}

T1

pF

ns

Periods

ps

9)10)

11)

Phase Jitter Sample Size

Reference clock jitter, filtered

Reference clock deterministic jitter

NSAMPLE

T_REF-JITTER

T_REF-DJ

10¹⁶

12)13)

40

TBD

ps

1) 133MHz for PC2-4200, 166MHz for PC2-5300 and 200MHz for PC2-6400.

2) Measured with SSC disabled.

3) Measured differentially through the range of 0.175V to 0.525V.

4) The crossing point must meet the absolute and relative crossing point specification simultaneously.

5) V_{Cross_rel_(min)}and V_{Cross_rel_(max)}are derived using the following calculation: Min = 0.5 (V_havg- 0.710) + 0.250; and Max = 0.5

(V_havg- 0.710) + 0.550, where V_havgis the average of V_SCK-highm

6) Measured with a single-ended input voltage of 1V.

7) Applies to Reference Clocks SCK and SCK.

8) Differance between SCK and SCK input

9) T1 = |Tdatapath - Tclockpath| (excluding PLL loop delays). This parameter is not a direct clock output parameter but it

indirectly determines the clock output parameter TREF-JITTER.

10) The net transport delay is the difference in time of flight between associated data and clock paths. The data path is defined

from the reference clock source, through the TX, to data arrival at the data sampling point in the RX. The clock path is

defined from the reference clock source to clock arrival at the same sampling point. See Figure 3-3. The path delays are

caused by copper trace routes, on-chip routing, on-chip buffering, etc. They include the time-of-flight of interpolators or

other clock adjustment mechanisms. They do *not* include the phase delays caused by finite PLL loop bandwidth because

these delays are modeled by the PLL transfer functions.

11) Direct measurement of phase jitter records over 1016 periods is impractical. It is expected that the jitter will be measured

over a smaller, yet statistically significant, sample size and the total jitter at 1016 samples extrapolated from an estimate

of the sigma of the random jitter components.

12) Measured with SSC enabled on reference clock generator.

13) As measured after the phase jitter filter. This number is separate from the receiver jitter budget that is defined by the TRX-

Total-MIN parameters.

10.5

Differential Transmitter Output Specifications

This specification defines a differential current mode _Min(specified later). The eye diagrams must be valid for

driver with a three different TX voltage swing modes at least N_MIN-UI-TXconsecutive UIs (specified in Table 3-

(large, regular and small). The AMBs supports all three 3). An appropriate average transmitter UI must be used

voltage swing modes. The specification defines several as the interval for measuring the eye diagram. The eye

de-emphasis settings for each voltage swing. Each diagram is created using all edges of the N_MIN-UI-TX

setting is defined as a separate differential eye diagram consecutive UIs. The eye diagrams shall be measured

that must be met for the transmitter. Figure 3-4 defines by observing a continuous TBD pattern at the pin of the

the eye heights for the large, regular and small voltage device for the non de-emphasized eye and by

swing. The no de-emphasis voltages are for a transition observing a continuous TBD pattern at the pin of the

bit while the other voltages are for a de-emphasized bit. device for the deemphasized eye. The transmitter

All eye diagrams must be aligned in time using the jitter output eye is referenced to V_SSand all transmitter

median to locate the center of the eye diagram. All eyes terminations must be referenced to V_{SS .}

must meet the minimum timing requirement of T_TX-Total-

Data Sheet

34

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

High-Speed Differential Point-to-Point Link Interface

6_48ꢃ$)&&ꢄ ꢀM6

ꢅ$ꢆ $ꢂ #ROSSING 0OINTꢇ

6_48ꢃ$)&&ꢄ ꢀM6

ꢅ$ꢆ $ꢂ #ROSSING 0OINTꢇ

6_{48 $)&&P PMIN}

ꢈ

ꢂ

;$%ꢂEMPHASIZED "ITS=

6_{48 $)&&P P}

ꢈ

ꢂ

6_{48ꢂ%QꢂMIN,T}ꢈ 6_{48ꢂ%Q$)&&PꢂPꢂMIN}ꢈ 6_{48ꢂ%QꢂMAX,T}

6_{48 $)&&P PMAX}

ꢂ

4_{48ꢂ4OTALꢂMIN}

-0%4ꢀꢀꢁꢀ

Figure 12 Differential requirement minimum transmitter output eye specifications shown with and

without de-emphasis

0ULSE MIN 3PECꢂ

4X 4OTAL MIN

-0%4ꢀꢀꢁꢀ

Figure 13 Illustrates the transmitter timing specifications

$ ꢂ

4X MIN 6DIFF PꢂP

ꢃ.O $EꢂEMPHASISꢄ

ꢃ$EꢂEMPHASISꢄ

$ ꢅ

-0%4ꢀꢁꢀꢀ

Figure 14 Illustrates the de-emphasized string of patterns at the output of a transmitter

Data Sheet

35

Rev. 0.9, 2005-04

08122004-IISJ-Y0AE

HYS72T[64/128/256]0[00/20]HF–[3.7/3]

512-Mbit DDR2 SDRAM

Preliminary

High-Speed Differential Point-to-Point Link Interface

Table 17

Differential Transmitter Output Specifications

Parameter

Symbol

Values

Unit Comments

Min. Max.

Differential peak-to-peak output voltage V_{TX-DIFFp-p_L}

for large voltage swing

900 1300 mV see Equation (1)

Measured as Note¹⁾

Differential peak-to-peak output voltage V_{TX-DIFFp-p_R}

for regular voltage swing

Differential peak-to-peak output voltage V_{TX-DIFFp-p_S}

for small voltage swing

800

520

mV see Equation (1)

Measured as Note¹⁾

mV see Equation (1)

Measured as Note¹⁾

DC common code output voltage for

large voltage swing

V_{TX-CM_L}

375 mV see Equation (2)

Measured as Note¹⁾

DC common code output voltage for

small voltage swing

V_{TX-CM_S}

135 280 mV see Equation (2)

Measured as Note¹⁾


型号：	HYS72T128000HF-3-A
厂家：	Infineon
描述：	DDR DRAM Module, 128MX72, CMOS, GREEN, DIMM-240 动态存储器双倍数据速率
文件：	总75页 (文件大小：1328K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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