HYS72T128020GU-3-A [INFINEON]
DDR DRAM Module, 128MX72, 0.45ns, CMOS, DIMM-240;
| 型号： | HYS72T128020GU-3-A |
| 厂家： | 
Infineon |
| 描述： | DDR DRAM Module, 128MX72, 0.45ns, CMOS, DIMM-240 动态存储器 双倍数据速率 |
| 文件： | 总26页 (文件大小：761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, V0.82, Oct. 2003
HYS64T32000GU (256 MByte)
HYS64T64000GU (512 MByte)
HYS72T64000GU (512 MByte ECC)
HYS64T128020GU (1 GByte)
HYS72T128020GU (1 GByte ECC)
DDR2 Unbuffered DIMM Modules
Memory Products
N e v e r s t o p t h i n k i n g .
HYS64T32000GU
HYS64T64000GU, HYS72T64000GU
HYS64T128020GU, HYS72T128020GU
Preliminary Datasheet Rev. 0.82 (10.03)
1.8 V 240-pin Unbuffered DDR2 SDRAM Modules
256 MByte, 512 MByte & 1 GByte Modules
PC2-3200U /-4300U /-5300U
•
240-pin ECC and Non-ECC Unbuffered 8-
Byte Dual-In-Line DDR2 SDRAM Module for
PC, Workstation and Server main memory
applications
•
Programmable CAS Latencies (3, 4 & 5),
Burst Length (8 & 4) and Burst Type
•
•
•
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_1.8 compatible
•
•
•
One rank 32M x 64, 32M x 72, 64M x 64, 64M
x 72 and two ranks 128M × 64 and 128M x 72
organization
OCD (Off-Chip Driver Impedance
Adjustment) and ODT (On-Die Termination)
JEDEC standard Double Data Rate 2
Synchronous DRAMs (DDR2 SDRAM) with a
single + 1.8 V (±0.1 V) power supply
•
•
Serial Presence Detect with E2PROM
Low Profile Modules form factor:
133.35 mm x 30,00 mm (MO-237)
Built with 512Mb DDR2 SDRAMs in 60-ball /
84-ball FBGA chipsize packages
•
Based on JEDEC standard reference card
layouts RawCard “A”, “B” & “C”
•
Performance:
Speed Grade Indicator
-5
-3.7
DDR2-533
PC2-4300
200
-3
DDR2-667
PC2-5300
200
Unit
Component Speed Grade
DDR2-400
PC2-3200
200
Module Speed Grade
Max. Clock Frequency @ CL = 3
Max. Clock Frequency @ CL = 4 & 5
MHz
MHz
200
266
333
1.0 Introduction
The INFINEON HYS64/72Txxxx0GU module family are low profile Unbuffered DIMM modules with
30,0 mm height based on DDR2 technology. DIMMs are available as non-ECC modules in
32M x 64 (256MB), 64M x 64 (512MB) and 128M x 64 (1024MB) and as ECC-modules in 32M x 72
(256MB), 64M x 72 (512MB) and 128M x 72 (1024MB) organisation and density, intended for
mounting into 240 pin connector sockets.
The memory array is designed with 512Mb Double Data Rate (DDR2) Synchronous DRAMs for
ECC and Non-ECC applications. Decoupling capacitors are mounted on the PCB board. The
DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C
protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
available to the customer.
INFINEON Technologies
Rainer.Weidlich@Infineon.com
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10.03
HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
1.1 Ordering Information
Type & Partnumber
Compliance Code
Description
ECC/
SDRAM
Non-ECC Technology
PC2-3200:
HYS64T32000GU-5-A
HYS64T64000GU-5-A
HYS72T64000GU-5-A
HYS64T128020GU-5-A
HYS72T128020GU-5-A
PC2-4300:
PC2-3200U-33310-C one rank 256 MB Unb. DIMM Non-ECC 512 Mbit (x16)
PC2-3200U-33310-A one rank 512 MB Unb.DIMM Non-ECC 512 Mbit (x8)
PC2-3200U-33310-A one rank 512 MB Unb.DIMM ECC
512 Mbit (x8)
Non-ECC 512 Mbit (x8)
ECC 512 Mbit (x8)
PC2-3200U-33310-B two ranks 1 GB Unb. DIMM
PC2-3200U-33310-B two ranks 1 GB Unb. DIMM
HYS64T32000GU-3.7-A PC2-4300U-44410-C one rank 256 MB Unb. DIMM Non-ECC 512 Mbit (x16)
HYS64T64000GU-3.7-A PC2-4300U-44410-A one rank 512 MB Unb.DIMM Non-ECC 512 MBit (x8)
HYS72T64000GU-3.7-A PC2-4300U-44410-A one rank 512 MB Unb.DIMM ECC
512 MBit (x8)
Non-ECC 512 Mbit (x8)
ECC 512 Mbit (x8)
HYS64T128020GU-3.7-A PC2-4300U-44410-B two ranks 1 GB Unb. DIMM
HYS72T128020GU-3.7-A PC2-4300U-44410-B two ranks 1 GB Unb. DIMM
PC2-5300:
HYS64T32000GU-3-A
HYS64T64000GU-3-A
HYS72T64000GU-3-A
HYS64T128020GU-3-A
HYS72T128020GU-3-A
Notes:
PC2-5300U-44410-C one rank 256 MB Unb. DIMM Non-ECC 512 Mbit (x16)
PC2-5300U-44410-A one rank 512 MB Unb.DIMM Non-ECC 512 MBit (x8)
PC2-5300U-44410-A one rank 512 MB Unb.DIMM ECC
512 MBit (x8)
Non-ECC 512 Mbit (x8)
ECC 512 Mbit (x8)
PC2-5300U-44410-B two ranks 1 GB Unb. DIMM
PC2-5300U-44410-B two ranks 1 GB Unb. DIMM
1. All part numbers end with a place code, designating the silicon die revision. Example: HYS 72T6400GU-5-A, indicating
Rev. A dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see
section 8 of this datasheet.
2. The Compliance Code is printed on the module label and describes the speed grade, f.e. “PC2-4300U-44410-C”, where
4300U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and “44410” means CAS latency = 4, trcd
latency = 4 and trp latency = 4 using the latest JEDEC SPD Revision 1.0 and produced on the Raw Card “C”.
1.2 Address Format
Density
Module
Organization
Memory
Ranks
ECC/
# of
# of row/bank/ Refresh Period Interval
columns bits
Non-ECC SDRAMs
256 MB
512 MB
512 MB
32M x 64
64M × 64
64M × 72
1
1
1
2
2
Non-ECC
Non-ECC
ECC
4
8
13/2/10
14/2/10
14/2/10
14/2/10
14/2/10
8k
8k
8k
8k
8k
64 ms
64 ms
64 ms
64 ms
64 ms
7.8 µs
7.8 µs
7.8 µs
7.8 µs
7.8 µs
9
1024 MB 2 x 64M × 64
1024 MB 2 x 64M × 72
Non-ECC
ECC
16
18
INFINEON Technologies
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HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
1.3 Components on Modules
Density
DRAM components
reference datasheet
DRAM Density
DRAM Organisation
256 MB
512 MB
1024 MB
HYB18T512160AC
HYB18T512800AC
HYB18T512800AC
512 Mbit
512 Mbit
512 Mbit
32Mb x 16
64Mb x 8
64Mb x 8
For a detailed description of all functionalities of the DRAM components on these modules see
the referenced component datasheet
1.4 Pin Definition and Function
Pin Name
A[13:0]
Description
Row Address Inputs 4)
Column Address Inputs
Pin Name
CB[7:0]
Description
DIMM ECC Check Bits 2)
A[9:0]
DQS[8:0]
SDRAM data strobes 2)
(positive line of differential pair)
A10/AP
Column Address Input for Auto-
Precharge
DQS[8:0]
SDRAM data strobes 2)
(negative line of differential pair)
BA[1:0]
CK[2:0]
SDRAM Bank Selects
DM[8:0]
SCL
SDRAM data mask 2)
Serial bus clock
Clock input
(positive line of differential pair)
CK[2:0]
Clock input
(negative line of differential pair)
SDA
Serial bus data line
RAS
Row Address Strobe
Column Address Strobe
Read/Write Input
Chip Select 3)
SA[2:0]
VDD
slave address select
Power (+ 1.8 V)
I/O reference supply
Ground
CAS
WE
VREF
CS[1:0]
CKE[1:0]
ODT[1:0]
DQ[63:0]
VSS
Clock Enable 3)
VDDSPD
EEPROM power supply
no connect
Active termination control lines 1) 3) NC
Data Input/Output
1) Active termination only applies to DQ, DQS, DQS and DM signals
2) CB[7:0], DQS8, DQS8 and DM8 are used on ECC modules only and are not connected to components on Non-ECC modules
3) CS1, ODT1 and CKE1 are used on dual rank modules only
4) A13 is not used on memory modules based on x16 organised memory components
INFINEON Technologies
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HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
1.5 Pin Configuration
Symbol
VREF
VSS
PIN#
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
Symbol
VSS
PIN#
61
Symbol
A4
PIN#
181
182
183
184
Symbol
VDDQ
A3
PIN#
1
2
DQ4
62
VDDQ
A2
3
DQ0
DQ5
63
A1
4
DQ1
VSS
64
VDD
VDD
KEY
CK0
5
VSS
DM0
KEY
6
DQS0
DQS0
VSS
DQS9
VSS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
VSS
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
7
VSS
CK0
8
DQ6
VDD
VDD
A0
9
DQ2
DQ7
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DQ3
VSS
VDD
VDD
BA1
VSS
DQ12
DQ13
VSS
A10/AP
BA0
DQ8
VDDQ
RAS
CS0
DQ9
VDDQ
WE
VSS
DM1
DQS1
DQS1
VSS
NC
CAS
VDDQ
ODT0
A13 / NC 3)
VDD
VSS
VSS
VDDQ
CS1
CK1
NC
CK1
ODT1
VDDQ
VSS
NC
VSS
VSS
DQ14
DQ15
VSS
DQ36
DQ37
VSS
DQ10
DQ11
VSS
DQ32
DQ33
VSS
DQ20
DQ21
VSS
DM4
NC
DQ16
DQ17
VSS
DQS4
DQS4
VSS
VSS
DM2
DQ38
DQ39
VSS
DQS2
DQS2
VSS
NC
DQ34
DQ35
VSS
VSS
DQ22
DQ23
VSS
DQ44
DQ45
VSS
DQ18
DQ19
VSS
DQ40
DQ41
VSS
DQ28
DQ29
VSS
DM5
NC
DQ24
DQ25
VSS
DQS5
DQS5
VSS
VSS
DM3
DQ46
DQ47
VSS
DQS3
DQS3
VSS
NC
DQ42
DQ43
VSS
VSS
DQ30
DQ31
VSS
CB4 / NC 2)
CB5 / NC 2)
DQ52
DQ53
VSS
DQ26
DQ27
VSS
DQ48
DQ49
VSS
CK2
CB0 / NC 2)
SA2
CK2
INFINEON Technologies
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Unbuffered DDR2 SDRAM-Modules
Pin Configuration (cont’d)
Symbol
CB1 / NC 2)
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
43
163
164
165
166
167
168
169
170
171
172
173
176
175
176
177
178
179
180
VSS
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
NC
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
VSS
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VSS
DM8
VSS
DM6
NC
DQS8
DQS8
VSS
CB2 / NC 2)
CB3 / NC 2)
VSS
NC
DQS6
DQS6
VSS
VSS
VSS
CB6 / NC 2)
CB7 / NC 2)
VSS
DQ54
DQ55
VSS
DQ50
DQ51
VSS
VDDQ
CKE1
VDD
NC, (A15)1)
NC, (A14)1)
VDDQ
A12
DQ60
DQ61
VSS
VDDQ
CKE0
VDD
DQ56
DQ57
VSS
DM7
NC
NC, (BA2)1)
DQS7
NC
NC
VSS
VDDQ
A11
VSS
DQ62
DQ63
VSS
A9
DQ58
DQ59
VSS
A7
VDD
VDD
A8
VDDSPD
SA0
A5
A6
SDA
SCL
SA1
1) Pins 54, 173 and 174 are not connected on this modules and are reserved for future DIMM module products
based on higher density memory components.
2) These pins are the check bit DQ’s for ECC unbuffered DIMMs and no-connects for Non-ECC DIMMs
3) Address A13 is not used on memory modules based on x 16 components
1.6 Pin Locations
Front
120
240
pin
1
64
65
pin 121
185
184
Backside
240 pin Modules (MO-237)
INFINEON Technologies
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HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
1.7 Unbuffered DIMM Input/Output Functional Description
Type Polarity
Input Cross point
Input Active High
Function
Symbol
CK[2:0],
CK[1:0]
The system clock inputs. All address and command lines are sampled on the cross point of
the rising edge of CK and the falling edge of CK.
Activates the SDRAM clock signals when high and deactivates when low. By deactivating the
clocks, CKE low initiates the Power Down Mode or the Self Refresh Mode
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored and previous operations con-
tinue. This signal provides for external rank selection on systems with multiple ranks.
CKE[1:0]
CS[1:0]
Active Low
Input
When high, termination resistance is enabled for all DQ, DQS and DM pins, assuming this
Input Active High
Input Active Low
ODT[1:0]
function is enabled in the Extended mode Register Set (EMRS).
RAS, CAS,
WE
When sampled at the positive edge of the clock, RAS, CAS and WE define the operation to
be executed by the SDRAM.
DM is an input mask signal for write data. Input data is masked when DM is sampled high
DM[8:0]
BA[1:0]
Input Active High coincident with that input data during a write access. DM is samples on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
Input
-
Selects which internal SDRAM memory bank is activated
During Bank Activate command cycle, Address defines the row address. During a Read or
Write command cycle, Address defines the column address. In addition to the column
address, A10(=AP) is used to invoke Auto-Precharge operation at the end of the burst read
or write cycle. If AP is high, Auto Precharge is selected and BA[1:0] defines the bank to be
precharged. If AP is low, Auto-Precharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all
banks will be precharged regardless of the state of BA[1:0]. If AP is low, BA[1:0] are used to
define which bank to precharge.
A[13:0]
Input
-
DQ[63:0],
CB[7:0]
I/O
I/O
-
Data and Check Bit Input /Output pins.
The data strobes, associated with one data byte, source with data transfer. In Write mode,
the data strobe is sourced by the controller and is centered in the data window. In Read
mode the data strobe is sources by the DDR2 SDRAM and is sent at the leading edge of the
data window. DQS signals are complements, and timing is relative to the crosspoint of
respective DQS and DQS. If the module is to be operated in single ended strobe mode, all
DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers
programmed appropriately.
DQS[8:0],
DQS[8:0]
Cross point
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial
SPD EEPROM address range
This bidirectional pin is used to transfer data into and out of the SPD EEPROM. A resistor
maybe connected from the SDA bus line to VDDSPD on the system level to act as a pull-up.
This signal is used to clock data into the SPD EEPROM. A resistor maybe connected from
the SCL bus line to VDDSPD on the system planar to act as a pull-up.
Input
I/O
-
-
-
SA[2:0]
SDA
Input
SCL
Supply
Supply
Supply
-
-
-
Isolated power supply for the SDRAM output buffers to provide improved noise immunity.
Power and ground for the DDR SDRAM input buffers and core logic.
Reference voltage for the SSTL-18 inputs.
VDDQ
V
DD, VSS
VREF
Serial EEPROM positive power supply, wired to a separated power pin at the connector
which supports from 1.7 Volt to 3.6 Volt.
Supply
-
VDDSPD
INFINEON Technologies
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HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
2.0 Block Diagrams
2.2 One Rank 32M x 64 (256 MByte) DDR2 SDRAM DIMM Modules (x16 components.)
HYS64T32000GU on Raw Card C
CS0
CS
CS
LDQS
LDQS
LDM
DQS4
DQS4
DM4
LDQS
LDQS
LDM
DQS0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
D0
D2
DQS1
DQS1
DM1
DQS5
UDQS
UDM
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
I/O 8
I/O 8
DQ9
I/O 9
I/O 9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 10
I/O 11
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
I/
O 12
I/O 13
I/0 14
I/O 15
CS
CS
LDQS
LDQS
LDM
DQS6
DQS6
DM6
LDQS
LDQS
LDM
DQS2
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
DQ51
DQ52
DQ53
DQ54
DQ55
D1
D3
DQS3
DQS3
DM3
DQS7
UDQS
UDM
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 8
I/O 8
I/O 9
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
I/O 10
I/O 11
I/
O 12
I/O 13
I/O 14
I/O 15
V
EEPROM
DDSPD
Clock Wiring
SDRAMs
Serial PD
Clock Input
V
V
SDA
DD, DDQ
VREF
D0 - D3
D0 - D3
D0 - D3
CK0, CK0
CK1, CK1
CK2, CK2
NC
SCL
WP A0
SA0 SA1 SA2
A1 A2
2
2
SDRAMs
SDRAMs
V
SS
BA0, BA1
BA0, BA1 : SDRAMs D0 - D3
A0 - A12 : SDRAMs D0 - D3
DQ-to-I/O wiring may be changed within a byte
A0 - A12
RAS
DQ/DQS/DQS/DM/CKE/S relationships must be maintained as shown
DQ/DQS/DQS, adress and control resistors are 22 Ohms +/- 5%
RAS
CAS
WE
: SDRAMs D0 - D3
: SDRAMs D0 - D3
: SDRAMs D0 - D3
CAS
WE
BAx, Ax, RAS,CAS, WE resistors are 10 Ohms +/- 5%
CKE0
ODT0
CKE
ODT
: SDRAMs D0 - D3
: SDRAMs D0 - D3
INFINEON Technologies
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HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
Block Diagrams
2.2 One Rank 64M x 64 / 72 (512 MByte) DDR2 SDRAM DIMM Modules (x8 comp.)
HYS64T64000GU / HYS72T64000GU on Raw Card A
CS0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
CS DQS DQS
D4
DM
CS DQS DQS
D0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
D1
DM
CS DQS DQS
D5
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
D2
DM
CS DQS DQS
D6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ51
DQ52
DQ53
DQ54
DQ55
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
D3
DM
CS DQS DQS
D7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS8
DQS8
DM8
V
EEPROM
DDSPD
Serial PD
DM
CS DQS DQS
D8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
V
V
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DD, DDQ
VREF
D0 - D7, D8
D0 - D7, D8
SDA
SCL
WP A0
SA0 SA1
A1 A2
V
SS
D0 - D7, D8
SA2
Clock Wiring
SDRAMs
D8 for ECC modules only
Clock Input
CK0, CK0
CK1, CK1
CK2, CK2
3
3
3
SDRAMs
SDRAMs
SDRAMs
BA0, BA1
A0 - A13
RAS
CAS
WE
CKE0
ODT0
BA0, BA1 : SDRAMs D0 - D7, D8
A0 - A13 : SDRAMs D0 - D7, D8
RAS
CAS
WE
: SDRAMs D0 - D7, D8
: SDRAMs D0 - D7, D8
: SDRAMs D0 - D7, D8
: SDRAMs D0 - D7, D8
DQ-to-I/O wiring may be changed within a byte
DQ/DQS/DQS/DM/CKE/S relationships must be maintained as shown
CKE
DQ/DQS/DQS, adress and control resistors are 22 Ohms +/- 5%
ODT
: SDRAMs D0 - D7, D8
BAx, Ax, RAS,CAS, WE resistors are 5.1 Ohms +/- 5%
INFINEON Technologies
9
10.03
HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
Block Diagrams
2.3 Two Ranks 128M x 64/72 (1GByte) DDR2 SDRAM DIMM Modules (x8 comp.)
HYS64T128020GU / HYS72T128020GU on Raw Card B
CS1
CS0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
CS DQS DQS
D4
DM
CS DQS DQS
D13
DM
CS DQS DQS
D0
DM
CS DQS DQS
D9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
D5
DM
CS DQS DQS
D1
DM
CS DQS DQS
D14
DM
CS DQS DQS
D10
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
D15
DM
CS DQS DQS
D2
DM
CS DQS DQS
D11
DM
CS DQS DQS
D6
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ51
DQ52
DQ53
DQ54
DQ55
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
D3
DM
CS DQS DQS
D7
DM
CS DQS DQS
D16
DM
CS DQS DQS
D12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS8
DQS8
DM8
V
EEPROM
DDSPD
DM
CS DQS DQS
D8
DM
CS DQS DQS
D17
V
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
V
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DD, DDQ
VREF
D0 - D17
D0 - D17
V
SS
D0 - D17
Serial PD
Clock Wiring
SDRAMs
SDA
Clock Input
D8 and D17 on ECC modules only
SCL
WP A0
SA0 SA1 SA2
A1 A2
BA0, BA1
A0 - A13
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
BA0, BA1 : SDRAMs D0 - D17
A0 - A13 : SDRAMs D0 - D17
CK0, CK0
CK1, CK1
CK2, CK2
6
6
6
SDRAMs
SDRAMs
SDRAMs
RAS
CAS
WE
CKE
CKE
ODT
ODT
: SDRAMs D0 - D17
: SDRAMs D0 - D17
: SDRAMs D0 - D17
: SDRAMs D0 - D8
: SDRAMs D9 - D17
: SDRAMs D0 - D8
: SDRAMs D9 - D17
DQ-to-I/O wiring may be changed within a byte
DQ/DQS/DQS/DM/CKE/S relationships must be maintained as shown
DQ/DQS/DQS, adress and control resistors are 22 Ohms +/- 5%
BAx, Ax, RAS,CAS, WE resistors are 3 Ohms +/- 5%
INFINEON Technologies
10
10.03
HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
3.0 Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
max.
2.3
Voltage on any pins relative to VSS
Voltage on VDD relative to VSS
Voltage on VDD Q relative to VSS
Storage temperature range
VIN, VOUT
VDD
– 0.5
– 1.0
– 0.5
-55
V
V
2.3
VDDQ
2.3
TSTG
+100
oC
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
3.1 Operating Temperature Range
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
DIMM Module Operating Temperature Range (ambient)
DRAM Component Case Temperature Range
TOPR
0
0
+55
+95
oC
TCASE
oC
1 - 4
1. DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For
measurement conditions, please refer to the JEDEC document JESD51-2.
2. Within the DRAM Component Case Temperature range all DRAM specification will be supported.
3. Above 85oC DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below
85oC case temperature before initiating self-refresh operation.
3.2 Supply Voltage Levels and DC Operating Conditions (SSTL_1.8)
Parameter
Symbol
Limit Values
Unit
Notes
min.
1.7
nom.
max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
EEPROM Supply Voltage
DC Input Logic High
VDD
1.8
1.9
V
V
-
VDDQ
VREF
VDDSPD
VIH (DC)
VIL (DC)
IIL
1.7
1.8
1.9
1)
2)
0.49 x VDDQ
1.7
0.5 x VDDQ
0.51 x VDDQ
V
–
–
–
3.6
V
VREF + 0.125
– 0.30
– 5
VDDQ + 0.3
V
DC Input Logic Low
VREF – 0.125
V
Input Leakage Current
Output Leakage Current
5
5
µA
µA
3)
3)
IOL
– 5
1
2
3
Under all conditions, VDDQ must be less than or equal to VDD
Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise variations in VDDQ
For any pin under test input of 0 V ≤VIN ≤VDDQ + 0.3 V. Values are shown per DDR2-SDRAM component
.
INFINEON Technologies
11
10.03
HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
4.0 IDD Specifications and Conditions
4.1 256 MByte Non- ECC Module HYS64T32000GU (one rank, four components x16)
256 MByte HYS64T32000GU PC2-3200 -5” PC2-4300 “-3.7” PC2-5300 “-3”
typ.
201
239
7,1
65
max.
241
287
9,9
typ.
216
260
9,4
87
max.
259
312
13,1
104
90
typ.
237
286
11,8
109
81
max.
284
343
16,5
131
113
61
Symbol
IDD0
IDD1
Parameter / Condition
Operating Current
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Operating Current
Precharge PD Standby Current
IDD2P
IDD2N Precharge Standby Current
78
IDD2Q Precharge Quiet Standby Current
49
68
65
Active PD Standby Current
IDD3P(0)
26
37
35
49
43
IDD3P(1) LP Active PD Standby Current
IDD3N Active Standby Current
tbd.
97
tbd.
117
304
323
462
tbd.
10,8
671
tbd.
127
312
331
404
tbd.
7,4
616
tbd.
tbd.
158
372
395
419
tbd.
7,6
tbd.
153
374
397
485
tbd.
189
447
474
503
tbd.
Operating Current Burst Read
IDD4R
253
269
385
tbd.
7,2
569
IDD4W Operating Current Burst Write
IDD5B Auto-Refresh Current (tRFCmin.)
Auto-Refresh Current (tREFI)
Self-Refresh Current
Operating Current
IDD5D
IDD6
IDD7
11,1
726
11,3
801
679
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
4.2 512 MByte Non-ECC Module HYS64T64000GU (one rank, eight components x8)
512 MByte HYS64T64000GU
PC2-3200 “-5”
PC2-4300 “-3.7”
PC2-5300 “-3”
typ.
379
435
13,8
129
96
max.
455
522
19,4
155
135
72
typ.
408
472
18,4
172
128
68
max.
490
566
25,8
206
179
95
typ.
447
520
23,1
216
160
85
max.
536
624
32,3
259
225
119
tbd.
Symbol
IDD0
IDD1
Parameter / Condition
Operating Current
Unit Note
1
1
1
1
1
1
1
1
1
1
1
1
1
1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Operating Current
IDD2P Precharge PD Standby Current
Precharge Standby Current
IDD2N
IDD2Q Precharge Quiet Standby Current
IDD3P(0) Active PD Standby Current
51
LP Active PD Standby Current
tbd.
184
422
448
755
tbd.
14
tbd.
tbd.
tbd.
tbd.
IDD3P(1)
IDD3N Active Standby Current
220
507
538
906
240
520
552
792
288
624
662
950
297
620
659
822
357
745
790
987
IDD4R Operating Current Burst Read
Operating Current Burst Write
IDD4W
IDD5B Auto-Refresh Current (tRFCmin.)
IDD5D Auto-Refresh Current (tREFI)
tbd.
tbd.
tbd.
tbd.
tbd.
Self-Refresh Current
Operating Current
IDD6
IDD7
21
14,4
1080
21,6
1274
14,7
1191
22
998
1177
1405
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
INFINEON Technologies
12
10.03
HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
4.3 512 MByte ECC Module HYS72T64000GU (one rank, nine components x8)
512 MByte HYS72T64000GU PC2-3200 “-5” PC2-4300 “-3.7” PC2-5300 “-3”
typ.
427
489
15,6
146
108
58
max.
512
587
21,8
175
152
81
typ.
459
531
20,7
194
144
77
max.
551
637
29,0
232
202
107
tbd.
typ.
593
585
25,9
243
180
96
max.
603
702
36,3
291
253
134
tbd.
Symbol
IDD0
IDD1
Parameter / Condition
Operating Current
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Operating Current
IDD2P Precharge PD Standby Current
IDD2N Precharge Standby Current
Precharge Quiet Standby Current
IDD2Q
IDD3P(0) Active PD Standby Current
IDD3P(1) LP Active PD Standby Current
tbd.
tbd.
tbd.
tbd.
Active Standby Current
IDD3N
207
475
505
849
tbd.
248
570
605
1019
tbd.
270
585
621
891
tbd.
324
702
745
1069
tbd.
335
698
741
925
tbd.
402
838
889
1110
tbd.
IDD4R Operating Current Burst Read
IDD4W Operating Current Burst Write
Auto-Refresh Current (tRFCmin.)
IDD5B
IDD5D Auto-Refresh Current (tREFI)
IDD6
IDD7
Self-Refresh Current
Operating Current
15,8
1122
23,7
1324
16,2
1215
24,3
1434
16,5
1340
24,8
1581
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
4.4 1024 MByte Non-ECC Module HYS64128020GU (two ranks, sixteen components x8)
1024 MByte HYS64T128020GU
PC2-3200 “-5”
PC2-4300 “-3.7”
PC2-5300 “-3”
typ.
393
449
27,7
259
193
102
tbd.
max.
474
541
38,7
310
270
143
tbd.
typ.
426
490
36,8
344
256
136
tbd.
max.
515
592
51,5
413
358
190
tbd.
typ.
470
543
46,1
431
321
170
tbd.
max.
568
656
64,6
517
449
239
tbd.
Symbol
IDD0
IDD1
Parameter / Condition
Operating Current
Unit Note
1, 2
mA
Operating Current
mA 1, 2
mA 1, 3
IDD2P Precharge PD Standby Current
Precharge Standby Current
1, 3
IDD2N
mA
IDD2Q Precharge Quiet Standby Current
IDD3P(0) Active PD Standby Current
mA 1, 3
mA 1, 3
LP Active PD Standby Current
1, 3
IDD3P(1)
mA
IDD3N Active Standby Current
367
436
462
769
tbd.
441
526
558
925
tbd.
480
538
570
810
tbd.
576
650
688
976
tbd.
595
643
682
645
tbd.
714
777
823
1019
tbd.
mA 1, 3
mA 1, 2
IDD4R Operating Current Burst Read
Operating Current Burst Write
1, 2
IDD4W
mA
IDD5B Auto-Refresh Current (tRFCmin.)
IDD5D Auto-Refresh Current (tREFI)
mA 1, 2
mA 1, 3
Self-Refresh Current
Operating Current
1, 3
IDD6
IDD7
28,1
1012
42,1
1197
28,84
1098
43,2
1300
29,4
1214
44,1
1438
mA
mA 1, 2
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD current mode
INFINEON Technologies
13
10.03
HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
4.5 1024 MByte ECC Module HYS72T128020GU (two ranks, eighteen components x8)
1024 MByte HYS72T128020GU
PC2-3200 “-5”
PC2-4300 “-3.7”
PC2-5300 “-3”
typ.
442
505
31,1
291
217
115
tbd.
max.
534
609
43,6
349
303
161
tbd.
typ.
480
552
41,4
387
288
153
tbd.
max.
580
666
58,0
464
403
214
tbd.
typ.
529
611
51,9
485
361
192
tbd.
max.
640
738
72,6
582
505
268
tbd.
Symbol
IDD0
IDD1
Parameter / Condition
Operating Current
Unit Note
mA 1, 2
Operating Current
1, 2
mA
IDD2P Precharge PD Standby Current
IDD2N Precharge Standby Current
mA 1, 3
mA 1, 3
Precharge Quiet Standby Current
1, 3
IDD2Q
mA
IDD3P(0) Active PD Standby Current
IDD3P(1) LP Active PD Standby Current
mA 1, 3
mA 1, 3
Active Standby Current
1, 3
IDD3N
413
491
520
865
tbd.
496
592
627
1041
tbd.
540
606
642
912
tbd.
648
731
774
1098
tbd.
669
724
767
951
tbd.
803
874
925
1146
tbd.
mA
IDD4R Operating Current Burst Read
IDD4W Operating Current Burst Write
mA 1, 2
mA 1, 2
Auto-Refresh Current (tRFCmin.)
1, 2
IDD5B
mA
IDD5D Auto-Refresh Current (tREFI)
mA 1, 3
IDD6
IDD7
Self-Refresh Current
Operating Current
31,6
1138
47,4
1346
32,4
1236
48,6
1463
33,1
1366
49,6
1617
mA
mA
1,3
1, 2
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD current mode
INFINEON Technologies
14
10.03
HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
4.6 IDD Measurement Conditions
(VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V)
Symbol
Parameter/Condition
Operating Current - One bank Active - Precharge
tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and con-
trol inputs are SWITCHING, Databus inputs are SWITCHING.
IDD0
IDD1
IDD2P
Operating Current - One bank Active - Read - Precharge
IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin.,tRCD = tRCDmin.,AL = 0, CL = CLmin.;
CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are
SWITCHING.
Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.;
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.;
IDD2N
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.;
IDD2Q
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STA-
IDD3P(0)
IDD3P(1)
IDD3N
BLE, Data bus inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STA-
BLE, Data bus inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax; tRP = tRPmin.,CKE is HIGH; CS is high
between valid commands. Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4;AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands.
IDD4R
Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING;
IDD4W
Burst Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is
IDD5B
IDD5D
IDD6
HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS
is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current: CKE ≤0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85oC max.
All Bank Interleave Read Current:
1. All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address
bus inputs are STABLE during DESELECTS. Iout = 0mA.
2. Timing pattern:
IDD7
- DDR2 -400: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
- DDR2 -533: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
- DDR2 -667: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
3. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Notes:
1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
2. Definitions for IDD:
LOW is defined as VIN <= VIL(ac)max; HIGH is defined as VIN >= VIH(ac)min.
STABLE is defined as inputs are stable at a HIGH or LOW level.
FLOATING is defined as inputs are VREF = VDDQ / 2.
SWITCHING is defined as:
inputs are changing between HIGH and LOW every other clock (once per two cycles) for address and control signals, and
inputs changing between HIGH and LOW every other clock (once per cycle) for DQ signals not including mask or strobes.
3. IDD1, IDD4R, and IDD7A current measurements are defined with the outputs disabled (Iout = 0 mA). To achieve this on module
level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
3. For two rank modules: For all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
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4.6 IDD Measurement Conditions (cont’d)
For testing the IDD parameters, the following timing parameters are used:
-5
-3.7
PC2-4300
-3
Unit
PC2-3200
PC2-5300
Parameter
Symbol
3-3-3
3
4-4-4
4
4-4-4
4
CAS Latency
CLmin
tCKmin
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
5
3.75
15
3
Active to Read or Write delay
tRCDmin
tRCmin
15
12
Active to Active / Auto-Refresh command period
60
60
57
x8
tRRDmin
tRRDmin
tRASmin
tRASmax
tRPmin
7.5
10
7.5
10
7.5
10
Active bank A to Active bank B
command delay
x16
45
45
45
Active to Precharge Command
70000
15
70000
15
70000
12
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh command
period
tRFCmin
tREFI
105
7.8
105
7.8
105
7.8
ns
µs
Average periodic Refresh interval
4.7 ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The cur-
rent consumption for any terminated input pin, depends on the input pin is in tri-state or driving “0” or “1”, as long
a ODT is enabled during a given period of time.
ODT current per terminated pin:
EMRS(1) State
Unit
min.
5
typ.
6
max.
7.5
A6 = 0, A2 = 1
A6 = 1, A2 = 0
A6 = 0, A2 = 1
mA/DQ
mA/DQ
mA/DQ
Enabled ODT current per DQ
IODTO
IODTT
added IDDQ current for ODT enabled;
ODT is HIGH; Data Bus inputs are FLOATING
2.5
10
3
3.75
15
12
Active ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; worst case of Data Bus inputs
are STABLE or SWITCHING.
A6 = 1, A2 = 0
5
6
7.5
mA/DQ
note: For power consumption calculations the ODT duty cycle has to be taken into account
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5.0 Electrical Characteristics & AC Timings
5.1 AC Timing Parameter by Speed Grade (Component level data, for reference only)
-5
-3.7
-3
DDR2 -400
DDR2 -533
DDR2 -667
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
tAC DQ output access time from CK/CK
tDQSCK DQS output access time from CK/CK
tCH CK, CK high-level width
−600
−500
0.45
0.45
+600
-500
−450
0.45
0.45
+500
-450
+450
+400
0.55
0.55
ps
ps
tCK
tCK
+500
0.55
0.55
+450
0.55
0.55
-400
0.45
0.45
tCL CK, CK low-level width
tHP Clock Half Period
min. (tCL, tCH)
min. (tCL, tCH)
min. (tCL, tCH)
CL = 3
tCK Clock cycle time
CL = 4 & 5
5000
5000
600
8000
8000
-
5000
3750
600
8000
8000
-
5000
3000
tbd.
8000
8000
-
ps
ps
ps
Address and control input setup time
Address and control input hold time
DQ and DM input hold time
tIS
tIH
600
400
400
0.6
-
600
350
350
0.6
-
tbd.
tbd.
tbd.
0.6
-
-
-
-
-
ps
ps
ps
tCK
tCK
-
-
tDH
tDS
tIPW
tDIPW
tHZ
DQ and DM input setup time
-
-
Control and Addr. input pulse width (each input)
DQ and DM input pulse width (each input)
Data-out high-impedance time from CK/CK
Data-out low-impedance time from CK/CK
-
-
0.35
-
-
0.35
-
-
0.35
-
tACmax
tACmax
tACmax
tACmax
tACmax ps
tACmax ps
tACmin
tACmin
tACmin
tLZ
DQS-DQ skew
-
350
-
300
-
tbd.
ps
ps
tDQSQ
(for DQS & associated DQ signals)
tQHS Data hold skew factor
-
450
-
-
400
-
-
tbd.
-
tQH Data Output hold time from DQS
tHP-tQHS
tHP-tQHS
tHP-tQHS
WL
WL
WL
WL
WL
WL
tDQSS Write command to 1st DQS latching transition
tDQSL,H DQS input low (high) pulse width (write cycle)
tCK
tCK
tCK
-0.25
+0.25
-0.25
+0.25
-0.25
+0.25
0.35
0.2
-
-
0.35
0.2
-
-
0.35
0.2
-
-
DQS falling edge to CLK setup time
tDSS
(write cycle)
DQS falling edge hold time from CLK
(write cycle)
0.2
-
0.2
-
0.2
-
tCK
tDSH
Mode register set command cycle time
Write preamble setup time
Write preamble
2
-
2
-
2
-
tCK
ps
tCK
tCK
tCK
tCK
ns
ns
tMRD
tWPRES
tWPRE
tWPST
tRPRE
tRPST
tRAS
0
-
-
0
-
-
0
-
-
0.25
0.40
0.9
0.40
45
0.25
0.40
0.9
0.40
45
0.35
0.40
0.9
0.40
45
Write postamble
0.60
1.1
0.60
-
0.60
1.1
0.60
-
0.60
1.1
0.60
-
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command period
60
-
60
-
57
-
tRC
Auto-refresh to Active/Auto-refresh command
period
tRFC
105
-
105
-
105
-
ns
INFINEON Technologies
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Unbuffered DDR2 SDRAM-Modules
-5
-3.7
-3
DDR2 -400
DDR2 -533
DDR2 -667
Symbol
Parameter
Unit
Min
15
Max
Min
15
Max
Min
Max
Active to Read or Write delay (with and without
Auto-Precharge) delay
-
-
12
-
-
-
ns
ns
ns
tRCD
tRP Precharge command period
15
-
-
15
-
-
12
x4 & x8
7.5
7.5
7.5
Active bank A to Active
tRRD
(1k page size)
bank B command
x16 (2k page size)
10
2
-
-
-
-
-
-
10
2
-
-
-
-
-
-
10
2
-
-
-
-
-
-
ns
tCK
ns
tCK
ns
ns
CAS A to CAS B Command Period
Write recovery time
tCCD
tWR
15
15
12
Auto precharge write recovery + precharge time WR+tRP
WR+tRP
7.5
WR+tRP
7.5
tDAL
tWTR
tRTP
Internal write to read command delay
10
Internal read to precharge command delay
7.5
7.5
7.5
Exit power down to any valid command
(other than NOP or Deselect)
2
6 - AL
2
-
-
-
2
6 - AL
2
-
-
-
2
6 - AL
2
-
-
-
tCK
tCK
tCK
tXARD
tXARDS
tXP
Exit active power-down mode to read command
(slew exit, lower power)
Exit precharge power-down to any valid com-
mand (other than NOP or Deselect)
Exit Self-Refresh to read command
Exit Self-Refresh to non-read command
CKE minimum high and low pulse width
OCD drive mode output delay
200
-
-
200
-
-
200
-
-
tCK
ns
tCK
ns
tXSRD
tXSNR
tCKE
tRFC + 10
tRFC + 10
tRFC + 10
3
0
-
3
0
-
3
0
-
12
12
12
tOIT
Minimum time clocks remain ON after CKE
asynchronously drops low
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
-
-
-
ns
µs
tDELAY
0oC - 85oC
-
-
7.8
3.9
-
-
7.8
3.9
-
-
7.8
3.9
Average Periodic
tREFI
Refresh Interval
85oC - 95oC
1. For details and notes see the relevant INFINEON component datasheet
2. Timing definition and values for tis, tih, tds and tdh may change due to actual JEDEC work. This may also
effect the SPD code for these parameters
5.2 ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition
min.
2
max.
2
Units
tAOND ODT turn-on delay
tCK
DDR2-400/533
DDR2-667
tAC(min)
tAC(min)
tAC(min) + 2ns
tAC(max) + 1 ns
tAC(max) + 0.7 ns
2 tCK + tAC(max) + 1ns
ODT turn-on
tAON
ns
tAONPD ODT turn-on (Power-Down Modes)
tAOFD ODT turn-off delay
ns
tCK
ns
ns
tCK
tCK
2.5
2.5
tAOF
tAOFPD
tANPD
tAXPD
ODT turn-off
tAC(min)
tAC(max) + 0.6ns
ODT turn-off delay (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
tAC(min) + 2ns
2.5 tCK + tAC(max) + 1ns
3
8
-
-
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6.0 Serial Presence Detect Codes for Unbuffered DIMM Modules
Byte# Description
Speed
Grade
SPD Entry
Value
Hex Value
0
1
2
3
4
5
6
7
8
9
Number of SPD Bytes
all
all
128
256
80
08
08
0E
0A
60
48
00
05
50
3D
30
60
50
tbd
02
82
08
08
00
0C
04
38
00
02
00
01
50
3D
30
60
50
tbd
50
60
3C
30
Total Bytes in Serial PD
Memory Type
all
DDR2-SDRAM
13 / 14
10
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks, Package and Height
Module Data Width
all
0D
0A
60
40
0E
0A
60
40
0E
0A
61
40
0E
0A
61
48
all
all
1 / 2
all
x64 / x72
Undefined
SSTL_1.8
5 ns
Reserved
all
Module Interface Levels
Min. Clock Cycle Time at CAS Latency = 5
all
-5
-3.7
-3
3.7 ns
3 ns
10
SDRAM Access Time from Clock at CL = 5
-5
0.6 ns
-3.7
-3
0.5 ns
tbd
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM Configuration Type
Refresh Rate/Type
all
non-ECC / ECC
7.8 µs, SR
x16, x8
na / x8
-
00
00
00
02
all
SDRAM Width, Primary
Error Checking SDRAM Data Width
Reserved
all
10
00
08
00
08
00
08
08
all
all
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
Reserved
all
4 & 8
all
4
all
5, 4, 3
all
Undefined
unbuffered DIMM
normal DIMM
incl. weak driver
5 ns
DIMM Type Information
SDRAM Module Attributes
SDRAM Device Attributes: General
Min. Clock Cycle Time at CAS Latency = 4
all
all
all
-5
-3.7
-3
3.7 ns
3 ns
24
SDRAM Access Time from Clock for CL = 4
-5
0.6 ns
-3.7
-3
0.5 ns
tbd
25
26
27
Minimum Clock Cycle Time at CL = 3
Access Time from Clock at CL = 3
Minimum Row Precharge Time (tRP)
all
5 ns
all
0.6 ns
-5 & -3.7
-3
15 ns
12 ns
28
29
Minimum Row Act. to Row Act. Delay (tRRD)
Minimum RAS to CAS Delay (tRCD)
all
10 / 7.5 ns
15 ns
28
40
1E
80
1E
3C
30
2D
80
1E
1E
-5 & -3.7
-3
12 ns
30
31
Minimum RAS Pulse Width (tRAS)
Module Density (per rank)
all
45 ns
80
80
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Byte# Description
Speed
Grade
SPD Entry
Value
Hex Value
32
33
34
Address and Command Setup Time (tIS)
-5 & -3.7
0.6 ns
tbd
60
tbd
60
tbd
40
35
tbd
40
35
tbd
3C
30
28
1E
1E
00
00
3C
39
69
-3
-5 & -3.7
-3
Address and Command Hold Time (tIH)
Data Input Setup Time (tDS)
0.6 ns
tbd
-5
0.40 ns
0.35 ns
tbd
-3.7
-3
35
Data Input Hold Time (tDH)
Write Recovery Time (tWR)
-5
0.40 ns
0.35 ns
-3.7
-3
-5 & -3.7
-3
tbd
15 ns
36
37
12 ns
Internal Write to Read Command delay
(tWTR)
-5
10 n
-3.7 & -3
all
7.5 ns
7.5 ns
Undefined
38
39
40
41
Internal Read to Precharge delay (tRTP)
Reserved
Extension of Byte 41 tRC and Byte 42 tRFC
Minimum Core Cycle Time (tRC)
all
-5 & -3.7
-3
60 ns
57 ns
42
Min. Auto Refresh Command Cycle Time
(tRFC)
all
105 ns
43
44
Maximum Clock Cycle Time tck
all
-5
8 ns
0.35 ns
0.30 ns
tbd
80
23
Max. DQS-DQ Skew (tDQSQmax.)
-3.7
-3
1E
tbd.
2D
28
45
Read Data Hold Skew Factor (tQHS)
-5
0.45 ns
0.40 ns
tbd
-3.7
-3
tbd
00
46-61 Superset Information
-
62
63
SPD Revision
Revision 1.0
10
Checksum for Bytes 0 - 62
-5
-3.7
-3
tbd
tbd
tbd
tbd
tbd
64-71 Manufacturers JEDEC ID Code
72 Module Assembly Location
–
C1000000
73-90 Module Part Number
91-92 Module Revision Code
93-94 Module Manufacturing Date
95-98 Module Serial Number
99-127 Manufacturer’s Specific Data
128-255 Open for Customer use
Year/Week Code
Serial Number
unused
blank
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7.0 Package Outlines
7.1 Raw Card A
Module Package
DDR2 Unbuffered DIMM Modules Raw Card A
one physical rank, 8 (Non-ECC) or 9 (ECC) components x8
+ 0.15
-
133.35
3.18 m ax.
Not installed on x64
(Non-ECC) Configuration
Front View
4.0
120
pin
1
64
65
+ 0.1
-
1.27
63,0
5,175
5,175
55,0
PCB warpage 0.40
5.0
Backside View
pin 121
185
240
184
3
3
D etail of C ontacts
5.0
B
D etail of C ontacts
A
0.75R
+ 0.05
-
0.8
1.0
1.5
2.5
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
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7.2 Raw Card B
Module Package
DDR2 Unbuffered DIMM Modules Raw Card B
two physical ranks, 16 (Non-ECC) or 18 (ECC) components x8
+ 0.15
-
133.35
4.00 m ax.
Front View
4.0
120
pin
1
64
65
+ 0.1
-
1.27
63,0
5,175
5,175
55,0
PCB warpage 0.40
5.0
Not installed on x64
(Non-ECC) Configuration
Backside View
pin 121
240
185
184
3
3
D etail of C ontacts
A
Detail of C ontacts
5.0
B
0.75R
+ 0.05
-
0.8
1.0
1.5
2.5
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
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Unbuffered DDR2 SDRAM-Modules
7.3 Raw Card C
Module Package
DDR2 Registered DIMM Modules Raw Card C
one physical rank, 4 components x16 (tbd.)
+ 0.15
-
133.35
3.18 m ax.
Front View
4.0
120
pin
1
64
65
+ 0.1
-
1.27
63,0
5,175
5,175
55,0
PCB warpage 0.40
5.0
Backside View
pin 121
240
185
184
3
3
D etail of Contacts
A
D etail of C ontacts
5.0
B
0.75R
+ 0.05
-
0.8
1.0
1.5
2.5
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
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8.0 Nomenclature (Modules & Components)
8.1 DDR2 DIMM Modules
1
2
3
4
5
6
7
8
9
10
11
H Y S 7 2
T
1 2 8
0
2
0
G
U
- 5
-A
Example:
1
2
INFINEON Prefix
HYS for DIMM Modules
7
8
Product Variations
Package
0 = standard
64 = Non-ECC Modules
72 = ECC Modules
G = standard modules
H = “green” modules
Module Data Width
R = Registered DIMMs
U = Unbuffered DIMMs
DL = Small Outline DIMMs)
-5 = PC2-3200 (DDR2-400)
-3.7 = PC2-4300 (DDR2-533)
-3 = PC2-5300 (DDR2-667)
A = 1st Generation
B = 2nd Generation
C = 3rd Generation
T = DDR2
DRAM Technology
Module Type
3
4
5
6
9
64 = 64 Mb
Memory Density per I/O 128 = 128 Mb
256 = 256 Mb
10 Speed Grade
11 Die Revision
Raw Card Revision
0 = first revision
Multiplying “Memory Density per I/O” with “Module Data Width”
and dividing by 8 for Non-ECC and 9 for ECC modules gives the
overall module memory density in MBytes.
Number of Memory
Ranks
0 = One Rank
2 = Two Ranks
8.2 DDR2 Memory Components
1
2
3
4
5
6
7
8
9
H Y B 1 8
T
5 1 2 8 0
0
A
- 5
C
Example:
INFINEON
1
2
HYB for DRAM Components
18 = 1.8 V Power Supply
6
7
Product Variations
Die Revision
0 = standard
Component Prefix
A = 1st Generation
B = 2nd Generation
C = 3rd Generation
C = BGA package
F = BGA package (lead and
halogen free)
-5 =...DDR2-400
-3.7 =.DDR2-533
-3 =...DDR2-667
Power Supply Voltage
DRAM Technology
Memory Density
3
4
5
T = DDR2
8
Package Type
Speed Grade
256 = 256 Mb
512 = 512 Mb
1G = 1024Mb
40 = x4, 4 data in/outputs
80 = x8, 8 data in/outputs
16 = x16, 16 data in/outputs
9
Memory Organisation
INFINEON Technologies
24
10.03
HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
INFINEON Technologies
25
10.03
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