HYS72T128020HFN-3S-A [INFINEON]
DDR DRAM Module, 64MX8, CMOS, GREEN, DIMM-240;型号: | HYS72T128020HFN-3S-A |
厂家: | Infineon |
描述: | DDR DRAM Module, 64MX8, CMOS, GREEN, DIMM-240 动态存储器 双倍数据速率 内存集成电路 |
文件: | 总78页 (文件大小:1795K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.41, Jan. 2006
Cover Page
HYS72T64000HF[A/N]–[3.7/3S]–A
HYS72T128020HF[A/N]–[3.7/3S]–A
HYS72T256020HF[A/N]–[3.7/3S]–A
240-Pin Fully-Buffered DDR2 SDRAM Modules
DDR2 SDRAM
FB-DIMM SDRAM
RoHS Compliant Products
Green Product
High-Speed Differential Point-to-Point Link
Interface at 1.5 V
Memory Products
Imprint
Edition 2006-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Revision Histrory
HYS72T64000HF[A/N]–[3.7/3S]–A, HYS72T128020HF[A/N]–[3.7/3S]–A, HYS72T256020HF[A/N]–[3.7/3S]–A
Revision History: 2006-01, Rev. 1.41
Previous Version: 1.40
Page
75
Subjects (major changes since last revision)
Add note to Figure 16 “Package Outline L-DIM-240-21” on Page 74
Add note to Figure 17 “Package Outline L-DIM-240-22” on Page 75
Add note to Figure 18 “Package Outline L-DIM-240-25” on Page 76
76
77
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Template: mp_a4_s_rev321 / 3 / 2005-10-05
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Table of Contents
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
3
4
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
FB-DIMM Input/Output Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
5.1
5.2
5.3
Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Advanced Memory Buffer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Advanced Memory Buffer Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DDR2 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Channel Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Peak Theoretical Channel Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Hot-add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Hot-remove . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Hot-replace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.5
5.6
5.7
6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
7.1
High-Speed Differential Point-to-Point Link Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Differential Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Transition Density in Transmitted Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Jitter and Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
De-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Electrical Idle (EI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
High Speed Serial Link Reference Clocks (SCK, SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Spread Spectrum Clocking (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reference Clock Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Differential Transmitter Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Differential Receiver Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Receiver Input Compliance Eye Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.3
7.4
7.5
7.6
7.6.1
8
8.1
8.1.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
Channel Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
RESET Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Inband Control ‘Signals’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Channel Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Firmware Transition Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AMB Internal State Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Disable State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Training State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Testing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Polling State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Config State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9
Channel Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.1
Southbound Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Data Sheet
4
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Table of Contents
9.1.1
9.1.2
9.1.3
9.1.3.1
9.1.3.2
9.1.4
9.1.4.1
9.1.4.2
9.1.4.3
9.1.4.4
9.1.4.5
9.1.4.6
9.1.4.7
9.1.4.8
9.1.4.9
9.2
Normal Southbound Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Fail-over Southbound Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Command Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Command Frame with Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Command+Wdata Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Southbound Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CKE Control Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Soft Channel Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Sync Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
NOP Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Command Delivery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Concurrent Command Delivery Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Command Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Northbound CRC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Northbound Idle Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Northbound Alert Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Northbound Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14-bit Lane Northbound Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13-bit Lane Fail-over Northbound Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13-bit Lane Northbound Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13-bit Lane Fail-Over Northbound Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12-bit Lane Northbound Data Frame (Non-ECC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Northbound Register Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Northbound Status Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DRAM Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Write Data FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Simultaneous Read and Write Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DRAM Bus Segment Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2.1
9.2.2
9.2.3
9.2.3.1
9.2.3.2
9.2.3.3
9.2.3.4
9.2.3.5
9.2.3.6
9.2.3.7
9.3
9.3.1
9.3.2
9.3.2.1
9.3.3
9.3.4
10
10.1
10.2
10.2.1
10.2.2
10.2.3
10.3
Reliability, Availability and Serviceability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Example Error Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Command Error Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Write Data Error Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Read Error Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Overview of Error Protection, Detection, Correction, and Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Error Protection and Detection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CRC Logic Used on Normal Southbound Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Fail-over Southbound Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Write and Read Data ECC Error Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Southbound Error Handling at the AMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Exiting Command Error State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Northbound Error Handling at the AMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Error Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Fail-over Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Fail-over Mode Operation on Southbound Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Fail-over Mode Operation on Northbound Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
AMB Pass-through Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.4
10.4.1
10.4.2
10.4.3
10.5
10.5.1
10.6
10.7
10.8
10.8.1
10.8.2
10.9
Data Sheet
5
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Table of Contents
10.10
10.11
Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Thermal Trip Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11
12
13
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
DDR2 Nomencature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Data Sheet
6
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
240-Pin Fully-Buffered DDR2 SDRAM Modules
DDR2 SDRAM
HYS72T64000HF[A/N]–[3.7/3S]–A
HYS72T128020HF[A/N]–[3.7/3S]–A
HYS72T256020HF[A/N]–[3.7/3S]–A
1
Overview
This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product
family.
1.1
Features
•
•
•
240-pin Fully-Buffered ECC Dual-In-Line
DDR2 SDRAM Module for PC, Workstation and
Server main memory applications.
Module organisation one rank 64M x 72,
one rank 128M x 72, two ranks 128M x 72,
two ranks 256M x 72
JEDEC Standard Double Data Rate 2
Synchronous DRAMs (DDR2 SDRAMs) with 1.8 V
(± 0.1 V) power supply.
Built with 512Mb DDR2 SDRAMs in 60-ball FBGA
Chipsize Packages.
Re-drive and re-sync of all address, command,
clock and data signals using AMB (Advanced
Memory Buffer).
•
•
Supports SMBus protocol interface for access to
the AMB configuration registers.
Detects errors on the channel and reports them to
the host memory controller.
Automatic DDR2 DRAM Bus Calibration.
Automatic Channel Calibration.
Full Host Control of the DDR2 DRAMs.
Over-Temperature Detection and Alert.
Hot Add-on and Hot Remove Capability.
MBIST and IBIST Test Functions.
Transparent Mode for DRAM Test Support.
Low profile: 133.35mm x 30,35mm
240 Pin gold plated card connector with 1.00mm
contact centers (JEDEC standard pending).
Based on JEDEC standard reference card designs
(Jedec standard pending).
SPD (Serial Presence Detect) with 256 Byte serial
E2PROM.Performance:
RoHS Compliant Products1)
•
•
•
•
•
•
•
•
•
•
•
•
•
High-Speed Differential Point-to-Point Link
Interface at 1.5 V (Jedec standard pending).
Host Interface and AMB component industry
standard compliant.
•
•
•
Table 1
Performance for DDR2–533 and DDR2–667
Product Type Speed Code
Speed Grade
–3S
–3.7
Unit
—
PC2–5300 5–5–5
PC2–4200 4–4–4
max. Clock Frequency
@CL5
@CL4
@CL3
fCK5
fCK4
fCK3
333
266
200
266
266
200
15
MHz
MHz
MHz
ns
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
tRCD 15
tRP
15
45
60
15
ns
tRAS
tRC
45
ns
60
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and
polybrominated biphenyl ethers.
Data Sheet
7
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Overview
1.2
Description
This document describes the electrical and mechanical including data in- and output. The AMB communicates
features of Infineon’s 240-pin, PC2-4200F, PC2-5300F with the host controller and / or the adjacent DIMMs on
ECC type, Fully Buffered Double-Data-Rate Two a system board using an Industry Standard High-
Synchronous DRAM Dual In-Line Memory Modules Speed Differential Point-to-Point Link Interface at 1.5 V.
(DDR2 SDRAM FB-DIMMs). Fully Buffered DIMMs use
commodity DRAMs isolated from the memory channel
memory traffic to support large memory capacities. All
behind a buffer on the DIMM. They are intended for use
as main memory when installed in systems such as
including memory request initiation, timing, refresh,
servers and workstations. PC2-4200, PC2-5300 refers
to the DIMM naming convention indicating the DDR2
management. The Advanced Memory Buffer interface
SDRAMs running at 266, 333 MHz clock speed and
offering 4200, 5300 MB/s peak bandwidth. FB-DIMM
requests to and from the local DIMM and for forwarding
features a novel architecture including the Advanced
Memory Buffer. This single chip component, located in
Buffered DIMM provides a high memory bandwidth,
the center of each DIMM, acts as a repeater and buffer
for all signals and commands which are exchanged
interface. The maximum memory capacity is 288 DDR2
between the host controller and the DDR2 SDRAMs
The Advanced Memory Buffer also allows buffering of
memory control for the DRAM resides in the host,
scrubbing, sparing, configuration access, and power
is responsible for handling channel and memory
requests to other DIMMs on the memory channel. Fully
large capacity channel solution that has a narrow host
SDRAM devices per channel or 8 DIMMs.
Table 2
Ordering Information (Pb-free components and assembly)
Type & Partnumber1)
Compliance Code2)
Description
SDRAM
Technology
PC2-4200F (DDR2-533):
HYS72T64000HFA–3.7–A
HYS72T64000HFN–3.7–A
HYS72T128020HFA–3.7–A
HYS72T128020HFN–3.7–A
HYS72T256020HFA–3.7–A
HYS72T256020HFN–3.7–A
PC2-5300F (DDR2-667):
HYS72T64000HFA–3S–A
HYS72T64000HFN–3S–A
HYS72T128020HFA–3S–A
HYS72T128020HFN–3S–A
HYS72T256020HFA–3S–A
HYS72T256020HFN–3S–A
PC2–4200F–444–10–A one rank 512 MB FB-DIMM
PC2–4200F–444–10–A one rank 512 MB FB-DIMM
PC2–4200F–444–10–B two ranks 1 GB FB-DIMM
PC2–4200F–444–10–B two ranks 1 GB FB-DIMM
PC2–4200F–444–10–H two ranks 2 GB FB-DIMM
PC2–4200F–444–10–H two ranks 2 GB FB-DIMM
512 Mbit (x8)
512 Mbit (x8)
512 Mbit (x8)
512 Mbit (x8)
512 Mbit (x4)
512 Mbit (x4)
PC2–4200F–444–10–A one rank 512 MB FB-DIMM
PC2–4200F–444–10–A one rank 512 MB FB-DIMM
PC2–4200F–444–10–B two ranks 1 GB FB-DIMM
PC2–4200F–444–10–B two ranks 1 GB FB-DIMM
PC2–4200F–444–10–H two ranks 2 GB FB-DIMM
PC2–4200F–444–10–H two ranks 2 GB FB-DIMM
512 Mbit (x8)
512 Mbit (x8)
512 Mbit (x8)
512 Mbit (x8)
512 Mbit (x4)
512 Mbit (x4)
1) All product types end with a place code, designating the silicon die revision. Example: HYS 72T64000HFA-3.7-A, indicating
Rev. A dice are used for DDR2 SDRAM components. To learn more on INFINEON DDR2 module and component
nomenclature see section 8 of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, e.g. “PC2-4200F-444-10-A”, where
4200F means Fully Buffered DIMM with 4.26 GB/sec Module Bandwidth and “444-10” means CAS latency = 4, trcd latency
= 4 and trp latency = 4 using JEDEC SPD Revision 1.0 and assembled on Raw Card “A”.
Data Sheet
8
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Overview
Table 3
DIMM
Density Organization
Address Format
Module
Memory
Ranks
ECC/
Non-ECC
# of
SDRAMs
# of row/bank/columns bits
Raw
Card
512 MB
1 GB
64M ×72
128M ×72
256M ×72
1
2
2
ECC
ECC
ECC
9
13/2/10
13/2/10
13/2/11
A
B
H
18
36
2 GB
Table 4
Components on Modules1)
Product Type
DRAM components2)
DRAM Density
512 Mbit
DRAM Organisation
64M ×8
HYS72T64000HF
HYS72T128020HF
HYS72T256020HF
HYB18T512800AF
HYB18T512800AF
HYB18T512400AF
512 Mbit
64M ×8
512 Mbit
128M ×4
1) For a detailed description of all functionalities of the DRAM components on these modules see the component datasheet.
2) Green Product
Data Sheet
9
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Pin Configuration
2
Pin Configuration
The pin configuration of the DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 7 and Table 6 respectively. The pin numbering is
depicted in Figure 1.
Table 5
Pin#
Pin Configuration of FB-DIMM
Name
Pin
Type
Buffer
Type
Function
Clock Signals
228
SCK
SCK
I
I
HSDL_15 System Clock Input, positive line
HSDL_15 System Clock Input, negative line
229
Control Signals
17
RESET
I
LV-CMOS AMB reset signal
Northbound
22
25
28
31
34
37
51
54
57
60
63
66
48
40
23
26
29
32
35
38
52
55
58
61
64
67
49
41
PN0
PN1
PN2
PN3
PN4
PN5
PN6
PN7
PN8
PN9
PN10
PN11
PN12
PN13
PN0
PN1
PN2
PN3
PN4
PN5
PN6
PN7
PN8
PN9
PN10
PN11
PN12
PN13
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
HSDL_15 Primary Northbound Data, positive
lines
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15 Primary Northbound Data, negative
lines
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
Data Sheet
10
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Pin Configuration
Table 5
Pin#
Pin Configuration of FB-DIMM (cont’d)
Name
Pin
Buffer
Type
Function
Type
142
145
148
151
154
157
171
174
177
180
183
186
168
160
143
146
149
152
155
158
172
175
178
181
184
187
169
161
Southbound
70
SN0
SN1
SN2
SN3
SN4
SN5
SN6
SN7
SN8
SN9
SN10
SN11
SN12
SN13
SN0
SN1
SN2
SN3
SN4
SN5
SN6
SN7
SN8
SN9
SN10
SN11
SN12
SN13
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
HSDL_15 Secondary Northbound Data,
positive lines
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15 Secondary Northbound Data,
positive lines
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15 Secondary Northbound Data,
negative lines
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
I
I
I
I
I
I
I
I
I
I
HSDL_15 Primary Southbound Data, positive
lines
73
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
76
79
82
93
96
99
102
90
Data Sheet
11
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Pin Configuration
Table 5
Pin#
Pin Configuration of FB-DIMM (cont’d)
Name
Pin
Buffer
Type
Function
Type
71
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
SS0
SS1
SS2
SS3
SS4
SS5
SS6
SS7
SS8
SS9
SS0
SS1
SS2
SS3
SS4
SS5
SS6
SS7
SS8
SS9
I
HSDL_15 Primary Southbound Data, negative
lines
74
I
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
77
I
80
I
83
I
94
I
97
I
100
I
103
I
91
I
190
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
HSDL_15 Secondary Southbound data,
positive lines
193
HSDL_15
HSDL_15
HSDL_15
HSDL_15
196
199
202
213
HSDL_15 Secondary Southbound data,
positive lines
216
HSDL_15
HSDL_15
HSDL_15
HSDL_15
219
222
210
191
HSDL_15 Secondary Southbound data,
negative lines
194
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
197
200
203
214
217
220
223
211
EEPROM
120
SCL
SDA
SA0
SA1
SA2
I
CMOS
OD
Serial Bus Clock
119
I/O
Serial Bus Data
239
I
I
I
CMOS
CMOS
CMOS
Serial Address Select Bus 2:0
240
118
Power Supplies
238
VDDSPD
VCC
PWR
PWR
–
–
EEPROM Power Supply
9,10,12,13,129,130,132,133
AMB Core Power / Channel Interface
Power
Data Sheet
12
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Pin Configuration
Table 5
Pin#
Pin Configuration of FB-DIMM (cont’d)
Name
Pin
Buffer
Type
Function
Type
15,117,135,237
VTT
PWR
–
Address/Command/Clock
Termination Power
1,2,3,5,6,7,108,109,111,112,113, VDD
115,116,121,122,123,125,126,
127,231,232,233,235,236
PWR
–
Power Supply
4,8,11,14,18,21,24,27,30,33,36,
39,42,43,46,47,50,53,56,59,62,
65,68,69,72,75,78,81,84,85,88,
89,92,95,98,101,104,107,110,
114,124,128,131,134,138,141,
144,147,150,153,156,159,162,
163,166,167,170,173,176,179,
182,185,188,189,192,195,198,
201,204,205,208,209,212,215,
218,221,224,227,230,234
VSS
GND
–
Ground Plane
Other Pins
19,20,44,45,86,87,105,106,139,
140,164,165,206,207,225,226
NC
NC
–
Not connected
Pins not connected on Infineon FB-
DIMM’s
136
16
VID0
VID1
–
–
–
–
Voltage ID
Note: These Pins must be unconnected
for DDR2-based Fully Buffered
DIMMs VID[0] is VDD value:
OPEN = 1.8 V, GND = 1.5 V;
VID[1] is VCC value: OPEN = 1.5
V, GND = 1.2 V
137
Test
AI
–
VREF
Note: Pin must be unconnected for
normal operation
Table 6
Abbreviations for Buffer Type
Description
Abbreviation
HSDL_15
LV-CMOS
CMOS
High-Speed Differential Point-to-Point Link Interface at 1.5 V
Low Voltage CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and
tristate, and allows multiple devices to share as a wire-OR.
Data Sheet
13
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Pin Configuration
Table 7
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NU
NC
Ground
Not Usable
Not Connected
Data Sheet
14
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Pin Configuration
6$$ ꢀ 0IN ꢁꢁꢂ
6$$ ꢀ 0IN ꢁꢁꢃ
6$$ ꢀ 0IN ꢁꢁꢄ
6$$ ꢀ 0IN ꢁꢁꢅ
6## ꢀ 0IN ꢁꢁꢆ
633 ꢀ 0IN ꢁꢂꢂ
6## ꢀ 0IN ꢁꢂꢃ
644 ꢀ 0IN ꢁꢂꢄ
2%3%4 ꢀ 0IN ꢁꢂꢅ
.# ꢀ 0IN ꢁꢂꢆ
0IN ꢂꢇꢂ ꢀ 6$$
0IN ꢂꢇꢇ ꢀ 6$$
6$$ ꢀ 0IN ꢁꢁꢇ
633 ꢀ 0IN ꢁꢁꢈ
6$$ ꢀ 0IN ꢁꢁꢉ
633 ꢀ 0IN ꢁꢁꢊ
6## ꢀ 0IN ꢁꢂꢁ
6## ꢀ 0IN ꢁꢂꢇ
633 ꢀ 0IN ꢁꢂꢈ
6)$ꢂ ꢀ 0IN ꢁꢂꢉ
633 ꢀ 0IN ꢁꢂꢊ
.# ꢀ 0IN ꢁꢇꢁ
0IN ꢂꢇꢃ ꢀ 6$$
ꢀ
0IN ꢂꢇꢈ 633
0IN ꢂꢇꢄ ꢀ 6$$
0IN ꢂꢇꢅ ꢀ 6$$
0IN ꢂꢇꢆ ꢀ 6##
0IN ꢂꢃꢂ ꢀ 633
0IN ꢂꢃꢃ ꢀ 6##
0IN ꢂꢃꢄ ꢀ 644
0IN ꢂꢃꢅ ꢀ 4%34
0IN ꢂꢃꢆ ꢀ .#
0IN ꢂꢇꢉ ꢀ 6$$
ꢀ
0IN ꢂꢇꢊ 633
0IN ꢂꢃꢁ ꢀ 6##
ꢀ
0IN ꢂꢃꢇ 6##
0IN ꢂꢃꢈ ꢀ 633
0IN ꢂꢃꢉ ꢀ 6)$ꢁ
0IN ꢂꢃꢊ ꢀ 633
0IN ꢂꢈꢁ ꢀ .#
ꢀ
633
6
33
0IN ꢁꢇꢂ
0IN ꢂꢈꢂ ꢀ
ꢀ
ꢀ
0IN ꢂꢈꢇ 3.ꢁ
0.ꢁ 0IN ꢁꢇꢇ
ꢀ
0.ꢁ 0IN ꢁꢇꢃ
0.ꢂ ꢀ 0IN ꢁꢇꢄ
0IN ꢂꢈꢃ ꢀ 3.ꢁ
0IN ꢂꢈꢄ ꢀ 3.ꢂ
0IN ꢂꢈꢅ ꢀ 633
0IN ꢂꢈꢆ ꢀ 3.ꢇ
0IN ꢂꢄꢂ ꢀ 3.ꢃ
0IN ꢂꢄꢃ ꢀ 633
0IN ꢂꢄꢄ ꢀ 3.ꢈ
0IN ꢂꢄꢅ ꢀ 3.ꢄ
0IN ꢂꢄꢆ ꢀ 633
0IN ꢂꢉꢂ ꢀ 3.ꢂꢃ
0IN ꢂꢉꢃ ꢀ 633
0IN ꢂꢉꢄ ꢀ .#
0IN ꢂꢉꢅ ꢀ 633
0IN ꢂꢉꢆ ꢀ 3.ꢂꢇ
0IN ꢂꢅꢂ ꢀ 3.ꢉ
0IN ꢂꢅꢃ ꢀ 633
0IN ꢂꢅꢄ ꢀ 3.ꢅ
0IN ꢂꢅꢅ ꢀ 3.ꢊ
0IN ꢂꢅꢆ ꢀ 633
0IN ꢂꢊꢂ ꢀ 3.ꢆ
0IN ꢂꢊꢃ ꢀ 3.ꢂꢁ
0IN ꢂꢊꢄ ꢀ 633
ꢀ
ꢀ
633 0IN ꢁꢇꢈ
0IN ꢂꢈꢈ 633
&
2
/
.
4
3
)
"
!
#
+
3
)
ꢀ
ꢀ
0.ꢂ 0IN ꢁꢇꢉ
0IN ꢂꢈꢉ 3.ꢂ
6
33 ꢀ 0IN ꢁꢇꢅ
ꢀ
ꢀ
0.ꢇ 0IN ꢁꢇꢊ
0IN ꢂꢈꢊ 3.ꢇ
0.ꢇ ꢀ 0IN ꢁꢇꢆ
0.ꢃ ꢀ 0IN ꢁꢃꢂ
633 ꢀ 0IN ꢁꢃꢃ
0.ꢈ ꢀ 0IN ꢁꢃꢄ
0.ꢄ ꢀ 0IN ꢁꢃꢅ
633 ꢀ 0IN ꢁꢃꢆ
0.ꢂꢃ ꢀ 0IN ꢁꢈꢂ
633 ꢀ 0IN ꢁꢈꢃ
.# ꢀ 0IN ꢁꢈꢄ
633 ꢀ 0IN ꢁꢈꢅ
0.ꢂꢇ ꢀ 0IN ꢁꢈꢆ
0.ꢉ ꢀ 0IN ꢁꢄꢂ
633 ꢀ 0IN ꢁꢄꢃ
0.ꢅ ꢀ 0IN ꢁꢄꢄ
0.ꢊ ꢀ 0IN ꢁꢄꢅ
633 ꢀ 0IN ꢁꢄꢆ
0.ꢆ ꢀ 0IN ꢁꢉꢂ
0.ꢂꢁ ꢀ 0IN ꢁꢉꢃ
633 ꢀ 0IN ꢁꢉꢄ
0.ꢂꢂ ꢀ 0IN ꢁꢉꢅ
ꢀ
ꢀ
633 0IN ꢁꢃꢁ
0IN ꢂꢄꢁ 633
ꢀ
ꢀ
0.ꢃ 0IN ꢁꢃꢇ
0IN ꢂꢄꢇ 3.ꢃ
ꢀ
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0.ꢈ 0IN ꢁꢃꢈ
0IN ꢂꢄꢈ 3.ꢈ
ꢀ
ꢀ
633 0IN ꢁꢃꢉ
0IN ꢂꢄꢉ 633
$
%
$
%
ꢀ
ꢀ
0IN ꢂꢄꢊ 3.ꢄ
ꢀ
0IN ꢂꢉꢁ 3.ꢂꢃ
0.ꢄ 0IN ꢁꢃꢊ
ꢀ
0.ꢂꢃ 0IN ꢁꢈꢁ
ꢀ
ꢀ
633 0IN ꢁꢈꢇ
0IN ꢂꢉꢇ 633
ꢀ
ꢀ
.# 0IN ꢁꢈꢈ
0IN ꢂꢉꢈ .#
ꢀ
ꢀ
633 0IN ꢁꢈꢉ
0IN ꢂꢉꢉ 633
ꢀ
ꢀ
0.ꢂꢇ 0IN ꢁꢈꢊ
0IN ꢂꢉꢊ 3.ꢂꢇ
ꢀ
ꢀ
633 0IN ꢁꢄꢁ
0IN ꢂꢅꢁ 633
ꢀ
ꢀ
0.ꢉ 0IN ꢁꢄꢇ
0IN ꢂꢅꢇ 3.ꢉ
ꢀ
ꢀ
0.ꢅ 0IN ꢁꢄꢈ
0IN ꢂꢅꢈ 3.ꢅ
ꢀ
ꢀ
0IN ꢂꢅꢉ 633
ꢀ
0IN ꢂꢅꢊ 3.ꢊ
633 0IN ꢁꢄꢉ
ꢀ
0.ꢊ 0IN ꢁꢄꢊ
ꢀ
ꢀ
0.ꢆ 0IN ꢁꢉꢁ
0IN ꢂꢊꢁ 3.ꢆ
ꢀ
ꢀ
633 0IN ꢁꢉꢇ
0IN ꢂꢊꢇ 633
ꢀ
ꢀ
0.ꢂꢁ 0IN ꢁꢉꢈ
0IN ꢂꢊꢈ 3.ꢂꢁ
ꢀ
ꢀ
0.ꢂꢂ 0IN ꢁꢉꢉ
0IN ꢂꢊꢉ 3.ꢂꢂ
0IN ꢂꢊꢅ
ꢀ 3.ꢂꢂ
ꢀ
ꢀ
633 0IN ꢁꢉꢊ
0IN ꢂꢊꢊ 633
633 ꢀ 0IN ꢁꢉꢆ
03ꢁ ꢀ 0IN ꢁꢅꢂ
03ꢂ ꢀ 0IN ꢁꢅꢃ
633 ꢀ 0IN ꢁꢅꢄ
03ꢇ ꢀ 0IN ꢁꢅꢅ
03ꢃ ꢀ 0IN ꢁꢅꢆ
0IN ꢂꢊꢆ ꢀ 633
0IN ꢂꢆꢂ
ꢀ
ꢀ
0IN ꢂꢆꢁ 33ꢁ
ꢀ
0IN ꢂꢆꢇ 633
03ꢁ 0IN ꢁꢅꢁ
ꢀ 33ꢁ
ꢀ
633 0IN ꢁꢅꢇ
0IN ꢂꢆꢃ ꢀ 33ꢂ
0IN ꢂꢆꢄ ꢀ 633
0IN ꢂꢆꢅ ꢀ 33ꢇ
0IN ꢂꢆꢆ ꢀ 33ꢃ
ꢀ
ꢀ
03ꢂ 0IN ꢁꢅꢈ
0IN ꢂꢆꢈ 33ꢂ
ꢀ
ꢀ
03ꢇ 0IN ꢁꢅꢉ
0IN ꢂꢆꢉ 33ꢇ
ꢀ
ꢀ
633 0IN ꢁꢅꢊ
0IN ꢂꢆꢊ 633
ꢀ
ꢀ
03ꢃ 0IN ꢁꢊꢁ
0IN ꢇꢁꢁ 33ꢃ
0IN ꢁꢊꢂ
0IN ꢇꢁꢂ
633
03ꢈ ꢀ 0IN ꢁꢊꢃ
0IN ꢁꢊꢄ
ꢀ
ꢀ 633
0IN ꢇꢁꢃ ꢀ 33ꢈ
0IN ꢇꢁꢄ
ꢀ
ꢀ
03ꢈ 0IN ꢁꢊꢇ
0IN ꢇꢁꢇ 33ꢈ
ꢀ
ꢀ
633 0IN ꢁꢊꢈ
0IN ꢇꢁꢈ 633
633
.# ꢀ 0IN ꢁꢊꢅ
0IN ꢁꢊꢆ
ꢀ
ꢀ 633
0IN ꢇꢁꢅ ꢀ .#
0IN ꢇꢁꢆ
ꢀ 633
ꢀ
ꢀ
.# 0IN ꢁꢊꢉ
0IN ꢇꢁꢉ .#
ꢀ
ꢀ
0IN ꢇꢁꢊ 633
ꢀ
0IN ꢇꢂꢁ 33ꢆ
633 0IN ꢁꢊꢊ
633
ꢀ
ꢀ
03ꢆ 0IN ꢁꢆꢁ
03ꢆ ꢀ 0IN ꢁꢆꢂ
03ꢄ ꢀ 0IN ꢁꢆꢃ
633 ꢀ 0IN ꢁꢆꢄ
03ꢉ ꢀ 0IN ꢁꢆꢅ
0IN ꢇꢂꢂ ꢀ 33ꢆ
0IN ꢇꢂꢃ ꢀ 33ꢄ
0IN ꢇꢂꢄ ꢀ 633
0IN ꢇꢂꢅ ꢀ 33ꢉ
ꢀ
ꢀ
633 0IN ꢁꢆꢇ
0IN ꢇꢂꢇ 633
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03ꢄ 0IN ꢁꢆꢈ
0IN ꢇꢂꢈ 33ꢄ
ꢀ
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03ꢉ 0IN ꢁꢆꢉ
0IN ꢇꢂꢉ 33ꢉ
ꢀ
ꢀ
633 0IN ꢁꢆꢊ
0IN ꢇꢂꢊ 633
0IN ꢁꢆꢆ
0IN ꢇꢂꢆ
03ꢅ ꢀ
633 ꢀ 0IN ꢂꢁꢂ
0IN ꢂꢁꢃ
ꢀ 33ꢅ
0IN ꢇꢇꢂ ꢀ 633
0IN ꢇꢇꢃ
ꢀ
ꢀ
03ꢅ 0IN ꢂꢁꢁ
0IN ꢇꢇꢁ 33ꢅ
ꢀ
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03ꢊ 0IN ꢂꢁꢇ
0IN ꢇꢇꢇ 33ꢊ
03ꢊ ꢀ
.# ꢀ 0IN ꢂꢁꢄ
0IN ꢂꢁꢅ
ꢀ 33ꢊ
0IN ꢇꢇꢄ ꢀ .#
0IN ꢇꢇꢅ
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ꢀ
633 0IN ꢂꢁꢈ
0IN ꢇꢇꢈ 633
ꢀ
ꢀ
0IN ꢇꢇꢉ .#
ꢀ
0IN ꢇꢇꢊ 3#+
.# 0IN ꢂꢁꢉ
633
ꢀ
ꢀ 633
ꢀ
6$$ 0IN ꢂꢁꢊ
6$$ ꢀ 0IN ꢂꢁꢆ
6$$ ꢀ 0IN ꢂꢂꢂ
6$$ ꢀ 0IN ꢂꢂꢃ
6$$ ꢀ 0IN ꢂꢂꢄ
0IN ꢇꢇꢆ ꢀ 3#+
0IN ꢇꢃꢂ ꢀ 6$$
0IN ꢇꢃꢃ ꢀ 6$$
0IN ꢇꢃꢄ ꢀ 6$$
ꢀ
ꢀ
633 0IN ꢂꢂꢁ
0IN ꢇꢃꢁ 633
ꢀ
ꢀ
6$$ 0IN ꢂꢂꢇ
0IN ꢇꢃꢇ 6$$
ꢀ
ꢀ
633 0IN ꢂꢂꢈ
0IN ꢇꢃꢈ 633
ꢀ
ꢀ
6$$ 0IN ꢂꢂꢉ
0IN ꢇꢃꢉ 6$$
0IN ꢂꢂꢅ
0IN ꢇꢃꢅ
644
ꢀ
644
ꢀ
3!ꢇ 0IN ꢂꢂꢊ
0IN ꢇꢃꢊ 6$$30$
0IN ꢇꢈꢁ 3!ꢂ
3$! ꢀ 0IN ꢂꢂꢆ
0IN ꢇꢃꢆ 3!ꢁ
-004ꢁꢂꢆꢁ
ꢀ
3#, 0IN ꢂꢇꢁ
Figure 1
Pin Configuration for FB-DIMM (240 pin)
Data Sheet
15
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
FB-DIMM Input/Output Functional Description
3
FB-DIMM Input/Output Functional Description
Table 8
FB-DIMM Input/Output Functional Description
Type Polarity Function
Symbol
Channel Signals
SCK, SCK
Input
Differential System Clock Input
PN[13:0], PN[13:0] Output Differential Primary Northbound Data
PS[9:0], PS[9:0]
Input
Differential Primary Southbound Data
Differential Secondary Northbound Data
SN[13:0], SN[13:0] Input
SS[9:0], SS[9:0]
SMB Bus Signals
SA[2:0]
Output Differential Secondary Southbound Data
Input
I/O
—
—
SPD Address, also used to select the DIMM number in the AMB
SDA
SPD Data. A resistor must be connected from the SDA bus line to
VDDSPD on the system planar to act as a pull-up.
SCL
Input
—
SPD Clock
Miscellaneous Signals
RESET
VID[1:0]
TEST
Input
Input
Active Low AMB Reset Signal
Voltage ID. Both pins shall be NC in case of VDD = 1.8 V, VCC = 1.5 V
—
Analog + 0.9 V
DRAM VREF Margin Test. Do not connect on the system planar.
Power / Ground
VDD
Supply + 1.8 V
Supply + 1.5 V
Supply + 3.3 V
DDR2 DRAM Power
AMB Core Power
SPD Power
VCC
VDDSPD
Data Sheet
16
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Block Diagrams
4
Block Diagrams
3ꢀ
$ꢈ
$ꢀ
#3
$ꢆ
$ꢇ
$ꢄ
$ꢅ
#3
#3
$13ꢈ
$13ꢈ
$13
$13
$13ꢀ
$13ꢀ
$13ꢂ
$13
$13ꢆ
$13ꢆ
$13
$13
$13
$13ꢃꢅ
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
$13ꢃꢉ
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
#"ꢀ
#"ꢃ
#"ꢁ
#"ꢉ
#"ꢆ
#"ꢇ
#"ꢄ
#"ꢅ
$1ꢀ
$1ꢃ
$1ꢁ
$1ꢉ
$1ꢆ
$1ꢇ
$1ꢄ
$1ꢅ
$1ꢉꢁ
$1ꢉꢉ
$1ꢉꢆ
$1ꢉꢇ
$1ꢉꢄ
$1ꢉꢅ
$1ꢉꢈ
$1ꢉꢂ
)ꢊ/ ꢃ
)ꢊ/ ꢃ
)ꢊ/ ꢃ
)ꢊ/ ꢁ
)ꢊ/ ꢁ
)ꢊ/ ꢁ
)ꢊ/ ꢉ
)ꢊ/ ꢉ
)ꢊ/ ꢉ
)ꢊ/ ꢆ
)ꢊ/ ꢆ
)ꢊ/ ꢆ
)ꢊ/ ꢇ
)ꢊ/ ꢇ
)ꢊ/ ꢇ
)ꢊ/ ꢄ
)ꢊ/ ꢄ
)ꢊ/ ꢄ
)ꢊ/ ꢅ
)ꢊ/ ꢅ
)ꢊ/ ꢅ
$ꢃ
$ꢁ
$ꢉ
%ꢀ
#3
$13
#3
$13
3#,
3$!
!ꢀ
3#,
3$!
3!ꢀ
3!ꢃ
3!ꢁ
633
$13ꢃ
$13ꢃ
$13ꢃꢀ
$13ꢇ
$13ꢇ
$13ꢃꢆ
$13
$13
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
!ꢃ
!ꢁ
$1ꢈ
$1ꢂ
$1ꢆꢀ
$1ꢆꢃ
$1ꢆꢁ
$1ꢆꢉ
$1ꢆꢆ
$1ꢆꢇ
$1ꢆꢄ
$1ꢆꢅ
70
)ꢊ/ ꢃ
)ꢊ/ ꢃ
$1ꢃꢀ
$1ꢃꢃ
$1ꢃꢁ
$1ꢃꢉ
$1ꢃꢆ
$1ꢃꢇ
)ꢊ/ ꢁ
)ꢊ/ ꢁ
)ꢊ/ ꢉ
)ꢊ/ ꢉ
644
6##
4ERMINATORS
)ꢊ/ ꢆ
)ꢊ/ ꢆ
)ꢊ/ ꢇ
)ꢊ/ ꢇ
!-"
)ꢊ/ ꢄ
)ꢊ/ ꢄ
6$$ꢍ30$
6$$ꢊ6$$1
62%&
6$$ꢌ 30$ꢍ !-"
)ꢊ/ ꢅ
)ꢊ/ ꢅ
6$$ꢊ6$$1ꢌ 3$2!-S $ꢀ ꢋ $ꢈꢍ!-"
62%&ꢌ 3$2!-S $ꢀ ꢋ $ꢈ
633ꢌ 3$2!-S $ꢀ ꢋ $ꢈ
#3
$13
#3
$13
$13ꢄ
$13ꢄ
$13ꢃꢇ
$13ꢁ
$13ꢁ
$13ꢃꢃ
$13
$13
633
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
$1ꢆꢈ
$1ꢆꢂ
$1ꢇꢀ
$1ꢇꢃ
$1ꢇꢁ
$1ꢇꢉ
$1ꢇꢆ
$1ꢇꢇ
$1ꢃꢄ
$1ꢃꢅ
$1ꢃꢈ
$1ꢃꢂ
$1ꢁꢀ
$1ꢁꢃ
$1ꢁꢁ
$1ꢁꢉ
)ꢊ/ ꢃ
)ꢊ/ ꢃ
)ꢊ/ ꢁ
)ꢊ/ ꢁ
)ꢊ/ ꢉ
)ꢊ/ ꢉ
0.ꢀꢋ0.ꢃꢉ
0.ꢀꢋ0.ꢃꢉ
03ꢀꢋ03ꢂ
03ꢀꢋ03ꢂ
3.ꢀꢋ3.ꢃꢉ
3.ꢀꢋ3.ꢃꢉ
33ꢀꢋ33ꢂ
33ꢀꢋ33ꢂ
!-"
)ꢊ/ ꢆ
)ꢊ/ ꢆ
)ꢊ/ ꢇ
)ꢊ/ ꢇ
)ꢊ/ ꢄ
)ꢊ/ ꢄ
)ꢊ/ ꢅ
)ꢊ/ ꢅ
$1ꢀꢋ$1ꢄꢉ
#"ꢀꢋ#"ꢅ
$13ꢀꢋ$13ꢃꢅ
$13ꢀꢋ$13ꢈ
3ꢀ
#3ꢌ 3$2!-S $ꢀꢋ$ꢈ
#+%ꢌ 3$2!-S $ꢀꢋ$ꢈ
#+%ꢀ
#3
$13
#3
$13
$13ꢉ
$13ꢉ
$13ꢃꢁ
$13ꢅ
$13ꢅ
$13ꢃꢄ
$13
$13
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
3#,
3$!
3!ꢀꢋ3!ꢁ
/$4
/$4ꢌ 3$2!-S $ꢀꢋ$ꢈ
"!ꢀꢋ"!Nꢌ 3$2!-S $ꢀꢋ$ꢈ
!ꢀꢋ!Nꢌ 3$2!-S $ꢀꢋ$ꢈ
2!3ꢌ 3$2!-S $ꢀꢋ$ꢈ
#!3ꢌ 3$2!-S $ꢀꢋ$ꢈ
7%ꢌ 3$2!-S $ꢀꢋ$ꢈ
#+ꢊ#+ꢌ 3$2!- $ꢀꢋ$ꢈ
"!ꢀꢋ"!ꢁ
!ꢀꢋ!N
2!3
$1ꢁꢆ
$1ꢁꢇ
$1ꢁꢄ
$1ꢁꢅ
$1ꢁꢈ
$1ꢁꢂ
$1ꢉꢀ
$1ꢉꢃ
$1ꢇꢄ
$1ꢇꢅ
$1ꢇꢈ
$1ꢇꢂ
$1ꢄꢀ
$1ꢄꢃ
$1ꢄꢁ
$1ꢄꢉ
)ꢊ/ ꢃ
)ꢊ/ ꢃ
)ꢊ/ ꢁ
)ꢊ/ ꢁ
2%3%4
#!3
)ꢊ/ ꢉ
)ꢊ/ ꢉ
7%
)ꢊ/ ꢆ
)ꢊ/ ꢆ
3#+ꢊ3#+
#+ꢊ#+
)ꢊ/ ꢇ
)ꢊ/ ꢇ
)ꢊ/ ꢄ
)ꢊ/ ꢄ
)ꢊ/ ꢅ
)ꢊ/ ꢅ
-0"4ꢀꢁꢂꢀ
Figure 2
Block Diagram Raw Card A FB-DIMM ECC (x72, 1Rank, x8)
Notes
2. There are two physical copies of each address,
command, control, clock
3. All address, command, control, clock have
termination resitors to VTT
1. DQ to I/O wiring may be changed within a byte
Data Sheet
17
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Block Diagrams
644
6##
4ERMINATORS
!-"
6$$ꢊ6$$1
62%&
6$$ꢊ6$$1ꢌ 3$2!-S $ꢀ ꢋ $ꢂꢇꢍ!-"
62%&ꢌ 3$2!-S $ꢀ ꢋ $ꢂꢇ
6$$ꢍ30$
633
6$$ꢌ 30$ꢍ !-"
633ꢌ 3$2!-S $ꢀ ꢋ $ꢂꢇ
633
633ꢌ 3$2!-S $ꢀ ꢋ $ꢂꢇ
0.ꢀꢋ0.ꢂꢁ
0.ꢀꢋ0.ꢂꢁ
03ꢀꢋ03ꢉ
03ꢀꢋ03ꢉ
$1ꢀꢋ$1ꢆꢁ
#"ꢀꢋ#"ꢇ
$13ꢀꢋ$13ꢂꢇ
$13ꢀꢋ$13ꢈ
3#,
3.ꢀꢋ3.ꢂꢁ
3ꢀ
3ꢂ
!-"
3.ꢀꢋ3.ꢂꢁ
33ꢀꢋ33ꢉ
33ꢀꢋ33ꢉ
3ꢀ
$ꢀ
$ꢂ
$ꢃ
$ꢁ
$ꢄ
$ꢉ
#3
#3
#3ꢌ 3$2!-S $ꢀꢋ$ꢈ
$13ꢀ
$13ꢀ
$13ꢉ
$13
$13
$13
$13
#+%ꢀ
3ꢂ
#+%ꢌ 3$2!-S $ꢀꢋ$ꢈ
#3ꢌ 3$2!-S $ꢉꢋ$ꢂꢇ
#+%ꢌ 3$2!-S $ꢉꢋ$ꢂꢇ
/$4ꢌ 3$2!-S $ꢀꢋ$ꢂꢇ
"!ꢀꢋ"!Nꢌ 3$2!-S $ꢀꢋ$ꢂꢇ
!ꢀꢋ!Nꢌ 3$2!-S $ꢀꢋ$ꢂꢇ
2!3ꢌ 3$2!-S $ꢀꢋ$ꢂꢇ
#!3ꢌ 3$2!-S $ꢀꢋ$ꢂꢇ
7%ꢌ 3$2!-S $ꢀꢋ$ꢂꢇ
#+ꢊ#+ꢌ 3$2!- $ꢀꢋ$ꢂꢇ
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
#+%ꢂ
/$4
$1ꢀ
$1ꢂ
$1ꢃ
$1ꢁ
$1ꢄ
$1ꢅ
$1ꢆ
$1ꢇ
3$!
3!ꢀꢋ3!ꢃ
"!ꢀꢋ"!ꢃ
!ꢀꢋ!N
2!3
)ꢊ/ ꢂ
)ꢊ/ ꢂ
)ꢊ/ ꢃ
)ꢊ/ ꢃ
)ꢊ/ ꢁ
)ꢊ/ ꢁ
2%3%4
#!3
)ꢊ/ ꢄ
)ꢊ/ ꢄ
7%
)ꢊ/ ꢅ
)ꢊ/ ꢅ
3#+ꢊ3#+
#+ꢊ#+
)ꢊ/ ꢆ
)ꢊ/ ꢆ
)ꢊ/ ꢇ
)ꢊ/ ꢇ
$ꢂꢀ
#3
$ꢅ
$ꢆ
$ꢇ
$ꢈ
$ꢂꢄ
$ꢂꢅ
$ꢂꢆ
$ꢂꢇ
#3
$13
#3
#3
$13ꢂ
$13ꢂ
$13ꢂꢀ
$13
$13
$13ꢅ
$13ꢅ
$13ꢂꢄ
$13
$13
$13
$13
$13
%ꢀ
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
$-ꢊ2$13
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
$-ꢊ2$13
.5ꢊ2$13
)ꢊ/ ꢀ
3#,
3$!
!ꢀ
3#,
.5ꢊ2$13
3$!
$1ꢈ
$1ꢉ
)ꢊ/ ꢀ
3!ꢀ
$1ꢄꢀ
$1ꢄꢂ
$1ꢄꢃ
$1ꢄꢁ
$1ꢄꢄ
$1ꢄꢅ
$1ꢄꢆ
$1ꢄꢇ
)ꢊ/ ꢂ
)ꢊ/ ꢂ
3!ꢂ
)ꢊ/ ꢂ
)ꢊ/ ꢂ
!ꢂ
$1ꢂꢀ
$1ꢂꢂ
$1ꢂꢃ
$1ꢂꢁ
$1ꢂꢄ
$1ꢂꢅ
)ꢊ/ ꢃ
)ꢊ/ ꢃ
3!ꢃ
)ꢊ/ ꢃ
)ꢊ/ ꢃ
!ꢃ
70
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-0"4ꢀꢁꢀꢀ
Figure 3
Block Diagram Raw Card B FB-DIMM ECC (x72, 2Ranks, x8)
Notes
2. There are two physical copies of each address,
command, control and clock
3. All address, command, control, clock have
termination resitors to VTT
1. DQ to I/O wiring may be changed within a byte
Data Sheet
18
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Block Diagrams
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Figure 4
Block Diagram Raw Card H FB-DIMM ECC (×72, 2Ranks, ×4)
Notes
2. Two physical copies of each address, command,
control and four physical copies of each clock
3. All address, command, control, clock have
termination resitors to VTT
1. DQ to I/O wiring may be changed within a nibble
Data Sheet
19
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Basic Functionality
5
Basic Functionality
5.1
Advanced Memory Buffer Overview
The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol
Specification.The AMB block diagram is depicted in Figure 5.
5.2
Advanced Memory Buffer Functionality
The Advanced Memory Buffer will perform the following
FB-DIMM channel functions:
•
•
•
•
•
•
•
•
Detects errors on the channel and reports them to
the host memory controller.
Support the FB-DIMM configuration register set as
defined in the register chapters.
Acts as DRAM memory buffer for all read, write, and
configuration accesses addressed to the DIMM.
Provides a read buffer FIFO and a write buffer
FIFO.
Supports an SMBus protocol interface for access to
the AMB configuration registers.
Provides logic to support MEMBIST and IBIST
Design for Test functions.
Provides a register interface for the thermal sensor
and status indicator.
Functions as a repeater to extend the maximum
length of FB-DIMM Links.
•
•
•
Supports channel initialization procedures as
defined in the initialization chapter of the FB-DIMM
Architecture and Protocol Specification to align the
clocks and the frame boundaries, verify channel
connectivity, and identify AMB DIMM position.
Supports the forwarding of southbound and
northbound frames, servicing requests directed to a
specific AMB or DIMM, as defined in the protocol
chapter, and merging the return data into the
northbound frames.
If the AMB resides on the last DIMM in the channel,
the AMB initializes northbound frames.
Transparent Mode for DRAM Test Support
In this mode, the Advanced Memory Buffer will provide
lower speed tester access to DRAM pins through the
FB-DIMM I/O pins. This allows the tester to send an
arbitrary test pattern to the DRAMs. Transparent mode
only supports a maximum DRAM frequency equivalent
to DDR2 400. Transparent mode functionality:
•
•
•
Reconfigures FB-DIMM inputs from differential high
speed link receivers to two single ended lower
speed receivers (~200 MHz)
These inputs directly control DDR2
Command/Address and input data that is replicated
to all DRAMs
Uses low speed direct drive FB-DIMM outputs to
bypass high speed Parallel/Serial circuitry and
provide test results back to tester
DDR2 SDRAM Interface
•
•
Supports DDR2 at speeds of 533, 667MT/s
Supports 256Mb, 512Mb and 1Gb devices in x4 and
x8 configurations
•
72-bit DDR2 SDRAM memory array
Data Sheet
20
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Basic Functionality
3OUTHBOUND
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-0"4ꢀꢁꢁꢀ
Figure 5
Block Diagram Advanced Memory Buffer FB–DIMM ECC
Note:Figure is a conceptual Block Diagram of the Advanced Memory Bufferis data flow and clock domains.
Data Sheet
21
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Basic Functionality
5.3
Interfaces
Figure 6 illustrates the Advanced Memory Buffer and host memory controller or an adjacent FB-DIMM. The
all of its interfaces. They consist of two FB-DIMM links, DDR2 channel supports direct connection to the DDR2
one DDR2 channel and an SMBus interface. Each FB- SDRAMs on a Fully Buffered DIMM.
DIMM link connects the Advanced Memory Buffer to a
-EMORY )NTERFACE
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Figure 6
Block Diagram Advanced Memory Buffer Interface
Interface Topology
The FB-DIMM channel uses a daisy-chain topology to drives the data to the next DIMM until the last DIMM
provide expansion from a single DIMM per channel to receives the data. The last DIMM in the chain initiates
up to 8 DIMMs per channel. The host sends data on the the transmission of data in the direction of the host
southbound link to the first DIMM where it is received (a.k.a. northbound). On the northbound data path each
and redriven to the second DIMM. On the southbound DIMM receives the data and re-drives the data to the
data path each DIMM receives the data and again re- next DIMM until the host is reached.
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Figure 7
Block Diagram FB–DIMM Channel Soutbound and Northbound Paths
Data Sheet
22
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Basic Functionality
5.4
High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces
The Advanced Memory Buffer supports one FB-DIMM multiplexes in any read return data or status
Channel consisting of two bidirectional link interfaces information that is generated internally. Data and
using highspeed differential point-to-point electrical commands sent to the DRAMs travel southbound on 10
signaling. The southbound input link is 10 lanes wide primary differential signal line pairs. Data received from
and carries commands and write data from the host the DRAMs and status information travel northbound
memory controller or the adjacent DIMM in the host on 14 primary differential pairs. Data and commands
direction. The southbound output link forwards this sent to the adjacent DIMM upstream are repeated and
same data to the next FB-DIMM. The northbound input travel further southbound on 10 secondary differential
link is 14 lanes wide and carries read return data or pairs. Data and status information received from the
status information from the next FB-DIMM in the chain adjacent DIMM upstream travel further northbound on
back towards the host. The northbound output link 14 secondary differential pairs.
forwards this information back towards the host and
5.4.1
DDR2 Channel
The DDR2 channel on the Advanced Memory Buffer delays between read data/check-bit strobe lanes on a
supports direct connection to DDR2 SDRAMs. The given channel can differ. Each strobe can be calibrated
DDR2 channel supports two ranks of eight banks with by hardware state machines using write/read trial and
16 row/column request, 64 data, and eight check-bit error. Hardware aligns the read data and check-bits to
signals. There are two copies of address and command a single core clock. The Advanced Memory Buffer
signals to support DIMM routing and electrical provides four copies of the command clock phase
requirements. Four transfer bursts are driven on the references (CLK[3:0]) and write data/check-bit strobes
data and check-bit lines at 800 MHz. Propagation (DQSs) for each DRAM nibble.
5.4.2
SMBus Slave Interface
The Advanced Memory Buffer supports an SMBus Memory Buffer may be a requirement to boot and to set
interface to allow system access to configuration link strength, frequency and other parameters needed
registers independent of the FB-DIMM link. The to insure robust configurations. It is also required for
Advanced Memory Buffer will never be a master on the diagnostic support when the link is down. The SMBus
SMBus, only a slave. Serial SMBus data transfer is address straps located on the DIMM connector are
supported at 100 kHz. SMBus access to the Advanced used by the unique ID.
5.4.3
Channel Latency
FB-DIMM channel latency is measured from the time a based on the point-to-point interconnection of buffer
read request is driven on the FB-DIMM channel pins to components between DIMMs, memory requests are
the time when the first 16 bytes (2nd chunk) of read required to travel through N-1 buffers before reaching
completion data is sampled by the memory controller. the Nth buffer. The result is that a 4 DIMM channel
When not using the Variable Read Latency capability, configuration will have greater idle read latency
the latency for a specific DIMM on a channel is always compared to a 1 DIMM channel configuration. The
equal to the latency for any other DIMM on that Variable Read Latency capability can be used to
channel. However, the latency for each DIMM in a reduce latency for DIMMs closer to the host. The idle
specific configuration with some number of DIMMs latencies listed in this section are representative of
installed may not be equal to the latency for each FB- what might be achieved in typical AMB designs. Actual
DIMM in a configuration with some different number of implementations with latencies less than the values
DIMMs installed. As more DIMMs are added to the listed will have higher application performance and vice
channel, additional latency is required to read from versa.
each DIMM on the channel. Because the channel is
Data Sheet
23
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Basic Functionality
5.4.4
Peak Theoretical Channel Throughput
An FB-DIMM channel transfers read completion data command clock. A DRAM burst of 8 transfers from a
on the Northbound data connection. 144 bits of data single channel, or a burst of 4 from two lock-step
are transferred for every Northbound data frame. This channels provides a total of 72 bytes of data (64 bytes
matches the 18-byte data transfer of an ECC DDR plus 8 bytes ECC). When the frame rate matches the
DRAM in a single DRAM command clock. A DRAM DRAM command clock, the Southbound command and
burst of 8 from a single channel or a DRAM burst of four data connection will exhibit one half the peak
from two lockstepped channels provides a total of 72 theoretical throughput of a single DRAM channel. For
bytes of data (64 bytes plus 8 bytes ECC). The FB- example, when using DDR2 533 DRAMs, the peak
DIMM frame rate matches the DRAM command clock theoretical bandwidth of the Southbound command and
because of the fixed 6:1 ratio of the FB-DIMM channel data connection is 2.133 GB/sec. The total peak
clock to the DRAM command clock. Therefore, the theoretical throughput for a single FB-DIMM channel is
Northbound data connection will exhibit the same peak defined as the sum of the peak theoretical throughput
theoretical throughput as a single DRAM channel. For of the Northbound data connection and the
example, when using DDR2 533 DRAMs, the peak Southbound command and data connection. When the
theoretical bandwidth of the Northbound data frame rate matches the DRAM command clock, this is
connection is 4.267 GB/sec. Write data is transferred equal to 1.5 times the peak theoretical throughput of a
on the Southbound command and data connection, via single DRAM channel. For example, when using DDR2
Command+Wdata frames. 72 bits of data are 533 DRAMs, the peak theoretical throughput of a single
transferred for every Command+Wdata frame. Two DDR2-533 channel would be 4.267 GB/sec, while the
Command+Wdata frames match the 18-byte data peak theoretical throughput of the entire FB-DIMM
transfer of an ECC DDR DRAM in a single DRAM PC4200F channel would be 6.4GB/sec.
5.5
Hot-add
The FB-DIMM channel does not provide a mechanism controller to initialize the newly added DIMM(s) and
to automatically detect and report the addition of a new perform a Hot-Add Reset to bring them into the channel
DIMM south of the currently active last DIMM. It is timing domain. It should be noted that the power to the
assumed the system will be notified through some DIMM socket must be removed before a “hot-add”
means of the addition of one or more new DIMMs so DIMM is inserted or removed. Applying or removing the
that specific commands can be sent to the host power to a DIMM socket is a system platform function.
5.6
Hot-remove
In order to accomplish removal of DIMMs the host must appropriate outputs are disabled the system can
perform a Fast Reset sequence targeted at the last coordinate the procedure to remove power in
DIMM that will be retained on the channel. The Fast preparation for physical removal of the DIMM if needed.
Reset re-establish the appropriate last DIMM so that It should be noted that the power to the DIMM socket
the Southbound Tx outputs of the last active DIMM and must be removed before a “hot-add” DIMM is inserted
the Southbound and Northbound outputs of the DIMMs or removed. Applying or removing the power to a DIMM
beyond the last active DIMM are disabled. Once the socket is a system platform function.
5.7
Hot-replace
Hot replace of DIMM is accomplished through combining the Hot-Remove and Hot-Add process.
Data Sheet
24
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Electrical Characteristics
6
Electrical Characteristics
6.1
Operating Conditions
Table 9
Symbol
Absolute Maximum Ratings
Parameter
Values
Min.
–0.3
–0,3
–0.5
–0.5
–55
Unit Note
Max.
1.75
1.75
2.3
1)
VIN, VOUT Voltage on any pin relative to VSS
V
1)
VCC
VDD
VTT
Voltage on VCC pin relative to VSS
Voltage on VDD pin relative to VSS
Voltage on VTT pin relative to VSS
Storage Temperature
V
1)
V
1)
2.3
V
1)
TSTG
+100
°C
1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Table 10
Symbol
Operating Temperature Range
Parameter
Values
Unit
Note
Min.
Max.
+95
1)2)3)4)
1)
TCASE
TCASE
DRAM Component Case Temperature Range
AMB Component Case Temperature Range
0
0
°C
°C
+110
1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2) Within the DRAM Component Case Temperature range all DRAM specification will be supported.
3) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below
85C case temperature before initiating self-refresh operation.
4) Above 85C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
Table 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Limit Values
Unit
Notes
Min.
1.455
1.7
Nom.
1.5
Max.
1.575
1.9
AMB Supply Voltage
VCC
V
V
V
V
V
V
V
V
–
–
–
DRAM Supply Voltage
Termination Voltage
VDD
1.8
VTT
0.48 ×VDD
3.0
0.50 ×VDD
3.3
0.52 ×VDD
3.6
EEPROM Supply Voltage
DC Input Logic High(SPD)
DC Input Logic Low(SPD)
VDDSPD
VIH(DC)
VIL(DC)
–
1)
2.1
—
VDDSPD
0.8
1)
2)
1)
—
—
DC Input Logic High(RESET) VIH(DC)
1.0
—
—
DC Input Logic Low(RESET)
VIL(DC)
—
—
+0.5
Data Sheet
25
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Electrical Characteristics
Table 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Limit Values
Unit
Notes
Min.
–90
–5
Nom.
—
Max.
+90
+5
2)
3)
Leakage Current (RESET)
Leakage Current (Link)
IL
IL
µΑ
µΑ
—
1) applies for SMB and SPD Bus Signals
2) applies for AMB CMOS Signal RESET
3) for all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications
Table 12
Timing Parameters
Parameter
Symbol
EI Propagatet
tEID
tEI
Min.
—
Typ.
—
Max.
4
Units Notes
EI Assertion Pass-Thru Timing
EI Deassertion Pass-Thru Timing
EI Assertion Duration
t
clks
clks
clks
ns
—
—
—
Bitlock
—
2
1)2)
100
—
—
3)
FBD Cmd to DDR Clk out that latches Cmd —
8.1
—
FBD Cmd to DDR Write
DDR Read to FBD (last DIMM)
Resample Pass-Thru time
ResynchPass-Thru time
Bit Lock Interval
—
—
TBD
5.0
—
ns
4)
—
—
—
ns
—
—
1.075
2.075
—
—
ns
—
—
—
ns
1)
1)
tBitLock
tFrameLock
—
119
154
frames
frames
Frame Lock Interval
—
—
1) Defined in FB-DIMM Architecture and Protocol Spec
2) Clocks defined as core clocks = 2x SCK input
3) @ DDR2-667 - measured from beginning of frame at southbound input to DDR clock output that latches the first command
of a frame to the DRAMs
4) @ DDR2-667 - measured from latest DQS input to AMB to start of matching data frame at northbound FB-DIMM outputs
Table 13
Environmental Parameters
Parameter
Symbol
TOPR
Rating
Units
Notes
1)
Operating Temperature
See Note
10 to 90
-50 to +100
5 to 95
2)
2)
2)
2)
2)
Operating Humidity (relative)
Storage Temperature
HOPR
TSTG
%
°C
%
m
m
Storage Humidity (without condensation)
Barometric pressure (operating)
Barometric pressure (storage)
HSTG
PBAR
3050
PBAR
14240
1) The designer must meet the case temperature specifications for individual module components.
2) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and the device
funcional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Data Sheet
26
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
High-Speed Differential Point-to-Point Link Interface
7
High-Speed Differential Point-to-Point Link Interface
The following specifications define the High-Speed them into a serialized bit-stream. This FB-DIMM link is
Differential Point-to-Point Signaling Link for FB- being specified to operate from 3.2 to 4.8 Gb/s. The
DIMMD, operating at the AMB supply voltage of 1.5 V specifications are defined for three distinct bit-rates of
that is provided at the DIMM connector. The link operation: 3.2 Gb/s (PC2-4200F), 4.0 Gb/s (PC2-
consists of a transmitter and a receiver and the 5300F) and 4.8 Gb/s (PC2-6400F). The link utilizes a
interconnect in between them. The transmitter sends derived clock approach and transmitter de-emphasis to
serialized bits into a lane and the receiver accepts the compensate for channel loss characteristics.
electrical signals of the serialized bits and transforms
7.1
Differential Signaling
A Differential Signal is defined by taking the voltage (VDIFF = VD+ - VD-). The Common Mode Voltage
difference between two conductors. In this (VCM) is defined as the average or mean voltage
specification, a differential signal or differential pair is present on the same differential pair (VCM = [VD++
comprised of a voltage on a positive conductor, VD+, VD-]/2). This documentís electrical specifications often
and a negative conductor, VD-. The differential voltage refer to peak-to-peak measurements or peak
(VDIFF) is defined as the difference of the positive measurements, which are defined by the following 5
conductor voltage and the negative conductor voltage equations:
1. VDIFFp-p = (2*max|VD+ - VD-|) (This applies to a symmetric differential swing)
2. VDIFFp-p = (max|VD+ - VD-| {VD+ > VD-} + max|VD+ - VD-| {VD+ < VD-}) (This applies to an asymmetric
differential swing.)
3. VDIFFp = (max|VD+ - VD-|) (This applies to a symmetric differential swing)
4. VDIFFp = (max|VD+ - VD-| {VD+ > VD-}) or (max|VD+ - VD-| {VD+ < VD-}) which ever is greater (This applies to
an asymmetric differential swing.)
5. VCMp = (max|VD+ + VD-|/2)
Note: The maximum value is calculated on a per unit kHz. AC is defined as all frequency components at or
interval evaluation. The maximum function as above Fdc = 30 kHz. These definitions pertain to all
described is implicit for all peak-to-peak and peak voltage and current specifications. An example
equations throughout the rest of this chapter, and thus waveform is shown in Figure 1-2. In this waveform the
a max function will not appear in any following differential peak-peak signal is approximately 0.6 V, the
representations of these equations. In this section, DC differential peak signal is approximately 0.3 V and the
is defined as all frequency components below Fdc = 30 common mode is approximately 0.25 V.
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Figure 8
Sample Differental Signal FB-DIMMUnit Interval (UI)
27
Data Sheet
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
High-Speed Differential Point-to-Point Link Interface
Average time interval between voltage transitions of a intentional frequency modulation of the source clock
signal. This is the same as the period of the FB-DIMM negligible. The UI will be different depending on the
link bit-rate clock. Given a <...1010...> between voltage data rate of operation. UI=312.5ps (PC2-4200F),
transitions, over a time interval long enough to make all UI=250ps (PC2-5300F), UI=208ps (PC2-6400F).
7.1.1
Transition Density in Transmitted Signals
The FB-DIMM link doesn’t prescribe encoding. Density_min is: 6 transitions per 512 bits: FB-DIMM at
However the link bit stream needs to maintain a 3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s. The prescribed
minimum transition density. The transition density is minimum is required to enable phase tracking of the
defined as the number of transitions that occurs either received data by the receiver while at the same time
from 0 to 1 or from 1 to 0 within any bit stream of a minimize the overhead requirements.
prescribed length. The minimum prescribed Transition-
7.1.2
Jitter and Bit Error Rate
Jitter is defined as the deviation in the edges of a approximated as Gaussian and can be used to
sequence of data bits from their ideal timing positions. estimate the bit error rate (BER) of the link. In this
This deviation can be in phase, period or duty cycle. document the allocation to random jitter and
Jitter is further categorized into random jitter and deterministic jitter has not been separately specified.
deterministic jitter. The total jitter is the convolution of The total jitter must support a maximum BER of 10 -16.
the probability density for all the independent jitter The methods for measuring BER compliance are still
sources. The random jitter magnitude can be being evaluated.
7.1.3
De-Emphasis
De-emphasis is the engineering term used to describe interference (ISI) due to the difference in loss across
the technique of utilizing a voltage swing reduction of the frequency band where the main energy of the
non-transition bits. Figure 1-3 shows an example of a transmitted bit patterns is located. De-emphasis must
de-emphasized differential signal. De-emphasis is be implemented when multiple bits of the same polarity
different from pre-emphasis in that non-transition bits are output in succession. Subsequent bits are driven at
are reduced in voltage as opposed to an increase in a differential voltage level below the first bit and
voltage swing for transition bits with pre-emphasis. De- individual bits are always driven at the full voltage level,
emphasis is included to minimize Inter-symbol for normal operation.
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Figure 9
De-Emphasis
7.1.4
Electrical Idle (EI)
The condition when both conductors of a differential primarily used in power saving and inactive states (i.e.
pair are at 0 volt (grounded) level. Electrical idle is DISABLE).
Data Sheet
28
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
High-Speed Differential Point-to-Point Link Interface
7.1.5
Reference Clock
The reference clock network consists of the clock the chips at both ends of the link. The reference clock
generator and the clock buffer that drives the PLL of signal meets the High-Speed Current Steering Logic
any front-end transmitter or receiver. The same (HCSL) specification.
reference clock shall be transmitted to the front-end of
7.2
High Speed Serial Link Reference Clocks (SCK, SCK)
To reduce jitter and allow for future silicon fabrication Logic) clocks are used. The nominal single-ended
process changes, HCSL (High-Speed Current Steering swing for each clock is 0 to 0.7 V.
The reference clock frequency is 1/24 of the link data reference clock is unspecified. However, in order to
rate, e.g. 166.67 MHz for a data rate of 4.0Gb/s. The limit the jitter difference between TX and RX there is an
reference clock pair is routed point-to-point to each upper limit for the phase difference between data and
DIMM on the system board. The FB-DIMM channel reference clock at the RX, called the transport delay,
utilizes mesochronous clocking, i.e. the phase T1).
relationship between TX reference clock and RX
7.3
Spread Spectrum Clocking (SSC)
Spread Spectrum Clock (SSC) with up to -0.5% down a modulation rate in the range between 30 kHz and 33
spread in frequency shall be supported. The frequency kHz. The modulation profile of SSC shall be able to
of the clock and therefore bit rate can be modulated provide optimal or close to optimal EMI reduction.
from 0% to -0.5% of the nominal data rate/frequency, at Typical profiles include Triangular or Hershey profile.
7.4
Reference Clock Input Specifications
Table 14
Reference Clock Input Specifications
Symbol
Parameter
Values
Min.
Unit
Notes
Max.
200.00
700
1)2)
3)
Reference clock frequency
Rise time, Fall time
fSCK
133.33
175
MHz
psec
Tsck-rise
Tsck-fall
Voltage high
VSCK-high
VSCK-low
VCross-abs
VCross-rel
660
-150
250
850
mV
mV
mV
Voltage low
4)
Absolute crossing point
Relative crossing point
550
5)4)
Calculated Calculated
% mismatch between rise and fall times TSCK-Rise-Fall-Match
-
10
60
10
2
%
Duty cycle of referance clock
Clock leakage current
TSCK-Dutycycle
II_CK
40
%
6)7)
7)
-10
0.5
-0.25
uA
pF
Clock input capacitance
Clock input capacitance delta
Transport delay
CI_CK
8)
CI_CK(D)
T1
0.25
5
pF
9)10)
11)
ns
Phase Jitter Sample Size
Reference clock jitter, filtered
Reference clock deterministic jitter
NSAMPLE
TREF-JITTER
TREF-DJ
1016
Periods
ps
12)13)
40
TBD
ps
Data Sheet
29
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
High-Speed Differential Point-to-Point Link Interface
1) 133MHz for PC2-4200, 166MHz for PC2-5300 and 200MHz for PC2-6400.
2) Measured with SSC disabled.
3) Measured differentially through the range of 0.175V to 0.525V.
4) The crossing point must meet the absolute and relative crossing point specification simultaneously.
5) VCross_rel_(min) and VCross_rel_(max) are derived using the following calculation: Min = 0.5 (Vhavg - 0.710) + 0.250; and Max = 0.5
(Vhavg - 0.710) + 0.550, where Vhavg is the average of VSCK-highm
6) Measured with a single-ended input voltage of 1V.
7) Applies to Reference Clocks SCK and SCK.
8) Differance between SCK and SCK input
9) T1 = |Tdatapath - Tclockpath| (excluding PLL loop delays). This parameter is not a direct clock output parameter but it
indirectly determines the clock output parameter TREF-JITTER.
10) The net transport delay is the difference in time of flight between associated data and clock paths. The data path is defined
from the reference clock source, through the TX, to data arrival at the data sampling point in the RX. The clock path is
defined from the reference clock source to clock arrival at the same sampling point. See Figure 3-3. The path delays are
caused by copper trace routes, on-chip routing, on-chip buffering, etc. They include the time-of-flight of interpolators or
other clock adjustment mechanisms. They do *not* include the phase delays caused by finite PLL loop bandwidth because
these delays are modeled by the PLL transfer functions.
11) Direct measurement of phase jitter records over 1016 periods is impractical. It is expected that the jitter will be measured
over a smaller, yet statistically significant, sample size and the total jitter at 1016 samples extrapolated from an estimate of
the sigma of the random jitter components.
12) Measured with SSC enabled on reference clock generator.
13) As measured after the phase jitter filter. This number is separate from the receiver jitter budget that is defined by the TRX-
Total-MIN parameters.
7.5
Differential Transmitter Output Specifications
This specification defines a differential current mode Min(specified later). The eye diagrams must be valid for
driver with a three different TX voltage swing modes at least NMIN-UI-TX consecutive UIs (specified in Table 3-
(large, regular and small). The AMBs supports all three 3). An appropriate average transmitter UI must be used
voltage swing modes. The specification defines several as the interval for measuring the eye diagram. The eye
de-emphasis settings for each voltage swing. Each diagram is created using all edges of the NMIN-UI-TX
setting is defined as a separate differential eye diagram consecutive UIs. The eye diagrams shall be measured
that must be met for the transmitter. Figure 3-4 defines by observing a continuous TBD pattern at the pin of the
the eye heights for the large, regular and small voltage device for the non de-emphasized eye and by
swing. The no de-emphasis voltages are for a transition observing a continuous TBD pattern at the pin of the
bit while the other voltages are for a de-emphasized bit. device for the deemphasized eye. The transmitter
All eye diagrams must be aligned in time using the jitter output eye is referenced to VSS and all transmitter
median to locate the center of the eye diagram. All eyes terminations must be referenced to VSS .
must meet the minimum timing requirement of TTX-Total-
Data Sheet
30
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
High-Speed Differential Point-to-Point Link Interface
648ꢃ$)&& ꢄ ꢀM6
ꢅ$ꢆ $ꢂ #ROSSING 0OINTꢇ
648ꢃ$)&& ꢄ ꢀM6
ꢅ$ꢆ $ꢂ #ROSSING 0OINTꢇ
648 $)&&P PMIN
ꢈ
ꢂ
ꢂ
;$%ꢂEMPHASIZED "ITS=
648 $)&&P P
ꢈ
ꢂ
ꢂ
648ꢂ%QꢂMIN,T ꢈ 648ꢂ%Q$)&&PꢂPꢂMIN ꢈ 648ꢂ%QꢂMAX,T
648 $)&&P PMAX
ꢂ
ꢂ
448ꢂ4OTALꢂMIN
-0%4ꢀꢀꢁꢀ
Figure 10 Differential requirement minimum transmitter output eye specifications
0ULSE MIN 3PECꢂ
4X 4OTAL MIN
-0%4ꢀꢀꢁꢀ
Figure 11 Illustrates the transmitter timing specifications
$ ꢂ
4X MIN 6DIFF PꢂP
4X MIN 6DIFF PꢂP
ꢃ.O $EꢂEMPHASISꢄ
ꢃ$EꢂEMPHASISꢄ
$ ꢅ
-0%4ꢀꢁꢀꢀ
Figure 12 Illustrates the de-emphasized string of patterns at the output of a transmitter
Table 15
Differential Transmitter Output Specifications
Symbol Values
Min. Max.
Parameter
Unit Comments
Differential peak-to-peak output voltage VTX-DIFFp-p_L
for large voltage swing
900 1300 mV see Equation (1)
Measured as Note1)
Differential peak-to-peak output voltage VTX-DIFFp-p_R
for regular voltage swing
800
mV see Equation (1)
Measured as Note1)
Data Sheet
31
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
High-Speed Differential Point-to-Point Link Interface
Table 15
Differential Transmitter Output Specifications (cont’d)
Parameter
Symbol
Values
Min. Max.
520
Unit Comments
Differential peak-to-peak output voltage VTX-DIFFp-p_S
for small voltage swing
mV see Equation (1)
Measured as Note1)
DC common code output voltage for
large voltage swing
VTX-CM_L
375 mV see Equation (2)
Measured as Note1)
DC common code output voltage for
small voltage swing
VTX-CM_S
135 280 mV see Equation (2)
Measured as Note1)
See also Note2)
1)3)4)
De-emphasized differential output
voltage ratio for -3.5 dB de-emphasis
VTX-DE-3.5-Ratio
VTX-DE-6.0-Ratio
-3.0 -4.0 dB
1)2)3)
De-emphasized differential output
voltage ratio for -6.0 dB de-emphasis
-5.0 -7.0 dB
AC peak-to-peak common mode output VTX-CM-ACp-p-L
voltage for large swing
90
80
70
mV see Equation (7)
Measured as Note1)
See also Note5)
AC peak-to-peak common mode output VTX-CM-ACp-p-R
voltage for regular swing
mV see Equation (7)
Measured as Note1)
See also Note5)
AC peak-to-peak common mode output VTX-CM-ACp-p-S
voltage for small swing
mV see Equation (7)
Measured as Note1)
See also Note5)
6)
Maximum single-ended voltage in EI
condition DC + AC
VTX-IDLE-SE
VTX-IDLE-SE-DC
VTX-IDLE-DIFFp-p
VTX-SE
50
20
40
mV
6)
Maximum single-ended voltage in EI
condition DC + AC
mV
Maximum peak-to-peak differential
voltage in EI condition
mV
1)7)
Single-ended voltage (w.r.t. VSS) on
D+/D-
-75
750 mV
1)8)
Mimimum TX eye width, 3.2 and
4.0Gb/s
TTX-Eye-MIN
TTX-Eye-MIN4.8
0.7
UI
1)8)
Mimimum TX eye width 4.8Gb/s
TBD
UI
1)8)9)
Maximum TX deterministic jitter,3.2 and TTX-DJ-DD
4.8 Gb/s
0.2
UI
1)8)9)
Maximum TX deterministic jitter, 4.8
Gb/s
TTX-DJ-DD-4.8
TBD UI
10)
Instantaneous puls width
TTX -PULSE
0.85
UI
Differential TX outout rise/fall time
TTX-RISE TTX-FALL 30
90
20
ps
ps
Given by 20 % - 80 % voltage
levels. Measured as Note1)
Mismatch between rise and fall times
Differential return loss
TTX-RF-MISMATCH
RLTX-DIFF
8
6
dB Measured over 0.1 GHz to 2.4
GHz. See also Note11)
Common mode return loss
RLTX-CM
dB Measured over 0.1 GHz to 2.4
GHz. See also Note11)
Data Sheet
32
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
High-Speed Differential Point-to-Point Link Interface
Table 15
Differential Transmitter Output Specifications (cont’d)
Parameter
Symbol
Values
Unit Comments
Min. Max.
12)
Transmitter termination impender
D+/D- TX Impedance difference
RTX
41
55
RTX-MATCH-DC
4%
see Equation (4)
Bounda are applied separately to
high and low output voltages
states
13)15)
Lane-to lane skew at TX
LTX-SKEW 1
LTX-SKEW 2
100+ ps
3UI
14)15)
Lane-to lane skew at TX
100+ ps
2UI
16)
16)
Maximum TX Drift (resync mode)
TTX-Drift-RESYNC
240 ps
120 ps
Maximum TX Drift (resample mode
only)
TTX-Drift-RESAMPLE
17)
BER
Bir Error Ratio 10-12
1) Specified at the package pins into a timing and voltage compliance test load as shown in Figure 4-2 and in steps outlined
in 4.1.2.1. Common-mode measurements to be performed using a 101010 pattern.
2) The transmitter designer should not artifically elevate the common mode in order to meet this specification.
3) This is the ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit
after a transition.
4) De-emphasis shall be disabled in the calibration state.
5) Includes all sources of AC common mode noise
6) Single-ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as the Electrical Idle
condition.
7) The maximum value is specified to be at least (VTX-DIFFp-pL/4 ) + VTX-CML + (VTX-CM-ACp-p/2).
8) This number does not include the effects of SSC or reference clock jitter.
9) Defined as the expected maximum jitter for the given probability as measured in the system (TJ), les the unbounded jitter.
10) Puls width measure at 0V differential.
11) One of the components that contribute to the deterioration of the return loss is the ESD structure wich needs to be carefully
designed
12) The termination small signal resistance; tolerance across voltages from 100 mV to 400 mV shall not exceed +/- 5 W with
regard to the average of the values measured at 100 mV and 400 mV for that pin.
13) Lane to Lane skew at the Transmitter pins for an end component.
14) Lane to Lane skew at the Transmitter pins for an intermediate component (assuming zero Lane to Lane skew at the
Receiver pins of the incoming PORT).
15) This is a static skew. An FB-DIMM component is not allowed to change its lane to lane phase relationship after initialization.
16) Measured from the reference clock edge to the center of the output eye. This specification must be met across specified
voltage and temperature ranges for a single component. Drift rate change is significantly below the tracking capability of
the reciver.
17) BER per differential lane.
VTX – DIFFp – p = 2 × VTX – D+ – VTX – D
(1)
(2)
(3)
VTX – CM = DC(avg)of ( VTX – D+ + VTX – D- ⁄ 2)
VTX – CM – AC = ((Max VTX – D+ + VTX – D- ) ⁄ 2) – ((Min VTX – D+ + VTX – D- ) ⁄ 2)
RTX-D+ – RTX-D-
-------------------------------------------
RTX – Match – DC = 2 ×
(4)
RTX-D+ + RTX-D-
Data Sheet
33
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
High-Speed Differential Point-to-Point Link Interface
7.6
Differential Receiver Input Specifications
The receiver definition starts from the input pin of the receiver end package and therefore includes the package
and the receiver end chip.
7.6.1
Receiver Input Compliance Eye Specification
Following the specification of the transmitter, the NMIN-UI-RX consecutive UIs. An appropriate average
receiver is specified in terms of the minimum input eye transmitter UI must be used as the interval for
that must be maintained at the input to the receiver, and measuring the eye diagram. The eye diagram is
under which the receiver must function at the specified created using all edges of the NMIN-UI-TX consecutive
data rates. The receiver eye is referenced to VSS and UIs. The eye diagrams shall be measured by observing
all input terminations at receiver must be referenced to a continuous TBD pattern at the pin of the device.
VSS. This input eye must be maintained for at least
628ꢃ$)&& ꢄ ꢀM6
ꢅ$ꢆ $ꢂ #ROSSING 0OINTꢇ
628ꢃ$)&& ꢄ ꢀM6
ꢅ$ꢆ $ꢂ #ROSSING 0OINTꢇ
628ꢂ$)&&PꢂPꢂMIN
428ꢂ4OTALꢂMIN
-0%4ꢀꢁꢁꢀ
Figure 13 Required receiver input eye (differential) showing minimum voltage and timing Spec.
Table 16
Revision History
Initials Comment
Filename Date
Conditional Tags R/SC Number
mpit2113 2005-11-21 msc
mpit2112
new template_321
mpit2111
mpit2110
Initial document
Table 17
Differential Receiver Input Specifications
Symbol
Parameter
Values
Min.
Unit
Comments
Max.
Differential peak-to-peak input voltage
VRX-DIFFp-p
170
TBD
mV
mV
mV
mV
mV
mV
see Equation (5)
Measured as Note1)
2)3)
Maximum single-ended voltage for EI
condition
VRX-IDLE_SE
VRX-IDLE_SE_DC
VRX-IDLE-DIFFp-p
VRX-SE
75
2)3)
3)
Maximum single-ended voltage for EI
condition(DC only)
50
Maximum peak-to-peak differental
voltage for EI condition
65
4)
Single ended voltage (w.r.t. VSS) on
D+/D-
-300
85
900
4)5)
Single-pulse peak differential input
voltage
VRX-DIFF-PULSE
Data Sheet
34
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
High-Speed Differential Point-to-Point Link Interface
Table 17
Differential Receiver Input Specifications
Parameter
Symbol
Values
Min.
Unit
Comments
Max.
4)6)
Amplitude ratio between adjacent
symbols
VRX-DIFF-ADJ-Ratio
TRX-TJ-MAX
TRX-TJ-MAX4.8
VRX-DJ-DD
VRX-DJ-DD-4.8
TRX-PW-ZC
TBD
4)7)8)
4)7)8)
4)7)8)9)
4)7)8)9)
4)5)
Maximum RX inherent timing error, 3.2
and 4.0 Gb/s
0.4
UI
UI
UI
UI
UI
UI
ps
mV
Maximum RX inherent timing error,
4.8Gb/s
TBD
0.3
Maximum RX inherent deterministic
timing error, 3.2 and 4.0 Gb/s
Maximum RX inherent deterministic
timing error, 4.8 Gb/s
TBD
Single-puls width at zero-voltage
crossing
0.55
0.2
4)5)
Single-puls width at minimum-level
crossing
TRX-PW-ML
Differential RX input rise/fall time
TRX-RISE,TRX-
50
Given by 20 % -
80 % voltage levels.
FALL,
Common mode of the input voltage
VRX-CM
120
400
see Equation (6)
Measure as Note1),
See also Note10)
AC peak-to-peak common mode of input VRX-CM-ACp-p
voltage
270
45
mV
%
see Equation (7)
Note1)
11)
Ratio of VRX-CM-ACp-p to minimum VRX-DIFFp- VRX-CM-EH-Ratop
p
Differential return loss
RLRX-DIFF
9
dB
Measured over 0.1
GHz to 2.4 GHz. See
also Note12)
Common mode return loss
RRX-CM
6
dB
Measured over 0.1
GHz to 2.4 GHz. See
also Note 12)
13)
RX termination impendance
D+/D- RX impendance difference
Lane-to-lane PCB skew at Rx
RRX
41
55
4
Ω
RRX-Match-DC
LRX-PCB-SKEW
%
UI
see Equation (8)
6
Laneto Lane skew at
the Receiver that
must be tolerated.
See also Note14)
15)
Minimum RX Drift Tolerance
TRX-DRIFT
FTRK
400
0.2
ps
16)
17)
Minimum data tracking 3 dB bandwidth
Electrical idle entry datect time
MHz
ns
TEI-ENTRY-
60
DETECT
Electrical idle exit datect time
Bit Error Ratio
TEI-ENTRY-
30
ns
DETECT
18)
BER
10-12
1) Specified at the package pins into a timing and voltage compliant test setup. Note that signal levels at the pad will be lower
than at the pin.
Data Sheet
35
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
High-Speed Differential Point-to-Point Link Interface
2) Single-ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as the Electrical Idle
condition. Worst-case margins are determined for the case with transmitter using small voltage swing.
3) Multiple lanes need to detect the EI condition before the device can act upon the EI detection.
4) Specified at the package pins into a timing and voltage compliance test setup.
5) See Figure 3-8 and Figure 3-9. The single-pulse mask provides sufficient symbol energy for reliable RX reception. Each
symbol must comply with both the single-pulse mask and the cumulative eyemask.
6) See Figure 3-10. The relative amplitude ratio limit between adjacent symbols prevents excessive intersymbol interference
in the Rx. Each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent
symbols.
7) This number does not include the effects of SSC or reference clock jitter.
8) This number includes setup and hold of the RX sampling flop.
9) Defined as the dual-dirac deterministic timing error.
10) Allows for 15 mV DC offset between transmit and receive devices.
11) The received differential signal must satisfy both this ratio as well as the absolute maximum AC peaktopeak common mode
specification. For example, if VRX-DIFFp-p is 200 mV, the maximum AC peak-to peak common mode is the lesser of (200 mV
* 0.45 = 90 mV) and VRX-CM-AC-p-p .
12) One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully
designed.
13) The termination small signal resistance; tolerance across voltages from 100 mV to 400 mV shall not exceed +/- 5 W with
regard to the average of the values measured at 100 mV and at 400 mV for that pin.
14) This number represents the lane-to-lane skew between TX and RX pins and does not include the transmitter output skew
from the component driving the signal to the receiver. This is one component of the end-to-end channel skew in the AMB
specification.
15) Measured from the reference clock edge to the center of the input eye. This specification must be met across specified
voltage and temperature ranges for a single component. Drift rate of change is significantly below the tracking capability of
the receiver.
16) This bandwidth number assumes the specified minimum data transition density. Maximum jitter at 0.2 MHz is 0.05 UI, see
Section 4 for full jitter tolerance mask.
17) The specified time includes the time required to forward the EI entry condition.
18) BER per differential lane. Refer to Section 4 for a complete definition of Bit Error Ratio.
VRX – DIFFp – p = 2 × VRX-D+ – VRX-D-
(5)
(VRX – CM = DC(avg)of VRX – D+ + VRX – D- ) ⁄ 2
VRX – CM – AC = ((Max VRX – D+ + VRX – D- ) ⁄ 2)((Min VRX – D+ + VRX – D- ) ⁄ 2)
RRX-D+ – RRX-D-
(6)
(7)
--------------------------------------------
RRX – Match – DC = 2 ×
(8)
R
RX-D+ + RRX-D-
Data Sheet
36
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Channel Initialization
8
Channel Initialization
The FB-DIMM channel initialization process generally Disable), Training, Testing, and Polling states in order
follows the top to bottom sequence of state transitions to transition the AMBs into the active channel L0 state.
shown in the high level AMB Initialization Flow diagram The value in parenthesis in each state bubble indicates
in Figure 3-4. The host must sequence the AMB the condition/activity of the links during these states.
devices through the Disable, Calibrate, (back to
0OWERꢂUP
$ISABLE
4RAINING ꢃ43/ꢅ
4ESTING ꢃ43ꢄꢅ
0OLLING ꢃ43ꢆꢅ
#ONFIG ꢃ43ꢁꢅ
#ALIBRATE ꢃꢄ|Sꢅ
,/ ꢃFRAMESꢅ
,/S ꢃ%ꢄꢅ
2ECALIBRATE ꢃ./0Sꢅ
-0&4ꢀꢀꢁꢀ
Figure 14 Flow Chart AMB Initialization
8.1
RESET Signal
The RESET signal acts as a hardware reset and technology defines any DRAM specific mechanisms. If
immediately puts the AMB into a known state. The AMB the DRAMs were in self refresh prior to RESET being
Initialization FSM is put into the Disable state and the asserted, they will remain in self refresh through the
NB Tx outputs are put into Electrical Idle regardless of hardware reset. The host must wait until the power and
the state of the NB Rx inputs. All ’sticky’ bits are set to the reference clock to the AMBs have been stable for
their default values. The CKE signals to the DRAM greater than or equal to 1ms before transitioning the
devices are driven inactive to turn off the DRAM output channel out of the Disable state. The relationship
drivers. DRAM specific mechanisms in the AMB may between supply voltage, reference clock and the
generate additional signal transitions to the DRAM RESET signal is defined in the AMB Buffer
devices to make sure that they do not hang in an Specification
unknown state. The AMB specification for each DRAM
8.1.1
Inband Control ‘Signals’
There are no dedicated control signals implemented on characteristics are exploited to deliver inband control
an FB-DIMM channel. Two different channel information on the FB-DIMM channel wires when no
Data Sheet
37
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Channel Initialization
clock timing has been established between the host ground to receive inband control information. Clock
and the AMBs: Electrical Idle (EI): During normal Training Violation: During normal channel operation the
channel operation the Tx outputs are enabled and a southbound bit lanes contain a minimum number of
differential voltage is present on each bit lane. In transitions every tClkTrain frames to keep the clock
Electrical Idle the Tx outputs source insignificant tracking circuits on each bit lane locked to the data
current and the termination resistors at the receiver pull stream. It is the absence of these periodic bit lane
both signals of the differential pair to ground. The Rx transitions that is used by the host to communicate
inputs can detect if both differential inputs are near control information..
8.2
Channel Initialization Sequence
The host controller sequences the FB-DIMM channel times before reporting a failure to the system. It is
through the initialization sequence. The AMB devices undesirable to continuously drive high frequency
on each DIMM monitor in-band signals from the host signals into un-terminated transmission lines because
and use events and patterns on these signals to of the EMI that is generated and the power that is
transition from one state to another. If the channel fails wasted. To avoid this the host must return to the
to initialize properly the host may transition the channel Disable state if the channel does not properly initialize.
back to the Disable state and try again a number of
8.2.1
Firmware Transition Control
The channel initialization and configuration sequence initialization and configuration process be controlled by
may be controlled by a hardware state machine or firmware. It is recommended that implementation
directed by firmware. To provide a flexible mechanism specific control registers be included in the host to allow
for dealing with a variety of FB-DIMM channel failure firmware to step through the initialization steps and
conditions it is recommended that the channel perform the following functions:
•
•
•
•
•
•
Put the SB Tx outputs into Electrical Idle.
Drive SB Tx outputs to all ones.
Detect if the NB port is receiving Electrical Idle.
Drive TS0 patterns with an arbitrary AMB_ID value.
Receive TS0 patterns and read the returned AMB_ID value
Drive TS1 patterns with an arbitrary AMB_ID value and with a sequence of electrical stress test patterns on
each bit lane. Registers to hold an arbitrary 24 bits of Test Parameter values are recommended.
Receive TS1 electrical stress test patterns and check the patterns.
Test the NB bit lanes and report NB test results.
Drive TS2 patterns.
Receive TS2 patterns and determine the round trip channel delay.
Drive TS3 patterns with channel configuration values.
Receive TS3 patterns and check the returned values.
Set the Last_AMB_ID value.
•
•
•
•
•
•
•
•
•
•
•
•
Set the Hot_Add_AMB_ID value
Set the Fast_Reset_Flag value.
Set the Recalibrate_Duration value.
Set the L0s_Duration value.
Transition the channel to the L0 state and send the first Sync command.
8.2.2
AMB Internal State Variables
A number of internal flags and timers are referenced in to describe internal AMB state that may or may not be
the following sections. These flags and timers are visible in defined AMB registers. These flags and timers
implementation specific and included in the state tables include:
•
Last_AMB_Flag - set in the last AMB to enable unique properties of the AMB in this position.
Data Sheet
38
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Channel Initialization
•
•
•
•
•
First_Sync_Received_Flag - set to disable further initialization of the Idle/Alert Frame LFSR.
Idle/Alert Frame LFSR - a counter in each AMB used to generate Idle and Alert frames on the NB channel.
Alert_Flag - a flag that indicated that this AMB detected an error and is or was generating NB Alert frames.
Recalibrate_Timer - a timer that keeps track of how long the AMB has been in the Recalibrate state.
L0s_Timer - a timer that keeps track of how long the AMB has been in the L0s state.
8.2.3
Disable State
The channel is forced into the Disable state during outputs into Electrical Idle. The host must not put the
hardware reset. The host may put the channel into the channel into the Disable state from the L0 state until
Disable state at any time and from any other state other any DRAM write operations have had time to complete.
than L0s by putting the three least significant Tx Channel initialization always starts in the Disable state.
8.2.4
Training State
The host drives a repetitive series of TS0 patterns to filled with an alternating 1010 pattern to align the clock
transition the AMBs from the Disable state to the trackers with the incoming data stream. The sequence
Training state and to perform initial link training. The generally has logic zeroes in the even bit positions and
host may detect that the last AMB has acquired frame logic ones in the odd bit positions. The beginning of the
lock when TS0 patterns are received on the required sequence is identified by the header pattern shown in
number of inputs. Bit patterns in TS0 are used to the table below and is used to establish the alignment
perform bit lock and frame lock. The pattern is mostly of the serial data onto frame boundaries.
8.2.5
Testing State
The host drives a TS1 pattern to transition the AMBs send an arbitrary number of TS1 patterns to test the
from the Training state to the Testing state and may channel.
8.2.6
Polling State
The host drives a TS2 pattern to transition the AMBs pattern to each intermediate AMB to test if it has
from the Testing state to the Polling state. The host aligned its northbound merge data timing to the timing
sends a continuous stream of TS2 patterns to the last of the last AMB and can properly merge its data into the
AMB to determine the round trip latency of the channel. northbound data stream.
The host may subsequently and optionally send a TS2
8.2.7
Config State
The TS3 training sequence is used to communicate the channel configuration to the AMBs in the Config state. On
exit transitions to L0 state if 4 consecutive NOP frames are received.
Data Sheet
39
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Channel Protocol
9
Channel Protocol
The host performs all of the scheduling of the and facilitates the use of two or more FB-DIMM
southbound and northbound data paths. The FB channels in lock stepped configurations. The host
DIMMs do not initiate any northbound traffic but instead sends commands and data to the DIMMs in 120-bit
respond to commands provided by the host. This southbound frames. Similarly the DIMMs return data to
protocol style results in a memory channel that has the host in 168-bit northbound frames.
deterministic behavior (in the absence of error events)
9.1
Southbound Frames
After initialization the host communicates with the normal and fail-over. In normal mode the southbound
AMBs on the channel using southbound frames of link is full width and has a stronger CRC code. In fail-
information containing commands and data. There are over mode the southbound link is reduced in width by
two modes of operation of the southbound channel, one bit and uses a weaker CRC code.
9.1.1
Normal Southbound Frames
Normal southbound frames consist of 12 transfers of command type and is protected by 22-bits of CRC
data delivered on 10 southbound bit lanes. Each frame information.
contains 72-bits of data, 24-bits of command, 2-bits of
9.1.2
Fail-over Southbound Frames
Fail-over southbound frames consist of 12 transfers of fail-over mode and the CRC code size is reduced in this
data delivered on 9 southbound bit lanes. The most mode.
significant bit lane is not available to carry CRC bits in
9.1.3
Command Frame Format
The Command frame contains up to three independent each command specify which DIMM should execute
commands that can be executed in parallel by separate the command.
DIMMs and in some cases by the same DIMM. Bits in
9.1.3.1
Command Frame with Data Format
Specific commands, such as configuration register commands to deliver a data payload with information
write commands, may need to deliver data to the AMB that cannot be encoded in the command itself.
devices. The Command frame is used by these
9.1.3.2
Command+Wdata Frame Format
The Command+Wdata frame is used to deliver write payload is not examined by the AMB. The write data is
data to write FIFO structures on each DIMM for future loaded into the write FIFO on the DIMM from 3
transfer to the DRAM devices. The content of the data consecutive Command+Wdata frames.
9.1.4
Southbound Commands
There are two categories of southbound commands.
DRAM commands and channel commands.
9.1.4.1
DRAM Commands
DRAM commands are generated by the host to access has access to the DRAM devices as if the devices were
the DRAM devices behind each AMB buffer. The host directly connected to the host. The AMB decodes the
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512-Mbit DDR2 SDRAM
Channel Protocol
DRAM commands and generates the control signals to each ECC DIMM. Non-ECC memory DIMMs support
the DRAM devices. The command delivery on the the Data Mask function. Write accesses transfer the
DRAM address and control signals (excluding CKE) data from the write data FIFO located inside the AMB
use 1n command timing. 1n command timing means device on the DIMM. A register instructs the AMB when
that the commands are present on the DRAM pins for a to drive the data after the Write command. The DDR2
single clock cycle. DRAM Read and Write commands specific Off-Chip Driver (OCD) impedance Adjust
always transfer complete bursts of data determined by command also transfers data from the write data FIFO
the Burst Length field programmed into the DRAM to the DRAM devices. The host is responsible for
MRS registers. A burst length of 4 will transfer 36 bytes memory ordering, FB-DIMM channel scheduling, and
and a burst length of 8 will transfer 72 bytes to/from error handling.
Available DRAM Commands
•
•
•
•
•
•
•
•
•
Activate
Write
Read
Precharge All
Precharge Single
Auto Refresh
Enter Self Refresh
Enter Power Down
Exit Self Refresh and Exit Power Down
9.1.4.2
Channel Commands
Channel commands include the Sync command, register read and write commands, and miscellaneous
miscellaneous DRAM commands, configuration maintenance commands.
Available Channel Commands
•
•
•
•
•
•
•
•
Channel NOP
Sync
Soft Channel Reset
Write Config Register
Read Config Register
DRAM CKE per DIMM
DRAM CKE per Rank
Debug
9.1.4.3
CKE Control Commands
Two versions of the CKE control command allows for more than one of the commands targets any one DIMM
individual rank control, where up to 4 DIMMs may be on the same DRAM clock. The Host Controller is
targeted at once, or per DIMM control, where all 8 responsible for CKE timing with respect to the DRAM
DIMMs can be accessed from a single command. The protocol, including the explicit Self Refresh command.
CKE control commands will affect the CKE pins for the The AMB will not do any protocol checking. The Per
addressed DIMM(s) with the same timing as a DRAM DIMM CKE command allows all 8 DIMMs to be targeted
command, based on slot location. Multiple CKE by a single command. The Per Rank CKE command
commands may be included in one frame as long as no allows for individual Rank CKE control.
9.1.4.4
Soft Channel Reset Command
The Soft Channel Reset command may be used to channel. In the case of a minor transient bit error a
attempt to recover from a transient bit failure on the single or a small group of commands may be corrupted.
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512-Mbit DDR2 SDRAM
Channel Protocol
The AMB will detect the corruption as a CRC error and
Status return would be located if the Soft Channel
will ignore the corrupted commands and report the
error to the host with Alert frames. The host may issue
a Soft Channel Reset command to acknowledge the
receipt of the Alert frames and reset the command state
of the AMBs. The Soft Channel Reset command must
be preceded by at least 1 NOP frame and followed by
at least 4 NOP frames. The AMB recognizes the Soft
Channel Reset command while ignoring all others and
resets its internal command state.
Reset command was a Sync command.
Discard all data content in the Write FIFO
Reset the DIMM target Write FIFO state machine
•
•
The host may follow the Soft Channel Reset command
(and the 4 NOP frames) with a sequence of DRAM
commands to clear the command state of the DRAM
devices. The sequence may look something like this:
1. Assert CKE to all ranks
2. Wait the appropriate number of clocks
3. Issue a Precharge All command to all ranks If the
Soft Channel Reset itself is corrupted the stream of
Alert frames will continue and the host may perform
a Fast Reset to reinitialize the channel.
The following actions are performed by the AMB:
•
Discontinue Alert frame generation and generate
Idle frames or forward NB traffic in the frame that a
9.1.4.5
Sync Command
The FB-DIMM channel periodically requires a minimum send syncs at any interval between the programmed
number of transitions on each bit lane to maintain clock interval and 42. For example, if the host controller
recovery synchronization. The host must periodically design can send syncs in the range of 38 to 42 frames
send a Sync command on the channel to maintain the apart, the register would be programmed to 38. The
required transition density. The maximum interval best power management for the AMB can be achieved
between sync frames is 42 frames, in order to maintain by the host controller being as consistent as possible in
clock recovery synchronization. The host controller its sync generation. Power Management within the
must adhere to a minimum interval between sync AMB can have an impact on bandwidth capabilities in
frames to guarantee that the AMB clock recovery some platforms. The AMB specification provides
circuits will be adjusted. This allows the AMB to save information on the programming of this register as well
power by switching off internal circuits between sync as the default and minimum values. Following a reset,
commands. The AMB contains a register in which the the host may ignore the minimum sync interval up until
host controller programs the minimum interval between the 4th sync.
syncs which it will send. The host controller may then
9.1.4.6
NOP Frame
The NOP frame contains three NOP commands and is commands to send on the channel. The frame is a
sent on the southbound link when there are no other normal Command frame format.
9.1.4.7
Command Delivery Timing
DRAM access latency is minimized by allowing the after the first 4 transfers of the frame have been
command to be delivered to the DRAM immediately received.
9.1.4.8
Concurrent Command Delivery Rules
Commands may be issued in any combination, as long
as they do not collide on any DRAM pin or FB-DIMM
data slot, and follow a few additional rules below.
DRAM Command and Address Pins
Only one of the following commands may target a Multiple commands within this list may be issued if each
particular DIMM in the same DRAM clock due to targets a different DIMM, as long as there is no collision
collisions on the DRAM command and address pins. on the FB-DIMM channel northbound data bus:
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512-Mbit DDR2 SDRAM
Channel Protocol
Activate, Write, Read, Precharge Single, Precharge All,
Auto Refresh, and Enter Self Refresh.
DRAM CKE Pins
Only one of the following commands may target a commands may target a single DIMM, or 4 or 8 DIMMs
particular DIMM in the same DRAM clock due to at once. When multiple DIMMs are targeted by a
collisions on the CKE pins: Enter Self Refresh, Exit Self command, no other command affecting the CKE pins
Refresh, DRAM CKE per DIMM, DRAM CKE per Rank, may be issued to any of the targeted DIMMs.
and Enter Power Down. Note that DRAM CKE
DRAM Data and Strobe Pins
Commands cannot be issued to a DIMM that would within a DIMM. In addition, all turnaround times for the
cause collisions on the DRAM data and strobe pins DRAM data and strobe pins must be observed.
Northbound Data Bus
Commands cannot be issued on the channel that would of responses must be preserved. Commands issued
cause collisions on the Northbound data bus. following a Sync command with SD > 0 must not return
Commands that generate data on the northbound data data before or on top of the Sync status return.
bus are: Read, Read Config Reg, and Sync. The order
Other Restrictions
Only one outstanding configuration read or write Reg command following an Alert Frame. A Soft
register transaction is allowed on the channel. A Channel Reset requires NOP commands in all other
configuration register read begins with the command command slots in the previous DRAM clock, the current
and ends with the data being returned to the host. A DRAM clock, and the next 4 DRAM clocks. Only one In-
configuration write begins with the command and ends band Debug event may be sent within a DRAM clock.
when the read data would have been returned if the The host controller is responsible for state and timing of
command were a Read Config Reg. This is the same the CKE pins vs. DRAM commands based on the
point that an Alert Frame would be generated if there DRAM specifications. A DRAM command and CKE
were a CRC error on the Write Config Reg command. command may target the same DIMM on the same
Allowing only one outstanding configuration transaction DRAM clock provided that the DRAM specifications are
on the bus allows for proper replay of the Write Config met.
9.1.4.9
Command Encoding
Commands are encoded into the 24 bit of Command
frames. For detailed command bit maps please refer to
the AMB Buffer Specification.
9.2
Northbound CRC Modes
FB-DIMM supports three northbound CRC modes to ECC coverage only 12 bit lanes: 6-bit CRC over 64-bit
support applications that require different levels of error data payload, no fail-over The selection on the mode of
detection. The frames contain two 72-bit or 64-bit data operation is controlled by the host and communicated
payloads. Each data payload is protected by either a during the initialization process. Northbound CRC is
12-bit CRC or a 6-bit CRC. The three supported only computed for Data frames. The Idle, Alert, and
northbound CRC modes are: 14 bit lanes: 12-bit CRC Status frame types drive the upper bit lanes with a
over 72-bit data payload, fail-over to 6-bit CRC 13 bit known data pattern. During fail-over the host simply
lanes: 6-bit CRC over 72-bit data payload, fail-over to ignores the missing bit lanes.
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512-Mbit DDR2 SDRAM
Channel Protocol
9.2.1
Northbound Idle Frame
Each Idle frame contains a permuting data pattern. The pattern of the Idle and Alert frames to their initial value.
last DIMM on the channel sends this permuting data The first Idle frame follows immediately after the Status
pattern when not sending requested data from the frame returned for the first Sync command. The
DIMM. The content of the frame is designed to permuting data pattern is generated by a 12-bit linear-
intentionally generate CRC errors if not in fail-over feedback shift register (LFSR) with a polynomial of x12
mode so that the host can easily detect when an +x7 + x4 + x3 + 1. The LFSR counter cycles through
expected Northbound Data frame with good CRC is 212-1 states (4095 frames) before the pattern is
missing. The host does not log the CRC errors repeated. Each bit of the counter is mapped onto a
generated by the Idle frames. Host hardware will issue corresponding northbound bit lane. The LFSR does not
a Sync command on the channel immediately following generate an all zero data payload.
entry into the L0 state to reset the permuting data
9.2.2
Northbound Alert Frame
AMBs report detection of errors on the channel using AMB on the channel will send this permuting data
the Northbound Alert frame. The Northbound Alert pattern after it has detected a CRC error in any
frame contains the inverse of the Idle frame data southbound command frame. The AMB will continue to
pattern. The host may use detection of this permuting generate Northbound Alert frames until it receives a
data pattern to indicate that an error has occurred. An Soft Channel Reset command or a channel reset.
9.2.3
Northbound Data Frames
This section defines the format of the Northbound Data is sent on the 12th, 13th, or 13th & 14th bit lanes if not
frames. Each frame contains either two 72-bit data in fail-over mode. Each data payload has its own CRC
payloads or two 64-bit data payloads. A CRC code is code to minimize the latency to deliver the first data
computed across each of the 72-bit data payloads and payload to the host.
9.2.3.1
14-bit Lane Northbound Data Frame
This is the highest RAS mode of operation for the payload. For the mapping of the data from each of the
northbound channel. In this mode a 12-bit CRC is DRAM devices into the Northbound Data frame please
delivered during the transfer of each 72-bit data refer to the AMB Buffer Specification.
9.2.3.2
13-bit Lane Fail-over Northbound Data Frame
When the 14 lane mode has failed over to 13 lanes, the
northbound data frame is identical to the 13 bit lane
frame below.
9.2.3.3
13-bit Lane Northbound Data Frame
This is the medium RAS mode of operation for the payload. For the mapping of the data from each of the
northbound channel. In this mode a 6-bit CRC is DRAM devices into the Northbound Data frame please
delivered during the transfer of each 72-bit data refer to the AMB Buffer Specification.
9.2.3.4
13-bit Lane Fail-Over Northbound Data Frame
When 13-bit lane mode has failed over and is operating host is the only error detection available. Note that this
on 12 lanes, each transfer consists of only the 72 bit frame format is NOT the same as the 12-bit Lane frame
payload with no CRC. The ECC implemented by the format.
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HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Channel Protocol
9.2.3.5
12-bit Lane Northbound Data Frame (Non-ECC Mode)
This is the lowest RAS mode of operation for the and the CRC code is the only form of protection. For the
northbound channel. In this mode a 6-bit CRC is mapping of the data from each of the DRAM devices
delivered during the transfer of each 64-bit data into the Northbound Data frame please refer to the
payload. The data payload does not contain ECC bits AMB Buffer Specification.
9.2.3.6
Northbound Register Data Frame
The NB Register Data frame is used to return data in must select the appropriate bytes from the four data
response to a Read Configuration command. The bytes delivered if fewer than four bytes are needed.
frame always returns 32-bits of register data. The host
9.2.3.7
Northbound Status Frame
The Status frame is returned to the host in response to status bits could not be calculated within this
a Sync command from the host. The status returned in mechanism. Each AMB drives all 12 bits delivered in
the Status frame corresponds to the status of the AMB the frame for its assigned bit lane, including the
to commands before the Sync command. Errors that alternating one/zero pattern. The AMB in the last DIMM
are generated by commands after the Sync command position of the daisy chain initiates the northbound
are reported in subsequent Status frames. In other Status frame and fills the bit lane corresponding to its
words the Sync command provides a fence for status DIMM position with its status information and fills the
reporting. Each AMB will merge its status into the remainder of the bit lanes with a zero status code and
northbound bit stream on the appropriate bit lane. The an invalid zero parity value. This is done so that the
northbound Status frame contains a group of status bits host may detect a missing status response if an AMB
from each AMB. The status bits are protected by an odd misinterprets the Sync command. The host is expected
parity bit DnSP that covers the status bits from each (but not required) to detect the status response error
AMB individually. This is necessary because the status and reissue the Sync command to request the status
from each AMB is merged ìon-the-flyî into the Status again. The CRC bit lanes are filled with the same fixed
Frame by each AMB and a CRC that covers all of the pattern because the CRC is not valid in this frame type.
9.3
DRAM Memory Timing
The host accesses the DRAM devices on an FB-DIMM controller must deliver commands onto the FB-DIMM
DIMM as if they were directly connected to the host but channel exactly as the host intends the commands to
with a few differences. First there is generally a longer be delivered to the DRAM devices. This section
than usual delay in the return data path between the illustrates the DRAM timing on the channel. The
DRAM and the host,and second there is a FIFO command delivery on the DRAM address and control
mechanism in the write data path between the host and pins use 1n command timing. 1n command timing
the DRAM. The host sends ‘RAS’ and ‘CAS’ style means that the commands are present on the DRAM
commands directly to the DRAM devices. The pins for a single clock cycle. This allows the commands
commands on the FB-DIMM channel are delivered to present on the channel to be forwarded to the DRAM
the DRAM devices with a fixed delay. The host channel without timing modification.
9.3.1
Read Timing
The command timing of the DRAM devices on an FB- propagation delay characteristics of the channel. For
DIMM is identical to the timing of an individual DRAM single DIMM configurations the timing behaves similar
device. The RAS latency, CAS latency, etc. are to a Registered SDRAM DIMM. As DIMMs are added
controlled by the MRS values loaded into the DRAM to the channel the accumulated delay due to PCB flight
devices. Figure 4-15 illustrates an example DRAM time and delay through intermediate AMB components
Read operation. The data returned to the host is increases the delay in the return data path.
delayed for an interval of time determined by the
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512-Mbit DDR2 SDRAM
Channel Protocol
Back-to-back reads from different DIMMs is illustrated separateDIMMs can be returned without a dead clock
in Figure 4-16. Unlike DDR2, the data from the between the data bursts.
Figure 15
9.3.2
Write Timing
The write command timing of a DRAM device on an FB- southbound channel and when the data can be driven
DIMM is identical to the timing of an individual DRAM onto the DRAM data pins. The data can be loaded into
device. The Write latency is controlled by the MRS the FIFO earlier than what is shown but will occupy an
values loaded into the DRAM devices. Figure 4-17 entry in the FIFO until used. The fixed fall through time
illustrates an example DRAM Write operation. The host shown defines the just-in-time arrival of the data to
transfers the data to be written into a write FIFO in the meet delivery to the DRAM. This just-in-time arrival
AMB preceding the DRAM write transfer. The write time allows the controller to deliver a burst of 64
FIFO is used to accumulate write data in the AMB so transfers to the DRAM using the 35 deep FIFO in the
that the data can be transferred to the DRAM devices AMB. Writes may be followed by a Sync command that
at full burst rate during the write operation. The host returns status information to indicate to the host that no
must be aware of the DRAM Write latency value in errors are associated with the write operation(s). The
order to make sure that the write data is available in the figure shows the earliest the Sync command can be
Write FIFO early enough to be delivered to the DRAMs issued and report completion of the write operations. If
when expected. The AMB must be aware of the DRAM there are errors with the write command or the write
Write latency value in order to deliver the write data to data the AMB will report the error by sending Alert
the DRAMs when expected. Note that the Write frames. Following error detection, the host may issue
command may be issued before the frame holding the the Soft Channel Reset command to discard any data
last payload of data. The figure shows the shortest time in the write FIFO. This would empty the write FIFO and
between the last frame of data is driven on the put the write FIFO state machines into a known state.
9.3.2.1
Write Data FIFO
The Write Data FIFO is a data structure that is used to Multiple bursts of data can be accumulated in the FIFO
accumulate write data in the AMB in preparation for to amortize the read-write-read DRAM data bus
bursting the data to the DRAM devices. The FIFO can turnaround penalty over a number of write operations.
be filled at a maximum of half of the DRAM burst rate The DRAM Write command pulls the data from the
but is emptied at the full DRAM burst data rate. The head of the FIFO and delivers it to the DRAM devices
Command+Wdata frames contain a data payload of in the clock cycle determined by register settings in the
72-bits that is loaded into the designated write FIFO. AMB. Additional data can be loaded into the FIFO while
The Command+Wdata frames are not required to be data is being delivered to the DRAM. The depth of the
contiguous and may be separated by an arbitrary FIFO supports a continuous burst of 64 transfers to the
number of intervening frames. The write FIFO on each DRAM devices.
DIMM can hold thirty-five (35) 72-bit data payloads.
9.3.3
Simultaneous Read and Write Data Transfers
The FB-DIMM channel provides separate data path for devices on one FB-DIMM can be read at the same time
read completion data and write request data. Because that write data is being written to the DRAM devices on
each FB-DIMM contains an isolated DRAM channel another FB-DIMM.
behind the AMB component, read data from the DRAM
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512-Mbit DDR2 SDRAM
Channel Protocol
9.3.4
DRAM Bus Segment Restrictions
Either one or two ranks of DRAM devices may be two separate ranks to avoid electrical conflict on the
located behind the AMB on an FB-DIMM. These DQS and DQS signals. The turnaround times for dead
devices sit on a DRAM bus segment and must observe times such as read-to-read, read-to-write, and write-to-
the restrictions on the usage of the bus segment. The read are DIMM layout specific and are captured in the
DDR2 SDRAM data sheets should be referenced for SPD EEPROM on the DIMM. These parameters are
details of the restrictions. A dead time is required readable by firmware to direct the appropriate behavior
between read operations for DDR2 devices from the of the host controller.
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512-Mbit DDR2 SDRAM
Reliability, Availability and Serviceability
10
Reliability, Availability and Serviceability
10.1
Overview
The FB-DIMM channel specification provides the command or (write) data. A Status response
comprehensive RAS support including, error detection mechanism is provided to return to the host quick
and frame transmission retry, error logging, error abbreviated status information from all of the AMBs
injection, host add/remove of DIMMs, and the simultaneously. An AMB will discard any commands or
mechanisms for in-operation test and fault recovery data received with a CRC error. For reads, the read
using the Fast Reset capability of the channel. The data that is returned to the host with correct ECC and/or
philosophy for FB-DIMM channel reliability is to provide CRC is the positive acknowledgement that all has
strong error detection of channel transaction errors, transpired without error. If the host does not receive a
and the ability to retry the transactions after automatic read return when scheduled, or if the read return
hardware recovery. Both the northbound and contains an error, the host may reissue the read
southbound links include fail-over mechanisms that can command or the entire read sequence, and/or send a
keep the links running after any one wire fails with sync command to acquire error status from the AMBs.
enough fault detection to maintain reliable operation Error free writes are silently accepted by the AMB with
until repair. The FB-DIMM channel protects data from no response returned to the host. Write data or any
errors using CRC codes generated by both the host commands that are received by the AMB in error will
and the AMB. FB-DIMM provides error detection and cause the AMB to notify the host through Alert frames.
retry mechanisms for commands and data. It further Alert frames are continuously sent until acknowledged
provides an Alert frame reporting mechanism whereby by the host with a Soft Channel Reset command or a
the host is made aware of errors found by an AMB in channel reset.
10.2
Example Error Flows
This section gives an informal overview of error
handling by walking through example write and read
flows. Precise details follow in subsequent sections.
10.2.1
Command Error Flow
The AMB checks for errors in all commands but cannot the host may issue a Soft Channel Reset command or
discriminate one failed type of command from any other a Fast Reset to attempt to recover from the error. The
type of command. All command errors are reported to AMB will close all DRAM pages and place the DRAM
the host and all subsequent commands except Soft devices into self-refresh upon detection of the Fast
Channel Reset are ignored. Command errors are Reset. Following the Fast Reset the host may reissue
reported to the host by a stream of Alert frames in place all read and write transactions since the previous
of normally returned frames. Upon receiving an Alert verified transaction completion and continue normal
response indicating that there was a command error, operation.
10.2.2
Write Data Error Flow
The AMB checks for errors in the write data by to check for link transmission errors in the write data.
computing a 22-bit CRC covering the write data frame. CRC errors detected in the write data are reported to
When in wire fail-over mode a 10-bit CRC is available the host the same as command errors.
10.2.3
Read Error Flow
A read differs from a write primarily in that the AMB of the read data in the specified northbound data frame.
provides a positive acknowledgement that there were If the AMB detects an error in a read command, the
no errors with the read command through the delivery AMB discards the command and Alert frames will be
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512-Mbit DDR2 SDRAM
Reliability, Availability and Serviceability
returned. Upon receiving a read return, the host verifies either be retried or the host may attempt to correct the
that it has received the correct amount of data at the [data] error. Section 5.7 describes the algorithm in
scheduled time, and checks the correctness of the more detail.
data. If any of these are in error the read command may
10.3
Overview of Error Protection, Detection, Correction, and Logging
FB-DIMM uses several different mechanisms for error
protection, detection, correction, and error logging.
Error handling elements are made up of the following:
Southbound Commands and DataB
a) The host computes check bits for commands -14-bit commands except the
CRC on a per command basis. Reduced to 10-bit CRC d) Soft Channel Reset command or until the channel is
in fail-over mode.
reset by the host - The AMB does not evaluate any
b) The host computes check bits for (write) data - 22-bit ECC information sent with the (DRAM) write or attempt
CRC on a per 72-bit write burst basis. Reduced to 10- to correct any errors
bit CRC in fail-over mode.
e) The AMB returns error status on detected errors -
c) The AMB detects CRC errors in southbound CRC errors are reported on the northbound link by
commands or (write) data, and logs information on the inserting Alert frames in place of other content. - Alerts
errors detected - Command or write data errors once continue to be sent until a Soft Channel Reset
observed prevent the AMB from decoding any command is received or the channel is reset.
Northbound Read Data B
FB-DIMM supports three northbound CRC modes to Northbound CRC is only computed for Data frames.
support applications that require different levels of error The Idle, Alert, and Status frame types drive the upper
detection and cost. The frames contain two 72-bit or bit lanes with a known data pattern. During fail-over the
64-bit data payloads. Each data payload is protected by host ignores the missing bit lanes and operates with
either a 12-bit CRC or a 6-bit CRC, with reduced reduced CRC coverage.
protection during fail-over. The three supported a) The host detects an error in the data through CRC
northbound
CRC modes are:
(added by the AMB when not in fail-over mode) or by
ECC provided with the data when read from DRAM
14 bit lanes: 12-bit CRC over 72-bit data payload, fail- (provided by the host with the data when written to
over to 6-bit CRC
DRAM)
13 bit lanes: 6-bit CRC over 72-bit data payload, fail-
over to ECC coverage only
12 bit lanes: 6-bit CRC over 64-bit data payload, no fail-
over
The selection on the mode of operation is controlled by
the host and communicated during the initialization
process as defined in the Initialization chapter.
- The host logs the information on errors detected
- The host corrects the data if possible using the ECC
included within the data
- The host takes whatever other steps deemed prudent
(such as reissuing the command to see if the data
error was transient or scrubbing the DRAM location if it
were a correctable error)
Northbound StatusB
a) The AMB computes a parity bit over its own status - If there were no errors in the status return itself then
information the host would log any error information reported
b) The host detects an error in the northbound status through the status return and take whatever other steps
return
deemed prudent. As noted above, the host is the only
agent that corrects errors in system data. However, to
- The host logs the information on errors detected
- The host takes whatever other steps deemed prudent provide enhanced data integrity, the host may first retry
(such as issuing another sync command ñ up to a limit) a read request upon detecting a data error before
Data Sheet
49
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Reliability, Availability and Serviceability
attempting to correct the error. Furthermore, the host host designers to determine their own memory scrub
may choose to patrol memory, reading memory methodology. The error logging done by the AMB(s)
locations and writing back corrected data for any errors and the host are designed to permit isolation of the
detected. Such patrol ‘scrubbing’ is orthogonal to the error source.
FB-DIMM error handling specification. It is left to the
10.4
Error Protection and Detection Methods
10.4.1
CRC Logic Used on Normal Southbound Frames
See the AMB Buffer Specification for details.
10.4.2
Fail-over Southbound Frames
Fail-over southbound frames consist of 12 transfers of is not available to carry CRC bits in fail-over mode, and
data delivered on the 9 southbound bit lanes. Bit lane 9 the CRC code size is reduced in this mode.
10.4.3
Write and Read Data ECC Error Protection
FB-DIMM makes provision for both read and write data complex ECC algorithms, possibly spread across
to be protected with system defined ECC check bits per multiple channels. The mapping of the data and ECC
data block by supporting 8 check bits per 64 data bits in bits to the DRAM components and channel bit lanes
14 and 13 lane northbound frames. The host generates can enhance the protection provided by the ECC code
the ECC code and passes it along with the write data to to cover DRAM device failures and channel bit lane
the AMB. The AMB will store the ECC along with the failures. Refer to the Southbound Command+Wdata
data in the DRAM memory. The AMB will not check the frame format and Northbound Data frame definitions for
ECC code for errors and the host may use whatever details.
algorithm it chooses. This allows the host to use various
10.5
Southbound Error Handling at the AMB
Errors in southbound frames are handled using the Command+Wdata frame; evaluate each command
following method: within a frame separately.
a) Check for CRC errors in the command. If the AMB c) Check if the command is a Sync command. If Sync
detects an error in the command then discard the entire then respond with Status.
frame, and marks as faulted the commands or data d) Check if the command is targeted for this AMB then
from the previous frame. Process as command error. process command. If the command is an
Log the error. The first CRC error latches the error data unrecognizable command then ignore the command.
contents. The AMB will save the 72-bits plus CRC bits The AMB is not expected to do DRAM protocol
from the previous frame and the command plus CRC checking (e.g., looking for command conflicts such as a
from the current frame. Enter Command Error state: write interrupting a read, etc.)
The AMB is forced to discard [all] subsequent e) Process the next command in the command frame if
commands until the channel is reset. Indicate error by any are left.
returning Alert frames.
f) Process next frame.
b) Determine if the frame is a Command, or
10.5.1
Exiting Command Error State
Once an AMB has entered the Command Error state it hardware setting of the appropriate configuration
will no longer process commands other than the Soft register bit and returning Alert frames. The AMB will
Channel Reset command. Indication that the AMB is in continue to operate in this mode until a Soft Channel
the Command Error state is made manifest by the
Data Sheet
50
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Reliability, Availability and Serviceability
Reset command is received or the host resets the
channel.
10.6
Northbound Error Handling at the AMB
The AMB does not evaluate the data and/or ECC error detection. An AMB does not evaluate the data
information provided to it by the DRAM in response to and/or ECC or CRC information passing through it from
a read command; it will forward the information AMBs further south than it.
supplied by the DRAM unchanged with a CRC for link
10.7
Error Logging
Refer to the AMB Buffer Specification
10.8
Fail-over Mode Operation
During channel initialization each bit lane is tested to bit lane(s) may be used to map out the bad bit lane.
determine if it is functioning properly. If one of the Operation with the redundant bit lane used to map out
southbound bit lanes, northbound bit lanes, or one bit a bad bit lane is described as ‘fail-over mode.’
lane in both directions is non-functional, the redundant
10.8.1
Fail-over Mode Operation on Southbound Lanes
Without the redundant bit lane used for CRC protection within the write data payload and the optional 12-bit
on the southbound lanes, commands continue to be CRC across each 72-bit data block, and the
protected by the 10-bit compound checksum CRC configuration
register
write
data
(within
a
included with each command, DRAM write data Command+Data frame) continues to be protected by a
continues to be protected by system level ECC data 10-bit compound checksum CRC.
10.8.2
Fail-over Mode Operation on Northbound Lanes
The 14-lane northbound frame provides a 12-bit CRC protection. The read data continues to be protected by
over 72-bits of data in normal operation, and a 6- bit system level ECC data within the read data payload,
CRC over 72-bits of data in fail-over mode. The 13-lane and the status response continues to be covered by its
frames are without the redundant bit lane used for CRC 10-bit compound checksum CRC.
10.9
AMB Pass-through Functionality
As noted earlier much of the discussion regarding AMB responses. Each AMB must maintain the compound
behavior was from the viewpoint of having only a single checksums used on the southbound channel. As can
AMB on the channel. FB-DIMM supports from one to be seen from the four simple steps above an AMB does
eight DIMMs and several additional AMB components not check [for errors in] frames moving north that have
per channel. As outlined in the protocol chapter, in been forwarded by another AMB, the frames are either
terms of data movement an AMB is responsible for:
discarded and replaced by frames from this AMB (if it is
- Receiving southbound frames from the host or responsible for providing a read response), selectively
another AMB and in general re-driving those frames to overwritten by this AMB (if this AMB is providing a
a more southerly AMB.
status response), or simply forwarded on to the next
- Evaluating southbound frames for commands or data AMB or host. Because an AMB component does not
targeted to that AMB and for checking all commands evaluate data passing northbound through it, a read
and data for errors.
response or Idle frame being delivered by a more
- Receiving northbound frames from another AMB southerly AMB at the same time as this AMB is simply
(generally) and re-driving those frames to another discarded without error notification. If a given AMB is
northerly AMB or to the host.
the last AMB (southern most AMB) it does not receive
- Supplying frame content for read and status frames from the south and thus does not forward such
Data Sheet
51
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Reliability, Availability and Serviceability
frames in the northerly direction. It is responsible, attention is paid to the reliability of the pass-through
however, for always generating Idle frames whenever it logic. The logic is isolated from the rest of the internal
is not providing a read response or status response AMB functions to ensure that the pass-through
frame in response to a command from the host. These mechanism is functional even if other AMB functions
frames enable easy error detection by the host have failed. This improves the reliability of the channel
whenever a read return or status return is not provided by minimizing the amount of logic that could result in a
by an AMB as scheduled by the host. Particular single point of failure.
10.10
Memory Initialization
The AMB contains
a memory built-in self-test DRAM devices to a known state. Refer to the FBD DFx
(MEMBIST) engine that is used to test the DRAM specification for details.
devices on the DIMM and initialize the contents of the
10.11
Thermal Trip Sensor
The AMB is outfitted with a thermal sensor that to signal thermal warnings whenever the value of the
measures the temperature of the AMB die. A DAC and Thermal Sensor register is higher than the Thermal Trip
comparator mechanism driven from a Finite State register trip points. The AMB provides the warning via
Machine in the AMB periodically adjusts its value to bits in the status response that indicates if the thermal
indicate the temperature of the die. The temperature of condition has been exceeded. Refer to the AMB Buffer
the AMB die can be read at any time in the Thermal Specification for details. Serial Presence Detect Codes
Sensor register. The Thermal Trip registers can be set for FB-DIMM Modules
Data Sheet
52
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
11
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet.
SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined
during production.
List of SPD Code Tables
•
•
•
•
Table 18 “PC2–4200F–444” on Page 53
Table 19 “PC2–4200F–444” on Page 58
Table 20 “PC2–5300F–555” on Page 63
Table 21 “PC2–5300F–555” on Page 68
Table 18
PC2–4200F–444
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–4200F–
444
PC2–4200F–
444
PC2–4200F–
444
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
92
Rev. 1
HEX
92
Rev. 1
HEX
92
0
SPD Size CRC / Total / Used
1
SPD Revision
10
10
10
2
Key Byte / DRAM Device Type
Voltage Level of this Assembly
SDRAM Addressing
09
09
09
3
12
12
12
4
44
44
48
5
Module Physical Attributes
Module Type
23
23
23
6
07
07
07
7
Module Organization
09
11
10
8
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
00
00
00
9
01
01
01
10
11
12
13
14
15
04
04
04
t
CK.MIN (min. SDRAM Cycle Time)
CK.MAX (max. SDRAM Cycle Time)
0F
20
0F
20
0F
20
t
CAS Latencies Supported
CAS.MIN (min. CAS Latency Time)
Write Recovery Values Supported (WR)
33
33
33
t
3C
32
3C
32
3C
32
Data Sheet
53
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 18
PC2–4200F–444 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–4200F–
444
PC2–4200F–
444
PC2–4200F–
444
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
3C
Rev. 1
HEX
3C
42
Rev. 1
HEX
3C
42
16
17
18
19
20
21
22
23
24
25
26
tWR.MIN (Write Recovery Time)
Write Latency Times Supported
Additive Latency Times Supported
42
40
40
40
t
t
t
t
t
t
t
t
RCD.MIN (min. RAS# to CAS# Delay)
RRD.MIN (min. Row Active to Row Active Delay)
RP.MIN (min. Row Precharge Time)
RAS and tRC Extension
3C
3C
1E
3C
1E
1E
3C
3C
00
3C
00
00
RAS.MIN (min. Active to Precharge Time)
RC.MIN (min. Active to Active / Refresh Time)
B4
B4
B4
F0
F0
F0
RFC.MIN LSB (min. Refresh Recovery Time Delay) A4
A4
A4
RFC.MIN MSB (min. Refresh Recovery Time 01
01
01
Delay)
27
28
t
WTR.MIN (min. Internal Write to Read Cmd Delay) 1E
1E
1E
1E
1E
tRTP.MIN (min. Internal Read to Precharge Cmd
1E
Delay)
29
30
31
32
33
34
35
36
37
38
39
40
Burst Lengths Supported
Terminations Supported
Drive Strength Supported
03
07
01
C2
51
78
3C
22
1E
1E
34
1E
03
07
01
C2
51
78
3C
22
1E
1E
34
1E
03
07
01
C2
51
78
3C
22
1E
1E
34
1E
tREFI (avg. SDRAM Refresh Period)
TCASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
∆T0 (DT0) DRAM
∆T2Q (DT2Q) DRAM
∆T2P (DT2P) DRAM
∆T3N (DT3N) DRAM
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) DRAM
∆T5B (DT5B) DRAM
Data Sheet
54
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 18
PC2–4200F–444 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–4200F–
444
PC2–4200F–
444
PC2–4200F–
444
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
20
00
01
00
02
00
10
56
40
36
30
54
6E
60
9A
78
00
00
00
49
00
80
20
00
44
00
80
Rev. 1
HEX
20
00
22
00
02
00
10
56
40
36
30
54
6E
60
9A
78
00
00
00
49
00
80
20
00
44
00
80
Rev. 1
HEX
20
00
22
00
02
00
10
58
42
38
30
62
7A
65
AA
89
00
00
00
49
00
80
20
00
44
00
80
41
42 - 78 Not used
FBDIMM ODT Values
∆T7 (DT7) DRAM
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
Not used
Channel Protocols Supported LSB
Channel Protocols Supported MSB
Back-to-Back Access Turnaround Time
AMB Read Access Delay for DDR2-800
AMB Read Access Delay for DDR2-667
AMB Read Access Delay for DDR2-533
Psi(T-A) AMB
∆TIdle_0 (DT Idle_0) AMB
∆TIdle_1 (DT Idle_1) AMB
∆TIdle_2 (DT Idle_2) AMB
∆TActive_1 (DT Active_1) AMB
∆TActive_2 (DT Active_2) AMB
∆TL0s (DT L0s) AMB
94 - 97 Not used
98
AMB Junction Temperature Maximum (Tjmax)
99
Category Byte
100
101
102
103
104
105
106
Not used
AMB Personality Bytes: Pre-initialization (1)
AMB Personality Bytes: Pre-initialization (2)
AMB Personality Bytes: Pre-initialization (3)
AMB Personality Bytes: Pre-initialization (4)
AMB Personality Bytes: Pre-initialization (5)
AMB Personality Bytes: Pre-initialization (6)
Data Sheet
55
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 18
PC2–4200F–444 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–4200F–
444
PC2–4200F–
444
PC2–4200F–
444
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
40
Rev. 1
HEX
40
Rev. 1
HEX
40
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
AMB Personality Bytes: Post-initialization (1)
AMB Personality Bytes: Post-initialization (2)
AMB Personality Bytes: Post-initialization (3)
AMB Personality Bytes: Post-initialization (4)
AMB Personality Bytes: Post-initialization (5)
AMB Personality Bytes: Post-initialization (6)
AMB Personality Bytes: Post-initialization (7)
AMB Personality Bytes: Post-initialization (8)
AMB Manufacturers JEDEC ID Code LSB
AMB Manufacturers JEDEC ID Code MSB
DIMM Manufacturers JEDEC ID Code LSB
DIMM Manufacturers JEDEC ID Code MSB
Module Manufacturing Location
53
53
53
00
00
00
00
00
00
65
65
65
4C
00
4C
00
4C
00
05
05
05
80
80
80
89
89
89
80
80
80
C1
xx
C1
xx
C1
xx
Module Manufacturing Date Year
xx
xx
xx
Module Manufacturing Date Week
xx
xx
xx
122 -
125
Module Serial Number
xx
xx
xx
126
127
128
129
130
131
132
133
134
135
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Module Product Type, Char #1
Module Product Type, Char #2
Module Product Type, Char #3
Module Product Type, Char #4
Module Product Type, Char #5
Module Product Type, Char #6
Module Product Type, Char #7
Module Product Type, Char #8
94
95
37
32
54
36
34
30
30
30
A8
9D
37
32
54
31
32
38
30
32
4E
A4
37
32
54
32
35
36
30
32
Data Sheet
56
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 18
PC2–4200F–444 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–4200F–
444
PC2–4200F–
444
PC2–4200F–
444
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
48
Rev. 1
HEX
30
Rev. 1
HEX
30
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
Module Product Type, Char #9
Module Product Type, Char #10
Module Product Type, Char #11
Module Product Type, Char #12
Module Product Type, Char #13
Module Product Type, Char #14
Module Product Type, Char #15
Module Product Type, Char #16
Module Product Type, Char #17
Module Product Type, Char #18
Module Revision Code
46
48
48
4E
33
46
46
4E
33
4E
33
2E
37
2E
37
2E
37
41
20
41
41
20
20
20
20
20
20
3x
3x
3x
Test Program Revision Code
xx
xx
xx
DRAM Manufacturers JEDEC ID Code LSB
DRAM Manufacturers JEDEC ID Code MSB
informal AMB content revision tag (MSB)
informal AMB content revision tag (LSB)
Not used
80
80
80
C1
00
C1
00
C1
00
08
08
08
152 -
175
00
00
00
176 -
255
Blank for customer use
FF
FF
FF
Data Sheet
57
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 19
PC2–4200F–444
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–4200F–
444
PC2–4200F–
444
PC2–4200F–
444
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
92
Rev. 1
HEX
92
Rev. 1
HEX
92
0
SPD Size CRC / Total / Used
1
SPD Revision
10
10
10
2
Key Byte / DRAM Device Type
Voltage Level of this Assembly
SDRAM Addressing
09
09
09
3
12
12
12
4
44
44
48
5
Module Physical Attributes
Module Type
23
23
23
6
07
07
07
7
Module Organization
09
11
10
8
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
00
00
00
9
01
01
01
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
04
04
04
t
CK.MIN (min. SDRAM Cycle Time)
CK.MAX (max. SDRAM Cycle Time)
0F
20
0F
20
0F
20
t
CAS Latencies Supported
CAS.MIN (min. CAS Latency Time)
Write Recovery Values Supported (WR)
WR.MIN (Write Recovery Time)
33
33
33
t
3C
32
3C
32
3C
32
t
3C
42
3C
42
3C
42
Write Latency Times Supported
Additive Latency Times Supported
40
40
40
t
t
t
t
t
t
t
RCD.MIN (min. RAS# to CAS# Delay)
RRD.MIN (min. Row Active to Row Active Delay)
RP.MIN (min. Row Precharge Time)
RAS and tRC Extension
3C
1E
3C
00
3C
1E
3C
00
3C
1E
3C
00
RAS.MIN (min. Active to Precharge Time)
RC.MIN (min. Active to Active / Refresh Time)
B4
F0
B4
F0
A4
B4
F0
A4
RFC.MIN LSB (min. Refresh Recovery Time Delay) A4
Data Sheet
58
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 19
PC2–4200F–444 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–4200F–
444
PC2–4200F–
444
PC2–4200F–
444
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
01
Rev. 1
HEX
01
Rev. 1
HEX
01
26
tRFC.MIN MSB (min. Refresh Recovery Time
Delay)
27
28
t
WTR.MIN (min. Internal Write to Read Cmd Delay) 1E
1E
1E
1E
1E
tRTP.MIN (min. Internal Read to Precharge Cmd
1E
Delay)
29
30
31
32
33
34
35
36
37
38
39
40
41
Burst Lengths Supported
Terminations Supported
Drive Strength Supported
03
07
01
C2
51
78
3C
22
1E
1E
34
1E
20
00
01
00
02
00
20
74
62
56
03
07
01
C2
51
78
3C
22
1E
1E
34
1E
20
00
22
00
02
00
18
74
62
56
03
07
01
C2
51
78
3C
22
1E
1E
34
1E
20
00
22
00
02
00
18
74
62
56
tREFI (avg. SDRAM Refresh Period)
TCASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
∆T0 (DT0) DRAM
∆T2Q (DT2Q) DRAM
∆T2P (DT2P) DRAM
∆T3N (DT3N) DRAM
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) DRAM
∆T5B (DT5B) DRAM
∆T7 (DT7) DRAM
42 - 78 Not used
79
80
81
82
83
84
85
86
FBDIMM ODT Values
Not used
Channel Protocols Supported LSB
Channel Protocols Supported MSB
Back-to-Back Access Turnaround Time
AMB Read Access Delay for DDR2-800
AMB Read Access Delay for DDR2-667
AMB Read Access Delay for DDR2-533
Data Sheet
59
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 19
PC2–4200F–444 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–4200F–
444
PC2–4200F–
444
PC2–4200F–
444
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
26
Rev. 1
HEX
26
Rev. 1
HEX
26
87
88
89
90
91
92
93
Psi(T-A) AMB
∆TIdle_0 (DT Idle_0) AMB
∆TIdle_1 (DT Idle_1) AMB
∆TIdle_2 (DT Idle_2) AMB
∆TActive_1 (DT Active_1) AMB
∆TActive_2 (DT Active_2) AMB
∆TL0s (DT L0s) AMB
3F
50
3F
50
3F
50
54
54
54
57
57
57
53
53
53
00
00
00
94 - 97 Not used
00
00
00
98
AMB Junction Temperature Maximum (Tjmax
)
15
15
15
99
Category Byte
49
49
49
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
Not used
00
00
00
AMB Personality Bytes: Pre-initialization (1)
AMB Personality Bytes: Pre-initialization (2)
AMB Personality Bytes: Pre-initialization (3)
AMB Personality Bytes: Pre-initialization (4)
AMB Personality Bytes: Pre-initialization (5)
AMB Personality Bytes: Pre-initialization (6)
15
15
15
00
00
00
03
03
03
00
00
00
00
00
00
00
00
00
AMB Personality Bytes: Post-initialization (1)
AMB Personality Bytes: Post-initialization (2)
AMB Personality Bytes: Post-initialization (3)
AMB Personality Bytes: Post-initialization (4)
AMB Personality Bytes: Post-initialization (5)
AMB Personality Bytes: Post-initialization (6)
AMB Personality Bytes: Post-initialization (7)
AMB Personality Bytes: Post-initialization (8)
AMB Manufacturers JEDEC ID Code LSB
AMB Manufacturers JEDEC ID Code MSB
00
00
00
00
00
00
00
00
00
C0
FF
FF
FF
01
C0
FF
FF
FF
01
C0
FF
FF
FF
01
80
80
80
C1
C1
C1
Data Sheet
60
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 19
PC2–4200F–444 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–4200F–
444
PC2–4200F–
444
PC2–4200F–
444
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
80
Rev. 1
HEX
80
Rev. 1
HEX
80
117
118
119
120
121
DIMM Manufacturers JEDEC ID Code LSB
DIMM Manufacturers JEDEC ID Code MSB
Module Manufacturing Location
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number
C1
C1
C1
xx
xx
xx
xx
xx
xx
xx
xx
xx
122 -
125
xx
xx
xx
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Module Product Type, Char #1
Module Product Type, Char #2
Module Product Type, Char #3
Module Product Type, Char #4
Module Product Type, Char #5
Module Product Type, Char #6
Module Product Type, Char #7
Module Product Type, Char #8
Module Product Type, Char #9
Module Product Type, Char #10
Module Product Type, Char #11
Module Product Type, Char #12
Module Product Type, Char #13
Module Product Type, Char #14
Module Product Type, Char #15
Module Product Type, Char #16
Module Product Type, Char #17
Module Product Type, Char #18
95
F6
37
32
54
36
34
30
30
30
48
46
41
33
2E
37
41
20
20
20
8E
AA
37
32
54
31
32
38
30
32
30
48
46
41
33
2E
37
41
20
20
5E
EE
37
32
54
32
35
36
30
32
30
48
46
41
33
2E
37
41
20
20
Data Sheet
61
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 19
PC2–4200F–444 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–4200F–
444
PC2–4200F–
444
PC2–4200F–
444
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
3x
Rev. 1
HEX
4x
Rev. 1
HEX
4x
146
147
148
149
150
151
Module Revision Code
Test Program Revision Code
xx
xx
xx
DRAM Manufacturers JEDEC ID Code LSB
DRAM Manufacturers JEDEC ID Code MSB
informal AMB content revision tag (MSB)
informal AMB content revision tag (LSB)
Not used
80
80
80
C1
C1
C1
00
00
00
10
10
10
152 -
175
00
00
00
176 -
255
Blank for customer use
FF
FF
FF
Data Sheet
62
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 20
PC2–5300F–555
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–5300F–
555
PC2–5300F–
555
PC2–5300F–
555
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
92
Rev. 1
HEX
92
Rev. 1
HEX
92
0
SPD Size CRC / Total / Used
1
SPD Revision
10
10
10
2
Key Byte / DRAM Device Type
Voltage Level of this Assembly
SDRAM Addressing
09
09
09
3
12
12
12
4
44
44
48
5
Module Physical Attributes
Module Type
23
23
23
6
07
07
07
7
Module Organization
09
11
10
8
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
00
00
00
9
01
01
01
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
04
04
04
t
CK.MIN (min. SDRAM Cycle Time)
CK.MAX (max. SDRAM Cycle Time)
0C
20
0C
20
0C
20
t
CAS Latencies Supported
CAS.MIN (min. CAS Latency Time)
Write Recovery Values Supported (WR)
WR.MIN (Write Recovery Time)
33
33
33
t
3C
42
3C
42
3C
42
t
3C
42
3C
42
3C
42
Write Latency Times Supported
Additive Latency Times Supported
40
40
40
t
t
t
t
t
t
t
RCD.MIN (min. RAS# to CAS# Delay)
RRD.MIN (min. Row Active to Row Active Delay)
RP.MIN (min. Row Precharge Time)
RAS and tRC Extension
3C
1E
3C
00
3C
1E
3C
00
3C
1E
3C
00
RAS.MIN (min. Active to Precharge Time)
RC.MIN (min. Active to Active / Refresh Time)
B4
E4
B4
E4
A4
B4
E4
A4
RFC.MIN LSB (min. Refresh Recovery Time Delay) A4
Data Sheet
63
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 20
PC2–5300F–555 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–5300F–
555
PC2–5300F–
555
PC2–5300F–
555
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
01
Rev. 1
HEX
01
Rev. 1
HEX
01
26
tRFC.MIN MSB (min. Refresh Recovery Time
Delay)
27
28
t
WTR.MIN (min. Internal Write to Read Cmd Delay) 1E
1E
1E
1E
1E
tRTP.MIN (min. Internal Read to Precharge Cmd
1E
Delay)
29
30
31
32
33
34
35
36
37
38
39
40
41
Burst Lengths Supported
Terminations Supported
Drive Strength Supported
03
07
01
C2
53
78
48
2E
26
26
4A
20
22
00
01
00
02
00
10
56
40
36
03
07
01
C2
53
78
48
2E
26
26
4A
20
22
00
22
00
02
00
10
56
40
36
03
07
01
C2
53
78
48
2E
26
26
4A
20
22
00
22
00
02
00
10
58
42
38
tREFI (avg. SDRAM Refresh Period)
TCASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
∆T0 (DT0) DRAM
∆T2Q (DT2Q) DRAM
∆T2P (DT2P) DRAM
∆T3N (DT3N) DRAM
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) DRAM
∆T5B (DT5B) DRAM
∆T7 (DT7) DRAM
42 - 78 Not used
79
80
81
82
83
84
85
86
FBDIMM ODT Values
Not used
Channel Protocols Supported LSB
Channel Protocols Supported MSB
Back-to-Back Access Turnaround Time
AMB Read Access Delay for DDR2-800
AMB Read Access Delay for DDR2-667
AMB Read Access Delay for DDR2-533
Data Sheet
64
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 20
PC2–5300F–555 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–5300F–
555
PC2–5300F–
555
PC2–5300F–
555
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
30
Rev. 1
HEX
30
Rev. 1
HEX
30
87
88
89
90
91
92
93
Psi(T-A) AMB
∆TIdle_0 (DT Idle_0) AMB
∆TIdle_1 (DT Idle_1) AMB
∆TIdle_2 (DT Idle_2) AMB
∆TActive_1 (DT Active_1) AMB
∆TActive_2 (DT Active_2) AMB
∆TL0s (DT L0s) AMB
67
67
76
7F
6E
AA
86
7F
6E
AA
86
8E
73
BB
97
00
00
00
94 - 97 Not used
00
00
00
98
AMB Junction Temperature Maximum (Tjmax
)
00
00
00
99
Category Byte
49
49
49
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
Not used
00
00
00
AMB Personality Bytes: Pre-initialization (1)
AMB Personality Bytes: Pre-initialization (2)
AMB Personality Bytes: Pre-initialization (3)
AMB Personality Bytes: Pre-initialization (4)
AMB Personality Bytes: Pre-initialization (5)
AMB Personality Bytes: Pre-initialization (6)
80
80
80
20
20
20
00
00
00
44
44
44
00
00
00
80
80
80
AMB Personality Bytes: Post-initialization (1)
AMB Personality Bytes: Post-initialization (2)
AMB Personality Bytes: Post-initialization (3)
AMB Personality Bytes: Post-initialization (4)
AMB Personality Bytes: Post-initialization (5)
AMB Personality Bytes: Post-initialization (6)
AMB Personality Bytes: Post-initialization (7)
AMB Personality Bytes: Post-initialization (8)
AMB Manufacturers JEDEC ID Code LSB
AMB Manufacturers JEDEC ID Code MSB
40
40
40
53
53
53
00
00
00
00
00
00
65
65
65
4C
00
4C
00
4C
00
05
05
05
80
80
80
89
89
89
Data Sheet
65
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 20
PC2–5300F–555 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–5300F–
555
PC2–5300F–
555
PC2–5300F–
555
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
80
Rev. 1
HEX
80
Rev. 1
HEX
80
117
118
119
120
121
DIMM Manufacturers JEDEC ID Code LSB
DIMM Manufacturers JEDEC ID Code MSB
Module Manufacturing Location
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number
C1
C1
C1
xx
xx
xx
xx
xx
xx
xx
xx
xx
122 -
125
xx
xx
xx
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Module Product Type, Char #1
Module Product Type, Char #2
Module Product Type, Char #3
Module Product Type, Char #4
Module Product Type, Char #5
Module Product Type, Char #6
Module Product Type, Char #7
Module Product Type, Char #8
Module Product Type, Char #9
Module Product Type, Char #10
Module Product Type, Char #11
Module Product Type, Char #12
Module Product Type, Char #13
Module Product Type, Char #14
Module Product Type, Char #15
Module Product Type, Char #16
Module Product Type, Char #17
Module Product Type, Char #18
6D
A6
37
32
54
36
34
30
30
30
48
46
4E
33
53
41
20
20
20
20
51
AE
37
32
54
31
32
38
30
32
30
48
46
4E
33
53
41
20
20
20
FE
2B
37
32
54
32
35
36
30
32
30
48
46
4E
33
53
41
20
20
20
Data Sheet
66
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 20
PC2–5300F–555 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–5300F–
555
PC2–5300F–
555
PC2–5300F–
555
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
4x
Rev. 1
HEX
4x
Rev. 1
HEX
4x
146
147
148
149
150
151
Module Revision Code
Test Program Revision Code
xx
xx
xx
DRAM Manufacturers JEDEC ID Code LSB
DRAM Manufacturers JEDEC ID Code MSB
informal AMB content revision tag (MSB)
informal AMB content revision tag (LSB)
Not used
80
80
80
C1
C1
C1
00
00
00
08
08
08
152 -
175
00
00
00
176 -
255
Blank for customer use
FF
FF
FF
Data Sheet
67
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 21
PC2–5300F–555
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–5300F–
555
PC2–5300F–
555
PC2–5300F–
555
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
92
Rev. 1
HEX
92
Rev. 1
HEX
92
0
SPD Size CRC / Total / Used
1
SPD Revision
10
10
10
2
Key Byte / DRAM Device Type
Voltage Level of this Assembly
SDRAM Addressing
09
09
09
3
12
12
12
4
44
44
48
5
Module Physical Attributes
Module Type
23
23
23
6
07
07
07
7
Module Organization
09
11
10
8
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
00
00
00
9
01
01
01
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
04
04
04
t
CK.MIN (min. SDRAM Cycle Time)
CK.MAX (max. SDRAM Cycle Time)
0C
20
0C
20
0C
20
t
CAS Latencies Supported
CAS.MIN (min. CAS Latency Time)
Write Recovery Values Supported (WR)
WR.MIN (Write Recovery Time)
33
33
33
t
3C
42
3C
42
3C
42
t
3C
42
3C
42
3C
42
Write Latency Times Supported
Additive Latency Times Supported
40
40
40
t
t
t
t
t
t
t
RCD.MIN (min. RAS# to CAS# Delay)
RRD.MIN (min. Row Active to Row Active Delay)
RP.MIN (min. Row Precharge Time)
RAS and tRC Extension
3C
1E
3C
00
3C
1E
3C
00
3C
1E
3C
00
RAS.MIN (min. Active to Precharge Time)
RC.MIN (min. Active to Active / Refresh Time)
B4
F0
B4
F0
A4
B4
F0
A4
RFC.MIN LSB (min. Refresh Recovery Time Delay) A4
Data Sheet
68
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 21
PC2–5300F–555 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–5300F–
555
PC2–5300F–
555
PC2–5300F–
555
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
01
Rev. 1
HEX
01
Rev. 1
HEX
01
26
tRFC.MIN MSB (min. Refresh Recovery Time
Delay)
27
28
t
WTR.MIN (min. Internal Write to Read Cmd Delay) 1E
1E
1E
1E
1E
tRTP.MIN (min. Internal Read to Precharge Cmd
1E
Delay)
29
30
31
32
33
34
35
36
37
38
39
40
41
Burst Lengths Supported
Terminations Supported
Drive Strength Supported
03
07
01
C2
53
78
48
2E
26
26
4A
20
22
00
01
00
02
00
20
74
62
56
03
07
01
C2
53
78
48
2E
26
26
4A
20
22
00
22
00
02
00
28
74
62
56
03
07
01
C2
53
78
48
2E
26
26
4A
20
22
00
22
00
02
00
28
74
62
56
tREFI (avg. SDRAM Refresh Period)
TCASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
∆T0 (DT0) DRAM
∆T2Q (DT2Q) DRAM
∆T2P (DT2P) DRAM
∆T3N (DT3N) DRAM
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) DRAM
∆T5B (DT5B) DRAM
∆T7 (DT7) DRAM
42 - 78 Not used
79
80
81
82
83
84
85
86
FBDIMM ODT Values
Not used
Channel Protocols Supported LSB
Channel Protocols Supported MSB
Back-to-Back Access Turnaround Time
AMB Read Access Delay for DDR2-800
AMB Read Access Delay for DDR2-667
AMB Read Access Delay for DDR2-533
Data Sheet
69
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 21
PC2–5300F–555 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–5300F–
555
PC2–5300F–
555
PC2–5300F–
555
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
26
Rev. 1
HEX
26
Rev. 1
HEX
26
87
88
89
90
91
92
93
Psi(T-A) AMB
∆TIdle_0 (DT Idle_0) AMB
∆TIdle_1 (DT Idle_1) AMB
∆TIdle_2 (DT Idle_2) AMB
∆TActive_1 (DT Active_1) AMB
∆TActive_2 (DT Active_2) AMB
∆TL0s (DT L0s) AMB
3F
50
3F
50
3F
50
54
54
54
57
57
57
53
53
53
00
00
00
94 - 97 Not used
00
00
00
98
AMB Junction Temperature Maximum (Tjmax
)
15
15
15
99
Category Byte
49
49
49
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
Not used
00
00
00
AMB Personality Bytes: Pre-initialization (1)
AMB Personality Bytes: Pre-initialization (2)
AMB Personality Bytes: Pre-initialization (3)
AMB Personality Bytes: Pre-initialization (4)
AMB Personality Bytes: Pre-initialization (5)
AMB Personality Bytes: Pre-initialization (6)
15
15
15
00
00
00
03
03
03
00
00
00
00
00
00
00
00
00
AMB Personality Bytes: Post-initialization (1)
AMB Personality Bytes: Post-initialization (2)
AMB Personality Bytes: Post-initialization (3)
AMB Personality Bytes: Post-initialization (4)
AMB Personality Bytes: Post-initialization (5)
AMB Personality Bytes: Post-initialization (6)
AMB Personality Bytes: Post-initialization (7)
AMB Personality Bytes: Post-initialization (8)
AMB Manufacturers JEDEC ID Code LSB
AMB Manufacturers JEDEC ID Code MSB
00
00
00
00
00
00
00
00
00
C0
FF
FF
FF
01
C0
FF
FF
FF
01
C0
FF
FF
FF
01
80
80
80
C1
C1
C1
Data Sheet
70
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 21
PC2–5300F–555 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–5300F–
555
PC2–5300F–
555
PC2–5300F–
555
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
80
Rev. 1
HEX
80
Rev. 1
HEX
80
117
118
119
120
121
DIMM Manufacturers JEDEC ID Code LSB
DIMM Manufacturers JEDEC ID Code MSB
Module Manufacturing Location
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number
C1
C1
C1
xx
xx
xx
xx
xx
xx
xx
xx
xx
122 -
125
xx
xx
xx
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Module Product Type, Char #1
Module Product Type, Char #2
Module Product Type, Char #3
Module Product Type, Char #4
Module Product Type, Char #5
Module Product Type, Char #6
Module Product Type, Char #7
Module Product Type, Char #8
Module Product Type, Char #9
Module Product Type, Char #10
Module Product Type, Char #11
Module Product Type, Char #12
Module Product Type, Char #13
Module Product Type, Char #14
Module Product Type, Char #15
Module Product Type, Char #16
Module Product Type, Char #17
Module Product Type, Char #18
E6
A2
37
32
54
36
34
30
30
30
48
46
41
33
53
41
20
20
20
20
76
0B
37
32
54
31
32
38
30
32
30
48
46
41
33
53
41
20
20
20
A6
4F
37
32
54
32
35
36
30
32
30
48
46
41
33
53
41
20
20
20
Data Sheet
71
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
SPD Codes
Table 21
PC2–5300F–555 (cont’d)
Product Type
Organization
Label Code
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–5300F–
555
PC2–5300F–
555
PC2–5300F–
555
JEDEC SPD Revision
Byte# Description
Rev. 1
HEX
5x
Rev. 1
HEX
5x
Rev. 1
HEX
5x
146
147
148
149
150
151
Module Revision Code
Test Program Revision Code
xx
xx
xx
DRAM Manufacturers JEDEC ID Code LSB
DRAM Manufacturers JEDEC ID Code MSB
informal AMB content revision tag (MSB)
informal AMB content revision tag (LSB)
Not used
80
80
80
C1
C1
C1
00
00
00
10
10
10
152 -
175
00
00
00
176 -
255
Blank for customer use
FF
FF
FF
Data Sheet
72
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Package Outline
12
Package Outline
All Components are surface mounted on one or both SDRAM devices are located near the device power
sides of the PCB and positioned on the PCB to meet pins. The AMB device in the center of the DIMM has a
the minimum and maximum trace lengths required for metal Heat Sink. The FB-DIMM mechanical outlines
DDR2 SDRAM signals. Bypass capacitors for DDR2 are consistent with JEDEC MO-256.
Table 22
Raw Card Reference
JEDEC Raw Card
Infineon PCB
Dimensions
Width [mm]
Height [mm] Thickness [mm]
Notes
1)
R/C A
R/C B
R/C H
L-DIM-240-21 Figure 16 133.35
L-DIM-240-22 Figure 17 133.35
L-DIM-240-25 Figure 18 133.35
30.35
30.35
30.35
7.1
7.1
7.1
1)
1)
1) Thickness includes Infineon Heat Sink. Some early production modules with Jedec Heatspreader may be
thicker up to 8.2mm.
Attention: Heat Sink heat up during operation. When unplugging a DIMM from a system direct skin contact
should be avoided until the Heat Sink has reached room temperature.
Attention: The Heat Sink is mechanically loaded. Do not remove. Removal of the clip may cause injuries.
Attention: Any mechanical stress on the Heat Sink should be avoided. Touching the Heat Sink while
plugging or unplugging the module may permanently damage the DIMM.
Data Sheet
73
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Package Outline
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Figure 16 Package Outline L-DIM-240-21
Note: Please contact your sales or marketing representative for more details on package dimensions.
Data Sheet
74
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Package Outline
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Figure 17 Package Outline L-DIM-240-22
Note: Please contact your sales or marketing representative for more details on package dimensions.
Data Sheet
75
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
Package Outline
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Figure 18 Package Outline L-DIM-240-25
Note: Please contact your sales or marketing representative for more details on package dimensions.
Data Sheet
76
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
HYS72T[64/128/256]0[00/20]HF[A/N]–[3.7/3S]–A
512-Mbit DDR2 SDRAM
DDR2 Nomencature
13
DDR2 Nomencature
Table 23
Nomenclature Fields and Examples
Field Number
Example for
1
2
3
T
T
4
5
6
7
0
0
8
9
10
–5
–5
11
Micro-DIMM
DDR2 DRAM
HYS
HYB
64
18
64
512
0
2
K
A
M
C
–A
16
1) Multiplying “Memory Density per I/O” with “Module Data
Width” and dividing by 8 for Non-ECC and 9 for ECC
modules gives the overall module memory density in
MBytes as listed in column “Coding”.
Table 24
DDR2 DIMM Nomenclature
Values Coding
Field Description
1
INFINEON
HYS
Constant
Modul Prefix
2
Module Data
Width [bit]
64
72
T
Non-ECC
ECC
Table 25
DDR2 DRAM Nomenclature
Values Coding
Field Description
3
4
DRAM
Technology
DDR2
1
2
3
4
INFINEON
Component Prefix
HYB
Constant
SSTL_18
DDR2
Memory Density
per I/O [Mbit];
Module Density1)
32
256 MByte
512 MByte
1 GByte
Interface Voltage 18
[V]
64
DRAM
Technology
T
128
256
512
0 .. 9
2 GByte
Component
256
512
1G
2G
40
256 Mbit
512 Mbit
1 Gbit
2 Gbit
×4
4 GByte
Density [Mbit]
5
6
Raw Card
Generation
Look up table
Number of Module 0, 2, 4 1, 2, 4
Ranks
5+6 Number of I/Os
7
8
Product Variations 0 .. 9
Look up table
80
×8
Package,
A .. Z
Look up table
16
×16
Lead-Free Status
7
8
Product Variations 0 .. 9
Look up table
First
9
Module Type
Speed Grade
Die Revision
D
SO-DIMM
Die Revision
A
B
C
M
Micro-DIMM
Registered
Second
R
9
Package,
FBGA,
lead-containing
U
Unbuffered
Lead-Free Status
F
Fully Buffered
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
PC2–4200 4–4–4
PC2–3200 3–3–3
First
F
FBGA, lead-free
DDR2-800 6-6-6
DDR2-667 4-4-4
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
10
11
–2.5
–3
–3S
–3.7
–5
–A
–B
10
Speed Grade
–2.5
–3
–3S
–3.7
–5
Second
Data Sheet
77
Rev. 1.41, 2006-01
08122004-IISJ-Y0AE
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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