HYS72T256020HR-3S-A_技术文档

Data Sheet, Rev. 1.2, Sep. 2005

HYS72T64000HR–[3/3S/3.7/5]–A

HYS72T1280[0/2]0HR–[3/3S/3.7/5]–A

HYS72T256[0/2]20HR–[3/3S/3.7/5]–A

240-Pin Registered DDR2 SDRAM Modules

DDR2 SDRAM

RDIMM SDRAM

RoHs Compliant

Memory Products

N e v e r s t o p t h i n k i n g .

Edition 2005-09

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

HYS72T64000HR–[3/3S/3.7/5]–A HYS72T1280[0/2]0HR–[3/3S/3.7/5]–A HYS72T256[0/2]20HR–[3/3S/3.7/5]–

A

Revision History: 2005-09, Rev. 1.2

Previous Version: 1.1

Page

42

Subjects (major changes since last revision)

updated “SPD Codes” on Page 42

59

updated Figure 9 “Package Outline Raw Card A-F L-DIM-240-11” on Page 59

updated Figure 10 “Package Outline Raw Card B-G L-DIM-240-12” on Page 60

updated Figure 11 “Package Outline Raw Card C-H L-DIM-240-13” on Page 61

updated Figure 12 “Package Outline Raw Card J L-DIM-240-20” on Page 62

updated Figure 13 “Package Outline Raw Card L L-DIM-240-40” on Page 63

60

61

62

63

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Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send us your proposal (including a reference to this document) to:

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Template: mp_a4_s_rev314 / 3 / 2005-05-02

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Table of Contents

1

1.1

1.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2

2.1

2.2

Pin Configuration and Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3

3.1

3.2

3.3

3.3.1

3.3.2

3.3.3

3.4

3.4.1

3.4.2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

I

_DDSpecifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

_DDTest Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

I

4

5

6

SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Data Sheet

4

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

240-Pin Registered DDR2 SDRAM Modules

DDR2 SDRAM

HYS72T64000HR–[3/3S/3.7/5]–A

HYS72T1280[0/2]0HR–[3/3S/3.7/5]–A

HYS72T256[0/2]20HR–[3/3S/3.7/5]–A

1

Overview

This chapter gives an overview of the 240-pin Registered DDR2 SDRAM Modules product family and describes

its main characteristics.

1.1

Features

•

240-pin PC2-5300, PC2-4200 and PC2-3200

DDR2 SDRAM memory modules for PC,

Workstation and Server main memory applications

One rank 64M x 72, 128M x 72 and two ranks

128M × 72 and 256M × 72 module organization and

64M × 4, 64M × 8, 128M × 4 chip organization

512 MByte, 1 GByte and 2 GByte modules built

with 512-Mbit DDR2 SDRAMs in P-TFBGA-60

chipsize packages.

Standard Double-Data-Rate-Two Synchronous

DRAMs (DDR2 SDRAM) with a single + 1.8 V

(± 0.1 V) power supply

All speed grades faster than DDR2-400 comply with

DDR2–400 timing specifications.

•

Programmable CAS Latencies (3, 4 & 5), Burst

Length (4 & 8) and Burst Type

•

Auto Refresh (CBR) and Self Refresh

All inputs and outputs SSTL_18 compatible

Off-Chip Driver Impedance Adjustment (OCD) and

On-Die Termination (ODT)

Serial Presence Detect with E²PROM

RDIMM Dimensions (nominal):

•

30,00 mm high, 133.35 mm wide

•

Based on standard reference layouts Raw Card “A-

F”, “B-G”, “C-H”, “J” & “L”

RoHS compliant products¹⁾

Table 1

Performance for DDR2–667

Product Type Speed Code

Speed Grade

–3

–3S

Unit

—

PC2–5300 4–4–4

PC2–5300 5–5–5

max. Clock Frequency @CL5 f_CK5333

@CL4 f_CK4333

333

266

200

15

MHz

ns

@CL3 f_CK3200

min. RAS-CAS-Delay

min. Row Precharge Time

min. Row Active Time

min. Row Cycle Time

t_RCD12

t_RP12

t_RAS45

t_RC57

15

ns

45

ns

60

ns

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic

equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January

2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and

polybrominated biphenyl ethers.

Data Sheet

5

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

OverviewFeatures

Table 2

Performance for DDR2-533 and DDR2-400

Product Type Speed Code

Speed Grade

–3.7

–5

Units

—

PC2–4200 4–4–4

PC2–3200 3–3–3

Max. Clock Frequency

@CL5

@CL4

@CL3

f_CK5266

200

15

MHz

ns

f_CK4266

f_CK3200

t_RCD15

Min. RAS-CAS-Delay

Min. Row Precharge Time

Min. Row Active Time

Min. Row Cycle Time

t_RP

t_RAS45

t_RC60

15

ns

40

ns

55

ns

Data Sheet

6

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

OverviewDescription

1.2

Description

The INFINEON HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A module family are Registered DIMM modules

“RDIMMs” with 30,0 mm height based on DDR2 technology. DIMMs are available as ECC modules in 64M x 72

(512 MByte), 128M x 72 (1 GByte) and 256M x 72 (2 GByte) organization and density, intended for mounting into

240-Pin connector sockets.

The memory array is designed with 512-Mbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. All control

and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This

reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors

are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E²PROM device

using the 2-pin I²C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes

are available to the customer.

Table 3

Ordering Information for RoHS Compliant Products

Product Type¹⁾

Compliance Code²⁾

Description SDRAM Technology

PC2-5300

HYS72T64000HR–3–A

HYS72T128000HR–3–A

HYS72T128020HR–3–A

HYS72T256220HR–3–A

HYS72T64000HR-3S-A

HYS72T128000HR-3S-A

HYS72T128020HR-3S-A

HYS72T256020HR-3S-A

HYS72T256220HR-3S-A

PC2–4200

512 MB 1R×8 PC2–5300R–444–12–F0 1 Rank, ECC 512 Mbit (×8)

1 GB 1R×4 PC2–5300R–444–12–H0

1 GB 2R×8 PC2–5300R–444–12–G0

2 GB 2R×4 PC2–5300R–555–12–J1

1 Rank, ECC 512 Mbit (×4)

2 Ranks, ECC 512 Mbit (×8)

2 Ranks, ECC 512 Mbit (×4)

512 MB 1R×8 PC2–5300R–555–12–F0 1 Rank, ECC 512 Mbit (×8)

1 GB 1R×4 PC2–5300R–555–12–H0

1 GB 2R×8 PC2–5300R–555–12–G0

2 GB 2R×4 PC2–5300R–555–12–L0

2 GB 2R×4 PC2–5300R–555–12–J1

1 Rank, ECC 512 Mbit (×4)

2 Ranks, ECC 512 Mbit (×8)

2 Ranks, ECC 512 Mbit (×4)

HYS72T64000HR–3.7–A

HYS72T128000HR–3.7–A

HYS72T128020HR–3.7–A

HYS72T256020HR–3.7–A

HYS72T256220HR–3.7–A

PC2-3200

512 MB 1R×8 PC2–4200R–444–12–F0 1 Rank, ECC 512 Mbit (×8)

1 GB 1R×4 PC2–4200R–444–12–H0

1 GB 2R×4 PC2–4200R–444–12–G0

2 GB 2R×4 PC2–4200R–444–12–J1

1 Rank, ECC 512 Mbit (×4)

2 Ranks, ECC 512 Mbit (×4)

HYS72T64000HR–5–A

HYS72T128000HR–5–A

HYS72T128020HR–5–A

HYS72T256020HR–5–A

HYS72T256220HR–5–A

512 MB 1R×8 PC2–3200R–333–12–F0 1 Rank, ECC 512 Mbit (×8)

1 GB 1R×4 PC2–3200R–333–12–H0

1 GB 2R×8 PC2–3200R–333–12–G0

2 GB 2R×4 PC2–3200R–333–12–L0

2 GB 2R×4 PC2–3200R–333–12–J1

1 Rank, ECC 512 Mbit (×4)

2 Ranks, ECC 512 Mbit (×8)

2 Ranks, ECC 512 Mbit (×4)

1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T64000HR–5–A, indicating

Rev. “A” dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see

Chapter 6 of this data sheet.

2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–11–

F0”, where 4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column

Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the

latest JEDEC SPD Revision 1.1 and produced on the Raw Card “F”

Data Sheet

7

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

OverviewDescription

Table 4

Address Format

DIMM

Module

Memory ECC/

# of

# of row/bank/columns bits Raw Card

Density

Organization

Ranks

Non-ECC

SDRAMs

512 MB

1 GB

64M × 72

1

2

ECC

9

14/2/10

14/2/11

14/2/10

14/2/11

A-F

B-H

C-G

L

128M × 72

256M × 72

18

36

1 GB

2 GB

J

Table 5

Components on Modules ¹⁾

Product Type²⁾

DRAM Components²⁾

HYB18T512800AF

HYB18T512400AF

HYB18T512800AF

HYB18T512400AF

DRAM Density

512 Mbit

DRAM Organization

64M × 8

HYS72T64000HR

HYS72T128000HR

HYS72T128020HR

HYS72T256020HR

HYS72T256220HR

512 Mbit

128M × 4

512 Mbit

64M × 8

512 Mbit

128M × 4

512 Mbit

128M × 4

1) For a detailed description of all available functions of the DRAM components on these modules see the component data

sheet.

2) Green Product

Data Sheet

8

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

2

Pin Configuration and Block Diagrams

2.1

Pin Configuration

The pin configuration of the Registered DDR2 SDRAM explained in Table 7 and Table 8 respectively. The pin

DIMM is listed by function in Table 6 (240 pins). The numbering is depicted in Figure 1.

abbreviations used in columns Pin and Buffer Type are

Table 6

Pin Configuration of RDIMM

Pin or Ball No.

Name Pin

Buffer Function

Type Type

Clock Signals

185

186

CK0

I

SSTL

Clock Signal CK0, Complementary Clock Signal CK0

The system clock inputs. All address and command lines are

sampled on the cross point of the rising edge of CK and the falling

edge of CK. A Delay Locked Loop (DLL) circuit is driven from the

clock inputs and output timing for read operations is synchronized

to the input clock.

52

CKE0

CKE1

I

SSTL

Clock Enables 1:0

Activates the DDR2 SDRAM CK signal when HIGH and

deactivates the CK signal when LOW. By deactivating the clocks,

CKE0 initiates the Power Down Mode or the Self Refresh Mode.

171

Note:2-Ranks module

Not Connected

NC

—

Note:1-Rank module

Control Signals

193

76

S0

S1

I

SSTL

Chip Select Rank 1:0

Enables the associated DDR2 SDRAM command decoder when

LOW and disables the command decoder when HIGH. When the

command decoder is disabled, new commands are ignored but

previous operations continue. Rank 0 is selected by S0; Rank 1 is

selected by S1. The input signals also disable all outputs (except

CKE and ODT) of the register(s) on the DIMM when both inputs are

high. When S is HIGH, all register outputs (except CK, ODT and

Chip select) remain in the previous state.

Note:2-Ranks module

Not Connected

NC

—

Note:1-Rank module

192

74

RAS

CAS

WE

I

SSTL

Row Address Strobe (RAS), Column Address Strobe (CAS),

Write Enable (WE)

When sampled at the cross point of the rising edge of CK, and

falling edge of CK, RAS, CAS and WE define the operation to be

executed by the SDRAM.

73

Data Sheet

9

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 6

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name Pin

Type Type

RESET I CMOS Register Reset

The RESET pin is connected to the RST pin on the register and to

Buffer Function

18

the OE pin on the PLL. When LOW, all register outputs will be

driven LOW and the PLL clocks to the DRAMs and the register(s)

will be set to low-level. The PLL will remain synchronized with the

input clock.

Address Signals

71

BA0

BA1

BA2

I

SSTL

Bank Address Bus 1:0

Selects internal SDRAM memory bank

190

54

Bank Address Bus 2

Greater than 512Mb DDR2 SDRAMS

NC

I

SSTL

Not Connected

Less than 1Gb DDR2 SDRAMS

188

183

63

A0

I

SSTL

Address Bus 12:0, Address Signal 10/AutoPrecharge

During a Bank Activate command cycle, defines the row address

when sampled at the crosspoint of the rising edge of CK and falling

edge of CK. During a Read or Write command cycle, defines the

column address when sampled at the cross point of the rising edge

of CK and falling edge of CK. In addition to the column address, AP

is used to invoke autoprecharge operation at the end of the burst

read or write cycle. If AP is HIGH, autoprecharge is selected and

BA[1:0] defines the bank to be precharged. If AP is LOW,

autoprecharge is disabled. During a Precharge command cycle,

AP is used in conjunction with BA[1:0] to control which bank(s) to

precharge. If AP is HIGH, all banks will be precharged regardless

of the state of BA[1:0] inputs. If AP is LOW, then BA[1:0] are used

to define which bank to precharge.

A1

A2

182

61

A3

A4

60

A5

180

58

A6

A7

179

177

70

A8

A9

A10

AP

A11

A12

A13

57

176

196

Address Signal 13

Note:modules based on ×4, ×8

Not Connected

NC

A14

NC

I

—

Note:modules based on ×16

Address Signal 14

174

SSTL

—

Note:2 Gbit based module

Not Connected

NC

Note:1 Gbit based module or smaller

Data Sheet

10

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 6

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name Pin

Buffer Function

Type Type

Data Signals

3

DQ0

I/O

SSTL

Data Bus 63:0

Data Input/Output pins

4

DQ1

9

DQ2

10

DQ3

122

123

128

129

12

DQ4

DQ5

DQ6

DQ7

DQ8

13

DQ9

21

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

22

131

132

140

141

24

25

30

31

143

144

149

150

33

34

39

40

152

153

158

159

80

81

86

87

199

200

205

Data Sheet

11

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 6

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name Pin

Buffer Function

Type Type

206

89

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O

SSTL

Data Bus 63:0

90

95

96

208

209

214

215

98

99

107

108

217

218

226

227

110

111

116

117

229

230

235

236

Check Bits

42

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O

SSTL

Check Bits 7:0

Check Bit Input / Output pins

43

Note:NC on Non-ECC module

48

49

161

162

167

168

Data Sheet

12

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 6

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name Pin

Buffer Function

Type Type

Data Strobe Bus

7

DQS0 I/O

DQS1 I/O

DQS2 I/O

DQS3 I/O

DQS4 I/O

DQS5 I/O

DQS6 I/O

DQS7 I/O

DQS8 I/O

DQS9 I/O

SSTL

Data Strobes 17:0

The data strobes, associated with one data byte, sourced with data

transfers. In Write mode, the data strobe is sourced by the

controller and is centered in the data window. In Read mode the

data strobe is sourced by the DDR2 SDRAM and is sent at the

leading edge of the data window. DQS signals are complements,

and timing is relative to the crosspoint of respective DQS and DQS.

If the module is to be operated in single ended strobe mode, all

DQS signals must be tied on the system board to VSS through a

20 ohm to 10 Kohm resistor and DDR2 SDRAM mode registers

programmed appropriately.

6

16

15

28

27

37

36

84

83

93

92

105

104

114

113

46

45

126

Note:See block diagram for corresponding DQ signals

Not Connected

Note:×8 based DIMMs only

Not Connected

NC

—

Note:×4 based DIMMs

Not Connected

135

147

156

203

DQS10 I/O

SSTL

—

Note:×8 based DIMMs only

Not Connected

NC

Note:×4 based DIMMs

Not Connected

DQS11 I/O

SSTL

—

Note:×8 based DIMMs only

Not Connected

NC

Note:×4 based DIMMs

Not Connected

DQS12 I/O

SSTL

—

Note:×8 based DIMMs only

Not Connected

NC

Note:×4 based DIMMs

Not Connected

DQS13 I/O

SSTL

—

Note:×8 based DIMMs only

Not Connected

NC

Note:×4 based DIMMs

Data Sheet

13

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 6

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name Pin

Buffer Function

Type Type

212

DQS14 I/O

SSTL

—

Not Connected

Note:×8 based DIMMs only

Not Connected

NC

Note:×4 based DIMMs

Not Connected

224

233

165

DQS15 I/O

SSTL

—

Note:×8 based DIMMs only

Not Connected

NC

Note:×4 based DIMMs

Not Connected

DQS16 I/O

SSTL

—

Note:×8 based DIMMs only

Not Connected

NC

Note:×4 based DIMMs

Not Connected

DQS17 I/O

SSTL

—

Note:×8 based DIMMs only

Not Connected

NC

Note:×4 based DIMMs

Data Strobes 17:9

Note:×4 based module

125

134

146

155

202

211

223

232

164

125

134

146

155

202

211

223

232

164

DQS9 I/O

DQS10 I/O

DQS11 I/O

DQS12 I/O

DQS13 I/O

DQS14 I/O

DQS15 I/O

DQS16 I/O

DQS17 I/O

SSTL

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

DM8

I

Data Masks 7:0

The data write masks, associated with one data byte. In Write

mode, DM operates as a byte mask by allowing input data to be

written if it is LOW but blocks the write operation if it is HIGH. In

Read mode, DM lines have no effect.

Note:×8 based module

Data Sheet

14

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 6

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name Pin

Buffer Function

Type Type

EEPROM

120

SCL

SDA

I

CMOS Serial Bus Clock

This signal is used to clock data into and out of the SPD EEPROM.

Serial Bus Data

119

I/O

OD

This is a bidirectional pin used to transfer data into or out of the

SPD EEPROM. A resistor must be connected from SDA to

VDDSPD on the motherboard to act as a pull-up.

239

SA0

SA1

SA2

I

CMOS Serial Address Select Bus 2:0

These signals are tied at the system planar to either VSS or

VDDSPD to configure the serial SPD EEPROM address range

240

CMOS

101

Power Supplies

1

VREF AI

—

I/O Reference Voltage

Reference voltage for the SSTL-18 inputs.

238

VDDSP PWR —

D

EEPROM Power Supply

Serial EEPROM positive power supply, wired to a separated power

pin at the connector which supports from 1.7 Volt to 3.6 Volt.

51, 56, 62, 72, 75, VDDQ PWR —

78, 170, 175,,

I/O Driver Power Supply

Power and ground for the DDR SDRAM

181, 191, 194

53, 59, 64, 67, 69, VDD

172, 178, 184,,

187, 189, 197

PWR —

GND —

Power Supply

Power and ground for the DDR SDRAM

2, 5, 8, 11, 14, 17, VSS

20, 23, 26, 29, 32,

35, 38, 41, 44, 47,

50, 65, 66, 79, 82,

85, 88, 91, 94, 97,

100, 103, 106,

109, 112, 115,

118, 121, 124,

127, 130, 133,

136, 139, 142,

145, 148, 151,

154, 157, 160,

163, 166, 169,

198, 201, 204,

207, 210, 213,

216, 219, 222,

225, 228, 231,

234, 237

Ground Plane

Power and ground for the DDR SDRAM

Data Sheet

15

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 6

Pin Configuration of RDIMM (cont’d)

Name Pin Buffer Function

Type Type

Pin or Ball No.

Other Pins

19, 55, 68, 102,

137, 138, 173,

220, 221

NC

—

Not connected

Pins not connected on Infineon RDIMM’s

195

77

ODT0

ODT1

I

SSTL

On-Die Termination Control 1:0

Asserts on-die termination for DQ, DM, DQS, and DQS signals if

enabled via the DDR2 SDRAM mode register.

Note:2-Ranks module

NC

—

Note:1-Rank modules

Table 7

Abbreviations for Buffer Type

Description

Abbreviation

SSTL

Serial Stub Terminated Logic (SSTL_18)

CMOS Levels

CMOS

OD

Open Drain. The corresponding pin has 2 operational states, active low and

tristate, and allows multiple devices to share as a wire-OR.

Table 8

Abbreviations for Pin Type

Abbreviation

Description

I

Standard input-only pin. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

O

I/O

AI

PWR

GND

NU

NC

Ground

Not Usable

Not Connected

Data Sheet

16

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

62%&

$1ꢀ

6₃₃

ꢃ 0IN ꢀꢀꢁ

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ꢃ 0IN ꢀꢀꢅ

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ꢃ 0IN ꢀꢀꢆ

ꢃ 0IN ꢀꢁꢁ

ꢃ 0IN ꢀꢁꢄ

ꢃ 0IN ꢀꢁꢅ

ꢃ 0IN ꢀꢁꢂ

ꢃ 0IN ꢀꢁꢆ

0IN ꢁꢇꢁ ꢃ 6₃₃

0IN ꢁꢇꢇ ꢃ $1ꢈ

6₃₃

ꢃ 0IN ꢀꢀꢇ

ꢃ 0IN ꢀꢀꢈ

0IN ꢁꢇꢄ ꢃ $1ꢅ

ꢃ

$1ꢁ

$13ꢀ ꢃ 0IN ꢀꢀꢉ

0IN ꢁꢇꢈ 6₃₃

0IN ꢁꢇꢅ ꢃ $-ꢀꢋ$13ꢆ

0IN ꢁꢇꢂ ꢃ 6₃₃

0IN ꢁꢇꢉ ꢃ .#ꢋ$13ꢆ

$13ꢀ

$1ꢇ

6₃₃

ꢃ

6₃₃

ꢃ 0IN ꢀꢀꢊ

ꢃ 0IN ꢀꢁꢀ

ꢃ 0IN ꢀꢁꢇ

ꢃ 0IN ꢀꢁꢈ

0IN ꢁꢇꢊ $1ꢉ

0IN ꢁꢇꢆ ꢃ $1ꢂ

0IN ꢁꢄꢁ ꢃ $1ꢁꢇ

0IN ꢁꢄꢄ ꢃ 6₃₃

$1ꢄ

$1ꢊ

6₃₃

0IN ꢁꢄꢀ ꢃ 6₃₃

ꢃ

0IN ꢁꢄꢇ $1ꢁꢄ

$1ꢆ

$13ꢁ

6₃₃

0IN ꢁꢄꢈ ꢃ $-ꢁꢋ$13ꢁꢀ

0IN ꢁꢄꢉ ꢃ 6₃₃

0IN ꢁꢄꢅ ꢃ .#ꢋ$13ꢁꢀ

0IN ꢁꢄꢂ ꢃ .#

0IN ꢁꢄꢆ ꢃ 6₃₃

$13ꢁ ꢃ 0IN ꢀꢁꢉ

2%3%4 ꢃ 0IN ꢀꢁꢊ

0IN ꢁꢄꢊ ꢃ .#

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6₃₃

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0IN ꢁꢈꢀ ꢃ $1ꢁꢈ

ꢃ

0IN ꢁꢈꢇ 6₃₃

ꢃ

$1ꢁꢀ

6₃₃

$1ꢁꢅ

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0IN ꢀꢇꢁ

ꢃ

$1ꢁꢁ

$1ꢁꢉ

6₃₃

0IN ꢀꢇꢇ

ꢃ

0IN ꢀꢇꢄ

0IN ꢁꢈꢄ ꢃ $1ꢇꢀ

0IN ꢁꢈꢅ ꢃ 6₃₃

ꢃ

0IN ꢀꢇꢈ

0IN ꢁꢈꢈ $1ꢇꢁ

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$13ꢇ

6₃₃

ꢃ 0IN ꢀꢇꢅ

ꢃ 0IN ꢀꢇꢂ

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ꢃ 0IN ꢀꢄꢁ

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ꢃ 0IN ꢀꢄꢅ

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ꢃ 0IN ꢀꢄꢆ

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ꢃ 0IN ꢀꢉꢁ

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ꢃ

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&

2

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3

)

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0IN ꢁꢅꢁ ꢃ 6₃₃

0IN ꢁꢅꢄ ꢃ $1ꢇꢆ

0IN ꢁꢅꢅ ꢃ $-ꢄꢋ$13ꢁꢇ

0IN ꢁꢅꢂ ꢃ 6₃₃

"

!

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+

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$13ꢇ

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6₃₃

ꢃ

0IN ꢁꢅꢇ $1ꢇꢊ

ꢃ

$1ꢇꢅ

$13ꢄ

6₃₃

0IN ꢁꢅꢈ 6₃₃

ꢃ

0IN ꢁꢅꢉ .#ꢋ$13ꢁꢇ

$13ꢄ

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6₃₃

ꢃ

0IN ꢁꢅꢊ $1ꢄꢀ

$

%

$

%

0IN ꢁꢅꢆ ꢃ $1ꢄꢁ

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0IN ꢁꢉꢄ ꢃ 6₃₃

ꢃ

$1ꢇꢂ

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#"ꢁ

$13ꢊ

6₃₃

ꢃ

6₃₃

0IN ꢁꢉꢈ $-ꢊꢋ$13ꢁꢂ

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0IN ꢁꢉꢂ ꢃ #"ꢉ

0IN ꢁꢉꢆ ꢃ 6₃₃

0IN ꢁꢂꢁ ꢃ .#ꢋ#+%ꢁ

0IN ꢁꢂꢄ ꢃ .#

ꢃ

$13ꢊ

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0IN ꢁꢉꢉ 6₃₃

ꢃ

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6_$$1

6_$$

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6₃₃

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0IN ꢁꢂꢇ 6_$$

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.#

0IN ꢁꢂꢅ ꢃ 6_$$1

0IN ꢁꢂꢂ ꢃ !ꢆ

ꢃ

0IN ꢁꢂꢉ !ꢁꢇ

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!ꢁꢁ

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0IN ꢁꢂꢊ 6_$$

6_$$

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!ꢅ

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6_$$

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!ꢇ

ꢃ

0IN ꢁꢊꢈ 6_$$

6₃₃

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ꢃ 0IN ꢀꢉꢂ

ꢃ 0IN ꢀꢉꢆ

ꢃ 0IN ꢀꢂꢁ

ꢃ 0IN ꢀꢂꢄ

ꢃ 0IN ꢀꢂꢅ

0IN ꢁꢊꢅ ꢃ #+ꢀ

0IN ꢁꢊꢂ ꢃ 6_$$

0IN ꢁꢊꢆ ꢃ 6_$$

ꢃ

6₃₃

.#

0IN ꢀꢉꢉ

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0IN ꢁꢊꢉ #+ꢀ

6_$$

"!ꢀ

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6_$$1

ꢃ

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ꢃ

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0IN ꢁꢆꢇ 2!3

!ꢁꢀꢋ!0 0IN ꢀꢂꢀ

0IN ꢁꢆꢁ

ꢃ 6_$$1

ꢃ

6_$$1

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.#ꢋ3ꢁ

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$1ꢄꢇ

6₃₃

0IN ꢀꢂꢇ

0IN ꢀꢂꢈ

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0IN ꢀꢂꢊ

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0IN ꢀꢆꢀ

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0IN ꢁꢀꢀ

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0IN ꢁꢁꢈ

0IN ꢁꢁꢉ

0IN ꢁꢁꢊ

0IN ꢁꢇꢀ

0IN ꢁꢆꢄ ꢃ 3ꢀ

ꢃ

0IN ꢁꢆꢈ 6_$$1

0IN ꢁꢆꢅ ꢃ /$4ꢀ

0IN ꢁꢆꢂ ꢃ 6_$$

0IN ꢁꢆꢆ ꢃ $1ꢄꢉ

ꢃ

0IN ꢁꢆꢉ .#ꢋ!ꢁꢄ

.#ꢋ/$4ꢁ ꢃ 0IN ꢀꢂꢂ

ꢃ

0IN ꢁꢆꢊ 6₃₃

6₃₃

ꢃ 0IN ꢀꢂꢆ

0IN ꢀꢊꢁ

ꢃ

0IN ꢇꢀꢀ $1ꢄꢂ

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$1ꢄꢄ

$13ꢈ

6₃₃

ꢃ

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0IN ꢇꢀꢄ ꢃ .#ꢋ$13ꢁꢄ

0IN ꢇꢀꢅ

ꢃ

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ꢃ 0IN ꢀꢊꢄ

ꢃ

$13ꢈ

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6₃₃

0IN ꢇꢀꢈ 6₃₃

0IN ꢀꢊꢅ

ꢃ

ꢃ $1ꢄꢊ

0IN ꢇꢀꢂ ꢃ 6₃₃

0IN ꢇꢀꢆ

ꢃ

0IN ꢇꢀꢉ $1ꢄꢆ

$1ꢄꢅ

$1ꢈꢀ

6₃₃

ꢃ 0IN ꢀꢊꢂ

0IN ꢀꢊꢆ

ꢃ

0IN ꢇꢀꢊ $1ꢈꢈ

ꢃ

ꢃ $1ꢈꢅ

ꢃ

0IN ꢇꢁꢀ 6₃₃

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ꢃ 0IN ꢀꢆꢁ

ꢃ 0IN ꢀꢆꢄ

ꢃ 0IN ꢀꢆꢅ

ꢃ 0IN ꢀꢆꢂ

0IN ꢇꢁꢁ ꢃ $-ꢅꢋ$13ꢁꢈ

0IN ꢇꢁꢄ ꢃ 6₃₃

ꢃ

0IN ꢇꢁꢇ .#ꢋ$13ꢁꢈ

$13ꢅ

$1ꢈꢇ

6₃₃

ꢃ

0IN ꢇꢁꢈ $1ꢈꢉ

0IN ꢇꢁꢅ ꢃ $1ꢈꢂ

0IN ꢇꢁꢂ ꢃ $1ꢅꢇ

ꢃ

$1ꢈꢄ

$1ꢈꢊ

6₃₃

0IN ꢇꢁꢉ 6₃₃

ꢃ

0IN ꢇꢁꢊ $1ꢅꢄ

0IN ꢀꢆꢆ

0IN ꢇꢁꢆ

$1ꢈꢆ

3!ꢇ

ꢃ

ꢃ 6₃₃

0IN ꢇꢇꢁ ꢃ .#

0IN ꢇꢇꢄ

ꢃ

0IN ꢇꢇꢀ .#

ꢃ 0IN ꢁꢀꢁ

ꢃ

.#

0IN ꢇꢇꢇ 6₃₃

0IN ꢁꢀꢄ

6₃₃

ꢃ

ꢃ $-ꢉꢋ$13ꢁꢅ

0IN ꢇꢇꢅ ꢃ 6₃₃

0IN ꢇꢇꢂ

ꢃ

$13ꢉ

6₃₃

0IN ꢇꢇꢈ .#ꢋ$13ꢁꢅ

$13ꢉ

$1ꢅꢀ

6₃₃

ꢃ 0IN ꢁꢀꢅ

0IN ꢁꢀꢂ

ꢃ

0IN ꢇꢇꢉ $1ꢅꢈ

ꢃ

ꢃ $1ꢅꢅ

ꢃ

0IN ꢇꢇꢊ 6₃₃

$1ꢅꢁ

$1ꢅꢉ

6₃₃

ꢃ 0IN ꢁꢀꢆ

ꢃ 0IN ꢁꢁꢁ

ꢃ 0IN ꢁꢁꢄ

ꢃ 0IN ꢁꢁꢅ

0IN ꢇꢇꢆ ꢃ $1ꢉꢀ

0IN ꢇꢄꢁ ꢃ 6₃₃

ꢃ

0IN ꢇꢄꢀ $1ꢉꢁ

$1ꢅꢂ

$13ꢂ

6₃₃

ꢃ

0IN ꢇꢄꢇ $-ꢂꢋ$13ꢁꢉ

0IN ꢇꢄꢄ ꢃ .#ꢋ$13ꢁꢉ

0IN ꢇꢄꢅ ꢃ $1ꢉꢇ

ꢃ

$13ꢂ

$1ꢅꢊ

6₃₃

0IN ꢇꢄꢈ 6₃₃

ꢃ

0IN ꢇꢄꢉ $1ꢉꢄ

0IN ꢁꢁꢂ

0IN ꢇꢄꢂ

$1ꢅꢆ

3$!

ꢃ

6₃₃

0IN ꢇꢄꢊ 6$$30$

0IN ꢇꢈꢀ 3!ꢁ

ꢃ 0IN ꢁꢁꢆ

0IN ꢇꢄꢆ 3!ꢀ

3#,

-004ꢀꢁꢂꢀ

Figure 1

Pin Configuration for RDIMM (240 pins)

Data Sheet

17

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsBlock Diagram

2.2

Block Diagram

6_$$ꢋ30$

6_$$ꢉ6_$$1

6_2%&

6_$$ꢍ 30$ %%02/- %ꢀ

6_$$ꢉ6_$$1ꢍ 3$2!-S $ꢀ ꢊ $ꢂ

6_2%&ꢍ 3$2!-S $ꢀ ꢊ $ꢂ

6₃₃ꢍ 3$2!-S $ꢀ ꢊ $ꢂ

#+ꢀ

0,,

/%

0#+ꢀꢊ0#+ꢅꢋ 0#+ꢂꢋ 0#+ꢌ

#+ꢍ 3$2!-S $ꢀꢊ$ꢂ

#+ꢍ 2EGISTER

0#+ꢀꢊ0#+ꢅꢋ 0#+ꢂꢋ 0#+ꢌ

0#+ꢆ

2%3%4

#+ꢍ 2EGISTER

6₃₃

3ꢀ

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!ꢀ ꢊ !N

2!3

23ꢀ

#3ꢍ 3$2!-S $ꢀꢊ$ꢂ

"!ꢀꢊ"!Nꢍ 3$2!-S $ꢀꢊ$ꢂ

ꢁꢍꢁ

2"!ꢀꢊ2"!N

2!ꢀꢊ2!N

22!3

2

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3

4

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2

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2!3ꢍ 3$2!-S $ꢀꢊ$ꢂ

#!3ꢍ 3$2!-S $ꢀꢊ$ꢂ

7%ꢍ 3$2!-S $ꢀꢊ$ꢂ

#+%ꢍ 3$2!-S $ꢀꢊ$ꢂ

/$4ꢍ 3$2!-S $ꢀꢊ$ꢂ

#!3

2#!3

27%

2#+%ꢀ

2/$4ꢀ

2EGISTER

%ꢀ

7%

6₃₃

3#,

3$!

!ꢀ

3#,

3$!

3!ꢀ

3!ꢁ

3!ꢃ

6₃₃

#ꢀ

#ꢁ

0!2?).

#+%ꢀ

/$4ꢀ

0!2?).

!ꢁ

0#+ꢆ

2%3%4

ꢁꢀꢀ+ OHMS

00/

1%22

!ꢃ

%RR?/UT

70

23ꢀ

$ꢀ

$ꢄ

$ꢇ

$ꢈ

$ꢅ

$ꢆ

$ꢂ

#3

$13ꢀ

$13

$13ꢄ

$13

$13ꢅ

$13

$-ꢀꢉ$13ꢌ

$13ꢌ

$1ꢀ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢄꢉ$13ꢁꢃ

$13ꢁꢃ

$1ꢃꢇ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢅꢉ$13ꢁꢈ

$13ꢁꢈ

$1ꢇꢂ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$1ꢁ

)ꢉ/ ꢁ

$1ꢃꢈ

)ꢉ/ ꢁ

$1ꢇꢌ

)ꢉ/ ꢁ

$1ꢃ

)ꢉ/ ꢃ

$1ꢃꢅ

)ꢉ/ ꢃ

$1ꢈꢀ

)ꢉ/ ꢃ

$1ꢄ

)ꢉ/ ꢄ

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$1ꢅ

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)ꢉ/ ꢆ

$ꢁ

#3

$13

#3

$13

$13ꢁ

$13

$13ꢇ

$13ꢆ

$13

$-ꢁꢉ$13ꢁꢀ

$13ꢁꢀ

$1ꢂ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢇꢉ$13ꢁꢄ

$13ꢁꢄ

$1ꢄꢃ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢆꢉ$13ꢁꢅ

$13ꢁꢅ

$1ꢈꢅ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

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)ꢉ/ ꢁ

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)ꢉ/ ꢁ

$1ꢁꢀ

)ꢉ/ ꢃ

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)ꢉ/ ꢃ

$1ꢈꢂ

)ꢉ/ ꢃ

$1ꢁꢁ

)ꢉ/ ꢄ

$1ꢄꢈ

)ꢉ/ ꢄ

$1ꢈꢌ

)ꢉ/ ꢄ

$1ꢁꢃ

)ꢉ/ ꢇ

$1ꢄꢅ

)ꢉ/ ꢇ

$1ꢅꢀ

)ꢉ/ ꢇ

$1ꢁꢄ

)ꢉ/ ꢈ

$1ꢄꢆ

)ꢉ/ ꢈ

$1ꢅꢁ

)ꢉ/ ꢈ

$1ꢁꢇ

)ꢉ/ ꢅ

$1ꢄꢂ

)ꢉ/ ꢅ

$1ꢅꢃ

)ꢉ/ ꢅ

$1ꢁꢈ

)ꢉ/ ꢆ

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)ꢉ/ ꢆ

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)ꢉ/ ꢆ

$ꢃ

#3

$13

#3

$13

#3

$13

$13ꢈ

$13ꢂ

$-ꢂꢉ$13ꢁꢆ

$13ꢁꢆ

#"ꢀ

$13ꢃ

$13

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢈꢉ$13ꢁꢇ

$13ꢁꢇ

$1ꢇꢀ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢃꢉ$13ꢁꢁ

$13ꢁꢁ

$1ꢁꢅ

)ꢉ/ ꢁ

$1ꢇꢁ

)ꢉ/ ꢁ

#"ꢁ

)ꢉ/ ꢁ

$1ꢁꢆ

)ꢉ/ ꢃ

$1ꢇꢃ

)ꢉ/ ꢃ

#"ꢃ

)ꢉ/ ꢃ

$1ꢁꢂ

)ꢉ/ ꢄ

$1ꢇꢄ

)ꢉ/ ꢄ

#"ꢄ

)ꢉ/ ꢄ

$1ꢁꢌ

)ꢉ/ ꢇ

$1ꢇꢇ

)ꢉ/ ꢇ

#"ꢇ

)ꢉ/ ꢇ

$1ꢃꢀ

)ꢉ/ ꢈ

$1ꢇꢈ

)ꢉ/ ꢈ

#"ꢈ

)ꢉ/ ꢈ

$1ꢃꢁ

)ꢉ/ ꢅ

$1ꢇꢅ

)ꢉ/ ꢅ

#"ꢅ

)ꢉ/ ꢅ

$1ꢃꢃ

)ꢉ/ ꢆ

$1ꢇꢆ

)ꢉ/ ꢆ

#"ꢆ

)ꢉ/ ꢆ

$1ꢃꢄ

-0"4ꢀꢁꢂꢀ

Figure 2

Block Diagram Raw Card A-F RDIMM (x72, 1Rank, x8)

Notes

2. S0 connects to DCS and V_DDconnects to CSR on

the register.

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

Data Sheet

18

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsBlock Diagram

6_$$ꢍ30$

6_$$ꢊ6_$$1

6_2%&

6_$$ꢋ 30$ %%02/- %ꢀ

6_$$ꢊ6_$$1ꢋ 3$2!-S $ꢀꢌ$ꢁꢆ

6_2%&ꢋ 3$2!-S $ꢀꢌ$ꢁꢆ

6₃₃ꢋ 3$2!-S $ꢀꢌ$ꢁꢆ

#+ꢀ

0,,

/%

0#+ꢀꢌ0#+ꢅꢍ 0#+ꢉꢍ 0#+ꢂ

0#+ꢆ

#+ꢋ 3$2!-S $ꢀꢌ$ꢁꢆ

#+ꢋ 2EGISTER

2%3%4

0#+ꢆ

#+ꢋ 2EGISTER

6₃₃

3ꢀ

3ꢁ

23ꢀ

#3ꢋ 3$2!-S $ꢀꢌ$ꢉ

#3ꢋ 3$2!-S $ꢂꢌ$ꢁꢆ

ꢁꢋꢃ

23ꢁ

2

%

'

)

3

4

%

2

"!ꢀ ꢌ "!N

!ꢀ ꢌ !N

2!3

2"!ꢀꢌ2"!N

2!ꢀꢌ2!N

22!3

"!ꢀꢌ"!Nꢋ 3$2!-S $ꢀꢌ$ꢁꢆ

!ꢀꢌ!Nꢋ 3$2!-S $ꢀꢌ$ꢁꢆ

2!3ꢋ 3$2!-S $ꢀꢌ$ꢁꢆ

#!3ꢋ 3$2!-S $ꢀꢌ$ꢁꢆ

7%ꢋ 3$2!-S $ꢀꢌ$ꢁꢆ

#+%ꢀꢋ 3$2!-S $ꢀꢌ$ꢉ

#+%ꢁꢋ 3$2!-S $ꢂꢌ$ꢁꢆ

/$4ꢀꢋ 3$2!-S $ꢀꢌ$ꢉ

/$4ꢁꢋ 3$2!-S $ꢂꢌ$ꢁꢆ

$ꢇ

$ꢈ

$ꢅ

$ꢆ

$ꢉ

$ꢁꢄ

$ꢁꢇ

$ꢁꢈ

$ꢁꢅ

$ꢁꢆ

#3

$13ꢇ

$13

#!3

2#!3

7%

27%

$-ꢇꢊ$13ꢁꢄ

$13ꢁꢄ

$1ꢄꢃ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

#+%ꢀ

#+%ꢁ

/$4ꢀ

/$4ꢁ

0#+ꢆ

2%3%4

2#+%ꢀ

2#+%ꢁ

2/$4ꢀ

2/$4ꢁ

$1ꢄꢄ

)ꢊ/ ꢁ

$1ꢄꢇ

)ꢊ/ ꢃ

$1ꢄꢈ

)ꢊ/ ꢄ

$1ꢄꢅ

)ꢊ/ ꢇ

$1ꢄꢆ

)ꢊ/ ꢈ

$1ꢄꢉ

)ꢊ/ ꢅ

23ꢀ

$1ꢄꢂ

)ꢊ/ ꢆ

$ꢀ

$ꢂ

#3

$13

#3

$13

$13ꢀ

$-ꢀꢊ$13ꢂ

$13ꢂ

$1ꢀ

$13

$13ꢈ

$13

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢈꢊ$13ꢁꢇ

$13ꢁꢇ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$1ꢇꢀ

$1ꢁ

)ꢊ/ ꢁ

$1ꢇꢁ

$1ꢇꢃ

$1ꢇꢄ

$1ꢇꢇ

$1ꢇꢈ

$1ꢇꢅ

$1ꢇꢆ

)ꢊ/ ꢁ

%ꢀ

$1ꢃ

)ꢊ/ ꢃ

3#,

3$!

!ꢀ

3#,

3$!

3!ꢀ

3!ꢁ

3!ꢃ

6₃₃

$1ꢄ

)ꢊ/ ꢄ

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)ꢊ/ ꢇ

$1ꢈ

)ꢊ/ ꢈ

!ꢁ

$1ꢅ

)ꢊ/ ꢅ

!ꢃ

70

$1ꢆ

)ꢊ/ ꢆ

$ꢁ

$ꢃ

$ꢄ

$ꢁꢀ

$ꢁꢁ

$ꢁꢃ

#3

$13

#3

$13

#3

$13

#3

$13

$13ꢁ

$13ꢅ

$13

$-ꢁꢊ$13ꢁꢀ

$13ꢁꢀ

$1ꢉ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢅꢊ$13ꢁꢈ

$13ꢁꢈ

$1ꢇꢉ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

2EGISTER !

0!2?).

6₃₃

6_$$

$1ꢂ

)ꢊ/ ꢁ

#ꢀ

#ꢁ

0!2?).

$1ꢇꢂ

)ꢊ/ ꢁ

$1ꢁꢀ

)ꢊ/ ꢃ

$1ꢈꢀ

)ꢊ/ ꢃ

$1ꢁꢁ

)ꢊ/ ꢄ

$1ꢈꢁ

)ꢊ/ ꢄ

$1ꢁꢃ

)ꢊ/ ꢇ

$1ꢈꢃ

)ꢊ/ ꢇ

00/

1%22

$1ꢁꢄ

)ꢊ/ ꢈ

$1ꢈꢄ

)ꢊ/ ꢈ

$1ꢁꢇ

)ꢊ/ ꢅ

$1ꢈꢇ

)ꢊ/ ꢅ

$1ꢁꢈ

)ꢊ/ ꢆ

$1ꢈꢈ

)ꢊ/ ꢆ

2EGISTER "

#3

$13

#3

$13

#3

$13

#3

$13

6_$$

#ꢀ

#ꢁ

0!2?).

$13ꢃ

$13ꢆ

$13

$-ꢃꢊ$13ꢁꢁ

$13ꢁꢁ

$1ꢁꢅ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢆꢊ$13ꢁꢅ

$13ꢁꢅ

$1ꢈꢅ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

00/

1%22

$1ꢁꢆ

)ꢊ/ ꢁ

$1ꢈꢆ

)ꢊ/ ꢁ

$1ꢁꢉ

)ꢊ/ ꢃ

$1ꢈꢉ

)ꢊ/ ꢃ

%RR?/UT

$1ꢁꢂ

)ꢊ/ ꢄ

$1ꢈꢂ

)ꢊ/ ꢄ

$1ꢃꢀ

)ꢊ/ ꢇ

$1ꢅꢀ

)ꢊ/ ꢇ

$1ꢃꢁ

)ꢊ/ ꢈ

$1ꢅꢁ

)ꢊ/ ꢈ

$1ꢃꢃ

)ꢊ/ ꢅ

$1ꢅꢃ

)ꢊ/ ꢅ

$1ꢃꢄ

)ꢊ/ ꢆ

$1ꢅꢄ

)ꢊ/ ꢆ

#3

$13

#3

$13

#3

$13

#3

$13

$13ꢄ

$13ꢉ

$-ꢉꢊ$13ꢁꢆ

$13ꢁꢆ

#"ꢀ

$13

$-ꢄꢊ$13ꢁꢃ

$13ꢁꢃ

$1ꢃꢇ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$-ꢊ2$13

.5ꢊ2$13

)ꢊ/ ꢀ

$1ꢃꢈ

)ꢊ/ ꢁ

#"ꢁ

)ꢊ/ ꢁ

$1ꢃꢅ

)ꢊ/ ꢃ

#"ꢃ

)ꢊ/ ꢃ

$1ꢃꢆ

)ꢊ/ ꢄ

#"ꢄ

)ꢊ/ ꢄ

$1ꢃꢉ

)ꢊ/ ꢇ

#"ꢇ

)ꢊ/ ꢇ

$1ꢃꢂ

)ꢊ/ ꢈ

#"ꢈ

)ꢊ/ ꢈ

$1ꢄꢀ

)ꢊ/ ꢅ

#"ꢅ

)ꢊ/ ꢅ

$1ꢄꢁ

)ꢊ/ ꢆ

#"ꢆ

)ꢊ/ ꢆ

-0"4ꢀꢁꢂꢀ

Figure 3

Block Diagram Raw Card B-G RDIMM (x72, 2Ranks, x8)

Notes

2. RS0 and RS1 alternate between the back and front

sides of the DIMM.

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

Data Sheet

19

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsBlock Diagram

#+ꢀ

0,,

/%

0#+ꢀꢉ0#+ꢄꢊ 0#+ꢈꢊ 0#+ꢋ

0#+ꢅ

#+ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

-0"4ꢀꢁꢀꢂ

6_$$ꢌ 30$ %%02/- %ꢀ

#+ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

#+ꢌ 2EGISTER

6_$$ꢊ30$

6_$$ꢍ6_$$1

6_2%&

2%3%4

0#+ꢅ

#+ꢌ 2EGISTER

6_$$ꢍ6_$$1ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

6_2%&ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

6₃₃ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

%ꢀ

3ꢀ

"!ꢀ ꢉ "!N

!ꢀ ꢉ !N

2!3

23ꢀ

#3ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

"!ꢀꢉ"!Nꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

ꢂꢌꢁ

2"!ꢀꢉ2"!N

2!ꢀꢉ2!N

22!3

6₃₃

2

%

'

)

3

4

%

2

!ꢀꢉ!Nꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

2!3ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

#!3ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

7%ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

#+%ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

/$4ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

#!3

2#!3

3#,

3$!

!ꢀ

3#,

3$!

3!ꢀ

3!ꢂ

3!ꢁ

6₃₃

7%

27%

#+%ꢀ

2#+%ꢀ

2/$4ꢀ

/$4ꢀ

0#+ꢅ

!ꢂ

!ꢁ

70

0#+ꢅ

2%3%4

23ꢀ

$ꢀ

$ꢄ

$ꢂꢁ

$ꢂꢃ

$ꢂꢆ

$ꢂꢇ

$ꢂꢄ

$ꢂꢅ

#3

$13ꢀ

$1ꢀ

$1ꢂ

$1ꢁ

$1ꢃ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢄ

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢁ

$1ꢁꢈ

$1ꢁꢋ

$1ꢃꢀ

$1ꢃꢂ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

2EGISTER !

0!2?).

6₃₃

6_$$

$13ꢄ

$1ꢆꢈ

$1ꢆꢋ

$1ꢇꢀ

$1ꢇꢂ

6₃₃

#ꢀ

#ꢂ

0!2?).

00/

1%22

$ꢂ

$ꢁ

$ꢃ

$ꢆ

$ꢇ

$ꢅ

#3

$13ꢂ

$1ꢈ

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢅ

$1ꢇꢄ

$1ꢇꢅ

$1ꢇꢈ

$1ꢇꢋ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢃ

$1ꢃꢄ

$1ꢃꢅ

$1ꢃꢈ

$1ꢃꢋ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

2EGISTER "

6_$$

#ꢀ

#ꢂ

0!2?).

$1ꢋ

$1ꢂꢀ

$1ꢂꢂ

6₃₃

00/

1%22

$ꢈ

%RR?/UT

$13

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)ꢍ/ ꢁ

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$-

$13ꢈ

#"ꢀ

#"ꢂ

#"ꢁ

#"ꢃ

6₃₃

$13

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)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢆ

$1ꢆꢆ

$1ꢆꢇ

$1ꢆꢄ

$1ꢆꢅ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢁ

$1ꢂꢄ

$1ꢂꢅ

$1ꢂꢈ

$1ꢂꢋ

6₃₃

$ꢋ

$13ꢃ

$1ꢁꢆ

$1ꢁꢇ

$1ꢁꢄ

$1ꢁꢅ

6₃₃

$13

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)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢋ

$1ꢆ

$1ꢇ

$1ꢄ

$1ꢅ

6₃₃

$13

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)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢇ

$1ꢇꢁ

$1ꢇꢃ

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$1ꢇꢇ

6₃₃

$13

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$1ꢃꢁ

$1ꢃꢃ

$1ꢃꢆ

$1ꢃꢇ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢀ

$1ꢂꢁ

$1ꢂꢃ

$1ꢂꢆ

$1ꢂꢇ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢄ

$1ꢄꢀ

$1ꢄꢂ

$1ꢄꢁ

$1ꢄꢃ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢇ

$1ꢆꢀ

$1ꢆꢂ

$1ꢆꢁ

$1ꢆꢃ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢅ

#"ꢆ

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢂ

$1ꢁꢀ

$1ꢁꢂ

$1ꢁꢁ

$1ꢁꢃ

6₃₃

#"ꢇ

#"ꢄ

#"ꢅ

6₃₃

Figure 4

Notes

Block Diagram Raw Card C-H RDIMM (x72, 1Rank, x4)

3. CSR of register1 and DCS of register2 connects to

V_DD.

4. RESET, PCK7 and PCK7 connect to both registers.

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

2. S0 connects to DCS of register1 and CSR of

register2.

Data Sheet

20

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsBlock Diagram

3ꢀ

3ꢂ

23ꢀ

#3ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

#3ꢍ 3$2!-S $ꢂꢃꢋ$ꢅꢊ

"!ꢀꢋ"!Nꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

!ꢀꢋ!Nꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

2!3ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

#!3ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

7%ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

#+%ꢀꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

#+%ꢂꢍ 3$2!-S $ꢂꢃꢋ$ꢅꢊ

/$4ꢀꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

/$4ꢂꢍ 3$2!-S $ꢂꢃꢋ$ꢅꢊ

-0"4ꢀꢁꢂꢀ

ꢂꢍꢁ

23ꢂ

"!ꢀ ꢋ "!N

!ꢀ ꢋ !N

2!3

2"!ꢀꢋ2"!N

2!ꢀꢋ2!N

22!3

2#!3

27%

2#+%ꢀ

2#+%ꢂ

2/$4ꢀ

2/$4ꢂ

#+ꢀ

0,,

0#+ꢀꢋ0#+ꢇꢌ 0#+ꢃꢌ 0#+ꢆ

0#+ꢈ

#+ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

#+ꢍ 2EGISTER

2

%

'

)

3

4

%

2

#!3

7%

2%3%4

/%

0#+ꢈ

#+ꢍ 2EGISTER

%ꢀ

#+%ꢀ

#+%ꢂ

/$4ꢀ

/$4ꢂ

0#+ꢈ

2%3%4

3#,

3$!

!ꢀ

3#,

3$!

3!ꢀ

3!ꢂ

3!ꢁ

6₃₃

6_$$ꢌ30$

6_$$ꢄ6_$$1

6_2%&

6_$$ꢍ 30$ %%02/- %ꢀ

6_$$ꢄ6_$$1ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

6_2%&ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

6₃₃ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

!ꢂ

!ꢁ

70

6₃₃

23ꢀ

23ꢂ

$13ꢆ

$1ꢉ

$13ꢀ

$1ꢀ

$ꢀ

$ꢂ

$ꢁ

$ꢅ

$ꢉ

$ꢊ

$ꢇ

$ꢈ

$ꢃ

$ꢂꢃ

$ꢆ

$ꢁꢈ

$ꢁꢃ

$ꢁꢆ

$ꢅꢀ

$ꢅꢂ

$ꢅꢁ

$ꢅꢅ

$ꢅꢉ

$ꢅꢊ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$1ꢊ

$1ꢂ

$1ꢇ

$1ꢈ

$1ꢁ

$1ꢅ

$13ꢂ

$1ꢃ

$1ꢆ

$1ꢂꢀ

$1ꢂꢂ

$13ꢂꢀ

$1ꢂꢁ

$1ꢂꢅ

$1ꢂꢉ

$1ꢂꢊ

$ꢂꢀ

$ꢂꢆ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢁ

$1ꢂꢇ

$1ꢂꢈ

$1ꢂꢃ

$1ꢂꢆ

$13ꢂꢂ

$1ꢁꢀ

$1ꢁꢂ

$1ꢁꢁ

$1ꢁꢅ

$ꢁꢀ

$ꢂꢂ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢂꢁ

$1ꢁꢃ

$1ꢁꢆ

$1ꢅꢀ

$1ꢅꢂ

$13ꢅ

$1ꢁꢉ

$1ꢁꢊ

$1ꢁꢇ

$1ꢁꢈ

$ꢁꢂ

$ꢂꢁ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢂꢅ

$1ꢅꢇ

$1ꢅꢈ

$1ꢅꢃ

$1ꢅꢆ

$13ꢉ

$1ꢅꢁ

$1ꢅꢅ

$1ꢅꢉ

$1ꢅꢊ

$ꢁꢁ

$ꢂꢅ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢊ

$1ꢉꢀ

$1ꢉꢂ

$1ꢉꢁ

$1ꢉꢅ

$13ꢂꢉ

$1ꢉꢉ

$1ꢉꢊ

$1ꢉꢇ

$1ꢉꢈ

$ꢂꢉ

$ꢁꢅ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢇ

$1ꢉꢃ

$1ꢉꢆ

$1ꢊꢀ

$1ꢊꢂ

$13ꢂꢊ

$1ꢊꢁ

$1ꢊꢅ

$1ꢊꢉ

$1ꢊꢊ

$ꢁꢉ

$ꢂꢊ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢈ

$1ꢊꢇ

$1ꢊꢈ

$1ꢊꢃ

$1ꢊꢆ

$13ꢂꢇ

$1ꢇꢀ

$1ꢇꢂ

$1ꢇꢁ

$1ꢇꢅ

$ꢂꢇ

$ꢁꢊ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢂꢈ

#"ꢉ

$13ꢃ

#"ꢀ

$ꢁꢇ

$ꢂꢈ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

#"ꢊ

#"ꢂ

#"ꢇ

#"ꢁ

#"ꢈ

#"ꢅ

Figure 5

Block Diagram Raw Card J RDIMM (x72, 2Ranks, x4)

Notes

3. S0 connects to DCS and S1 Connects to CSR on a

pair of registers. S1 connects to DCS and S0

connects to CSR on another pair of registers.

4. RESET, PCK7 and PCK7 connect to all registers.

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

2. RS0 and RS1 alternate between the bottom and

surface sides of the DIMM.

Data Sheet

21

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsBlock Diagram

3ꢀ

3ꢂ

23ꢀ

#3ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

#3ꢍ 3$2!-S $ꢂꢃꢋ$ꢅꢊ

"!ꢀꢋ"!Nꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

!ꢀꢋ!Nꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

2!3ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

#!3ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

7%ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

#+%ꢀꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

#+%ꢂꢍ 3$2!-S $ꢂꢃꢋ$ꢅꢊ

/$4ꢀꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

/$4ꢂꢍ 3$2!-S $ꢂꢃꢋ$ꢅꢊ

-0"4ꢀꢁꢂꢀ

ꢂꢍꢁ

23ꢂ

"!ꢀ ꢋ "!N

!ꢀ ꢋ !N

2!3

2"!ꢀꢋ2"!N

2!ꢀꢋ2!N

22!3

2#!3

27%

2#+%ꢀ

2#+%ꢂ

2/$4ꢀ

2/$4ꢂ

#+ꢀ

0,,

0#+ꢀꢋ0#+ꢇꢌ 0#+ꢃꢌ 0#+ꢆ

0#+ꢈ

#+ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

#+ꢍ 2EGISTER

2

%

'

)

3

4

%

2

#!3

7%

2%3%4

/%

0#+ꢈ

#+ꢍ 2EGISTER

%ꢀ

#+%ꢀ

#+%ꢂ

/$4ꢀ

/$4ꢂ

0#+ꢈ

2%3%4

3#,

3$!

!ꢀ

3#,

3$!

3!ꢀ

3!ꢂ

3!ꢁ

6₃₃

6_$$ꢌ30$

6_$$ꢄ6_$$1

6_2%&

6_$$ꢍ 30$ %%02/- %ꢀ

6_$$ꢄ6_$$1ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

6_2%&ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

6₃₃ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

!ꢂ

!ꢁ

70

6₃₃

23ꢀ

23ꢂ

$13ꢆ

$1ꢉ

$13ꢀ

$1ꢀ

$ꢀ

$ꢂ

$ꢁ

$ꢅ

$ꢉ

$ꢊ

$ꢇ

$ꢈ

$ꢃ

$ꢂꢃ

$ꢆ

$ꢁꢈ

$ꢁꢃ

$ꢁꢆ

$ꢅꢀ

$ꢅꢂ

$ꢅꢁ

$ꢅꢅ

$ꢅꢉ

$ꢅꢊ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$1ꢊ

$1ꢂ

$1ꢇ

$1ꢈ

$1ꢁ

$1ꢅ

$13ꢂ

$1ꢃ

$1ꢆ

$1ꢂꢀ

$1ꢂꢂ

$13ꢂꢀ

$1ꢂꢁ

$1ꢂꢅ

$1ꢂꢉ

$1ꢂꢊ

$ꢂꢀ

$ꢂꢆ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢁ

$1ꢂꢇ

$1ꢂꢈ

$1ꢂꢃ

$1ꢂꢆ

$13ꢂꢂ

$1ꢁꢀ

$1ꢁꢂ

$1ꢁꢁ

$1ꢁꢅ

$ꢁꢀ

$ꢂꢂ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢂꢁ

$1ꢁꢃ

$1ꢁꢆ

$1ꢅꢀ

$1ꢅꢂ

$13ꢅ

$1ꢁꢉ

$1ꢁꢊ

$1ꢁꢇ

$1ꢁꢈ

$ꢁꢂ

$ꢂꢁ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢂꢅ

$1ꢅꢇ

$1ꢅꢈ

$1ꢅꢃ

$1ꢅꢆ

$13ꢉ

$1ꢅꢁ

$1ꢅꢅ

$1ꢅꢉ

$1ꢅꢊ

$ꢁꢁ

$ꢂꢅ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢊ

$1ꢉꢀ

$1ꢉꢂ

$1ꢉꢁ

$1ꢉꢅ

$13ꢂꢉ

$1ꢉꢉ

$1ꢉꢊ

$1ꢉꢇ

$1ꢉꢈ

$ꢂꢉ

$ꢁꢅ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢇ

$1ꢉꢃ

$1ꢉꢆ

$1ꢊꢀ

$1ꢊꢂ

$13ꢂꢊ

$1ꢊꢁ

$1ꢊꢅ

$1ꢊꢉ

$1ꢊꢊ

$ꢁꢉ

$ꢂꢊ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢈ

$1ꢊꢇ

$1ꢊꢈ

$1ꢊꢃ

$1ꢊꢆ

$13ꢂꢇ

$1ꢇꢀ

$1ꢇꢂ

$1ꢇꢁ

$1ꢇꢅ

$ꢂꢇ

$ꢁꢊ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢂꢈ

#"ꢉ

$13ꢃ

#"ꢀ

$ꢁꢇ

$ꢂꢈ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

#"ꢊ

#"ꢂ

#"ꢇ

#"ꢁ

#"ꢈ

#"ꢅ

Figure 6

Block Diagram Raw Card L RDIMM (x72, 2Ranks, x4)

Notes

3. S0 connects to DCS and S1 Connects to CSR on a

pair of registers. S1 connects to DCS and S0

connects to CSR on another pair of registers.

4. RESET, PCK7 and PCK7 connect to all registers.

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

2. RS0 and RS1 alternate between the bottom and

surface sides of the DIMM.

Data Sheet

22

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsBlock Diagram

2EGISTER !ꢂ

2EGISTER !ꢃ

2EGISTER "ꢃ

2EGISTER "ꢂ

6₃₃

6_$$

6₃₃

6_$$

#ꢀ

#ꢂ

0!2?).

00/

1%22

00/

1%22

00/

1%22

00/

1%22

%RR?/UT

-0"4ꢀꢁꢀꢀ

Figure 7

Block Diagram Raw Card J Signal for Address and Command Parity Function

2EGISTER 5ꢃ

2EGISTER 5ꢄ

0!2?).

0!2?).ꢂ 00/ꢂ

0!2?).ꢅ 00/ꢅ

0!2?).ꢂ 00/ꢂ

0!2?).ꢅ 00/ꢅ

%RR?/UT

094%22ꢂ

094%22ꢅ

094%22ꢂ

094%22ꢅ

-0"4ꢀꢁꢂꢀ

Figure 8

Block Diagram Raw Card L Signal for Address and Command Parity Function

Data Sheet

23

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAbsolute Maximum Ratings

3

Electrical Characteristics

3.1

Absolute Maximum Ratings

Table 9

Absolute Maximum Ratings

Parameter

Symbol

Values

Min.

–0.5

–1.0

–0.5

5

Unit

Note/Test

Condition

1)

Max.

2.3

95

Voltage on any pins relative to V_SS

Voltage on V_DDrelative to V_SS

V_IN, V_OUT

V_DD

V

%

1)

Voltage on V_DDQrelative to V_SS

V_DDQ

Storage Humidity (without condensation)

H_STG

1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device

functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability

3.2

DC Operating Conditions

Table 10

Operating Conditions

Parameter

Symbol Values

Min.

Unit Notes

Max.

+55

DIMM Module Operating Temperature Range (ambient)

DRAM Component Case Temperature Range

Storage Temperature

T_OPR

T_CASE

T_STG

PBar

H_OPR

0

°C

1)2)3)4)

0

+95

°C

–50

+69

10

+100

+105

90

°C

5)

Barometric Pressure (operating & storage)

Operating Humidity (relative)

kPa

%

1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.

2) Within the DRAM Component Case Temperature range all DRAM specification will be supported.

3) Above 85 °C DRAM case temperature the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs.

4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below

85 °C case temperature before initiating self-refresh operation.

5) Up to 3000 m

Data Sheet

24

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsDC Operating Conditions

Table 11

Supply Voltage Levels and DC Operating Conditions

Parameter

Symbol

Values

Min.

Unit

Notes

Typ.

Max.

1.9

Device Supply Voltage

Output Supply Voltage

Input Reference Voltage

SPD Supply Voltage

V_DD

1.7

1.8

V

1)

2)

V_DDQ

V_REF

1.7

1.8

1.9

V

0.49 × V_DDQ

1.7

0.5 × V_DDQ

0.51 × V_DDQ

3.6

V

V_DDSPD

V_IH(DC)

V_{IL (DC}

I_L

—

V

DC Input Logic High

V

_REF+ 0.125

V

5

_DDQ+ 0.3

V

DC Input Logic Low

)

– 0.30

– 5

_REF– 0.125

V

3)

In / Output Leakage Current

µA

1) Under all conditions, V_DDQmust be less than or equal to V_DD

2) Peak to peak AC noise on V_REFmay not exceed ± 2% V_{REF (DC)}.V_REFis also expected to track noise in V_DDQ

3) Input voltage for any connector pin under test of 0 V ≤ V_IN≤ V_DDQ+ 0.3 V; all other pins at 0 V. Current is per pin

.

Data Sheet

25

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

3.3

AC Characteristics

3.3.1

Speed Grades Definitions

Table 12

Speed Grade Definition Speed Bins for DDR2–667

Speed Grade

DDR2–667

–3

DDR2–667

–3S

Unit

Note

IFX Sort Name

CAS-RCD-RP latencies

Parameter

4–4–4

5–5–5

t_CK

—

ns

Symbol

t_CK

Min.

5

Max.

Min.

5

Max.

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

8

@ CL = 4

@ CL = 5

t_CK

3

8

3.75

3

8

t_CK

3

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

45

57

12

70000

—

45

60

15

70000

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are

further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,

RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

4) The output timing reference voltage level is V_TT.

5) t_RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is

equal to 9 x t_REFI

.

Table 13

Speed Grade Definition Speed Bins for DDR2-533C and DDR2-400B

Speed Grade

DDR2–533

–3.7

DDR2–400

–5

Unit

Note

IFX Sort Name

CAS-RCD-RP latencies

Parameter

4–4–4

3–3–3

t_CK

—

ns

Symbol

t_CK

Min.

5

Max.

Min.

5

Max.

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

8

@ CL = 4

@ CL = 5

t_CK

3.75

45

8

5

8

t_CK

8

5

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

40

55

15

70000

—

60

15

—

15

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are

further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.

Data Sheet

26

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,

RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

4) The output timing reference voltage level is V_TT.

5) t_RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is

equal to 9 x t_REFI

.

3.3.2

AC Timing Parameters

Table 14

Timing Parameter by Speed Grade - DDR2-667

Parameter

Symbol

DDR2-667

Min.

Unit Note

1)2)3)4)5)6)

Max.

7)

DQ output access time from CK / CK

CAS A to CAS B command period

CK, CK high-level width

t_AC

t_CCD

t_CH

t_CKE

t_CL

t_DAL

t_DELAY

–450

2

+450

—

ps

t_CK

ns

0.45

3

0.55

—

CKE minimum high and low pulse width

CK, CK low-level width

0.45

WR + t_RP

0.55

—

Auto-Precharge write recovery + precharge time

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_IS+ t_CK+ t_IH––

DQ and DM input hold time (differential data strobe)

DQ and DM input hold time (single ended data strobe)

DQ and DM input pulse width (each input)

t_DH(base)

175

––

ps

t_CK

ps

t_CK

ps

t

_DH1(base) –25

––

t_DIPW

0.35

–400

0.35

240

—

DQS output access time from CK / CK

t_DQSCK

t_DQSL,H

t_DQSQ

t_DQSS

t_DS(base)

+400

—

DQS input low (high) pulse width (write cycle)

DQS-DQ skew (for DQS & associated DQ signals)

Write command to 1st DQS latching transition

DQ and DM input setup time (differential data strobe)

—

– 0.25

100

+ 0.25 t_CK

—

ps

t_CK

DQ and DM input setup time (single ended data strobe) t_DS1(base) –25

DQS falling edge hold time from CK (write cycle)

DQS falling edge to CK setup time (write cycle)

Clock half period

t_DSH

t_DSS

0.2

t_HP

MIN. (t_CL,t_CH)

Data-out high-impedance time from CK / CK

Address and control input hold time

t_HZ

—

t_AC.MAXps

t_IH(base)

t_IPW

275

0.6

—

ps

Address and control input pulse width

(each input)

t_CK

Address and control input setup time

DQ low-impedance time from CK / CK

DQS low-impedance from CK / CK

Mode register set command cycle time

OCD drive mode output delay

t_IS(base)

t_LZ(DQ)

t_LZ(DQS)

t_MRD

200

—

ps

2 x t_AC.MIN

t_AC.MAXps

t_AC.MIN

2

0

—

12

—

t_CK

t_OIT

ns

Data output hold time from DQS

t_QH

t_HP– t_QHS

Data Sheet

27

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

Table 14

Timing Parameter by Speed Grade - DDR2-667

Symbol

Parameter

DDR2-667

Min.

Unit Note

1)2)3)4)5)6)

Max.

7)

Data hold skew factor

t_QHS

t_REFI

340

—

ps

µs

ns

t_CK

ns

t_CK

ns

t_CK

ns

t_CK

8)

9)

Average periodic refresh Interval

7.8

3.9

—

Auto-Refresh to Active/Auto-Refresh command period t_RFC

105

0.9

0.40

7.5

10

Read preamble

t_RPRE

t_RPST

t_RRD

1.1

0.60

—

Read postamble

10)

11)

Active bank A to Active bank B command period

—

Internal Read to Precharge command delay

Write preamble

t_RTP

7.5

0.35

0.40

15

—

t_WPRE

t_WPST

t_WR

—

Write postamble

0.60

—

Write recovery time for write without Auto-Precharge

Write recovery time for write with Auto-Precharge

Internal Write to Read command delay

WR

t_WR/t_CK

t_WTR

t_XARD

7.5

2

—

Exit power down to any valid command

(other than NOP or Deselect)

Exit active power-down mode to Read command (slow t_XARDS

exit, lower power)

7 – AL

2

—

t_CK

Exit precharge power-down to any valid command (other t_XP

than NOP or Deselect)

Exit Self-Refresh to non-Read command

Exit Self-Refresh to Read command

t_XSNR

t_XSRD

t

_RFC+10

—

ns

200

t_CK

1) For details and notes see the relevant INFINEON component data sheet

2) V_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ± 0.1 V. See notes ^4)5)6)7)

3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be

powered down and then restarted through the specified initialization sequence before normal operation can continue.

4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.

The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode

6) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

7) The output timing reference voltage level is V_TT.

8) 0 ≤ T_CASE≤ 85 °C

9) 85 °C < T_CASE≤ 95 °C

10) x4 & x8

11) x16

Data Sheet

28

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

Table 15

Timing Parameter by Speed Grade - DDR2-533

Parameter

Symbol

DDR2–533

Min.

Unit Note¹⁾²⁾

3)4)5)6)7)

Max.

+500

—

DQ output access time from CK / CK

CAS A to CAS B command period

CK, CK high-level width

t_AC

–500

2

ps

t_CCD

t_CH

t_CKE

t_CL

t_DAL

t_DELAY

t_CK

ns

0.45

0.55

—

CKE minimum high and low pulse width

CK, CK low-level width

3

0.45

0.55

—

Auto-Precharge write recovery + precharge time

WR + t_RP

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_IS+ t_CK+ t_IH––

DQ and DM input hold time (differential data

strobe)

t_DH(base)

225

–25

––

—

ps

DQ and DM input hold time (single ended data

strobe)

t_DH1(base)

DQ and DM input pulse width (each input)

DQS output access time from CK / CK

DQS input low (high) pulse width (write cycle)

t_DIPW

0.35

—

t_CK

ps

t_CK

ps

t_CK

ps

t_DQSCK

t_DQSL,H

–450

0.35

+450

—

DQS-DQ skew (for DQS & associated DQ signals) t_DQSQ

—

300

Write command to 1st DQS latching transition

t_DQSS

WL – 0.25

100

WL + 0.25

—

DQ and DM input setup time (differential data

strobe)

t_DS(base)

DQ and DM input setup time (single ended data

strobe)

t

_DS1(base)

–25

—

ps

DQS falling edge hold time from CK (write cycle) t_DSH

0.2

—

t_CK

DQS falling edge to CK setup time (write cycle)

Clock half period

t_DSS

0.2

t_HP

MIN. (t_CL,t_CH)

Data-out high-impedance time from CK / CK

Address and control input hold time

t_HZ

—

t_AC.MAX

ps

t_CK

t_IH(base)

t_IPW

375

0.6

—

Address and control input pulse width

(each input)

—

Address and control input setup time

DQ low-impedance time from CK / CK

DQS low-impedance from CK / CK

Mode register set command cycle time

OCD drive mode output delay

t_IS(base)

t_LZ(DQ)

t_LZ(DQS)

t_MRD

250

—

ps

t_CK

ns

2 ° t_AC.MIN

t_AC.MAX

—

t_AC.MIN

2

0

t_OIT

12

Data output hold time from DQS

Data hold skew factor

t_QH

t

_HP– t_QHS

—

t_QHS

—

400

7.8

ps

8)

Average periodic refresh Interval

t_REFI

—

µs

9)

—

3.9

µs

Auto-Refresh to Active/Auto-Refresh command

period

t_RFC

105

—

ns

Read preamble

t_RPRE

0.9

1.1

t_CK

Data Sheet

29

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

Table 15

Timing Parameter by Speed Grade - DDR2-533 (cont’d)

Parameter

Symbol

DDR2–533

Min.

0.40

Unit Note¹⁾²⁾

3)4)5)6)7)

Max.

0.60

—

Read postamble

t_RPST

t_CK

10)

Active bank A to Active bank B command period t_RRD

7.5

ns

1)11)

10

—

ns

Internal Read to Precharge command delay

Write preamble

t_RTP

7.5

—

ns

t_CK

ns

t_WPRE

t_WPST

t_WR

0.35xt_CK

0.40

—

Write postamble

0.60

—

Write recovery time for write without Auto-

Precharge

15

Write recovery time for write with Auto-Precharge WR

t

_WR/t_CK

t_CK

ns

Internal Write to Read command delay

t_WTR

7.5

2

—

Exit power down to any valid command

(other than NOP or Deselect)

t_XARD

t_CK

Exit active power-down mode to Read command t_XARDS

(slow exit, lower power)

6 – AL

2

—

t_CK

Exit precharge power-down to any valid command t_XP

(other than NOP or Deselect)

Exit Self-Refresh to non-Read command

Exit Self-Refresh to Read command

t_XSNR

t_XSRD

t

_RFC+10

—

ns

200

t_CK

1) For details and notes see the relevant INFINEON component data sheet

2) V_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ± 0.1 V. See notes ^4)5)6)7)

3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be

powered down and then restarted through the specified initialization sequence before normal operation can continue.

4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS,

RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode

6) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

7) The output timing reference voltage level is V_TT.

8) 0 ≤ T_CASE≤ 85 °C

9) 85 < T_CASE≤ 95 °C

10) x4 & x8

11) x16

Data Sheet

30

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

Table 16

Timing Parameter by Speed Grade - DDR2-400

Symbol

Parameter

DDR2-400

Min.

Unit Note

1)2)3)4)5)6)7)

Max.

+600

—

DQ output access time from CK / CK

CAS A to CAS B command period

CK, CK high-level width

t_AC

t_CCD

t_CH

t_CKE

t_CL

t_DAL

t_DELAY

–600

2

ps

t_CK

ns

0.45

0.55

—

CKE minimum high and low pulse width

CK, CK low-level width

3

0.45

0.55

—

Auto-Precharge write recovery + precharge time

WR + t_RP

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_IS+ t_CK+ t_IH––

DQ and DM input hold time (differential data strobe)

DQ and DM input hold time (single-ended strobe)

DQ and DM input pulse width (each input)

DQS output access time from CK / CK

t_DH(base)

275

––

ps

t_CK

ps

t_CK

ps

t

_DH1(base) 25

––

t_DIPW

0.35

–500

0.35

—

t_DQSCK

t_DQSL,H

t_DQSQ

t_DQSS

t_DS(base)

+500

—

DQS input low (high) pulse width (write cycle)

DQS-DQ skew (for DQS & associated DQ signals)

Write command to 1st DQS latching transition

DQ and DM input setup time (differential data strobe)

DQ and DM input setup time (single-ended strobe)

DQS falling edge hold time from CK (write cycle)

DQS falling edge to CK setup time (write cycle)

Clock half period

350

– 0.25

150

+ 0.25 t_CK

—

ps

t_CK

t

_DS1(base) 25

t_DSH

t_DSS

t_HP

0.2

MIN. (t_CL,t_CH)

Data-out high-impedance time from CK / CK

Address and control input hold time

t_HZ

—

t_AC.MAXps

t_IH(base)

t_IPW

475

0.6

—

ps

Address and control input pulse width

(each input)

t_CK

Address and control input setup time

DQ low-impedance time from CK / CK

DQS low-impedance from CK / CK

Mode register set command cycle time

OCD drive mode output delay

t_IS(base)

t_LZ(DQ)

t_LZ(DQS)

t_MRD

350

—

ps

2 x t_AC.MIN

t_AC.MAXps

t_AC.MIN

2

0

—

t_CK

t_OIT

12

—

ns

Data output hold time from DQS

Data hold skew factor

t_QH

t_HP– t_QHS

t_QHS

—

450

7.8

3.9

—

ps

µs

ns

t_CK

ns

t_CK

8)

9)

Average periodic refresh Interval

t_REFI

—

Auto-Refresh to Active/Auto-Refresh command period t_RFC

105

0.9

0.40

7.5

10

Read preamble

t_RPRE

t_RPST

t_RRD

1.1

0.60

—

Read postamble

10)

11)

Active bank A to Active bank B command period

—

Internal Read to Precharge command delay

Write preamble

t_RTP

7.5

0.35

—

t_WPRE

—

Data Sheet

31

Rev. 1.2, 2005-09

09122003-AWKK-ZTPQ

HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

Table 16

Timing Parameter by Speed Grade - DDR2-400

Symbol

Parameter

DDR2-400

Min.

Unit Note

1)2)3)4)5)6)7)

Max.

0.60

—

Write postamble

t_WPST

0.40

t_CK

ns

Write recovery time for write without Auto-Precharge

Write recovery time for write with Auto-Precharge

Internal Write to Read command delay

t_WR

15

WR

t_WTR

t_XARD

t

_WR/t_CK

t_CK

ns

7.5

2

—

Exit power down to any valid command

(other than NOP or Deselect)

t_CK

Exit active power-down mode to Read command (slow t_XARDS

exit, lower power)

6 – AL

2

—

t_CK

Exit precharge power-down to any valid command

(other than NOP or Deselect)

t_XP