HYS72T64000HU [INFINEON]
240-Pin Unbuffered DDR2 SDRAM Modules; 240针无缓冲DDR2 SDRAM模组
| 型号： | HYS72T64000HU |
| 厂家： | 
Infineon |
| 描述： | 240-Pin Unbuffered DDR2 SDRAM Modules |
| 文件： | 总67页 (文件大小：1454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 0.87, June 2004
HYS64T32000[G/H]U–[3.7/5]–A
HYS[64/72]T64000[G/H]U–[3.7/5]–A
HYS[64/72]T128020[G/H]U–[3.7/5]–A
240-Pin Unbuffered DDR2 SDRAM Modules
DDR2 SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
The information in this document is subject to change without notice.
Edition 2004-06
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, Rev. 0.87, June 2004
HYS64T32000[G/H]U–[3.7/5]–A
HYS[64/72]T64000[G/H]U–[3.7/5]–A
HYS[64/72]T128020[G/H]U–[3.7/5]–A
240-Pin Unbuffered DDR2 SDRAM Modules
DDR2 SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
Revision History:
Rev. 0.87
2004-06
Previous Revision:
Rev. 0.84
2003-09
Page
all
Subjects (major changes since last revision)
New template
chapter 5
all
add currents
updated timings
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc.mp@infineon.com
Template: mp_a4_v2.3_2004-01-14.fm
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1
1.2
1.3
2
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4
4.1
4.2
I
DD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I
ODT (On Die Termination) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5
Electrical Characteristics & AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1
AC Timing Parameter by Speed Grade (Component level data, for reference only) . . . . . . . . . . . . . 28
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Raw Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Raw Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Raw Card C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.1
7.2
7.3
8
Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Data Sheet
5
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
1
Overview
This chapter gives an overview of the 1.8 V 240-pin Unbuffered DDR2 SDRAM Modules, 256 MByte, 512 MByte
& 1 GByte ECC and non-ECC Modules and describes its main characteristics.
1.1
Features
•
240-pin ECC and Non-ECC Unbuffered 8-Byte
Dual-In-Line DDR2 SDRAM Module for PC,
Workstation and Server main memory applications
One rank 32M x 64, 64M x 64, 64M x 72 and two
ranks 128M × 64 and 128M x 72 organization
JEDEC standard Double Data Rate 2 Synchronous
DRAMs (DDR2 SDRAM) with a single + 1.8 V
(± 0.1 V) power supply
•
Programmable CAS Latencies (3, 4 & 5), Burst
Length (8 & 4) and Burst Type
•
•
•
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_1.8 compatible
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
•
•
•
•
Serial Presence Detect with E2PROM
Low Profile Modules form factor:
•
256 ,512 MByte and 1GByte modules built with
512Mb DDR2 SDRAMs in 60-ball (P–TFBGA–60)
and 84-ball FBGA (P–TFBGA–84) chipsize
packages
133.35 mm x 30,00 mm (MO-237)
Based on JEDEC standard reference card layouts
Raw Card “A”, “B” & “C”
•
Table 1
Performance
Speed Grade Indicator
–5
–-3.7
Unit
—
Component Speed Grade
Module Speed Grade
DDR2–400
PC2–3200
200
DDR2–533
PC2–4200
200
—
Max. Clock Frequency @ CL = 3
Max. Clock Frequency @ CL = 4 & 5
MHz
MHz
200
266
1.2
Description
The INFINEON HYS[64/72]Txxxx0[G/H]U module The memory array is designed with 512Mb Double
family are low profile Unbuffered DIMM modules with Data Rate (DDR2) Synchronous DRAMs for ECC and
30,0 mm height based on DDR2 technology. DIMMs Non-ECC applications. Decoupling capacitors are
are available as non-ECC modules in 32M x 64 mounted on the PCB board. The DIMMs feature serial
(256MB), 64M x 64 (512MB) and 128M x 64 (1024MB) presence detect based on a serial E2PROM device
and as ECC-modules in 64M x 72 (512MB) and 128M using the 2-pin I2C protocol. The first 128 bytes are
x 72 (1024MB) organisation and density, intended for programmed with configuration data and the second
mounting into 240 pin connector sockets.
128 bytes are available to the customer.
Data Sheet
6
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 2
Ordering Information
Product Type
Compliance Code
Description
SDRAM
Technology
PC2-3200
HYS64T32000GU–5–A
HYS64T64000GU–5–A
HYS72T64000GU–5–A
HYS64T128020GU–5–A
HYS72T128020GU–5–A
256MB 1R×16 PC2–3200U–333–11–C0
512MB 1R×8 PC2–3200U–333–11–A0
512MB 1R×8 PC2–3200E–333–11–A0
1GB 2R×8 PC2–3200U–333–11–B0
1GB 2R×8 PC2–3200E–333–11–B0
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
2 Ranks, Non-ECC 512 Mbit (×8
2 Ranks, ECC
512 Mbit (×8)
HYS64T32000HU–5–A
HYS64T64000HU–5–A
HYS72T64000HU–5–A
HYS64T128020HU–5–A
HYS72T128020HU–5–A
PC2–4200
256MB 1R×16 PC2–3200U–333–11–C0
512MB 1R×8 PC2–3200U–333–11–A0
512MB 1R×8 PC2–3200E–333–11–A0
1GB 2R×8 PC2–3200U–333–11–B0
1GB 2R×8 PC2–3200E–333–11–B0
1 rank, Non-ECC
1 rank, Non-ECC
1 rank, ECC
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
2 ranks, Non-ECC
2 ranks, ECC
HYS64T32000GU–3.7–A
HYS64T64000GU–3.7–A
HYS72T64000GU–3.7–A
256MB 1R×16 PC2–4200U–444–11–C0
512MB 1R×8 PC2–4200U–444–11–A0
512MB 1R×8 PC2–4200E–444–11–A0
1 rank, Non-ECC
1 rank, Non-ECC
1 rank, ECC
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8
512 Mbit (×8)
HYS64T128020GU–3.7–A 1GB 2R×8 PC2–4200U–444–11–B0
HYS72T128020GU–3.7–A 1GB 2R×8 PC2–4200E–444–11–B0
2 ranks, Non-ECC
2 ranks, ECC
HYS64T32000HU–3.7–A
HYS72T64000HU–3.7–A
HYS64T64000HU–3.7–A
256MB 1R×16 PC2–4200U–444–11–C0
512MB 1R×8 PC2–4200E–444–11–A0
512MB 1R×8 PC2–4200U–444–11–A0
1 rank, Non-ECC
1 rank, ECC
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
1 rank, Non-ECC
2 ranks, Non-ECC
2 ranks, ECC
HYS64T128020HU–3.7–A 1GB 2R×8 PC2–4200U–444–11–B0
HYS72T128020HU–3.7–A 1GB 2R×8 PC2–4200E–444–11–B0
Note:
1. All part numbers end with a place code, designating
the silicon die revision. Example:
4200U-44410-C”, where 4200U means Unbuffered
DIMM modules with 4.26 GB/sec Module
Bandwidth and “44410” means CAS latency = 4,
trcd latency = 4 and trp latency = 4 using the latest
JEDEC SPD Revision 1.1 and produced on the
Raw Card “C”.
HYS72T64000GU–5-A, indicating Rev. A dice are
used for DDR2 SDRAM components. For all
INFINEON DDR2 module and component
nomenclature see section 8 of this datasheet.
2. The Compliance Code is printed on the module
label and describes the speed grade, f.e. “PC2-
Data Sheet
7
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 3
DIMM
Density Organization
Address Format
Module
Memory
Ranks
ECC/
Non-ECC
# of
SDRAMs
# of row/bank/columns bits
Raw
Card
256 MB
512 MB
512 MB
1 GB
32M ×64
1
1
1
2
2
Non-ECC
Non-ECC
ECC
4
13/2/10
14/2/10
14/2/10
14/2/10
14/2/10
C
A
A
B
B
64M ×64
8
64M ×72
9
2 × 64M ×72
2 × 64M ×72
Non-ECC
ECC
16
18
1 GB
Table 4
Components on Modules1)
Part Number
DIMM
Density
DRAM components
reference datasheet
DRAM Density
DRAM Organisation
HYS64T32000GU
HYS64T32000HU2)
HYS64T64000GU
HYS64T64000HU2)
HYS72T64000GU
HYS72T64000HU2)
HYS64T128020GU
HYS64T128020HU2)
HYS72T128020GU
HYS72T128020HU2)
256 MB HYB18T512160AC
256 MB HYB18T512160AF2)
512 MB HYB18T512800AC
512 MB HYB18T512800AF2)
512 MB HYB18T512800AC
512 MB HYB18T512800AF2)
512 Mbit
512 Mbit
512 Mbit
512 Mbit
512 Mbit
512 Mbit
512 Mbit
512 Mbit
512 Mbit
512 Mbit
32M ×16
32M ×16
64Mb ×8
64Mb ×8
64Mb ×8
64Mb ×8
64Mb ×8
64Mb ×8
64Mb ×8
64Mb ×8
1 GB
1 GB
1 GB
1 GB
HYB18T1G800AC
HYB18T1G800AF2)
HYB18T1G800AC
HYB18T1G800AF2)
1) For a detailed description of all functionalities of the DRAM components on these modules see the referenced component
datasheet.
2) Green Product
Data Sheet
8
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
1.3
Pin Configuration
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The
abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin
numbering is depicted in Figure 1 for non-ECC modules (×64) and Figure 2 for ECC modules (×72).
Table 5
Pin#
Pin Configuration of UDIMM
Name Pin Buffer Function
Type Type
Clock Signals
185
137
220
186
138
221
52
CK0
CK1
CK2
CK0
CK1
CK2
CKE0
CKE1
I
I
I
I
I
I
I
I
SSTL Clock Signals 2:0
SSTL
SSTL
SSTL Complement Clock Signals 2:0
SSTL
SSTL
SSTL Clock Enable Rank 0
SSTL Clock Enable Rank 1
Note:2 Ranks module
171
NC
NC
—
Note:1 Rank module
Control Signals
193
76
S0
S1
I
I
SSTL Chip Select Rank 0
SSTL Chip Select Rank 1
Note:2 Ranks module
NC
NC
—
Note:1 Rank module
192
RAS
CAS
WE
I
I
I
SSTL Row Address Strobe
SSTL Column Address Strobe
SSTL Write Enable
74
73
Address Signals
71
BA0
BA1
BA2
I
I
I
SSTL Bank Address Bus 1:0
SSTL
190
54
SSTL Bank Address Bus 2
Note:greater than 512Mb DDR2 SDRAMS
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
NC
—
Note:less than 1Gb DDR2 SDRAMS
188
183
63
I
I
I
I
I
I
I
I
I
I
SSTL Address Bus 12:0
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
182
61
60
180
58
179
177
Data Sheet
9
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin#
Pin Configuration of UDIMM (cont’d)
Name Pin Buffer Function
Type Type
70
A10
AP
I
I
I
I
I
SSTL Address Bus 12:0
SSTL
57
A11
A12
A13
SSTL
176
196
SSTL
SSTL Address Signal 13
Note:1 Gbit based module and 512M ×4/×8
Note:
NC
NC
—
1. Module based on 1 Gbit ×16
2. Module based on 512 Mbit ×16 or smaller
174
A14
NC
I
SSTL Address Signal 14
Note:Modules based on 2 Gbit
Note:Modules based on 1 Gbit or smaller
NC
—
Data Signals
3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL Data Bus 63:0
SSTL
4
9
SSTL
10
SSTL
122
123
128
129
12
SSTL
SSTL
SSTL
SSTL
SSTL
13
SSTL
21
DQ10 I/O
DQ11 I/O
DQ12 I/O
DQ13 I/O
DQ14 I/O
DQ15 I/O
DQ16 I/O
DQ17 I/O
DQ18 I/O
DQ19 I/O
DQ20 I/O
DQ21 I/O
DQ22 I/O
DQ23 I/O
DQ24 I/O
DQ25 I/O
SSTL
22
SSTL
131
132
140
141
24
SSTL
SSTL
SSTL
SSTL
SSTL
25
SSTL
30
SSTL
31
SSTL
143
144
149
150
33
SSTL
SSTL
SSTL
SSTL
SSTL
34
SSTL
Data Sheet
10
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin#
Pin Configuration of UDIMM (cont’d)
Name Pin Buffer Function
Type Type
39
DQ26 I/O
DQ27 I/O
DQ28 I/O
DQ29 I/O
DQ30 I/O
DQ31 I/O
DQ32 I/O
DQ33 I/O
DQ34 I/O
DQ35 I/O
DQ36 I/O
DQ37 I/O
DQ38 I/O
DQ39 I/O
DQ40 I/O
DQ41 I/O
DQ42 I/O
DQ43 I/O
DQ44 I/O
DQ45 I/O
DQ46 I/O
DQ47 I/O
DQ48 I/O
DQ49 I/O
DQ50 I/O
DQ51 I/O
DQ52 I/O
DQ53 I/O
DQ54 I/O
DQ55 I/O
DQ56 I/O
DQ57 I/O
DQ58 I/O
DQ59 I/O
DQ60 I/O
DQ61 I/O
DQ62 I/O
DQ63 I/O
SSTL Data Bus 63:0
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
Data Sheet
11
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin#
Pin Configuration of UDIMM (cont’d)
Name Pin Buffer Function
Type Type
Check Bit Signal
42
CB0
I/O
SSTL Check Bit 0
Note:ECC type module only
Note:Non-ECC module
SSTL Check Bit 1
Note:ECC type module only
Note:Non-ECC module
SSTL Check Bit 2
Note:ECC type module only
Note:Non-ECC module
SSTL Check Bit 3
Note:ECC type module only
Note:Non-ECC module
SSTL Check Bit 4
Note:ECC type module only
Note:Non-ECC module
SSTL Check Bit 5
Note:ECC type module only
Note:Non-ECC module
SSTL Check Bit 6
Note:ECC type module only
Note:Non-ECC module
SSTL Check Bit 7
Note:ECC type module only
Note:Non-ECC module
NC
NC
I/O
—
43
CB1
NC
NC
I/O
—
48
CB2
NC
NC
I/O
—
49
CB3
NC
NC
I/O
—
161
162
167
168
CB4
NC
NC
I/O
—
CB5
NC
NC
I/O
—
CB6
NC
NC
I/O
—
CB7
NC
NC
—
Data Strobe Bus
7
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
DQS5 I/O
DQS6 I/O
DQS7 I/O
DQS8 I/O
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
SSTL Data Strobe Bus 8:0
Note:See block diagram for corresponding DQ
signals
16
28
37
84
93
105
114
45
6
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL Complement Data Strobe Bus 8:0
Note:See block diagram for corresponding DQ
signals
15
27
36
83
SSTL
SSTL
SSTL
SSTL
Data Sheet
12
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin#
Pin Configuration of UDIMM (cont’d)
Name Pin Buffer Function
Type Type
92
DQS5 I/O
DQS6 I/O
DQS7 I/O
DQS8 I/O
SSTL Complement Data Strobe Bus 8:0
104
SSTL
SSTL
SSTL
113
46
Data Mask Signals
125
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
I
I
I
I
I
I
I
I
I
SSTL Data Mask Bus 8:0
134
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
146
155
202
211
223
232
164
EEPROM
120
SCL
SDA
SA0
SA1
SA2
I
CMOS Serial Bus Clock
119
I/O
OD
Serial Bus Data
239
I
I
I
CMOS Slave Address Select Bus 2:0
240
CMOS
CMOS
101
Power Supplies
1
VREF
AI
—
I/O Reference Voltage
EEPROM Power Supply
I/O Driver Power Supply
238
VDDSPD PWR —
51,56,62,72,75,78,170,175,181, VDDQ
191,194
PWR —
PWR —
GND —
53,59,64,67,69,172,178,184,187 VDD
189,197
Power Supply
Ground Plane
2,5,8,11,14,17,20,23,26,29,32,
35,38,41,44,47,50,65,66,79,82,
85,88,91,94,97,100,103,106,
109,112,115,118,121,124,127,
130,133,136,139,142,145,148,
151,154,157,160,163,166,169,
198,201,204,207,210,213,216,
219,222,225,228,231,234,237
VSS
Other Pins
195
77
ODT0
ODT1
NC
On-Die Termination Control 0
On-Die Termination Control 1
Note:1 Rank modules
NC
NC
—
—
18,19,55,68,102,126,135,147,
156,165,173,203,212, 224,233
NC
Not connected
Note:Pins not connected on Infineon UDIMMs
Data Sheet
13
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 6
Abbreviations for Buffer Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
Table 7
Abbreviation
SSTL
Abbreviations for Buffer Type
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
CMOS Levels
LV-CMOS
CMOS
OD
Open Drain. The corresponding pin has 2 operational states, active low and
tristate, and allows multiple devices to share as a wire-OR.
Data Sheet
14
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
VREF - Pin 001
DQ0 - Pin 003
VSS - Pin 005
DQS0 - Pin 007
DQ2 - Pin 009
VSS - Pin 011
DQ9 - Pin 013
DQS1 - Pin 015
VSS - Pin 017
Pin 121 - VSS
VSS
- Pin 002
- Pin 004
Pin 122 - DQ4
Pin 124 - VSS
Pin 126 - NC
Pin 128 - DQ6
Pin 130 - VSS
Pin 132 - DQ13
Pin 134 - DM1
Pin 136 - VSS
Pin 138 - CK1
Pin 140 - DQ14
Pin 123 - DQ5
Pin 125 - DM0
Pin 127 - VSS
Pin 129 - DQ7
Pin 131 - DQ12
Pin 133 - VSS
Pin 135 - NC
Pin 137 - CK1
Pin 139 - VSS
Pin 141 - DQ15
Pin 143 - DQ20
Pin 145 - VSS
Pin 147 - NC
Pin 149 - DQ22
Pin 151 - VSS
Pin 153 - DQ29
Pin 155 - DM3
Pin 157 - VSS
Pin 159 - DQ31
Pin 161 - NC
Pin 163 - VSS
Pin 165 - NC
Pin 167 - NC
Pin 169 - VSS
Pin 171 - CKE1
Pin 173 - NC
Pin 175 - VDDQ
Pin 177 - A9
DQ1
DQS0 - Pin 006
VSS
- Pin 008
- Pin 010
- Pin 012
- Pin 014
DQ3
DQ8
VSS
DQS1 - Pin 016
NC
- Pin 018
- Pin 020
NC
- Pin 019
-
VSS
DQ10 Pin 021
-
-
Pin 142 VSS
DQ11
DQ16
VSS
Pin 022
-
VSS
Pin 023
-
-
Pin 144 DQ21
Pin 024
DQ17 - Pin 025
DQS2 - Pin 027
-
-
-
-
-
Pin 146 DM2
Pin 026
Pin 028
Pin 030
Pin 032
-
Pin 148 VSS
DQS2
DQ18
VSS
VSS
- Pin 029
-
Pin 150 DQ23
DQ19 - Pin 031
DQ24 - Pin 033
-
Pin 152 DQ28
DQ25 - Pin 034
DQS3 - Pin 036
Pin 154 - VSS
Pin 156 - NC
Pin 158 - DQ30
Pin 160 - VSS
VSS
- Pin 035
DQS3 - Pin 037
DQ26 - Pin 039
VSS
- Pin 038
DQ27 - Pin 040
VSS
NC
NC
VSS
NC
- Pin 041
- Pin 043
- Pin 045
- Pin 047
- Pin 049
-
Pin 162 NC
NC
- Pin 042
-
-
-
-
-
-
Pin 164 NC
VSS
NC
Pin 044
Pin 046
Pin 048
Pin 050
Pin 052
-
Pin 166 VSS
-
Pin 168 NC
NC
-
Pin 170 VDDQ
VSS
CKE0
VDDQ - Pin 051
VDD - Pin 053
-
Pin 172 VDD
-
-
Pin 174 A14
NC/BA2 Pin 054
NC
- Pin 055
-
-
-
-
-
Pin 176 A12
VDDQ
A7
Pin 056
Pin 058
Pin 060
Pin 062
A11 - Pin 057
VDD - Pin 059
-
Pin 178 VDD
Pin 179 - A8
-
Pin 180 A6
A5
A4
A2
- Pin 061
- Pin 063
Pin 181 - VDDQ
Pin 183 - A1
-
VDDQ
VDD
Pin 182 A3
- Pin 064
Pin 184 - VDD
VSS
- Pin 065
Pin 185 - CK0
Pin 187 - VDD
Pin 189 - VDD
Pin 191 - VDDQ
Pin 193 - S0
-
Pin 186 CK0
VSS
NC
- Pin 066
- Pin 068
VDD - Pin 067
VDD - Pin 069
BA0 - Pin 071
-
Pin 188 A0
A10/AP - Pin 070
Pin 190 - BA1
-
-
-
-
-
-
-
-
-
Pin 192 RAS
VDDQ
CAS
Pin 072
Pin 074
Pin 076
Pin 078
Pin 080
Pin 082
Pin 084
Pin 086
WE
- Pin 073
-
Pin 194 VDDQ
VDDQ - Pin 075
ODT1 - Pin 077
Pin 195 - ODT0
Pin 197 - VDD
Pin 199 - DQ36
Pin 201 - VSS
Pin 203 - NC
Pin 205 - DQ38
Pin 207 - VSS
Pin 209 - DQ45
Pin 211 - DM5
Pin 213 - VSS
Pin 215 - DQ47
Pin 217 - DQ52
Pin 219 - VSS
Pin 221 - CK2
Pin 223 - DM6
Pin 225 - VSS
Pin 227 - DQ55
Pin 229 - DQ60
Pin 231 - VSS
Pin 233 - NC
Pin 235 - DQ62
Pin 237 VSS
Pin 239 SA0
-
Pin 196 NC/A13
NC/S1
VDDQ
DQ32
VSS
-
Pin 198 VSS
VSS
- Pin 079
-
Pin 200 DQ37
DQ33 - Pin 081
DQS4 - Pin 083
-
Pin 202 DM4
-
Pin 204 VSS
DQS4
DQ34
VSS
VSS
- Pin 085
-
Pin 206 DQ39
DQ35 - Pin 087
DQ40 - Pin 089
- Pin 088
Pin 208 - DQ44
Pin 210 - VSS
Pin 212 - NC
DQ41 - Pin 090
DQS5 - Pin 092
VSS
- Pin 091
DQS5 - Pin 093
DQ42 - Pin 095
VSS
- Pin 094
Pin 214 - DQ46
-
Pin 216 VSS
DQ43 - Pin 096
DQ48 - Pin 098
VSS
- Pin 097
-
Pin 218 DQ53
DQ49 - Pin 099
SA2 - Pin 101
-
-
-
-
-
-
-
-
-
-
Pin 220 CK2
VSS
Pin 100
Pin 102
Pin 104
Pin 106
Pin 108
Pin 110
Pin 112
Pin 114
Pin 116
-
Pin 222 VSS
NC
VSS
- Pin 103
-
Pin 224 NC
DQS6
VSS
DQS6 - Pin 105
DQ50 - Pin 107
-
Pin 226 DQ54
-
Pin 228 VSS
DQ51
DQ56
VSS
VSS
- Pin 109
-
Pin 230 DQ61
DQ57 - Pin 111
DQS7 - Pin 113
-
Pin 232 DM7
-
Pin 234 VSS
DQS7
DQ58
VSS
VSS
- Pin 115
-
Pin 236 DQ63
DQ59 - Pin 117
SDA - Pin 119
- Pin 118
- Pin 120
Pin 238 VDDSPD
Pin 240 SA1
SCL
MPPT0150
Figure 1
Pin Configuration UDIMM ×64 (240 Pin)
Data Sheet
15
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
VREF - Pin 001
DQ0 - Pin 003
VSS - Pin 005
DQS0 - Pin 007
DQ2 - Pin 009
VSS - Pin 011
DQ9 - Pin 013
DQS1 - Pin 015
VSS - Pin 017
Pin 121 - VSS
VSS
- Pin 002
- Pin 004
Pin 122 - DQ4
Pin 124 - VSS
Pin 126 - NC
Pin 128 - DQ6
Pin 130 - VSS
Pin 132 - DQ13
Pin 134 - DM1
Pin 136 - NC
Pin 138 - CK1
Pin 140 - DQ14
Pin 123 - DQ5
Pin 125 - DM0
Pin 127 - VSS
Pin 129 - DQ7
Pin 131 - DQ12
Pin 133 - VSS
Pin 135 - NC
Pin 137 - CK1
Pin 139 - VSS
Pin 141 - DQ15
Pin 143 - DQ20
Pin 145 - VSS
Pin 147 - NC
Pin 149 - DQ22
Pin 151 - VSS
Pin 153 - DQ29
Pin 155 - DM3
Pin 157 - VSS
Pin 159 - DQ31
Pin 161 - CB4
Pin 163 - VSS
Pin 165 - NC
Pin 167 - CB6
Pin 169 - VSS
Pin 171 - CKE1
Pin 173 - NC
Pin 175 - VDDQ
Pin 177 - A9
DQ1
DQS0 - Pin 006
VSS
- Pin 008
- Pin 010
- Pin 012
- Pin 014
DQ3
DQ8
VSS
DQS1 - Pin 016
NC
- Pin 018
- Pin 020
NC
- Pin 019
-
VSS
DQ10 Pin 021
-
-
Pin 142 VSS
DQ11
DQ16
VSS
Pin 022
-
VSS
Pin 023
-
-
Pin 144 DQ21
Pin 024
DQ17 - Pin 025
DQS2 - Pin 027
-
-
-
-
-
Pin 146 DM2
Pin 026
Pin 028
Pin 030
Pin 032
-
Pin 148 VSS
DQS2
VSS
VSS
- Pin 029
-
Pin 150 DQ23
DQ19 - Pin 031
DQ24 - Pin 033
-
VSS
Pin 152 DQ28
DQ25 - Pin 034
DQS3 - Pin 036
Pin 154 - VSS
Pin 156 - NC
Pin 158 - DQ30
Pin 160 - VSS
VSS
- Pin 035
DQS3 - Pin 037
DQ26 - Pin 039
VSS
- Pin 038
DQ27 - Pin 040
VSS
- Pin 041
-
Pin 162 CB5
CB0
VSS
- Pin 042
CB1 - Pin 043
DQS8 - Pin 045
-
-
-
-
-
-
Pin 164 DM8
Pin 044
Pin 046
Pin 048
Pin 050
Pin 052
-
Pin 166 VSS
DQS8
CB2
VSS
VSS
- Pin 047
-
Pin 168 CB7
CB3 - Pin 049
VDDQ - Pin 051
VDD - Pin 053
-
Pin 170 VDDQ
-
Pin 172 VDD
CKE0
-
-
Pin 174 A14
NC/BA2 Pin 054
NC
- Pin 055
-
-
-
-
-
Pin 176 A12
VDDQ
A7
Pin 056
Pin 058
Pin 060
Pin 062
A11 - Pin 057
VDD - Pin 059
-
Pin 178 VDD
Pin 179 - A8
-
Pin 180 A6
A5
A4
A2
- Pin 061
- Pin 063
Pin 181 - VDDQ
Pin 183 - A1
-
VDDQ
VDD
Pin 182 A3
- Pin 064
Pin 184 - VDD
VSS
- Pin 065
Pin 185 - CK0
Pin 187 - VDD
Pin 189 - VDD
Pin 191 - VDDQ
Pin 193 - S0
-
Pin 186 CK0
VSS
NC
- Pin 066
- Pin 068
VDD - Pin 067
VDD - Pin 069
BA0 - Pin 071
-
Pin 188 A0
A10/AP - Pin 070
Pin 190 - BA1
-
-
-
-
-
-
-
-
-
Pin 192 RAS
VDDQ
CAS
Pin 072
Pin 074
Pin 076
Pin 078
Pin 080
Pin 082
Pin 084
Pin 086
WE
- Pin 073
-
Pin 194 VDDQ
VDDQ - Pin 075
ODT1 - Pin 077
Pin 195 - ODT0
Pin 197 - VDD
Pin 199 - DQ36
Pin 201 - VSS
Pin 203 - NC
Pin 205 - DQ38
Pin 207 - VSS
Pin 209 - DQ45
Pin 211 - DM5
Pin 213 - VSS
Pin 215 - DQ47
Pin 217 - DQ52
Pin 219 - VSS
Pin 221 - CK2
Pin 223 - DM6
Pin 225 - VSS
Pin 227 - DQ55
Pin 229 - DQ60
Pin 231 - VSS
Pin 233 - NC
Pin 235 - DQ62
Pin 237 VSS
Pin 239 SA0
-
Pin 196 NC/A13
NC/S1
VDDQ
DQ32
VSS
-
Pin 198 VSS
VSS
- Pin 079
-
Pin 200 DQ37
DQ33 - Pin 081
DQS4 - Pin 083
-
Pin 202 DM4
-
Pin 204 VSS
DQS4
DQ34
VSS
VSS
- Pin 085
-
Pin 206 DQ39
DQ35 - Pin 087
DQ40 - Pin 089
- Pin 088
Pin 208 - DQ44
Pin 210 - VSS
Pin 212 - NC
DQ41 - Pin 090
DQS5 - Pin 092
VSS
- Pin 091
DQS5 - Pin 093
VSS
- Pin 094
Pin 214 - DQ46
VSS
VSS
- Pin 095
- Pin 097
-
Pin 216 VSS
DQ43 - Pin 096
DQ48 - Pin 098
-
Pin 218 DQ53
DQ49 - Pin 099
SA2 - Pin 101
-
-
-
-
-
-
-
-
-
-
Pin 220 CK2
VSS
Pin 100
Pin 102
Pin 104
Pin 106
Pin 108
Pin 110
Pin 112
Pin 114
Pin 116
-
Pin 222 VSS
NC
VSS
- Pin 103
-
Pin 224 NC
DQS6
VSS
DQS6 - Pin 105
DQ50 - Pin 107
-
Pin 226 DQ54
-
Pin 228 VSS
DQ51
DQ56
VSS
VSS
- Pin 109
-
Pin 230 DQ61
DQ57 - Pin 111
DQS7 - Pin 113
-
Pin 232 DM7
-
Pin 234 VSS
DQS7
DQ58
VSS
VSS
- Pin 115
-
Pin 236 DQ63
DQ59 - Pin 117
SDA - Pin 119
- Pin 118
- Pin 120
Pin 238 VDDSPD
Pin 240 SA1
SCL
MPPT0160
Figure 2
Pin Configuration UDIMM ×72 (240 Pin)
Data Sheet
16
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 8
Symbol
Input/Output Functional Description
Type
Polarity Function
CK0-CKn,
CK0-CKn
I
Cross
point
The system clock inputs. All address and command lines are sampled on the
cross point of the rising edge of CK and the falling edge of CK. A Delay Locked
Loop (DLL) circuit is driven from the clock inputs and output timing for read
operations is synchronized to the input clock.
CKE0-
CKEn
I
I
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal
when low. By deactivating the clocks, CKE low initiates the Power Down Mode
or the Self Refresh Mode.
S0-Sn
Active
Low
Enables the associated DDR2 SDRAM command decoder when low and
disables the command decoder when high. When the command decoder is
disabled, new commands are ignored but previous operations continue. Rank 0
is selected by S0; Rank 1 is selected by S1.
RAS, CAS, I
WE
Active
Low
When sampled at the cross point of the rising edge of CK,and falling edge of CK,
RAS, CAS and WE define the operation to be executed by the SDRAM.
BA0-BAn
I
I
—
Selects internal SDRAM memory bank
ODT0-
ODTn
Active
High
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the
DDR2 SDRAM mode register.
A[9:0],
A10/AP,
A[12:11]
I
—
During a Bank Activate command cycle, defines the row address when sampled
at the crosspoint of the rising edge of CK and falling edge of CK. During a Read
or Write command cycle, defines the column address when sampled at the cross
point of the rising edge of CK and falling edge of CK. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn
defines the bank to be precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA[1:0] to
control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used
to define which bank to precharge.
DQ[63:0]
DM[8:0]
I/O
I
—
Data Input/Output pins
Active
High
The data write masks, associated with one data byte. In Write mode, DM
operates as a byte mask by allowing input data to be written if it is low but blocks
the write operation if it is high. In Read mode, DM lines have no effect.
DQS[8:0], I/O
DQS[8:0]
Cross
point
The data strobes, associated with one data byte, sourced with data transfers. In
Write mode, the data strobe is sourced by the controller and is centered in the
data window. In Read mode the data strobe is sourced by the DDR2 SDRAM
and is sent at the leading edge of the data window. DQS signals are
complements, and timing is relative to the crosspoint of respective DQS and
DQS. If the module is to be operated in single ended strobe mode, all DQS
signals must be tied on the system board to VSS through a 20 ohm to 10 Kohm
resistor and DDR2 SDRAM mode registers programmed appropriately.
VDD,
Supply
—
—
Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
V
DDSPD, VSS
SDA
I/O
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM.
A resistor must be connected from SDA to to VDDSPD on the motherboard to act
as a pull-up.
SCL
I
I
—
—
This signal is used to clock data into and out of the SPD EEPROM.
Address pins used to select the Serial Presence Detect base address.
SA0-SAn
Data Sheet
17
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
2
Block Diagrams
ꢀꢒꢒꢙꢌꢁꢒ
ꢀꢒꢒꢖꢀꢒꢒꢗ
ꢀꢋꢏꢘ
ꢂꢆꢄꢇꢈꢇꢂꢆꢉꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢕ
ꢆꢄꢇꢈꢇꢆꢊꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢕ
ꢋꢆꢌꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢕ
ꢍꢆꢌꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢕ
ꢎꢏꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢕ
ꢍꢐꢏꢇꢄꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢕ
ꢑꢒꢃꢇꢄꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢕ
ꢀꢌꢌ
ꢂꢆꢄꢇꢈꢇꢂꢆꢉ
ꢆꢄꢇꢈꢇꢆꢊ
ꢋꢆꢌ
ꢀꢒꢒꢓꢇꢌꢁꢒꢇꢏꢏꢁꢋꢑꢀꢇꢏꢄ
ꢀꢒꢒꢖꢀꢒꢒꢗꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢕ
ꢀꢋꢏꢘꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢕ
ꢀꢌꢌꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢕ
ꢍꢆꢌ
ꢎꢏ
ꢍꢐꢏꢇꢄ
ꢇꢑꢒꢃꢇꢄ
ꢀꢌꢌ
ꢌꢄ
ꢒꢄ
ꢒꢚ
ꢒꢜ
ꢒꢟ
ꢒꢛ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢚ
ꢒꢗꢌꢚ
ꢒꢗꢌꢚ
ꢒꢗꢉꢜ
ꢒꢗꢉꢟ
ꢒꢗꢉꢛ
ꢒꢗꢉꢕ
ꢒꢗꢉꢝ
ꢒꢗꢉꢞ
ꢒꢗꢚꢄ
ꢒꢗꢚꢅ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢄ
ꢒꢗꢌꢄ
ꢒꢗꢌꢄ
ꢒꢗꢄ
ꢒꢗꢅ
ꢒꢗꢉ
ꢒꢗꢚ
ꢒꢗꢜ
ꢒꢗꢟ
ꢒꢗꢛ
ꢒꢗꢕ
ꢒꢀꢛ
ꢒꢗꢌꢛ
ꢒꢗꢌꢛ
ꢒꢗꢜꢝ
ꢒꢗꢜꢞ
ꢒꢗꢟꢄ
ꢒꢗꢟꢅ
ꢒꢗꢟꢉ
ꢒꢗꢟꢚ
ꢒꢗꢟꢜ
ꢒꢗꢟꢟ
ꢒꢅ
ꢒꢕ
ꢒꢀꢅ
ꢒꢗꢌꢅ
ꢒꢗꢌꢅ
ꢒꢗꢝ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢜ
ꢒꢗꢌꢜ
ꢒꢗꢌꢜ
ꢒꢗꢚꢉ
ꢒꢗꢚꢚ
ꢒꢗꢚꢜ
ꢒꢗꢚꢟ
ꢒꢗꢚꢛ
ꢒꢗꢚꢕ
ꢒꢗꢚꢝ
ꢒꢗꢚꢞ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢕ
ꢒꢗꢌꢕ
ꢒꢗꢌꢕ
ꢒꢗꢟꢛ
ꢒꢗꢟꢕ
ꢒꢗꢟꢝ
ꢒꢗꢟꢞ
ꢒꢗꢛꢄ
ꢒꢗꢛꢅ
ꢒꢗꢛꢉ
ꢒꢗꢛꢚ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢗꢞ
ꢒꢗꢅꢄ
ꢒꢗꢅꢅ
ꢒꢗꢅꢉ
ꢒꢗꢅꢚ
ꢒꢗꢅꢜ
ꢒꢗꢅꢟ
ꢒꢉ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢟ
ꢒꢗꢌꢟ
ꢒꢗꢌꢟ
ꢒꢗꢜꢄ
ꢒꢗꢜꢅ
ꢒꢗꢜꢉ
ꢒꢗꢜꢚ
ꢒꢗꢜꢜ
ꢒꢗꢜꢟ
ꢒꢗꢜꢛ
ꢒꢗꢜꢕ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢉ
ꢒꢗꢌꢉ
ꢒꢗꢌꢉ
ꢒꢗꢅꢛ
ꢒꢗꢅꢕ
ꢒꢗꢅꢝ
ꢒꢗꢅꢞ
ꢒꢗꢉꢄ
ꢒꢗꢉꢅ
ꢒꢗꢉꢉ
ꢒꢗꢉꢚ
ꢏꢄ
ꢌꢍꢢ
ꢌꢒꢆ
ꢌꢆꢄ
ꢌꢆꢅ
ꢇꢌꢍꢢ
ꢇꢌꢒꢆ
ꢇꢆꢄ
ꢇꢆꢅ
ꢇꢆꢉ
ꢇꢇꢇꢇꢇꢇꢇꢎꢁ
ꢡꢔꢔ
ꢀꢁꢂꢃꢄꢅꢅꢄ
Figure 3
Note
Block Diagram Raw Card A UDIMM (×64, 1 Rank, ×8)
1. DQ,DQS,DQS,DM resistors are 22 Ω ± 5 %
2. BAn, An, RAS, CAS, WE resistors are 5.1 Ω ± 5 %
3. ODT,CKE,S capacitors are 24 pF
4. All CK lines have resistor termination between CK
an CK.
Table 9
Clock Signal Loads
Clock Input
CK0,CKO
CK1,CK1
CK2,CK3
SDRAMs
Note
2
3
3
Data Sheet
18
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
ꢏꢄ
ꢇꢌꢍꢢ
ꢇꢌꢒꢆ
ꢇꢆꢄ
ꢇꢆꢅ
ꢇꢆꢉ
ꢌꢍꢢ
ꢌꢒꢆ
ꢌꢆꢄ
ꢌꢆꢅ
ꢂꢆꢄꢇꢈꢇꢂꢆꢉꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢝ
ꢆꢄꢇꢈꢇꢆꢊꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢝ
ꢋꢆꢌꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢝ
ꢂꢆꢄꢇꢈꢇꢂꢆꢉ
ꢆꢄꢇꢈꢇꢆꢊ
ꢋꢆꢌ
ꢀꢒꢒꢙꢌꢁꢒ
ꢀꢒꢒꢓꢇꢌꢁꢒꢇꢏꢏꢁꢋꢑꢀꢇꢏꢄ
ꢍꢆꢌꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢝ
ꢎꢏꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢝ
ꢍꢐꢏꢇꢄꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢝ
ꢑꢒꢃꢇꢄꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢝ
ꢍꢆꢌ
ꢎꢏ
ꢍꢐꢏꢇꢄ
ꢇꢑꢒꢃꢇꢄ
ꢀꢒꢒꢖꢀꢒꢒꢗ
ꢀꢋꢏꢘ
ꢀꢒꢒꢖꢀꢒꢒꢗꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢝ
ꢀꢋꢏꢘꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢝ
ꢀꢌꢌꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢝ
ꢇꢇꢇꢇꢇꢇꢇꢎꢁ
ꢀꢌꢌ
ꢀꢌꢌ
ꢡꢔꢔ
ꢌꢄ
ꢒꢄ
ꢒꢚ
ꢒꢛ
ꢒꢕ
ꢒꢝ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢚ
ꢒꢗꢌꢚ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢄ
ꢒꢗꢌꢄ
ꢒꢗꢌꢄ
ꢒꢗꢄ
ꢒꢗꢅ
ꢒꢗꢉ
ꢒꢗꢚ
ꢒꢗꢜ
ꢒꢗꢟ
ꢒꢗꢛ
ꢒꢗꢕ
ꢒꢀꢛ
ꢒꢗꢌꢛ
ꢒꢗꢌꢛ
ꢒꢗꢜꢝ
ꢒꢗꢜꢞ
ꢒꢗꢟꢄ
ꢒꢗꢟꢅ
ꢒꢗꢟꢉ
ꢒꢗꢟꢚ
ꢒꢗꢟꢜ
ꢒꢗꢟꢟ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢗꢌꢚ
ꢒꢗꢉꢜ
ꢒꢗꢉꢟ
ꢒꢗꢉꢛ
ꢒꢗꢉꢕ
ꢒꢗꢉꢝ
ꢒꢗꢉꢞ
ꢒꢗꢚꢄ
ꢒꢗꢚꢅ
ꢒꢅ
ꢒꢜ
ꢒꢀꢅ
ꢒꢗꢌꢅ
ꢒꢗꢌꢅ
ꢒꢗꢝ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢜ
ꢒꢗꢌꢜ
ꢒꢗꢌꢜ
ꢒꢗꢚꢉ
ꢒꢗꢚꢚ
ꢒꢗꢚꢜ
ꢒꢗꢚꢟ
ꢒꢗꢚꢛ
ꢒꢗꢚꢕ
ꢒꢗꢚꢝ
ꢒꢗꢚꢞ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢕ
ꢒꢗꢌꢕ
ꢒꢗꢌꢕ
ꢒꢗꢟꢛ
ꢒꢗꢟꢕ
ꢒꢗꢟꢝ
ꢒꢗꢟꢞ
ꢒꢗꢛꢄ
ꢒꢗꢛꢅ
ꢒꢗꢛꢉ
ꢒꢗꢛꢚ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢗꢞ
ꢒꢗꢅꢄ
ꢒꢗꢅꢅ
ꢒꢗꢅꢉ
ꢒꢗꢅꢚ
ꢒꢗꢅꢜ
ꢒꢗꢅꢟ
ꢒꢉ
ꢒꢟ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢟ
ꢒꢗꢌꢟ
ꢒꢗꢌꢟ
ꢒꢗꢜꢄ
ꢒꢗꢜꢅ
ꢒꢗꢜꢉ
ꢒꢗꢜꢚ
ꢒꢗꢜꢜ
ꢒꢗꢜꢟ
ꢒꢗꢜꢛ
ꢒꢗꢜꢕ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢉ
ꢒꢗꢌꢉ
ꢒꢗꢌꢉ
ꢒꢗꢅꢛ
ꢒꢗꢅꢕ
ꢒꢗꢅꢝ
ꢒꢗꢅꢞ
ꢒꢗꢉꢄ
ꢒꢗꢉꢅ
ꢒꢗꢉꢉ
ꢒꢗꢉꢚ
ꢇꢒꢀꢇꢇꢇꢇꢇꢍꢌ
ꢇꢒꢗꢌ
ꢇꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢝ
ꢒꢗꢌꢝ
ꢒꢗꢌꢝ
ꢍꢂꢄ
ꢍꢂꢅ
ꢍꢂꢉ
ꢍꢂꢚ
ꢍꢂꢜ
ꢍꢂꢟ
ꢍꢂꢛ
ꢍꢂꢕ
ꢀꢁꢂꢃꢄꢅꢉꢄ
Figure 4
Note
Block Diagram Raw Card A UDIMM (×72, 1 Rank, ×8)
1. DQ,DQS,DQS,DM,CB resistors are 22 Ω ± 5 %
2. BAn, An, RAS, CAS, WE resistors are 5.1 Ω ± 5 %
3. ODT,CKE,S capacitors are 24 pF
4. All CK lines have resistor termination between CK
an CK.
Table 10
Clock Signal Loads
Clock Input
CK0,CK0
CK1,CK1
SDRAMs
Note
1)
3
3
3
CK2,CK3
1)
2 SDRAMS for CK0 in case of non-ECC
Data Sheet
19
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
)
BA0 - BA2
A0 - An
RAS
BA0 - BA2: SDRAMs D0 - D15
A0 - An: SDRAMs D0 - D15
RAS: SDRAMs D0 - D15
CAS: SDRAMs D0 - D15
WE: SDRAMs D0 - D15
CKE 0: SDRAMs D0 - D7
CKE 1: SDRAMs D8 - D15
ODT 0: SDRAMs D0 - D7
ODT 0: SDRAMs D8 - D15
CAS
WE
CKE 0
CKE 1
ODT 0
ODT 1
E0
VDD,SPD
VDD/VDDQ
VREF
SCL
SDA
A0
A1
A2
SCL
SDA
SA0
SA1
VDD: SPD EEPROM E0
VDD/VDDQ: SDRAMs D0 - D15
VREF: SDRAMs D0 - D15
VSS: SDRAMs D0 - D15
VSS
WP
VSS
VSS
S0
S1
D0
D8
D4
D12
DM0
DQS0
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS
CS
CS
CS
DM
CS
DM4
DQS4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
CS
CS
CS
CS
DM
CS
CS
CS
CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
D2
D3
D9
D5
D6
D7
D13
D14
D15
DM1
DQS1
DQS1
DQ8
DM
DM
CS
CS
CS
DM5
DQS5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D10
DM2
DQS2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
DM
DM6
DQS6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D11
DM3
DQS3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
DM
DM7
DQS7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
MPBT0130
Figure 5
Note
Block Diagram Raw Card B UDIMM (×64, 1 Rank, ×8)
1. DQ,DQS,DQS,DM,CB resistors are 22 Ω ± 5 %
2. BAn, An, RAS, CAS, WE resistors are 7.5 Ω ± 5 %
3. ODT,CKE,S capacitors are 24 pF
4. All CK lines have resistor termination between CK
an CK.
Table 11
Clock Input
CK0,CK0
CK1,CK1
CK2,CK3
Clock Signal Loads
SDRAMs
Note
4
6
6
Data Sheet
20
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
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ꢀꢒꢒꢓꢇꢌꢁꢒꢇꢏꢏꢁꢋꢑꢀꢇꢏꢄ
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ꢀꢋꢏꢘꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢅꢕ
ꢀꢌꢌꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢅꢕ
ꢡꢔꢔ
ꢀꢌꢌ
ꢀꢁꢂꢃꢄꢅꢜꢄ
Figure 6
Block Diagram Raw Card B UDIMM (×72, 1 Rank, ×8)
Note:
1. DQ,DQS,DQS,DM,CB resistors are 22 Ω ± 5 %
2. BAn, An, RAS, CAS, WE resistors are 7.5 Ω ± 5 %
3. ODT,CKE,S capacitors are 24 pF
4. All CK lines have resistor termination between CK
an CK.
Table 12
Clock Input
CK0,CK0
CK1,CK1
CK2,CK3
Clock Signal Loads
SDRAMs
Note
6
6
6
Data Sheet
21
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
ꢂꢆꢄꢇꢈꢇꢂꢆꢅ
ꢆꢄꢇꢈꢇꢆꢊ
ꢋꢆꢌ
ꢂꢆꢄꢇꢈꢇꢂꢆꢅꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢚ
ꢆꢄꢇꢈꢇꢆꢊꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢚ
ꢋꢆꢌꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢚ
ꢍꢆꢌꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢚ
ꢎꢏꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢚ
ꢍꢐꢏꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢚ
ꢑꢒꢃꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢚ
ꢀꢒꢒꢙꢌꢁꢒ
ꢀꢒꢒꢖꢀꢒꢒꢗ
ꢀꢋꢏꢘ
ꢀꢒꢒꢓꢇꢌꢁꢒꢇꢏꢏꢁꢋꢑꢀꢇꢏꢄ
ꢀꢒꢒꢖꢀꢒꢒꢗꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢚ
ꢀꢋꢏꢘꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢚ
ꢀꢌꢌꢓꢇꢌꢒꢋꢆꢀꢔꢇꢒꢄꢇꢈꢇꢒꢚ
ꢍꢆꢌ
ꢎꢏ
ꢍꢐꢏꢄ
ꢑꢒꢃꢄ
ꢀꢌꢌ
ꢀꢌꢌ
ꢌꢄ
ꢒꢉ
ꢒꢄ
ꢏꢄ
ꢒꢀꢄ
ꢇꢢꢒꢀꢇꢇꢇꢍꢌ
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ꢇꢢꢒꢀꢇꢇꢇꢍꢌ
ꢇꢢꢒꢗꢌ
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ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
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ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢌꢍꢢ
ꢌꢒꢆ
ꢌꢆꢄ
ꢌꢆꢅ
ꢇꢌꢍꢢ
ꢇꢌꢒꢆ
ꢇꢆꢄ
ꢇꢆꢅ
ꢇꢆꢉ
ꢒꢗꢌꢄ
ꢒꢗꢌꢄ
ꢒꢗꢄ
ꢒꢗꢅ
ꢒꢗꢉ
ꢒꢗꢚ
ꢒꢗꢜ
ꢒꢗꢟ
ꢒꢗꢛ
ꢒꢗꢕ
ꢒꢀꢅ
ꢒꢗꢌꢅ
ꢒꢗꢌꢅ
ꢒꢗꢝ
ꢇꢢꢒꢗꢌ
ꢇꢢꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢇ%ꢒꢀ
ꢇ%ꢒꢗꢌ
ꢇ%ꢒꢗꢌ
ꢇꢠꢖꢑꢝ
ꢒꢗꢌꢜ
ꢒꢗꢌꢜ
ꢒꢗꢚꢉ
ꢒꢗꢚꢚ
ꢒꢗꢚꢜ
ꢒꢗꢚꢟ
ꢒꢗꢚꢛ
ꢒꢗꢚꢕ
ꢒꢗꢚꢝ
ꢒꢗꢚꢞ
ꢒꢀꢟ
ꢒꢗꢌꢟ
ꢒꢗꢌꢟ
ꢒꢗꢜꢄ
ꢒꢗꢜꢅ
ꢒꢗꢜꢉ
ꢒꢗꢜꢚ
ꢒꢗꢜꢜ
ꢒꢗꢜꢟ
ꢒꢗꢜꢛ
ꢒꢗꢜꢕ
ꢇꢇꢇꢇꢇꢇꢇꢎꢁ
ꢡꢔꢔ
ꢇ%ꢒꢀ
ꢇ%ꢒꢗꢌ
ꢇ%ꢒꢗꢌ
ꢇꢠꢖꢑꢝ
ꢒꢗꢞ
ꢇꢠꢖꢑꢞ
ꢇꢠꢖꢑꢞ
ꢒꢗꢅꢄ
ꢒꢗꢅꢅ
ꢒꢗꢅꢉ
ꢒꢗꢅꢚ
ꢒꢗꢅꢜ
ꢒꢗꢅꢟ
ꢇꢠꢖꢑꢅꢄ
ꢇꢠꢖꢑꢅꢅ
ꢇꢠꢖꢑꢅꢉ
ꢇꢠꢖꢑꢅꢚ
ꢇꢠꢖꢑꢅꢜ
ꢇꢠꢖꢑꢅꢟ
ꢇꢠꢖꢑꢅꢄ
ꢇꢠꢖꢑꢅꢅ
ꢇꢠꢖꢑꢅꢉ
ꢇꢠꢖꢑꢅꢚ
ꢇꢠꢖꢑꢅꢜ
ꢇꢠꢖꢑꢅꢟ
ꢒꢅ
ꢒꢚ
ꢒꢀꢉ
ꢒꢗꢌꢉ
ꢒꢗꢌꢉ
ꢒꢗꢅꢛ
ꢒꢗꢅꢕ
ꢒꢗꢅꢝ
ꢒꢗꢅꢞ
ꢒꢗꢉꢄ
ꢒꢗꢉꢅ
ꢒꢗꢉꢉ
ꢒꢗꢉꢚ
ꢒꢀꢚ
ꢒꢗꢌꢚ
ꢒꢗꢌꢚ
ꢒꢗꢉꢜ
ꢒꢗꢉꢟ
ꢒꢗꢉꢛ
ꢒꢗꢉꢕ
ꢒꢗꢉꢝ
ꢒꢗꢉꢞ
ꢒꢗꢚꢄ
ꢒꢗꢚꢅ
ꢇꢢꢒꢀꢇꢇꢇꢍꢌ
ꢇꢢꢒꢗꢌ
ꢇꢢꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢒꢀꢛ
ꢒꢗꢌꢛ
ꢒꢗꢌꢛ
ꢒꢗꢜꢝ
ꢒꢗꢜꢞ
ꢒꢗꢟꢄ
ꢒꢗꢟꢅ
ꢒꢗꢟꢉ
ꢒꢗꢟꢚ
ꢒꢗꢟꢜ
ꢒꢗꢟꢟ
ꢒꢀꢕ
ꢒꢗꢌꢕ
ꢒꢗꢌꢕ
ꢒꢗꢟꢛ
ꢒꢗꢟꢕ
ꢒꢗꢟꢝ
ꢒꢗꢟꢞ
ꢒꢗꢛꢄ
ꢒꢗꢛꢅ
ꢒꢗꢛꢉ
ꢒꢗꢛꢚ
ꢇꢢꢒꢀꢇꢇꢇꢍꢌ
ꢇꢢꢒꢗꢌ
ꢇꢢꢒꢗꢌ
ꢇꢠꢖꢑꢇꢄ
ꢇꢠꢖꢑꢇꢅ
ꢇꢠꢖꢑꢇꢉ
ꢇꢠꢖꢑꢇꢚ
ꢇꢠꢖꢑꢇꢜ
ꢇꢠꢖꢑꢇꢟ
ꢇꢠꢖꢑꢇꢛ
ꢇꢠꢖꢑꢇꢕ
ꢇ%ꢒꢀ
ꢇ%ꢒꢗꢌ
ꢇ%ꢒꢗꢌ
ꢇꢠꢖꢑꢝ
ꢇ%ꢒꢀ
ꢇ%ꢒꢗꢌ
ꢇ%ꢒꢗꢌ
ꢇꢠꢖꢑꢝ
ꢇꢠꢖꢑꢞ
ꢇꢠꢖꢑꢞ
ꢇꢠꢖꢑꢅꢄ
ꢇꢠꢖꢑꢅꢅ
ꢇꢠꢖꢑꢅꢉ
ꢇꢠꢖꢑꢅꢚ
ꢇꢠꢖꢑꢅꢜ
ꢇꢠꢖꢑꢅꢟ
ꢇꢠꢖꢑꢅꢄ
ꢇꢠꢖꢑꢅꢅ
ꢇꢠꢖꢑꢅꢉ
ꢇꢠꢖꢑꢅꢚ
ꢇꢠꢖꢑꢅꢜ
ꢇꢠꢖꢑꢅꢟ
ꢀꢁꢂꢃꢄꢅꢟꢄ
Figure 7
Note
Block Diagram Raw Card C UDIMM (×64, 1Rank, ×16)
1. DQ, DQS, DM resistors are 22 Ω ± 5 %
2. BAn, An, RAS, CAS, WE resistors are 10 Ω ± 5 %
Data Sheet
22
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 13
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
– 0.5
– 1.0
– 0.5
-55
max.
2.3
Voltage on any pins relative to VSS
Voltage on VDD relative to VSS
VIN, VOUT
VDD
V
V
2.3
Voltage on VDD Q relative to VSS
Storage temperature range
VDDQ
2.3
THSTG
HSTG
+100
95
°C
Storage Humidity (without condensation)
5
%
Note:Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Table 14
Operating Conditions
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
+55
DIMM Module Operating Temperature Range (ambient)
DRAM Component Case Temperature Range
Barometric Pressure (operating & storage)
TOPR
TCASE
PBar
0
°C
1)2)3)4)
0
+95
°C
+69
+105
kPa
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the
DRAMs. For measurement conditions, please refer to the JEDEC document JESD51-2.
2) Within the DRAM Component Case Temperature range all DRAM specification will be supported.
3) Above 85°C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the
DRAM is below 85°C case temperature before initiating self-refresh operation.
Table 15
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Limit Values
Unit
Notes
min.
nom.
max.
1.9
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
EEPROM Supply Voltage
DC Input Logic High
VDD
1.7
1.8
V
-
1)
VDDQ
VREF
VDDSPD
VIH (DC)
VIL (DC)
IL
1.7
1.8
1.9
V
2)
0.49 x VDDQ
1.7
0.5 x VDDQ
0.51 x VDDQ
3.6
V
–
–
–
V
V
REF + 0.125
V
V
5
DDQ + 0.3
V
DC Input Logic Low
– 0.30
– 5
REF – 0.125
V
3)
In / Output Leakage Current
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise variations
in VDDQ
3) Voltage for pin connector under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all othe pins at 0 V. Current is per pin
.
Data Sheet
23
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
4
IDD Specifications and Conditions
Table 16
I
DD Measurement Conditions1)2)
Parameter
Symbol
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
IDD1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin.
,
t
RCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
IDD2N
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current
IDD2Q
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Power-Down Current
All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
IDD3P(0)
IDD3P(1)
IDD3N
Active Power-Down Current
All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
t
RAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.
;
t
RAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.
;
t
RAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
IDD5B
t
CK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
IDD5D
t
CK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
24
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
Table 16
I
DD Measurement Conditions1)2) (cont’d)
Parameter
Symbol
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85 °C
max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) For details and notes see the relevant INFINEON component data sheet
Table 17
IDD Specification
Product Type
Unit
Notes
Organization
256MB
×64
1 Rank
–3.7
Max.
320
360
16
512MB
×64
1 Rank
–3.7
Max.
520
600
32
512MB
×72
1 Rank
–3.7
Max.
585
675
36
1GB
×64
2 Ranks
–3.7
Max.
552
632
64
1GB
×72
2 Ranks
–3.7
Max.
621
711
72
Symbol
IDD0
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2F
160
120
64
320
240
128
40
360
270
144
45
640
480
256
80
720
540
288
90
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
20
160
400
440
520
24
320
720
760
1040
48
360
810
855
1170
54
640
752
792
1072
96
720
846
891
1206
108
72
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
16
32
36
64
IDD7
880
1120
1260
1152
1296
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled
Data Sheet
25
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
Table 18
IDD Specification
Product Type
Unit
Notes
Organization
256MB
×64
1 Rank
–5
512MB
×64
1 Rank
–5
512MB
×72
1 Rank
–5
1GB
×64
2 Ranks
–5
1GB
×72
2 Ranks
–5
Symbol
IDD0
Max.
280
300
16
Max.
440
480
32
Max.
495
540
36
Max.
472
512
64
Max.
531
576
72
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2F
128
100
52
256
200
104
40
288
225
117
45
512
400
208
80
576
450
234
90
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
20
140
340
360
480
24
280
560
600
960
48
315
630
675
1080
54
560
592
632
992
96
630
666
711
1116
108
72
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
16
32
36
64
IDD7
840
1040
1170
1072
1206
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled
Data Sheet
26
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
4.1
IDD Test Conditions
For testing the IDD parameters, the following timing parameters are used:
Table 19
IDD Measurement Test Conditions
Parameter
Symbol
-5
-3.7
PC2-4200
4-4-4
4
Unit
PC2-3200
3-3-3
3
CAS Latency
CLmin
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
tCKmin
5
3.75
15
Active to Read or Write delay
tRCDmin
tRCmin
tRRDmin
tRRDmin
tRASmin
tRPmin
15
55
7.5
10
40
15
105
Active to Active / Auto-Refresh command period
Active bank A to Active bank B x8 1)
command delay
60
7.5
x16 2)
10
Active to Precharge Command
Precharge Command Period
45
15
Auto-Refresh to Active / Auto-Refresh command
period
tRFCmin
105
Average periodic Refresh interval
tREFI
7.8
7.8
µs
1) For modules based on x8 components
2) For modules based on x16 components
4.2
ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The current
consumption for any terminated input pin, depends on the input pin is in tristate or driving 0 or 1, as long a ODT
is enabled during a given period of time.
Table 20
ODT current per terminated pin:
EMRS(1)
State
min.
typ.
max.
Unit
Enabled ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; Data Bus inputs are
FLOATING
IODTO
A6 = 0, A2 = 1 5
6
3
7.5
mA/DQ
mA/DQ
A6 = 1, A2 = 0 2.5
3.75
Active ODT current per DQ
IODTT
A6 = 0, A2 = 1 10
A6 = 1, A2 = 0 5
12
6
15
mA/DQ
mA/DQ
added IDDQ current for ODT enabled;
ODT is HIGH; worst case of Data Bus inputs
are STABLE or SWITCHING.
7.5
Note:For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
27
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
5
Electrical Characteristics & AC Timings
5.1
AC Timing Parameter by Speed Grade (Component level data, for reference only)
Table 21
AC Timing - Absolute Specifications –5 / –3.7
Symbol Parameter
–5
–3.7
Unit Notes
DDR2–400
DDR2–533
min.
− 600
2
max.
min.
-500
2
max.
1)
tAC
DQ output access time from CK/CK
+ 600
-
+500
ps
1)
tCCD
tCH
tCK
CAS A to CAS B Command Period
CK, CK high-level width
Clock cycle time
-
tCK
1)
0.45
5000
5000
3
0.55
8000
8000
-
0.45
5000
3750
3
0.55
tCK
1)2)
8000
ps
1)3)
8000
ps
1)
tCKE
tCL
tDAL
tDELAY
CKE minimum high and low pulse width
CK, CK low-level width
-
tCK
1)
0.45
0.55
-
0.45
WR+tRP
0.55
tCK
1)
Auto precharge write recovery + precharge time WR+tRP
-
-
tCK
1)
Minimum time clocks remain ON after CKE
asynchronously drops low
tIS+tCK+tI -
tIS+tCK
+tIH
ns
H
1)4)
tDH
DQ and DM input hold time
400
-
350
-
ps
1)
tDIPW
tDQSCK
DQ and DM input pulse width (each input)
DQS output access time from CK/CK
0.35
− 500
0.35
-
0.35
−450
0.35
-
tCK
1)
+ 500
+450
ps
1)
tDQSL,H DQS input low (high) pulse width (write cycle)
-
-
tCK
1)
tDQSS
Write command to 1st DQS latching transition
WL -
0.25
WL
+0.25
WL
-0.25
WL
+0.25
tCK
1)
tDQSQ
DQS-DQ skew
-
350
-
300
ps
(for DQS & associated DQ signals)
1)4)
tDS
DQ and DM input setup time
400
0.2
-
-
350
0.2
-
-
ps
1)
tDSH
DQS falling edge hold time from CLK
(write cycle)
tCK
1)
tDSS
DQS falling edge to CLK setup time
(write cycle)
0.2
-
0.2
-
tCK
1)
tHP
Clock Half Period
min. (tCL, tCH)
min. (tCL, tCH)
1)
tHZ
Data-out high-impedance time from CK/CK
Address and control input hold time
-
tACmax
-
tACmax
ps
1)4)
tIH
600
-
-
-
600
0.6
600
-
-
-
ps
1)
tIPW
tIS
Control and Addr. input pulse width (each input) 0.6
tCK
1)4)
Address and control input setup time
DQ low-impedance from CK / CK
600
ps
1)
tLZ(DQ)
2*tACmin tACmax
2*tACmin tACmax
ps
1)
tLZ(DQS) DQS low-impedance from CK / CK
tACmin
tACmax
tACmin
tACmax
ps
1)
tMRD
tOIT
tRAS
tRC
Mode register set command cycle time
OCD drive mode output delay
2
-
2
0
-
tCK
1)
0
12
12
ns
1)
Active to Precharge command
40
70000 45
70000
ns
1)
Active to Active/Auto-refresh command period 55
-
-
60
15
-
-
ns
1)
tRCD
Active to Read or Write delay (with and without 15
Auto-Precharge) delay
ns
Data Sheet
28
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
Table 21
AC Timing - Absolute Specifications –5 / –3.7
Symbol Parameter
–5
–3.7
Unit Notes
DDR2–400
DDR2–533
min.
max.
min.
max.
1)
tREFI
tRFC
Average Periodic Refresh
Interval
0οC - 85οC
85οC - 95οC
-
7.8
3.9
-
-
7.8
3.9
-
µs
1)
-
-
1)
Auto-refresh to Active/Auto-refresh command
period
105
105
ns
1)
tRP
Precharge command period
Read preamble
15
-
15
-
ns
1)
tRPRE
tRPST
tRRD
0.9
0.40
7.5
1.1
0.60
-
0.9
0.40
7.5
1.1
0.60
-
tCK
1)
Read postamble
tCK
1)
Active bank A to Active bank B x8
ns
command
(1k page size)
1)
x16
(2k page size)
10
-
-
10
-
-
ns
1)
tRTP
Internal read to precharge command delay
7.5
7.5
ns
1)
1)
tQH
Data Output hold time from DQS
Data hold skew factor
Write preamble
tHP - tQHS
-
tHP-tQHS
-
-
1)
tQHS
tWPRE
tWPST
tWR
-
450
400
ps
1)
0.25
0.40
15
10
2
-
0.25
0.40
15
-
tCK
1)
Write postamble
0.60
0.60
tCK
1)
Write recovery time
-
-
-
-
-
-
ns
1)
tWTR
tXARD
Internal write to read command delay
7.5
2
ns
1)
Exit power down to any valid command
(other than NOP or Deselect)
tCK
1)
tXARDS
tXP
tXSNR
tXSRD
Exit active power-down mode to read command 6 - AL
(slew exit, lower power)
-
-
6 - AL
2
-
-
-
-
tCK
1)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
2
tCK
1)5)
Exit Self-Refresh to non-read command
t
RFC + 10 -
tRFC
+
ns
10
1)6)
Exit Self-Refresh to read command
200
-
200
tCK
1) For details and notes see the relevant INFINEON component datasheet
2) CL = 3
3) CL = 4 & 5
4) Timing definition and values for tIS, tIH, tDS and tDH may change due to actual JEDEC work. This may also effect the SPD
code for these parameters
5) 0 °C ≤ TCASE ≤ 85 °C
6) 85 °C < TCASE ≤ 95 °C
Data Sheet
29
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
Table 22
ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition
ODT to Power Down Mode Entry Latency
min.
max.
Unit
tCK
tANPD
tAOF
3
-
ODT turn-off
tAC(min)
2.5
tAC(max) + 0.6 ns
ns
tAOFD
tAOFPD
tAON
ODT turn-off delay
2.5
tCK
ODT turn-off delay (Power-Down Modes)
tAC(min) + 2 ns
tAC(min)
2.5 tCK + tAC(max) + 1 ns ns
ODT turn-on
DDR2-
tAC(max) + 1 ns
ns
400/533
tAOND
tAONPD
tAXPD
ODT turn-on delay
2
2
tCK
ODT turn-on (Power-Down Modes)
ODT Power Down Exit Latency
tAC(min) + 2 ns
2 tCK + tAC(max) + 1 ns ns
8
-
tCK
Data Sheet
30
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
6
SPD Codes
Table 23
SPD Codes for HYS[64/72]T[32/64]000GU–3.7–A
Product Type
Organization
256 MB
512 MB
×64
512 MB
×72
×64
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
0
Programmed SPD Bytes in EEPROM
1
Total number of Bytes in EEPROM
Memory Type (DDR2)
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
08
08
08
2
08
08
08
3
0D
0A
60
0E
0A
60
0E
0A
60
4
5
6
40
40
48
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
t
t
CK @ CLmax (Byte 18) [ns]
3D
50
3D
50
3D
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
AC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
00
00
02
82
82
82
10
08
08
00
00
08
00
00
00
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
Not used
0C
04
0C
04
0C
04
38
38
38
00
00
00
DIMM Type Information
DIMM Attributes
02
02
02
00
00
00
Component Attributes
01
01
01
t
t
t
t
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
CK @ CLmax -2 (Byte 18) [ns]
AC SDRAM @ CLmax -2 [ns]
3D
50
3D
50
3D
50
50
50
50
60
60
60
Data Sheet
31
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 23
SPD Codes for HYS[64/72]T[32/64]000GU–3.7–A (cont’d)
Product Type
Organization
256 MB
512 MB
×64
512 MB
×72
×64
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
3C
28
Rev. 1.1
HEX
3C
1E
3C
2D
80
Rev. 1.1
HEX
3C
1E
3C
2D
80
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
t
t
t
t
RP.min [ns]
RRD.min [ns]
RCD.min [ns]
RAS.min [ns]
3C
2D
40
Module Density per Rank
t
t
t
t
t
t
t
AS.min and tCS.min [ns]
AH.min and tCH.min [ns]
DS.min [ns]
25
25
25
37
37
37
10
10
10
DH.min [ns]
22
22
22
WR.min [ns]
3C
1E
1E
00
3C
1E
1E
00
3C
1E
1E
00
WTR.min [ns]
RTP.min [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.min [ns]
00
00
00
3C
69
3C
69
3C
69
RFC.min [ns]
CK.max [ns]
80
80
80
DQSQ.max [ns]
QHS.max [ns]
1E
28
1E
28
1E
28
PLL Relock Time
CASE.max Delta / ∆T4R4W Delta
00
00
00
T
53
51
51
Psi(T-A) DRAM
72
78
78
∆T0 (DT0)
52
3E
2E
1E
1E
24
3E
2E
1E
1E
24
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q, RDIMM) 2B
∆T2P (DT2P)
1D
1D
23
16
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
17
17
Data Sheet
32
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 23
SPD Codes for HYS[64/72]T[32/64]000GU–3.7–A (cont’d)
Product Type
Organization
256 MB
512 MB
×64
512 MB
×72
×64
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
36
Rev. 1.1
HEX
34
Rev. 1.1
HEX
34
55
56
57
58
59
60
61
62
63
64
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)
∆T5B (DT5B)
1C
30
1E
20
1E
20
∆T7 (DT7)
Psi(ca) PLL
00
00
00
Psi(ca) REG
00
00
00
∆TPLL (DTPLL)
00
00
00
∆TREG (DTREG) / Toggle Rate
SPD Revision
00
00
00
11
11
11
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
B9
C1
00
CF
C1
00
E1
C1
00
65 - 71 JEDEC ID Code of Infineon (2 - 8)
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Module Manufacturer Location
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
xx
xx
xx
36
36
37
34
34
32
54
54
54
33
36
36
32
34
34
30
30
30
30
30
30
30
30
30
47
47
47
55
55
55
33
33
33
2E
37
2E
37
2E
37
41
41
41
20
20
20
20
20
20
Data Sheet
33
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 23
SPD Codes for HYS[64/72]T[32/64]000GU–3.7–A (cont’d)
Product Type
Organization
256 MB
512 MB
×64
512 MB
×72
×64
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
20
Rev. 1.1
HEX
20
Rev. 1.1
HEX
20
89
90
91
92
93
94
95
96
97
98
Product Type, Char 17
Product Type, Char 18
20
20
20
Module Revision Code
2x
2x
2x
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1)
Module Serial Number (2)
Module Serial Number (3)
Module Serial Number (4)
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
99 -127 Not Used
00
00
00
128-
255
BLANK
FF
FF
FF
Data Sheet
34
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 24
SPD Codes HYS[64/72]T128020GU–3.7–A
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Byte#
0
Description
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
1
08
08
2
08
08
3
0E
0A
61
0E
0A
61
4
5
6
40
48
7
Not used
00
00
8
Interface Voltage Level
05
05
9
t
t
CK @ CLmax (Byte 18) [ns]
3D
50
3D
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
AC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
00
02
82
82
08
08
00
08
00
00
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
Not used
0C
04
0C
04
38
38
00
00
DIMM Type Information
DIMM Attributes
02
02
00
00
Component Attributes
01
01
t
t
t
t
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
CK @ CLmax -2 (Byte 18) [ns]
AC SDRAM @ CLmax -2 [ns]
3D
50
3D
50
50
50
60
60
Data Sheet
35
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 24
SPD Codes HYS[64/72]T128020GU–3.7–A (cont’d)
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
HEX
3C
1E
3C
2D
80
Rev. 1.1
HEX
3C
1E
3C
2D
80
Byte#
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Description
t
t
t
t
RP.min [ns]
RRD.min [ns]
RCD.min [ns]
RAS.min [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.min and tCS.min [ns]
AH.min and tCH.min [ns]
DS.min [ns]
25
25
37
37
10
10
DH.min [ns]
22
22
WR.min [ns]
3C
1E
1E
00
3C
1E
1E
00
WTR.min [ns]
RTP.min [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.min [ns]
00
00
3C
69
3C
69
RFC.min [ns]
CK.max [ns]
80
80
DQSQ.max [ns]
QHS.max [ns]
1E
28
1E
28
PLL Relock Time
CASE.max Delta / ∆T4R4W Delta
00
00
T
51
51
Psi(T-A) DRAM
78
78
∆T0 (DT0)
3E
2E
1E
1E
24
3E
2E
1E
1E
24
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
17
17
Data Sheet
36
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 24
SPD Codes HYS[64/72]T128020GU–3.7–A (cont’d)
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
HEX
34
Rev. 1.1
HEX
34
Byte#
55
Description
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)
∆T5B (DT5B)
56
1E
20
1E
20
57
∆T7 (DT7)
58
Psi(ca) PLL
00
00
59
Psi(ca) REG
00
00
60
∆TPLL (DTPLL)
00
00
61
∆TREG (DTREG) / Toggle Rate
SPD Revision
00
00
62
11
11
63
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2 - 8)
Module Manufacturer Location
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
D0
C1
00
E2
C1
00
64
65 - 71
72
xx
xx
73
36
37
74
34
32
75
54
54
76
31
31
77
32
32
78
38
38
79
30
30
80
32
32
81
30
30
82
47
47
83
55
55
84
33
33
85
2E
37
2E
37
86
87
41
41
88
20
20
Data Sheet
37
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 24
SPD Codes HYS[64/72]T128020GU–3.7–A (cont’d)
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
HEX
20
Rev. 1.1
HEX
20
Byte#
89
Description
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1)
Module Serial Number (2)
Module Serial Number (3)
Module Serial Number (4)
Not Used
90
20
20
91
2x
2x
92
xx
xx
93
xx
xx
94
xx
xx
95
xx
xx
96
xx
xx
97
xx
xx
98
xx
xx
99 -127
128-255
00
00
BLANK
FF
FF
Data Sheet
38
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 25
SPD Codes for HYS[64/72]T[32/64]000HU–3.7–A
Product Type
Organization
256 MB
512 MB
×64
512 MB
×72
×64
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Byte#
0
Description
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
1
08
08
08
2
08
08
08
3
0D
0A
60
0E
0A
60
0E
0A
60
4
5
6
40
40
48
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
t
CK @ CLmax (Byte 18) [ns]
3D
50
3D
50
3D
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
00
00
02
82
82
82
10
08
08
00
00
08
00
00
00
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
Not used
0C
04
0C
04
0C
04
38
38
38
00
00
00
DIMM Type Information
DIMM Attributes
02
02
02
00
00
00
Component Attributes
01
01
01
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tCK @ CLmax -2 (Byte 18) [ns]
tAC SDRAM @ CLmax -2 [ns]
tRP.min [ns]
3D
50
3D
50
3D
50
50
50
50
60
60
60
3C
3C
3C
Data Sheet
39
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 25
SPD Codes for HYS[64/72]T[32/64]000HU–3.7–A (cont’d)
Product Type
Organization
256 MB
512 MB
×64
512 MB
×72
×64
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
HEX
28
Rev. 1.1
HEX
1E
3C
2D
80
Rev. 1.1
HEX
1E
3C
2D
80
Byte#
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Description
tRRD.min [ns]
tRCD.min [ns]
tRAS.min [ns]
3C
2D
40
Module Density per Rank
t
t
t
t
t
t
t
AS.min and tCS.min [ns]
AH.min and tCH.min [ns]
DS.min [ns]
25
25
25
37
37
37
10
10
10
DH.min [ns]
22
22
22
WR.min [ns]
3C
1E
1E
00
3C
1E
1E
00
3C
1E
1E
00
WTR.min [ns]
RTP.min [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
00
00
00
RC.min [ns]
3C
69
3C
69
3C
69
RFC.min [ns]
CK.max [ns]
80
80
80
DQSQ.max [ns]
QHS.max [ns]
1E
28
1E
28
1E
28
PLL Relock Time
CASE.max Delta / ∆T4R4W Delta
00
00
00
T
53
51
51
Psi(T-A) DRAM
72
78
78
∆T0 (DT0)
52
3E
2E
1E
1E
24
3E
2E
1E
1E
24
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q, RDIMM)
∆T2P (DT2P)
2B
1D
1D
23
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)
16
17
17
36
34
34
Data Sheet
40
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 25
SPD Codes for HYS[64/72]T[32/64]000HU–3.7–A (cont’d)
Product Type
Organization
256 MB
512 MB
×64
512 MB
×72
×64
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
HEX
1C
30
Rev. 1.1
HEX
1E
20
Rev. 1.1
HEX
1E
20
Byte#
56
Description
∆T5B (DT5B)
57
∆T7 (DT7)
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆TPLL (DTPLL)
00
00
00
61
∆TREG (DTREG) / Toggle Rate
SPD Revision
00
00
00
62
11
11
11
63
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
B9
C1
00
CF
C1
00
E1
C1
00
64
65 - 71 JEDEC ID Code of Infineon (2 - 8)
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Module Manufacturer Location
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
xx
xx
xx
36
36
37
34
34
32
54
54
54
33
36
36
32
34
34
30
30
30
30
30
30
30
30
30
48
48
48
55
55
55
33
33
33
2E
37
2E
37
2E
37
41
41
41
20
20
20
20
20
20
20
20
20
Data Sheet
41
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 25
SPD Codes for HYS[64/72]T[32/64]000HU–3.7–A (cont’d)
Product Type
Organization
256 MB
512 MB
×64
512 MB
×72
×64
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
HEX
20
Rev. 1.1
HEX
20
Rev. 1.1
HEX
20
Byte#
90
Description
Product Type, Char 18
91
Module Revision Code
2x
2x
2x
92
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1)
Module Serial Number (2)
Module Serial Number (3)
Module Serial Number (4)
xx
xx
xx
93
xx
xx
xx
94
xx
xx
xx
95
xx
xx
xx
96
xx
xx
xx
97
xx
xx
xx
98
xx
xx
xx
99 -127 Not Used
128-255 BLANK
00
00
00
FF
FF
FF
Data Sheet
42
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 26
SPD Codes for HYS[64/72]T128020HU–3.7–A
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Byte#
0
Description
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
1
08
08
2
08
08
3
0E
0A
61
0E
0A
61
4
5
6
40
48
7
Not used
00
00
8
Interface Voltage Level
05
05
9
t
t
CK @ CLmax (Byte 18) [ns]
3D
50
3D
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
AC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
00
02
82
82
08
08
00
08
00
00
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
Not used
0C
04
0C
04
38
38
00
00
DIMM Type Information
DIMM Attributes
02
02
00
00
Component Attributes
01
01
t
t
t
t
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
CK @ CLmax -2 (Byte 18) [ns]
AC SDRAM @ CLmax -2 [ns]
3D
50
3D
50
50
50
60
60
Data Sheet
43
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 26
SPD Codes for HYS[64/72]T128020HU–3.7–A (cont’d)
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
HEX
3C
1E
3C
2D
80
Rev. 1.1
HEX
3C
1E
3C
2D
80
Byte#
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Description
t
t
t
t
RP.min [ns]
RRD.min [ns]
RCD.min [ns]
RAS.min [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.min and tCS.min [ns]
AH.min and tCH.min [ns]
DS.min [ns]
25
25
37
37
10
10
DH.min [ns]
22
22
WR.min [ns]
3C
1E
1E
00
3C
1E
1E
00
WTR.min [ns]
RTP.min [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.min [ns]
00
00
3C
69
3C
69
RFC.min [ns]
CK.max [ns]
80
80
DQSQ.max [ns]
QHS.max [ns]
1E
28
1E
28
PLL Relock Time
CASE.max Delta / ∆T4R4W Delta
00
00
T
51
51
Psi(T-A) DRAM
78
78
∆T0 (DT0)
3E
2E
1E
1E
24
3E
2E
1E
1E
24
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
17
17
Data Sheet
44
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 26
SPD Codes for HYS[64/72]T128020HU–3.7–A (cont’d)
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
HEX
34
Rev. 1.1
HEX
34
Byte#
55
Description
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)
∆T5B (DT5B)
56
1E
20
1E
20
57
∆T7 (DT7)
58
Psi(ca) PLL
00
00
59
Psi(ca) REG
00
00
60
∆TPLL (DTPLL)
00
00
61
∆TREG (DTREG) / Toggle Rate
SPD Revision
00
00
62
11
11
63
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2 - 8)
Module Manufacturer Location
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
D0
C1
00
E2
C1
00
64
65 - 71
72
xx
xx
73
36
37
74
34
32
75
54
54
76
31
31
77
32
32
78
38
38
79
30
30
80
32
32
81
30
30
82
48
48
83
55
55
84
33
33
85
2E
37
2E
37
86
87
41
41
88
20
20
Data Sheet
45
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 26
SPD Codes for HYS[64/72]T128020HU–3.7–A (cont’d)
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
HEX
20
Rev. 1.1
HEX
20
Byte#
89
Description
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1)
Module Serial Number (2)
Module Serial Number (3)
Module Serial Number (4)
Not Used
90
20
20
91
2x
2x
92
xx
xx
93
xx
xx
94
xx
xx
95
xx
xx
96
xx
xx
97
xx
xx
98
xx
xx
99 -127
128-255
00
00
BLANK
FF
FF
Data Sheet
46
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 27
SPD Codes for HYS[64/72]T32000GU–5–A
Product Type
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16) 1 Rank (×8) 1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Byte#
0
Description
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
1
08
08
08
2
08
08
08
3
0D
0A
60
0E
0A
60
0E
0A
60
4
5
6
40
40
48
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
t
t
CK @ CLmax (Byte 18) [ns]
50
50
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
AC SDRAM @ CLmax (Byte 18) [ns]
60
60
60
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
00
00
02
82
82
82
10
08
08
00
00
08
00
00
00
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
Not used
0C
04
0C
04
0C
04
38
38
38
00
00
00
DIMM Type Information
DIMM Attributes
02
02
02
00
00
00
Component Attributes
01
01
01
t
t
t
t
t
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
CK @ CLmax -2 (Byte 18) [ns]
AC SDRAM @ CLmax -2 [ns]
RP.min [ns]
50
50
50
60
60
60
50
50
50
60
60
60
3C
3C
3C
Data Sheet
47
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 27
SPD Codes for HYS[64/72]T32000GU–5–A (cont’d)
Product Type
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16) 1 Rank (×8) 1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
28
Rev. 1.1
HEX
1E
3C
2D
80
Rev. 1.1
HEX
1E
3C
2D
80
Byte#
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Description
t
t
t
RRD.min [ns]
RCD.min [ns]
RAS.min [ns]
3C
2D
40
Module Density per Rank
t
t
t
t
t
t
t
AS.min and tCS.min [ns]
AH.min and tCH.min [ns]
DS.min [ns]
35
35
35
47
47
47
15
15
15
DH.min [ns]
27
27
27
WR.min [ns]
3C
28
3C
28
3C
28
WTR.min [ns]
RTP.min [ns]
1E
00
1E
00
1E
00
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.min [ns]
00
00
00
3C
69
3C
69
3C
69
RFC.min [ns]
CK.max [ns]
80
80
80
DQSQ.max [ns]
QHS.max [ns]
23
23
23
2D
00
2D
00
2D
00
PLL Relock Time
CASE.max Delta / ∆T4R4W Delta
T
51
51
51
Psi(T-A) DRAM
72
78
78
∆T0 (DT0)
42
32
32
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q, RDIMM)
∆T2P (DT2P)
23
24
24
1D
19
1E
1B
1E
17
1E
1B
1E
17
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)
∆T5B (DT5B)
1C
16
2E
1A
28
28
1B
1B
Data Sheet
48
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 27
SPD Codes for HYS[64/72]T32000GU–5–A (cont’d)
Product Type
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16) 1 Rank (×8) 1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
2D
00
Rev. 1.1
HEX
1E
00
Rev. 1.1
HEX
1E
00
Byte#
57
Description
∆T7 (DT7)
58
Psi(ca) PLL
59
Psi(ca) REG
00
00
00
60
∆TPLL (DTPLL)
00
00
00
61
∆TREG (DTREG) / Toggle Rate
SPD Revision
00
00
00
62
11
11
11
63
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2- 8)
Module Manufacturer Location
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
0B
C1
00
23
35
64
C1
00
C1
00
65 - 71
72
xx
xx
xx
73
36
36
37
74
34
34
32
75
54
54
54
76
33
36
36
77
32
34
34
78
30
30
30
79
30
30
30
80
30
30
30
81
47
47
47
82
55
55
55
83
35
35
35
84
41
41
41
85
20
20
20
86
20
20
20
87
20
20
20
88
20
20
20
89
20
20
20
90
20
20
20
91
2x
2x
2x
Data Sheet
49
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 27
SPD Codes for HYS[64/72]T32000GU–5–A (cont’d)
Product Type
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16) 1 Rank (×8) 1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
xx
Rev. 1.1
HEX
xx
Rev. 1.1
HEX
xx
Byte#
92
Description
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1)
Module Serial Number (2)
Module Serial Number (3)
Module Serial Number (4)
93
xx
xx
xx
94
xx
xx
xx
95
xx
xx
xx
96
xx
xx
xx
97
xx
xx
xx
98
xx
xx
xx
99 -127 Not Used
128-255 BLANK
00
00
00
FF
FF
FF
Table 28
SPD Codes for HYS[64/72]T128020GU–5–A
Product Type
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Byte#
Description
0
1
2
3
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
08
08
08
08
Number of Row Addresses
0E
0E
Data Sheet
50
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 28
SPD Codes for HYS[64/72]T128020GU–5–A (cont’d)
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
0A
61
Rev. 1.1
HEX
0A
61
Byte#
4
Description
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
5
6
40
48
7
Not used
00
00
8
Interface Voltage Level
05
05
9
t
t
CK @ CLmax (Byte 18) [ns]
50
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
AC SDRAM @ CLmax (Byte 18) [ns]
60
60
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
00
02
82
82
08
08
00
08
00
00
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
Not used
0C
04
0C
04
38
38
00
00
DIMM Type Information
DIMM Attributes
02
02
00
00
Component Attributes
01
01
t
t
t
t
t
t
t
t
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
CK @ CLmax -2 (Byte 18) [ns]
AC SDRAM @ CLmax -2 [ns]
RP.min [ns]
50
50
60
60
50
50
60
60
3C
1E
3C
2D
80
3C
1E
3C
2D
80
RRD.min [ns]
RCD.min [ns]
RAS.min [ns]
Module Density per Rank
Data Sheet
51
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 28
SPD Codes for HYS[64/72]T128020GU–5–A (cont’d)
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
35
Rev. 1.1
HEX
35
Byte#
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
Description
t
t
t
t
t
t
t
AS.min and tCS.min [ns]
AH.min and tCH.min [ns]
DS.min [ns]
47
47
15
15
DH.min [ns]
27
27
WR.min [ns]
3C
28
3C
28
WTR.min [ns]
RTP.min [ns]
1E
00
1E
00
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.min [ns]
00
00
3C
69
3C
69
RFC.min [ns]
CK.max [ns]
80
80
DQSQ.max [ns]
QHS.max [ns]
23
23
2D
00
2D
00
PLL Relock Time
CASE.max Delta / ∆T4R4W Delta
T
51
51
Psi(T-A) DRAM
78
78
∆T0 (DT0)
32
32
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q, RDIMM)
∆T2P (DT2P)
24
24
1E
1B
1E
17
1E
1B
1E
17
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)
∆T5B (DT5B)
28
28
1B
1E
00
1B
1E
00
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
00
00
Data Sheet
52
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 28
SPD Codes for HYS[64/72]T128020GU–5–A (cont’d)
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
00
Rev. 1.1
HEX
00
Byte#
60
Description
∆TPLL (DTPLL)
61
∆TREG (DTREG) / Toggle Rate
SPD Revision
00
00
62
11
11
63
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
24
36
64
C1
00
C1
00
65 - 71 JEDEC ID Code of Infineon (2 - 8)
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
Module Manufacturer Location
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
xx
xx
36
37
34
32
54
54
31
31
32
32
38
38
30
30
32
32
30
30
47
47
55
55
35
35
41
41
20
20
20
20
20
20
20
20
20
20
2x
2x
xx
xx
xx
xx
Data Sheet
53
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 28
SPD Codes for HYS[64/72]T128020GU–5–A (cont’d)
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
xx
Rev. 1.1
HEX
xx
Byte#
94
Description
Module Manufacturing Date Week
Module Serial Number (1)
Module Serial Number (2)
Module Serial Number (3)
Module Serial Number (4)
95
xx
xx
96
xx
xx
97
xx
xx
98
xx
xx
99 -127 Not Used
128-255 BLANK
00
00
FF
FF
Table 29
SPD Codes for HYS[64/72]T[32/64]000HU–5–A
Product Type
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16) 1 Rank (×8) 1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Byte#
Description
0
1
2
3
4
5
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
08
08
08
08
08
08
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
0D
0E
0E
0A
0A
0A
60
60
60
Data Sheet
54
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 29
SPD Codes for HYS[64/72]T[32/64]000HU–5–A (cont’d)
Product Type
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16) 1 Rank (×8) 1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
40
Rev. 1.1
HEX
40
Rev. 1.1
HEX
48
Byte#
6
Description
Data Width
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
t
t
CK @ CLmax (Byte 18) [ns]
50
50
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
AC SDRAM @ CLmax (Byte 18) [ns]
60
60
60
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
00
00
02
82
82
82
10
08
08
00
00
08
00
00
00
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
Not used
0C
04
0C
04
0C
04
38
38
38
00
00
00
DIMM Type Information
DIMM Attributes
02
02
02
00
00
00
Component Attributes
01
01
01
t
t
t
t
t
t
t
t
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
CK @ CLmax -2 (Byte 18) [ns]
AC SDRAM @ CLmax -2 [ns]
RP.min [ns]
50
50
50
60
60
60
50
50
50
60
60
60
3C
28
3C
1E
3C
2D
80
3C
1E
3C
2D
80
RRD.min [ns]
RCD.min [ns]
3C
2D
40
RAS.min [ns]
Module Density per Rank
t
t
t
AS.min and tCS.min [ns]
AH.min and tCH.min [ns]
DS.min [ns]
35
35
35
47
47
47
15
15
15
Data Sheet
55
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 29
SPD Codes for HYS[64/72]T[32/64]000HU–5–A (cont’d)
Product Type
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16) 1 Rank (×8) 1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
27
Rev. 1.1
HEX
27
Rev. 1.1
HEX
27
Byte#
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Description
t
t
t
t
DH.min [ns]
WR.min [ns]
WTR.min [ns]
RTP.min [ns]
3C
28
3C
28
3C
28
1E
00
1E
00
1E
00
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.min [ns]
00
00
00
3C
69
3C
69
3C
69
RFC.min [ns]
CK.max [ns]
80
80
80
DQSQ.max [ns]
QHS.max [ns]
23
23
23
2D
00
2D
00
2D
00
PLL Relock Time
CASE.max Delta / ∆T4R4W Delta
T
51
51
51
Psi(T-A) DRAM
72
78
78
∆T0 (DT0)
42
32
32
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q, RDIMM)
∆T2P (DT2P)
23
24
24
1D
19
1E
1B
1E
17
1E
1B
1E
17
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)
∆T5B (DT5B)
1C
16
2E
1A
2D
00
28
28
1B
1E
00
1B
1E
00
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
00
00
00
∆TPLL (DTPLL)
00
00
00
∆TREG (DTREG) / Toggle Rate
SPD Revision
00
00
00
11
11
11
Checksum of Bytes 0-62
0B
23
35
Data Sheet
56
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 29
SPD Codes for HYS[64/72]T[32/64]000HU–5–A (cont’d)
Product Type
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16) 1 Rank (×8) 1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
C1
00
xx
Rev. 1.1
HEX
C1
00
xx
Rev. 1.1
HEX
C1
00
xx
Byte#
64
Description
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2 - 8)
Module Manufacturer Location
Product Type, Char 1
65 - 71
72
73
36
34
54
33
32
30
30
30
48
55
35
41
20
20
20
20
20
20
2x
36
34
54
36
34
30
30
30
48
55
35
41
20
20
20
20
20
20
2x
37
32
54
36
34
30
30
30
48
55
35
41
20
20
20
20
20
20
2x
74
Product Type, Char 2
75
Product Type, Char 3
76
Product Type, Char 4
77
Product Type, Char 5
78
Product Type, Char 6
79
Product Type, Char 7
80
Product Type, Char 8
81
Product Type, Char 9
82
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1)
Module Serial Number (2)
Module Serial Number (3)
Module Serial Number (4)
83
84
85
86
87
88
89
90
91
92
xx
xx
xx
93
xx
xx
xx
94
xx
xx
xx
95
xx
xx
xx
96
xx
xx
xx
97
xx
xx
xx
98
xx
xx
xx
Data Sheet
57
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 29
SPD Codes for HYS[64/72]T[32/64]000HU–5–A (cont’d)
Product Type
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16) 1 Rank (×8) 1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
00
Rev. 1.1
HEX
00
Rev. 1.1
HEX
00
Byte#
Description
99 -127
Not Used
128-255 BLANK
FF
FF
FF
Table 30
SPD Codes for HYS[64/72]T128020HU–5–A
Product Type
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Byte#
Description
0
1
2
3
4
5
6
7
8
9
10
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
08
08
08
08
0E
0E
0A
0A
61
61
40
48
Not used
00
00
Interface Voltage Level
05
05
t
t
CK @ CLmax (Byte 18) [ns]
50
50
AC SDRAM @ CLmax (Byte 18) [ns]
60
60
Data Sheet
58
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 30
SPD Codes for HYS[64/72]T128020HU–5–A (cont’d)
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
00
Rev. 1.1
HEX
02
Byte#
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Description
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
82
82
08
08
00
08
00
00
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
Not used
0C
04
0C
04
38
38
00
00
DIMM Type Information
DIMM Attributes
02
02
00
00
Component Attributes
01
01
t
t
t
t
t
t
t
t
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
CK @ CLmax -2 (Byte 18) [ns]
AC SDRAM @ CLmax -2 [ns]
RP.min [ns]
50
50
60
60
50
50
60
60
3C
1E
3C
2D
80
3C
1E
3C
2D
80
RRD.min [ns]
RCD.min [ns]
RAS.min [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.min and tCS.min [ns]
AH.min and tCH.min [ns]
DS.min [ns]
35
35
47
47
15
15
DH.min [ns]
27
27
WR.min [ns]
3C
28
3C
28
WTR.min [ns]
RTP.min [ns]
1E
1E
Data Sheet
59
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 30
SPD Codes for HYS[64/72]T128020HU–5–A (cont’d)
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
00
Rev. 1.1
HEX
00
Byte#
39
Description
Analysis Characteristics
40
t
t
t
t
t
t
RC and tRFC Extension
RC.min [ns]
00
00
41
3C
69
3C
69
42
RFC.min [ns]
43
CK.max [ns]
80
80
44
DQSQ.max [ns]
QHS.max [ns]
23
23
45
2D
00
2D
00
46
PLL Relock Time
CASE.max Delta / ∆T4R4W Delta
47
T
51
51
48
Psi(T-A) DRAM
78
78
49
∆T0 (DT0)
32
32
50
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q, RDIMM)
∆T2P (DT2P)
24
24
51
1E
1B
1E
17
1E
1B
1E
17
52
∆T3N (DT3N)
53
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)
∆T5B (DT5B)
54
55
28
28
56
1B
1E
00
1B
1E
00
57
∆T7 (DT7)
58
Psi(ca) PLL
59
Psi(ca) REG
00
00
60
∆TPLL (DTPLL)
00
00
61
∆TREG (DTREG) / Toggle Rate
SPD Revision
00
00
62
11
11
63
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2 - 8)
Module Manufacturer Location
24
36
64
C1
00
C1
00
65 - 71
72
xx
xx
Data Sheet
60
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 30
SPD Codes for HYS[64/72]T128020HU–5–A (cont’d)
Product Type
Organization
1 GByte
1 GByte
×72
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
HEX
36
34
54
31
32
38
30
32
30
48
55
35
41
20
20
20
20
20
2x
Rev. 1.1
HEX
37
32
54
31
32
38
30
32
30
48
55
35
41
20
20
20
20
20
2x
Byte#
73
Description
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1)
Module Serial Number (2)
Module Serial Number (3)
Module Serial Number (4)
Not Used
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
xx
xx
93
xx
xx
94
xx
xx
95
xx
xx
96
xx
xx
97
xx
xx
98
xx
xx
99 -127
128-255
00
FF
00
FF
BLANK
Data Sheet
61
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Package Outlines
7
Package Outlines
7.1
Raw Card A
±0.1
1.27
133.35
0.3
±0.1
128.95
C
1
120
±0.1
4
±0.1
±0.1
2.5
5
2.7 MAX.
±0.1
±0.1
55
63
A
±0.1
1.5
121
240
B
3 MIN.
Detail of contacts
1
±0.2
0.8
0.1 A B C
Burr max. 0.4 allowed
GLD09652
Figure 8
Package Outline L-DIM-240-1
Data Sheet
62
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Package Outlines
7.2
Raw Card B
±0.1
1.27
133.35
0.4
±0.1
128.95
C
1
120
±0.1
4
±0.1
±0.1
2.5
5
4 MAX.
±0.1
±0.1
55
63
A
±0.1
1.5
121
240
B
3 MIN.
Detail of contacts
1
±0.2
0.8
0.1 A B C
Burr max. 0.4 allowed
GLD09653
Figure 9
Package Outline L-DIM-240-2
Data Sheet
63
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Package Outlines
7.3
Raw Card C
133.35
2.7 MAX.
128.95
1
120
4
C
2.5
0.4
±0.1
1.27
5
63
55
A
±0.1
1.5
121
240
B
(3)
Detail of contacts
1
±0.05
0.8
0.1 A B C
Burr max. 0.4 allowed
GLD09654
Figure 10 Package Outline L-DIM-240-3
Data Sheet
64
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
8
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon’s nomenclature uses simple coding combined with some propriatory coding. Table 31 provides examples
for module and component product type number as well as the field number. The detailed field description together
with possible values and coding explanation is listed for modules in Table 32 and for components in Table 33.
Table 31
Nomenclature Fields and Examples
Field Number
Example for
1
2
3
T
T
4
5
6
7
0
0
8
9
10
–5
–5
11
Micro-DIMM
DDR2 DRAM
HYS
HYB
64
18
64
512
0
2
K
A
M
C
–A
16
Table 32
DDR2 DIMM Nomenclature
Description
Field
Values
Coding
1
2
INFINEON Modul Prefix
Module Data Width [bit]
HYS
64
Constant
Non-ECC
ECC
72
3
4
DRAM Technology
T
DDR2
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
512 MByte
1 GByte
64
128
256
0 .. 9
0, 2, 4
0 .. 9
A .. Z
S
2 GByte
5
6
7
8
9
Raw Card Generation
Number of Module Ranks
Product Variations
look up table
1, 2, 4
look up table
look up table
SO-DIMM
Micro-DIMM
Registered
Unbuffered
Package, Lead-Free Status
Module Type
M
R
U
10
11
Speed Grade
Die Revision
–3.7
–5
PC2–4200 4–4–4
PC2–3200 3–3–3
First
–A
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules
gives the overall module memory density in MBytes as listed in column “Coding”.
Data Sheet
65
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Table 33
Field
1
DDR2 DRAM Nomenclature
Description
Values
Coding
INFINEON
HYB
Constant
Component Prefix
2
3
4
Interface Voltage [V]
DRAM Technology
18
T
SSTL1.8
DDR2
256 Mbit
512 Mbit
1 Gbit
2 Gbit
×4
Component Density [Mbit]
256
512
1G
2G
40
80
16
0 .. 9
A
5+6
Number of I/Os
×8
×16
7
8
Product Variations
Die Revision
look up table
First
B
Second
9
Package,
C
FBGA,
Lead-Free Status
lead-containing
F
FBGA, lead-free
DDR2-533
10
11
Speed Grade
–3.7
–5
DDR2-400
N/A for Components
Data Sheet
66
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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