HYS72V32300GU-7-D [INFINEON]
3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules; 3.3 V 32M ×64 /72- BIT， 256MByte SDRAM模块168针无缓冲DIMM模块
| 型号： | HYS72V32300GU-7-D |
| 厂家： | 
Infineon |
| 描述： | 3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules |
| 文件： | 总16页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYS 64/72V32300GU
SDRAM-Modules
3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules
168-pin Unbuffered DIMM Modules
•
168 Pin unbuffered 8 Byte Dual-In-Line
SDRAM Modules for PC main memory
applications using 256Mbit technology.
•
•
Single + 3.3 V (± 0.3 V) power supply
Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
•
•
•
•
•
PC100-222, PC133-333 and PC133-222
versions
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Decoupling capacitors mounted on substrate
All inputs, outputs are LVTTL compatible
Serial Presence Detect with E2PROM
One bank 32M × 64 and 32M × 72
organisation
Optimized for byte-write non-parity or ECC
applications
Fully PC board layout compatible to INTEL’s
Rev. 1.0 module specification
Uses Infineon 256 Mbit SDRAM components
in 32M × 8 organization and TSOPII-54
packages
Programmed Latencies:
•
Gold contact pads, card size:
133.35 mm × 31.75 mm × 3.00 mm
(JEDEC MO-161-BA)
Product Speed
CL tRCD
tRP
2
-7
PC133
2
3
2
2
3
2
-7.5
-8
PC133
PC100
3
2
•
SDRAM Performance:
-7 / -7.5
PC133
133
-8
Unit
PC100
100
6
fCK
tAC
Clock Frequency (max.)
Clock Access Time
MHz
ns
5.4
Description
The HYS 64V32300GU and HYS 72V32300GU are industry standard 168-pin 8-byte Dual in-line
Memory Modules (DIMMs) which are organized as 32M × 64 and 32M × 72 in 1 memory bank high
speed memory arrays designed with 256M Synchronous DRAMs (SDRAMs) for non-parity and
ECC applications. The DIMMs use -7 speed sorted 32M × 8 SDRAM devices in TSOP54 packages
to meet the PC133-222 requirement, -7.5 components for PC133-333 and -8 components for the
standard PC100 applications. Decoupling capacitors are mounted on the PC board. The PC board
design is according to INTEL’s module specification. The DIMMs have a serial presence detect,
implemented with a serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by
the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-
pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with
1.25“ (31.75 mm) height.
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HYS 64/72V32300GU
SDRAM-Modules
Ordering Information
Type
Code
Package
Descriptions
Module
Height
HYS 64V32300GU-7-D
PC133-222-520 L-DIM-168-33 PC133 32M × 64 1 bank 1.25“
SDRAM module
HYS 72V32300GU-7-D
PC133-222-520 L-DIM-168-33 PC133 32M × 72 1 bank 1.25“
ECC-SDRAM module
HYS 64V32300GU-7.5-C2 PC133-333-520 L-DIM-168-33 PC133 32M × 64 1 bank 1.25“
HYS 64V32300GU-7.5-D SDRAM module
HYS 72V32300GU-7.5-C2 PC133-333-520 L-DIM-168-33 PC133 32M × 72 1 bank 1.25“
HYS 72V32300GU-7.5-D
ECC-SDRAM module
HYS 64V32300GU-8-C2
PC100-222-620 L-DIM-168-33 PC100 32M × 64 1 bank 1.25“
SDRAM module
HYS 72V32300GU-8-C2
PC100-222-620 L-DIM-168-33 PC100 32M × 72 1 bank 1.25“
ECC-SDRAM module
Note: All part numbers end with a place code designating the die revision. Consult factory for
current revision. Example: HYS 64V32300GU-8-C2, indicating Rev. C2 dies are used for
SDRAM components.
Pin Definitions and Functions
A0 - A12
Address Inputs
Bank Selects
CLK0 - CLK3
Clock Input
BA0, BA1
DQMB0 - DQMB7 Data Mask
DQ0 - DQ63 Data Input/Output
CS0, CS2
Chip Select
CB0 - CB7
RAS
Check Bits (x72 organisation only) VDD
Power (+ 3.3 V)
Ground
Row Address Strobe
Column Address Strobe
Read/Write Input
VSS
CAS
SCL
SDA
Clock for Presence Detect
WE
Serial Data Out for
Presence Detect
CKE0
Clock Enable
N.C./DU
No Connection
Address Format
Part Number
Rows Columns Bank Select Refresh Period Interval
32M × 64/72 HYS64/72V32300GU 13
10
2
8k
64 ms 7.8 µs
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SDRAM-Modules
Pin Configuration
PIN# Symbol
PIN# Symbol
PIN# Symbol
PIN# Symbol
1
VSS
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VSS
85
VSS
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
VSS
2
DQ0
DQ1
DQ2
DQ3
VDD
DU
86
DQ32
DQ33
DQ34
DQ35
VDD
CKE0
N.C.
3
CS2
87
4
DQMB2
DQMB3
DU
88
DQMB6
DQMB7
N.C.
5
89
6
90
7
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
VDD
91
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
VDD
8
N.C.
92
N.C.
9
N.C.
93
N.C.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
N.C. (CB2)
N.C. (CB3)
VSS
94
CB6
95
CB7
96
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ16
DQ17
DQ18
DQ19
VDD
97
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ48
DQ49
DQ50
DQ51
VDD
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ20
N.C.
DQ52
N.C.
DQ14
DQ15
N.C. (CB0)
N.C. (CB1)
VSS
DQ46
DQ47
N.C. (CB4)
N.C. (CB5)
VSS
DU
DU
N.C.
N.C.
VSS
VSS
DQ21
DQ22
DQ23
VSS
DQ53
DQ54
DQ55
VSS
N.C.
N.C.
VDD
N.C.
N.C.
VDD
WE
DQ24
DQ25
DQ26
DQ27
VDD
CAS
DQMB4
DQMB5
N.C.
DQ56
DQ57
DQ58
DQ59
VDD
DQMB0
DQMB1
CS0
DU
RAS
VSS
VSS
DQ28
DQ29
DQ30
DQ31
VSS
DQ60
DQ61
DQ62
DQ63
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
CLK2
N.C.
A9
CLK3
N.C.
A10
BA0
BA1
WP
A11
SA0
VDD
SDA
VDD
SA1
VDD
SCL
CLK1
A12
SA2
CLK0
VDD
VDD
Note: Pin names in parantheses are for the x72 ECC versions; example: Pin 106 = (CB5)
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SDRAM-Modules
WE
CS0
CS
DQM
WE
CS
DQM
DQ0-DQ7
D4
WE
DQMB0
DQ(7:0)
DQMB4
DQ0-DQ7
D0
DQ(39:32)
CS
WE
CS
WE
DQMB1
DQM
DQMB5
DQM
DQ(15:8)
DQ0-DQ7
DQ(47:40)
DQ0-DQ7
D5
D1
CS
WE
DQM
CB(7:0)
CS2
DQ0-DQ7
D8
CS
WE
CS
WE
DQMB2
DQM
DQMB6
DQM
DQ(23:16)
DQ0-DQ7
D2
DQ(55:48)
DQ0-DQ7
D6
CS
WE
CS
WE
DQMB3
DQM
DQMB7
DQM
DQ(31:24)
DQ0-DQ7
D3
DQ(63:56)
DQ0-DQ7
D7
A0-A12, BA0, BA1
VCC
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
E2PROM (256 word x 8 Bit)
SA0
SA0
SA1
SA2
SCL
SA1
SA2
SCL
SDA
WP
C0-C15, (C16, C17)
VSS
47 k
Ω
RAS
CAS
CKE0
Clock Wiring
16 M x 64
SDRAM+ 3.3 pF
16 M x 72
5 SDRAM
CLK0
CLK1
CLK2
CLK3
4
Termination
Termination
Note: D8 is only used in the x72 ECC version and
all resistor values are 10 Ohm except
otherwise noted.
4 SDRAM+ 3.3 pF
Termination
4 SDRAM+ 3.3 pF
Termination
BL013
Block Diagram: 32M x 64/72 One Bank SDRAM DIMM Modules
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SDRAM-Modules
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
– 1.0
– 1.0
-55
–
max.
4.6
Input / Output voltage relative to VSS
Power supply voltage on VDD
VIN, VOUT
VDD
V
4.6
+150
1
V
Storage temperature range
TSTG
PD
oC
W
mA
Power dissipation per SDRAM component
Data out current (short circuit)
IOS
–
50
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
max.
Unit
min.
2.0
Input High Voltage
VIH
VIL
V
DD + 0.3
V
Input Low Voltage
– 0.5
2.4
0.8
–
V
Output High Voltage (IOUT = – 4.0 mA)
Output Low Voltage (IOUT = 4.0 mA)
VOH
VOL
II(L)
V
–
0.4
40
V
Input Leakage Current, any input
– 40
µA
(0 V < VIN < 3.6 V, all other inputs = 0 V)
Output Leakage Current
IO(L)
– 40
40
µA
(DQ is disabled, 0 V < VOUT < VDD
)
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
max.
Unit
max.
32M x 64
32M x 72
Input Capacitance
CI1
65
72
pF
(A0 to A11, BA0, BA1, RAS, CAS, WE)
Input Capacitance (CS0 - CS3)
Input Capacitance (CLK0 - CLK3)
Input Capacitance (CKE0)
CI2
CICL
CI3
CI4
32
38
65
13
10
8
40
40
72
16
10
8
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (DQMB0 - DQMB7)
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) CIO
Input Capacitance (SCL, SA0-2)
Input/Output Capacitance
CSC
CSD
8
8
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SDRAM-Modules
Operating Currents per SDRAM Component 1)
TA = 0 to 70 oC, VDD = 3.3 V ± 0.3 V
Parameter
Test
Symbol -7.5
-8
Unit Note
Condition
max.
2)
Operating current
–
ICC1
230
170
mA
tRC = tRCMIN., tCK = tCKMIN.
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner
to maximize gapless data access
2)
Precharge stand-by current
in Power Down Mode
t
CK = min.
CK = min.
ICC2P
2
2
mA
CS = VIH(MIN.), CKE ≤ VIL(MAX.)
2)
Precharge Stand-by Current
in Non-Power Down Mode
t
ICC2N
40
30
mA
CS = VIH (MIN.), CKE ≥ VIH(MIN.)
2)
No operating current
CKE ≥ VIH(MIN.) ICC3N
CKE ≤ VIL(MAX.) ICC3P
50
10
45
10
mA
2)
mA
tCK = min., CS = VIH(MIN.),
active state (max. 4 banks)
2), 3)
Burst operating current
–
–
ICC4
ICC5
ICC6
150
240
3
100
220
3
mA
tCK = min.,
Read command cycling
2)
Auto refresh current
mA
tCK = min.,
Auto Refresh command cycling
2)
Self refresh current
mA
Self Refresh Mode, CKE = 0.2 V
1. All values are shown per one SDRAM component.
2. These parameters depend on the cycle rate. These values are measured at 133 MHz operation frequency
for -7 & -7.5 and at 100 MHz for -8 modules.
Input signals are changed once during tCK, excepts for ICC6 and for stand-by currents when tCK = infinity.
3. These parameters are measured with continuous data stream during read access and all DQ toggling.
CL = 3 and BL = 4 are assumed and the data-out current is excluded.
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SDRAM-Modules
1), 2)
AC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Symbol
Parameter
Limit Values
-7.5
Unit Note
-7
-8
PC133-222 PC133-333 PC100-222
min. max min. max. min. max.
Clock
Clock Cycle Time
tCK
fCK
tAC
–
ns
ns
CAS Latency = 3
CAS Latency = 2
System Frequency
7.5
7.5
–
–
7.5
10
–
–
10
10
–
–
–
CAS Latency = 3
CAS Latency = 2
–
–
133
133
–
–
133
100
–
–
100 MHz
100 MHz
3), 4)
Clock Access Time
CAS Latency = 3
CAS Latency = 2
–
–
5.4
5.4
–
–
5.4
6
–
–
6
6
ns
ns
4)
4)
Clock High Pulse Width
Clock Low Pulse Width
tCH
tCL
2.5
2.5
–
–
2.5
2.5
–
–
3
3
–
–
ns
ns
Setup and Hold Times
Input Setup Time
5)
5)
6)
7)
tCS
tCH
tSB
1.5
0.8
–
–
–
1
–
–
–
1.5
0.8
–
–
–
1
–
–
–
2
1
–
1
2
1
–
–
1
–
–
–
ns
Input Hold Time
ns
Power Down Mode Entry Time
CLK
CLK
CLK
ns
Power Down Mode Exit Setup Time tPDE
1
1
Mode Register Setup Time
Transition Time (rise and fall)
tRSC
tT
2
2
1
1
–
Common Parameters
RAS to CAS Delay
Precharge Time
tRCD
tRP
tRAS
tRC
15
15
42
60
14
1
–
–
–
–
–
–
20
20
45
67.5
15
1
–
–
20
20
–
–
ns
ns
–
–
–
–
–
–
Active Command Period
Cycle Time
100k 50
100k ns
–
–
–
70
16
1
–
–
–
ns
Bank to Bank Delay Time
tRRD
ns
CAS to CAS Delay Time (same bank) tCCD
CLK
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SDRAM-Modules
AC Characteristics (cont’d) 1), 2)
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Symbol
Parameter
Limit Values
-7.5
Unit Note
-7
-8
PC133-222 PC133-333 PC100-222
min. max min. max. min. max.
Refresh Cycle
6)
Refresh Period (8192 cycles)
Self Refresh Exit Time
tREF
64
–
–
64
–
64
ms
8)
tSREX
–
1
1
–
1
–
CLK
Read Cycle
2)
Data Out Hold Time
tOH
tLZ
3
0
3
–
–
–
7
2
3
0
3
–
–
–
7
2
3
0
3
–
–
–
8
2
ns
Data Out to Low Impedance
Data Out to High Impedance
DQM Data Out Disable Latency
ns
–
9)
tHZ
ns
tDQZ
CLK
–
Write Cycle
Data Input to Precharge
(write recovery)
tWR
2
0
–
–
2
0
–
–
2
0
–
–
CLK
CLK
–
–
DQM Write Mask Latency
tDQW
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SDRAM-Modules
Notes
1. All AC characteristics are shown for the SDRAM components.
An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume
tT = 1 ns with the AC output load circuit shown in Figure below. Specified tAC and tOH parameters
are measured with a 50 pF only, without any resistive termination and with a input signal of 1V/
ns edge rate between 0.8 V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (tT/2 − 0.5) ns must be added to this parameter.
4. Rated at 1.4 V.
5. If tT is longer than 1 ns, a time (tT − 1) ns must be added to this parameter.
6. Whenever the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
7. Timing is a asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
8. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
after the Self Refresh Exit command is registered.
9. This is referenced to the time at which the output achieved the open circuit condition, not to
output voltage levels.
tCH
2.4 V
0.4 V
1.4 V
CLOCK
tT
tCL
tIH
tIS
INPUT
1.4 V
tAC
tAC
tLZ
tOH
I/O
50 pF
OUTPUT
1.4 V
tHZ
Measurement conditions for
AC and tOH
t
IO.vsd
Serial Presence Detect
A serial presence detect storage device - E2PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E2PROM device during module
production using a serial presence detect protocol (I2C synchronous 2-wire bus).
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SDRAM-Modules
SPD-Table for 32M x 64 (256MByte non-ECC) Modules HYS64V32300GU
Byte# Description
SPD Entry Value
Hex
32M x 64
-7.5
80
-7
-8
0
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
128
1
256
08
2
SDRAM
04
3
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
13
0D
4
10
1
0A
5
01
6
64
40
7
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL = 3
SDRAM Access Time at CL = 3
DIMM Config
0
00
8
9
LVTTL
7.5 / 10 ns
5.4 / 6 ns
non-ECC
Self-Refresh,
7.8 µs
x8
01
75
75
54
A0
60
10
11
12
54
00
Refresh Rate/Type
82
13
14
15
SDRAM Width, Primary
08
00
01
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-to-
Back Random Column Address
Burst Length Supported
na
t
CCD = 1 CLK
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
1, 2, 4 & 8
4
0F
04
06
01
01
00
0E
A0
60
FF
FF
14
0F
14
2D
40
15
08
15
08
Number of SDRAM Banks
Supported CAS Latencies
CL = 2 & 3
CS Latencies
CS latency = 0
Write latency = 0
unbuffered
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
SDRAM Cycle Time at CL = 2
SDRAM Access Time at CL = 2
SDRAM Cycle Time at CL = 1
SDRAM Access Time at CL = 1
Minimum Row Precharge Time
Min. Row to Row Active Delay tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
SDRAM Input Setup Time
VDD tol +/– 10%
7.5 / 10.0 ns
5.4 / 6.0 ns
75
54
00
00
0F
0E
0F
2A
A0
60
FF
FF
14
10
14
32
not supported
not supported
15 / 20 ns
14 / 15 / 16 ns
15 / 20 ns
42 / 45 / 50 ns
256 MByte
1.5 / 2.0 ns
15
08
15
08
20
10
20
10
SDRAM Input Hold Time
0.8 / 1.0 ns
SDRAM Data Input Hold Time
SDRAM Data Input Setup Time
1.5 / 2.0 ns
0.8 / 1.0 ns
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SDRAM-Modules
Byte# Description
SPD Entry Value
Hex
32M x 64
-7
-7.5
-8
FF
12
99
36-61 Superset Information
–
FF
12
F3
FF
62
63
64
SPD Revision
Revision 1.2
12
36
Checksum for Bytes 0 - 62
Manufacturers JEDEC ID Code
–
–
C1
65-71 Manufacturer
INFINEO(N)
72
Module Assembly Locaction
73-90 Module Part Number
91-92 Module Revision Code
93-94 Module Manufacturing Code
95-98 Module Serial Number
99-125 Superset Information
126
Frequency Specification
100 MHz Support Details
Unused Storage Locations
64
64
AF
FF
64
127
–
–
AF
AF
128+
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
SPD-Table for 32M x 72 (256MByte ECC) Modules HYS72V32300GU
Byte# Description
SPD Entry Value
Hex
32M x 72
-7.5
80
-7
-8
0
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
128
1
256
08
2
SDRAM
04
3
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
13
0D
4
10
0A
5
1
72
01
6
48
7
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL = 3
SDRAM Access Time at CL = 3
DIMM Config
0
00
8
9
LVTTL
7.5 / 10 ns
5.4 / 6 ns
ECC
01
75
75
54
A0
60
10
11
12
54
02
Refresh Rate/Type
Self-Refresh,
7.8 µs
x8
82
13
14
15
SDRAM Width, Primary
08
08
01
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-to-
Back Random Column Address
Burst Length Supported
x8
t
CCD = 1 CLK
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
1, 2, 4 & 8
4
0F
04
06
01
01
00
0E
A0
60
FF
FF
14
0F
14
2D
40
15
08
15
08
Number of SDRAM Banks
Supported CAS Latencies
CL = 2 & 3
CS Latencies
CS latency = 0
Write latency = 0
unbuffered
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
SDRAM Cycle Time at CL = 2
SDRAM Access Time at CL = 2
SDRAM Cycle Time at CL = 1
SDRAM Access Time at CL = 1
Minimum Row Precharge Time
Min. Row to Row Active Delay tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
SDRAM Input Setup Time
VDD tol +/– 10%
7.5 / 10.0 ns
5.4 / 6.0 ns
75
54
00
00
0F
0E
0F
2A
A0
60
FF
FF
14
10
14
32
not supported
not supported
15 / 20 ns
14 / 15 / 16 ns
15 / 20 ns
42 / 45 / 50 ns
256 MByte
1.5 / 2.0 ns
15
08
15
08
20
10
20
10
SDRAM Input Hold Time
0.8 / 1.0 ns
SDRAM Data Input Hold Time
SDRAM Data Input Setup Time
1.5 / 2.0 ns
0.8 / 1.0 ns
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
Byte# Description
SPD Entry Value
Hex
32M x 72
-7
FF
12
05
-7.5
-8
FF
12
AB
36-61 Superset Information
–
FF
62
63
64
SPD Revision
Revision 1.2
12
48
Checksum for Bytes 0 - 62
Manufacturers JEDEC ID Code
–
–
C1
65-71 Manufacturer
INFINEO(N)
72
Module Assembly Locaction
73-90 Module Part Number
91-92 Module Revision Code
93-94 Module Manufacturing Code
95-98 Module Serial Number
99-125 Superset Information
126
Frequency Specification
100 MHz Support Details
Unused Storage Locations
64
64
AF
FF
64
127
–
–
AF
AF
128+
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
Package Outlines
L-DIM-168-33 (JEDEC MO-161-BA)
SDRAM DIMM Module Package
+ 0.15
-
133.35
127.35
3 max.
*)
3
1
10
11
6.35
40
41
6.35
84
+ 0.1
-
1.27
3
1.27
42.18
91 x 1.27 = 115.57
124 125
2
85 94
95
168
3 min.
3
Detail of Contacts
*) on ECC modules only
1
1.27
L-DIM-168-33
Note: All tolerances according to JEDEC standard
Dimensions in mm
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
Change List:
14.1.1999
Input capacitances adjusted
18.4.1999
-8A speed sort added
Infineon logo added
SPD codes updated according to new 256M speedsorts
12.5.99
21.7.99
Some ICC current values changed due to new inputs
HYS64/72V32200GU changed to HYS64/72V32300GU due to the use of L-
DIM168-33 instead of L-DIM168-30
23.8.99
6.9.99
Byte 126 changed to 64h for PC133 modules
Template from R&L
29.9.99
20.10.99
2.12.99
20.1.2000
Some minor errors corrected
CL=2 max. frequency for -7.5 modules changes to 83 MHz
Some timing parameters according to INTEL’S PC133 specification
Capacitance values for x72 adjusted (new measurements)
-8B version removed
10.3.2000
Implemented differences between 256Mbit S20 and S17 PC133 modules
256Mbit S20 based PC133 modules are backward compatible to PC100 3-2-2
256Mbit S17 based modules are backwards compatible to PC100-2-2-2
leading to changes in SPD code of bytes 23, 63 (checksum) and 126
TPCR issued
10.5.2000
Reference to JEDEC MO-161-BA added
14.02.2001
-8A speedsort removed
for 256M S17 and later only
25.07.2001
06.09.2001
256M S14 based modules including -7 added
SCR : Absolute Maximum Ratings table added
INFINEON Technologies
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