ICB2FL03G_技术文档

ICB2FL03G

2nd Generation FL Controller for

Fluorescent Lamp Ballasts

Data Sheet

V1.1, 2012-04-10

Preliminary

Power Management & Multimarket

Edition 2012-04-10

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Revision History

Page or Item

Subjects (major changes since previous revision)

V1.1, 2012-04-10

Added test condition for R_thJA

Updated package drawing

V1.0, 2010-09-28

First edition

Trademarks of Infineon Technologies AG

AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,

CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,

EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,

ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,

POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,

ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,

thinQ!™, TRENCHSTOP™, TriCore™.

Other Trademarks

Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,

PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR

development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,

FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.

FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of

Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data

Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of

MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics

Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA

MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of

OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF

Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™

of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.

TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™

of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas

Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes

Zetex Limited.

Last Trademarks Update 2011-11-11

Preliminary Data Sheet

3

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Table of Contents

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2nd Generation FL-Controller for Fluorescent Lamp Ballasts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1

Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PG-DSO-16-20 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1

1.2

1.3

2

2.1

2.2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Typical Application Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Normal Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Operating Levels from UVLO to Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Operating Levels from Soft Start to Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Filament Detection during Start-Up and Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Start-Up with broken Low Side Filament . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Low Side Filament Detection during Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Start-Up with Broken High Side Filament . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PFC Preconverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Discontinuous Conduction and Critical Conduction Mode Operation . . . . . . . . . . . . . . . . . . . . . . . 23

PFC Bus Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Bus Overvoltage and PFC Open Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Bus Voltage 95 % and 75 % Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PFC Structure of Mixed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

THD Correction via ZCD Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Detection of End-of-Life and Rectifier Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Detection of End of Life 1 (EOL1) – Lamp Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Detection of End of Life 2 (EOL2) – Rectifier Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Detection of Capacitive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Capacitive Load 1 (Idling Detection – Current Mode Preheating) . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Capacitive Load 2 (Overcurrent / Operation below Resonance) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Adjustable Self-adapting Dead Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Emergency Lighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Short-term PFC Bus Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Long-term PFC Bus Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Built-in Customer Test Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Preheating Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Skip the Preheating Phase – Set RTPH Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

IC Remains in Preheating Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Deactivation of the Filament Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Built-in Customer Test Mode (Clock Acceleration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Enabling of the Clock Acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Starting the Chip with Accelerated Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.2.1

2.2.2

2.3

2.3.1

2.3.2

2.3.3

2.4

2.4.1

2.4.2

2.4.2.1

2.4.2.2

2.4.3

2.4.4

2.5

2.5.1

2.5.2

2.6

2.6.1

2.6.2

2.6.3

2.7

2.7.1

2.7.2

2.8

2.8.1

2.8.1.1

2.8.1.2

2.8.2

2.8.3

2.8.3.1

2.8.3.2

3

State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Features during Different Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Operating Flow of the Start-Up Procedure into Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Auto Restart and Latched Fault Condition Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.1

3.2

3.3

Preliminary Data Sheet

4

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Table of Contents

4

Protection Functions Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5

5.1

5.2

5.3

5.3.1

5.3.2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Power Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

PFC Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PFC Current Sense (PFCCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PFC Zero Current Detection (PFCZCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PFC Bus Voltage Sense (PFCVS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

PFC PWM Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

PFC gate Drive (PFCGD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Inverter Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Low Side Current Sense (LSCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Low Side Gate Drive (LSGD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Inverter Control Run (RFRUN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Inverter Control Preheating (RFPH, RTPH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Restart after Lamp Removal (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Lamp Voltage Sense (LVS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

High Side Gate Drive (HSGD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Timer Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Built-In Customer Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.3.2.1

5.3.2.2

5.3.2.3

5.3.2.4

5.3.2.5

5.3.3

5.3.3.1

5.3.3.2

5.3.3.3

5.3.3.4

5.3.3.5

5.3.3.6

5.3.3.7

5.3.3.8

5.3.3.9

6

Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Schematic Ballast 54W T5 Single Lamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Multi Lamp Ballast Topologies (Series Connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1

6.2

6.3

7

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.1

Outline Dimensions of PG-DSO-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Preliminary Data Sheet

5

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

List of Figures

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Typical Application Circuit of Ballast for a Single Fluorescent Lamp . . . . . . . . . . . . . . . . . . . . . . . . 8

PG-DSO-16-20 Package (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Application Circuit of Ballast for a Single Fluorescent Lamp (FL). . . . . . . . . . . . . . . . . . . . . . . . . . 14

Typical Startup Procedure in Run Mode (in Normal Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Typical Startup Procedure in Run Mode (in Normal Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Typical Variation of Operating Frequency during Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Lamp Voltage versus Frequency during the different Startup Phases . . . . . . . . . . . . . . . . . . . . . . 18

Start-Up with Open Low Side Filament. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Restart from Open Low Side Filament . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10 Open Low Side Filament Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11 Restart from Open LS Filament . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 12 Start-Up with Open High Side Filament . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13 Restart from Open High Side Filament. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 14 Operating Frequency and ON Time versus Power in DCM and CritCM Operation . . . . . . . . . . . . 23

Figure 15 PFC Bus Voltage Operating Level and Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 16 Structure of the Mixed Digital and Analog Control of the PFC Preconverter . . . . . . . . . . . . . . . . . 25

Figure 17 THD Optimization using adjustable Pulse Width Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 18 End of Life and Rectifier Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 19 End of Life (EOL1) Detection, Lamp Voltage versus AC LVS Current . . . . . . . . . . . . . . . . . . . . . . 27

Figure 20 End of Life (EOL2) Detection, Lamp Voltage versus DC LVS Current. . . . . . . . . . . . . . . . . . . . . . 28

Figure 21 Capacitive and Inductive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 22 Capacitive Mode 1 Operation without Load during Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 23 Capacitive Mode 2 – Operation with Overcurrent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 24 Dead Time of ON and OFF of the Half-Bridge Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 25 BUS Voltage Drop below 75% (rated Bus Voltage) for t < 800 ms during RUN Mode. . . . . . . . . . 31

Figure 26 BUS Voltage Drop below 75% (rated Bus Voltage) for t > 800 ms during RUN Mode. . . . . . . . . . 32

Figure 27 Start-Up WITH Preheating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 28 Start-Up WITHOUT Preheating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 29 Start-Up WITH Preheating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 30 Start-Up WITHOUT Preheating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 31 Deactivation via RES PIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 32 Deactivation via LVS PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 33 Clock Acceleration (Built in Customer Test Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 34 Monitoring Features during Different Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 35 Operating Flow during Start-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 36 Operating Process during Start-Up Mode and Handling of Fault Conditions . . . . . . . . . . . . . . . . . 39

Figure 37 Application Circuit of Ballast for Single Fluorescent Lamp Voltage Mode Preheating . . . . . . . . . . 54

Figure 38 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 39 Application Circuit of Ballast for two Fluorescent Lamps Voltage Mode Preheating . . . . . . . . . . . 56

Figure 40 Package Outline with Creepage Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Preliminary Data Sheet

6

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

List of Tables

Table 1

Table 2

Table 3

Pin Configuration for PG-DSO-16-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Specified Acceleration Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Protection Functions Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Preliminary Data Sheet

7

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

2nd Generation FL-Controller for Fluorescent Lamp Ballasts

Product Highlights

•

Lowest count of external components

650 V half-bridge driver with coreless transformer technology

Supports Customer In-Circuit Test Mode for reduced tester time

Supports multi-lamp designs (series connection)

Integrated digital timers up to 40 seconds

Numerous monitoring and protection features for highest reliability

Very high accuracy of frequencies and timers over the whole temperature range

Very low standby losses

PFC Features

•

Discontinuous mode PFC for load range 0 to 100%

Integrated digital compensation of PFC control loop

Improved compensation for low THD of AC input current, also in DCM operation

Adjustable PFC current limitation

Lamp Ballast Inverter Features

•

Adjustable detection of overload and rectifier effect (EOL)

Detection of capacitive load operation

Improved ignition control allows operation close to the magnetic saturation of the lamp inductors

Restart with skipped preheating on short interruptions of line voltage (for emergency lighting)

Parameters adjustable by resistors only

Pb-free lead plating; RoHS-compliant

PFCZCD

HSGD

HSVCC

PFCGD

VIN

HSGND

PFCVS

LSGD

PFCCS

LSCS

Figure 1

Typical Application Circuit of Ballast for a Single Fluorescent Lamp

Description

The FL controller ICB2FL03G is designed to control fluorescent lamp ballast, including a discontinuous mode

Power Factor Correction (PFC), lamp inverter control and a high-voltage level shift half-bridge driver.

The control concept covers requirements for T5 lamp ballasts for single and multi-lamp designs (series connection

supported). ICB2FL03G is based on the 2nd-generation FL controller technology, is easy to use and simple to

design in. This makes the ICB2FL03G a basis for cost-effective solutions for fluorescent lamp ballasts with high

reliability. Figure 1 shows a typical application circuit of ballast for a single fluorescent T8 lamp with current mode

preheating.

Preliminary Data Sheet

8

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Pin Configuration and Functionality

1

Pin Configuration and Functionality

1.1

Pin Configuration

Table 1

Pin Configuration for PG-DSO-16-20

1

Symbol

LSGD

LSCS

Function

Low side gate drive (inverter)

Low side current sense (inverter)

Supply voltage

2

3

VCC

4

GND

Low side ground

5

PFCGD

PFCCS

PFCZCD

PFCVS

RFRUN

RFPH

RTPH

LVS

PFC gate drive

6

PFC current sense

7

PFC zero current detector

PFC voltage sense

8

9

Set R for run frequency

Set R for preheat frequency

Set R for preheating time

Lamp voltage sense

Restart after lamp removal

High side ground

10

11

12

13

14

15

16

RES

HSGND

HSVCC

HSGD

High side supply voltage

High side gate drive (inverter)

1.2

PG-DSO-16-20 Package

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LSGD

LSCS

HSGD

HSVCC

HSGND

RES

VCC

GND

PFCGD

PFCCS

PFCZCD

PFCVS

LVS

RTPH

RFPH

RFRUN

PG-DSO-16 (150mil)

Figure 2

PG-DSO-16-20 Package (top view)

Preliminary Data Sheet

9

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Pin Configuration and Functionality

1.3

Pin Functionality

LSGD (low-side gate drive, pin 1)

The gate of the low-side MOSFET in a half-bridge inverter topology is controlled by this pin. There is an active

L-level during UVLO (under voltage lockout) and limitation of the max H-level at 11.0 V during normal operation.

In order to turn on the MOSFET softly (with a reduced di_DRAIN/dt); the gate voltage typically rises within 245 ns from

L-level to H-level. The fall time of the gate voltage is less than 50 ns in order to turn off quickly. This measure

produces different switching speeds during turn-on and turn-off as it is usually achieved with a diode parallel to a

resistor in the gate drive loop. It is recommended to use a resistor of typically 10 Ω between drive pin and gate in

order to avoid oscillations and in order to shift the power dissipation of discharging the gate capacitance into this

resistor. The dead time between the LSGD signal and HSGD signal is self-adapting between 1.05 µs and 2.1 µs.

LSCS (low-side current sense, pin 2)

This pin is directly connected to the shunt resistor which is located between the source terminal of the low-side

MOSFET of the inverter and ground.

Internal clamping structures and filtering measures allow for sensing the source current of the low-side inverter

MOSFET without additional filter components.

The first threshold is 0.8 V. If this threshold is exceeded for longer than 500 ns during preheat or run mode, an

inverter overcurrent is detected and causes a latched shutdown of the IC. The ignition control is activated if the

sensed slope at the LSCS pin reaches typically 205 mV/µs ± 25 mV/µs and exceeds the 0.8 V threshold. This

stops the frequency decrease and waits for ignition. The ignition control is now continuously monitored by the

LSCS PIN. The ignition control is designed to handle choke operation in saturation during ignition in order to

reduce the choke size.

If the sensed current signal exceeds a second threshold of 1.6 V for longer than 500 ns during start-up, soft start,

ignition mode and pre-run, the IC changes over into latched shutdown.

There are further thresholds active at this pin during run mode that detect capacitive mode operation. An initial

threshold at 50 mV needs to sense a positive current during the second 50 % on-time of the low-side MOSFET for

proper operation (cap. load 1). A second threshold of -50mV senses the current before the high-side MOSFET is

turned on. A voltage level below this threshold indicates faulty operation (cap. load 2). Finally a third threshold at

2.0 V senses even short overcurrent during turn-on of the high-side MOSFET, typical for reverse recovery currents

of a diode (cap. load 2). If any of these three comparator thresholds indicates incorrect operating conditions for

longer than 620 µs (cap. load 2) or 2500 ms (cap. load 1) in run mode, the IC turns off the gates and changes into

fault mode due to detected capacitive mode operation (non-zero voltage switching).

The threshold of -50 mV is also used to adjust the dead time between turn-off and turn-on of the half-bridge drivers

in a range of 1.05 µs to 2.1 µs during all operating modes.

Vcc (supply voltage, pin 3)

This pin provides the power supply of the ground related section of the IC. There is a turn-on threshold at 14.0 V

and an UVLO threshold at 10.6 V. The upper supply voltage level is 17.5 V. There is an internal zener diode

clamping V_CCat 16.3 V (at I_VCC= 2 mA typically). The maximum zener current is internally limited to 5 mA. An

external zener diode is required for higher current levels. Current consumption during UVLO and during fault mode

is less than 170 µA. A ceramic capacitor close to the supply and GND pin is required in order to act as a low-

impedance power source for gate drive and logic signal currents. In order to skip preheating after short

interruptions to the mains supply it is necessary to feed the start-up current (160 µA) from the bus voltage. Note:

for external V_CCsupply, see notes in the flowchart (Section 3.3).

Preliminary Data Sheet

10

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Pin Configuration and Functionality

GND (ground, pin 4)

This pin is connected to ground and represents the ground level of the IC for supply voltage, gate drive and sense

signals.

PFCGD (PFC gate drive, pin 5)

This pin controls the gate of the MOSFET in the PFC preconverter designed in boost topology. There is an active

L-level during UVLO and limitation of the max H-level at 11.0 V during normal operation. In order to turn on the

MOSFET softly (with a reduced di_DRAIN/dt), the gate drive voltage rises within 245 ns from L-level to H-level. The

fall time of the gate voltage is less than 50 ns in order to turn off quickly.

A resistor of typically 10 Ω between the drive pin and gate is recommended in order to avoid oscillations and in

order to shift the power dissipation of discharging the gate capacitance into this resistor.

The PFC section of the IC controls a boost converter as a PFC preconverter in discontinuous conduction mode

(DCM). Control usually starts with gate drive pulses with a fixed on-time of typically 4.0 µs at V_ACIN= 230 V,

increasing up to 24 µs and with an off-time of 47 µs. As soon as sufficient zero current detector (ZCD) signals are

available, the operation mode changes from fixed frequency operation to operation with variable frequency. The

PFC works in critical conduction mode operation (CritCM) when rated and / or medium load conditions are present.

This means triangular-shaped currents in the boost converter choke without gaps and variable operating

frequency. During low loads (detected by an internal compensator) operation is in discontinuous conduction mode

(DCM) – i.e., triangular-shaped currents in the boost converter choke with gaps when reaching the zero current

level and variable operating frequency in order to avoid steps in the consumed line current.

PFCCS (PFC current sense, pin 6)

The voltage drop across a shunt resistor located between the source of the PFC MOSFET and GND is sensed

with this pin. If the level exceeds a threshold of 1.0 V for longer than 200 ns, the PFC gate drive is turned off as

long as the zero current detector (ZCD) enables a new cycle. If no ZCD signal is available within 52 µs after turn-off

of the PFC gate drive, a new cycle is initiated from an internal start-up timer.

PFCZCD (PFC zero current detector, pin 7)

This pin senses the point of time when the current through boost inductor becomes zero during off-time of the PFC

MOSFET in order to initiate a new cycle.

The moment of interest appears when the voltage of the separate ZCD winding changes from the positive to

negative level, which represents a voltage of zero at the inductor windings and therefore the end of current flow

from the lower input voltage level to the higher output voltage level. There is a threshold with hysteresis – for

increasing level 1.5 V, for decreasing level 0.5 V – which detects the change in inductor voltage.

A resistor, connected between ZCD winding and pin 7, limits the sink and source current of the sense pin when

the voltage of the ZCD winding exceeds the internal clamping levels (6.3 V and -2.9 V typically @ 5 mA) of the IC.

If the sensed voltage level of the ZCD winding is not sufficient (e.g. during start-up), an internal start-up timer will

initiate a new cycle every 52 µs after turn-off of the PFC gate drive. The source current flowing out of this pin during

the on-time of the PFC-MOSFET indicates the voltage level of the AC supply voltage. During low input voltage

levels the on-time of the PFC-MOSFET is increased in order to minimize gaps in the line current during zero

crossing of the line voltage and improve the THD (Total Harmonic Distortion) of the line current. Optimization of

the THD is possible by trimming of the resistor between this pin and the ZCD winding.

PFCVS (PFC voltage sense, pin 8)

The intermediate circuit voltage (bus voltage) at the smoothing capacitor is sensed by a resistive divider at this

pin. The internal reference voltage for rated bus voltage is 2.5 V. There are further thresholds at 0.3125 V (12.5 %

of the rated bus voltage) for the detection of open control loop, at 1.875 V (75 % of the rated bus voltage) for the

detection of undervoltage, and at 2.725 V (109 % of the rated bus voltage) for the detection of overvoltage. The

Preliminary Data Sheet

11

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Pin Configuration and Functionality

overvoltage threshold operates with a hysteresis of 100 mV (4 % of the rated bus voltage). For the detection of

successful start-up, the bus voltage is sensed at 95 % (2.375 V). It is recommended to use a small capacitor

between this pin and GND as a spike suppression filter.

In run mode, a PFC overvoltage stops the PFC gate drive within 5 µs. As soon as the bus voltage is less than

105 % of the rated level, the gate drives are enabled again. If the overvoltage lasts for longer than 625 ms, inverter

overvoltage is detected and the inverter turns off the gate drives also. This causes powerdown and powerup when

V

_BUS< 109 %.

A bus undervoltage (V_BUS> 75 %) or inverter overvoltage during run mode is handled as a fault U. In this situation

the IC changes into powerdown mode and generates a delay of 100 ms by an internal timer. Then startup

conditions are checked and if valid, a further startup is initiated. If startup conditions are not valid, a further delay

of 100 ms is generated.

This procedure is repeated a maximum of seven times. If startup is successful within these seven cycles, the

situation is interpreted as a short interruption of the mains supply and the preheating is skipped. Any further startup

attempt is initiated to include the preheating.

RFRUN (set R for run frequency, pin 9)

A resistor from this pin to ground sets the operating frequency of the inverter during run mode. The typical run

frequency range is 20 kHz to 120 kHz. The set resistor R_RFRUN can be calculated, based on the run frequency

f_RUNaccording to the equation:

5⋅10⁸ΩHz

R_FRUN

=

f_RUN

RFPH (set R for preheat frequency, pin 10)

A resistor from this pin to ground, together with the resistor at pin 9, sets the operating frequency of the inverter

during preheating mode. The typical preheating frequency range is from the run frequency (as a minimum) to

150 kHz. The set resistor R_RFPH can be calculated, based on the preheating frequency f_PHand the resistor

R

_RFRUNaccording to the equation:

R_RFRUN

f_PH⋅ R_RFRUN

5⋅10⁸ΩHz

R_RFPH

=

−1

RTPH (set R for preheating time, pin 11)

A resistor from this pin to ground sets the preheating time of the inverter during preheating mode. A set resistor

range from zero to 25 kΩ corresponds to a range of preheating times from zero to 2500 ms subdivided into 127

steps, as expressed below:

t_{Pr eHeating}

R_RTPH

=

ms

100

kΩ

LVS (lamp voltage sense, pin 12)

Before startup this pin senses a current fed from the rectified line voltage via resistors through the high-side

filaments of the lamp for detection of an inserted lamp.

Preliminary Data Sheet

12

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Pin Configuration and Functionality

The sensed current fed into the LVS pin has to exceed 12 µA typically at a voltage level of 6.0 V at the LVS pin.

The reaction on the high side filament detection is mirrored at the RES pin (see pin 13). In addition, the detection

of available mains supply after an interruption is sensed by this pin. Together with the RES pin, the IC can monitor

the lamp removal of one lamp path (series connection of lamps is possible). If the functionality of this pin is not

required, it can be disabled by connecting this pin to ground.

During run mode the lamp voltage is monitored with this pin by sensing a current proportional to the lamp voltage

via resistors. An overload is indicated by an excessive lamp voltage. If the peak-to-peak lamp voltage causes a

peak-to-peak current above a threshold of 210 µA_PPfor longer than 620 µs, a fault EOL1 (end-of-life) is assumed.

If the DC current at the LVS pin exceeds a threshold of ±42 µA for longer than 2500 ms, a fault EOL2 (rectifier

effect) is assumed. The levels of AC sense current and DC sense current can be set separately by an external RC

network. Note that in the case of deactivation of the LVS PIN, reactivation starts when the voltage at the LVS pin

exceeds V_LVSEnable1in RUN Mode.

RES (restart, pin 13)

A source current flowing out of this pin via resistor and filament to ground monitors the existence of the low-side

filament of the fluorescent lamp for restart after lamp removal. A capacitor from this pin directly to ground

eliminates a superimposed AC voltage that is generated as a voltage drop across the low-side filament. With a

second sense resistor, the filament of a parallel lamp can be included in the lamp removal sensing. Note that

during startup the chip supply voltage V_cchas to be below 14.0 V before V_RESreaches the filament detection level.

During typical start-up with connected filaments of the lamp a current source I_RES3(-21.3 µA) is active as long as

V

_CC> 10.6 V and V_RES< V_RES1(1.6 V). An open low-side filament is detected when V_RES> V_RES1. Such a condition

will prevent the start-up of the IC. In addition, the comparator threshold is set to V_RES2(1.3 V) and the current

source changes to I_RES4(-17.7 µA). The system is then waiting for a voltage level lower than V_RES2at the RES pin

to indicate a connected low-side filament, which will enable the start-up of the IC.

An open high-side filament is detected when there is no sink current I_LVSSINK(< 12 µA typ.) into the LVS pin before

the V_CCstart-up threshold is reached. Under these conditions the current source at the RES pin is I_RES1(-42.6 µA)

as long as V_CC> 10.6 V and V_RES< V_RES1(1.6 V) and the current source is I_RES2(-35.4 µA) when the threshold

has changed to V_RES2(1.3 V). In this way, the detection of the high-side filament is mirrored at the levels on the

RES pin.

There is a further threshold of 3.2 V active at the RES pin during run mode. If the voltage level rises above this

threshold for longer than 620 µs, the IC changes over into latched fault mode.

In any case of fault detection with different reaction times the IC turns off the gate drives and changes into

powerdown mode with a current consumption of 170 µA max. An internal timer generates a delay time of 200 ms

before start-up conditions are checked again. As soon as start-up conditions are valid, a second start-up attempt

is initiated. If this second attempt fails, the IC remains in latched fault mode until a reset is generated by UVLO or

lamp removal. The RES PIN can be deactivated by setting the PIN to GND (durable).

HSGND (high-side ground, pin 14)

This pin is connected to the source terminal of the high-side MOSFET, which is also the node of the high-side and

low-side MOSFET. This pin represents the floating ground level of the high-side driver and the high-side supply.

HSVCC (high-side supply voltage, pin 15)

This pin provides the power supply of the high-side ground-related section of the IC. An external capacitor between

pins 14 and 15 acts like a floating battery, which has to be recharged cycle by cycle via the high-voltage diode

from low-side supply voltage during on-time of the low-side MOSFET. There is a UVLO threshold with hysteresis

that enables the high-side section at 10.4 V and disables it at 8.6 V.

Preliminary Data Sheet

13

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

HSGD (high-side gate drive, pin 16)

The gate of the high-side MOSFET in a half-bridge inverter topology is controlled by this pin. There is an active

L-level during UVLO and limitation of the max H-level at 11.0 V during normal operation. The switching

characteristics are the same as described for LSGD (pin 1). It is recommended to use a resistor of about 10 Ω

between the drive pin and gate in order to avoid oscillations and in order to shift the power dissipation of

discharging the gate capacitance into this resistor. The dead time between LSGD signal and HSGD signals is

self-adapting between 1.05 µs and 2.1 µs (typically).

2

Functional Description

This section describes applications and functionality of the chip.

2.1

Typical Application Circuitry

The schematic shown in Figure 3 shows a typical application for a T5 single fluorescent lamp. It is designed for

universal input voltage from 90 V_ACup to 270 V_AC. The following sections explain the components in reference to

this schematic.

R41

R35

R42 R43 R44

R34

L1

L101 D1...4

C1

C40

R45

R13

R14

R15

D5

L2

PFCZCD

PFCGD

Q2

Q3

R26

HSGD

C17

R1

R2

HSVCC

Q1

C15

90 ...

HSGND

R16

C24

C14

R27

270 VAC

C10

PFCVS

PFCCS

LSGD

LSCS

R11

R12

C2

C16

R36

D6

D7

D8

R18

C11 R20

R30

C19

D9

R21R22R23

C13

DR12

R25

C12

Figure 3

Application Circuit of Ballast for a Single Fluorescent Lamp (FL)

2.2

Normal Startup

This section describes the basic operation flow (8 phases) from the UVLO (Under Voltage Lock Out) into run mode

without any error detection. For detailed information see Section 2.2.1 and Section 2.2.2. Figure 4 shows the 8

different phases during a typical start from UVLO (phase 1, Figure 4) to run mode (phase 8, Figure 4) and then

into normal operation (no failure detected).

If the AC line input is switched ON, the V_CCvoltage rises to the UVLO threshold V_CC= 10.6 V (no IC activity during

UVLO). If V_CCexceeds the first threshold of V_CC= 10.6 V, the IC starts the first level of detection activity, the high

and low side filament detection during the start-up hysteresis (phase 2, Figure 4).

Preliminary Data Sheet

14

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

Frequency /

Lamp Voltage

135 kHz

100 kHz

Frequency

6

1

2

3

4

5

7

8

50 kHz

42 kHz

Lamp Voltage

60ms

35ms

80ms

0 - 2500ms

40 - 237ms

625ms

11ms

Mode /

Time

0 kHz

Rated BUS

Voltage V_BUS

100 %

95 %

Rated BUS Voltage

30 %

Mode /

Time

Chip Supply

Voltage V_CC

V_CC= 17.5 V

V_CC= 14.0 V

Chip Supply Voltage

V

_CC= 10.6 V

V_CC= 0 V

Mode /

Time

Run Mode

into normal Operation

UVLO

Monitoring Start UpSoft Start Preheating

Pre-Run

Ignition

Figure 4

Typical Startup Procedure in Run Mode (in Normal Operation)

Followed at the end of the start-up hysteresis (phase 2, Figure 4) V_CC> 14.0 V and before phase 3 is active, a

second level of detection activity senses for 130 µs (propagation delay of the IC) whether the bus voltage is

between 12.5 % and 105 %. If the previous bus voltage conditions are fulfilled and the filaments are detected, the

IC starts the operation with an internally fixed startup frequency of typically 135 kHz (all gates are active). If the

bus voltage reaches a level of 95 % of the rated bus voltage within 80 ms at the latest (phase 3, Figure 4), the IC

enters the soft start phase. During soft start (phase 4 , Figure 4), the start-up frequency shifts from 135 kHz down

to the set preheating frequency (Section 2.2.2). In the soft start phase, the lamp voltage rises and the chip supply

voltage reaches its working level from 10.6 V < V_CC< 17.5 V. After the soft start has finished, the IC enters the

preheating mode (phase 5, Figure 4) for preheating the filaments (adjustable time) in order to extend the life cycle

of the FL filaments. On finishing preheating, the controller starts ignition (phase 6, Figure 4). During the ignition

phase, the frequency decreases from the set preheating frequency down to the set operation frequency

(adjustable, see Section 2.2.2). If ignition is successful, the IC enters the pre-run mode (phase 7, Figure 4).

This mode is provided in order to prevent a malfunction of the IC due to an unstable system – e.g., the lamp

parameters are not in a steady state condition. After finishing the 625 ms pre-run phase, the IC switches over to

the run mode (phase 8, Figure 4) with complete monitoring.

Preliminary Data Sheet

15

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

2.2.1

Operating Levels from UVLO to Soft Start

This section describes the operating flow from phase 1 (UVLO) to phase 4 (soft start) in detail. The control of the

ballast is able to start the operation within less than 100 ms (IC in active mode). This is achieved by a small start-

up capacitor (about 1 µF C12 and C13 – fed by start-up resistors R11 and R12 in Figure 3) and the low current

consumption during the UVLO (I_VCC= 130 µA – phase 1, Figure 5) and start-up hysteresis (I_VCC= 160 µA – defines

the start-up resistors – phase 2, Figure 5) phases. The chip supply stage of the IC is protected against overvoltage

via an internal Zener clamping network, which clamps the voltage at 16.3 V and allows a current of 2.5 mA. For

clamping currents above 2.5 mA, an external Zener diode (D9, Figure 3) is required.¹⁾

Frequency /

Lamp Voltage

Frequency

135 kHz

100 kHz

Lamp Voltage

V_BUS

100 %

95 %

30 %

V_CC

17.5 V

16.0 V

14.0 V

10.6 V

1

2

3

4

UVLO

Monitoring

Start Up

Soft Start

I_VCC

< 6.0 mA + I_Gate

< 160 µA

130 µA

V_RES

1.6 V

- 21.3 µA

I_RES

I_LVS

< 210µA_pp

> 18 µA

Figure 5

Typical Startup Procedure in Run Mode (in Normal Operation)

1) I_Gatedepends on MOSFET

Preliminary Data Sheet

16

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

If V_CCexceeds the 10.6 V level and stays below 14.0 V (start-up hysteresis – phase 2, Figure 5), the IC checks

whether the lamps are assembled by detecting a current across the filaments.

The low side filaments are checked from a source current of typical I_RES3= - 21.3 µA flowing out of pin 13 RES

(Figure 5 I_RES). This current produces a voltage drop of V_RES< 1.6 V (filament is ok) at the low side filament sense

resistor (R 36 in Figure 3), connected to GND (via low side filament). An open low side filament is detected (see

Section 2.3.2), when the voltage at the RES pin exceeds the V_RES> 1.6 V threshold (Figure 5 V_RES).

The high side filaments are checked by a current of I_LVS> 12 µA typically via resistors R41, R42, R43 and R44

(Figure 3) into the LVS pin 12 (for a single lamp operation). An unused LVS pin has to be disabled via connection

to GND. An open high side filament is detected (see Section 2.3.3) when there is no sink current into the LVS pin.

This causes a higher source current out of the RES pin (typically 42.6 µA / 35.4 µA) in order to exceed V_RES

>

1.6 V. In the case of defective filaments, the IC keeps monitoring until an adequate current from the RES or the

LVS pin is present (e.g. in case of removal of a defective lamp).

When V_CCexceeds the 14.0 V threshold – by the end of the start-up hysteresis in phase 2 , Figure 5 – the IC waits

for 130 µs and senses the bus voltage. If the rated bus voltage is in the corridor of 12.5 % < V_BUSrated< 105 %, the

IC powers up the system and enters phase 3 (Figure 5 V_BUSrated> 95 % sensing); if not, the IC initiates a UVLO

until the chip supply voltage falls below V_CC< 10.6 V. As soon as the condition for a power-up is fulfilled, the IC

starts the inverter gate operation with an internal fixed start-up frequency of 135 kHz. The PFC gate drive starts

with a delay of approx. 300 µs. Next, the bus voltage will be checked for a rated level above 95 % for a duration

of 80 ms (phase 3, Figure 5). When leaving phase 3, the IC enters the soft start phase and shifts the frequency

from the internal fixed start-up frequency of 135 kHz down to the set preheating frequency – e.g. f_RFPH= 100 kHz.

2.2.2

Operating Levels from Soft Start to Run Mode

This section describes the operating flow from phase 5 (preheating mode) to phase 8 (run mode) in detail. In order

to extend the lifetime of the filaments, the controller enters – after the soft start phase – the preheating mode

(phase 5, Figure 6). The preheating frequency is set by resistors R22 pin R_FPHto GND in combination with R21

(Figure 3) typ. 100 kHz e.g. R22 = 8.2 kꢀ in parallel to R21 = 11.0 kꢀ (see Figure 3, RFRUN pin). The preheating

time can be selected by the programming resistor (R23 in Figure 3) at pin RTPH from 0 ms up to 2500 ms

(phase 5, Figure 6).

135kHz

f , V

Frequency

65kHz

50kHz

6

3

4

5

7

8

40kHz

Lamp Voltage

t

10ms

0-2500ms

40-237ms 625ms

Ignition Pre-Run

Normal Operation

Run

Start-Up

Softstart

Preheating

V_LSCS

0.8 V

Softstart proceeds in 15 steps à 650µs according Δf_PH= (135kHz - f_PH)/ 15steps.

Ignition proceeds in 127 steps à 324µs according Δf_IGN= (f_PH- f_RUN)/ 127steps.

Preheating Frequency with 8.7 kꢀ Resistor from PIN RFPH to GND

RUN Frequency with a 12.0 kꢀ Resistor from PIN RFRUN to GND

Figure 6

Typical Variation of Operating Frequency during Startup

17

Preliminary Data Sheet

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

During ignition (phase 6, Figure 6), the operating frequency of the inverter is shifted downward in t_typ= 40 ms

(t_max= 237 ms) to the run frequency set by a resistor (R21 in Figure 3) at pin RFRUN to GND (typically 45 kHz

with an 11.0 kꢀ resistor). During this frequency shifting, the voltage and current in the resonant circuit will rise

when the operation is close to the resonant frequency with increasing voltage across the lamp. The ignition control

is activated if the sensed slope at the LSCS pin reaches typically 205 mV/µs ± 25 mV/µs and exceeds the 0.8 V

threshold. This stops the decrease of the frequency and waits for ignition. The ignition control is now continuously

monitored by the LSCS pin. The maximum duration of the ignition procedure is limited to 237 ms. If there is no

ignition within this time frame, the ignition control is disabled and the IC changes over into the latched fault mode.

Furthermore, in order to reduce the size of the lamp choke, the ignition control is designed to operate with a lamp

choke in magnetic saturation during ignition. For operation in magnetic saturation during ignition; the voltage at

the shunt at the LSCS pin 2 has to be V_LSCS= 0.75 V when the ignition voltage is reached. If ignition is successful,

the IC enters the pre-run mode (phase 7, Figure 6). The pre-run mode is a safety mode in order to prevent a

malfunction of the IC due to an unstable system – e.g., the lamp parameters are not in a steady state condition.

After 625 ms pre-run mode, the IC changes to the run mode (phase 8, Figure 6). The run mode monitors the

complete system regarding bus over- and undervoltage, open loop, overcurrent of PFC and / or inverter, lamp

overvoltage (EOL1) and rectifier effect (EOL2) (see Section 2.5) and capacitive loads 1 and 2 (see Section 2.6).

Figure 8 shows the lamp voltage versus the frequency during the different phases from preheating to the run

mode. The lamp voltage rises by the end of the preheating phase with decreasing frequency (e.g., 100 kHz to

50 kHz) up to, for example, 700 V during ignition. After ignition, the lamp voltage drops down to its working level

with continuous decreasing of the frequency (Figure 8) down to its working level e.g. 45 kHz (set by a resistor at

the RFRUN pin to ground). After decreasing of the frequency stops, the IC enters the pre-run mode.

Lamp Voltage vs Frequency @ different Modes

1000

900

800

700

600

500

400

300

200

100

0

1000

900

800

700

600

500

400

300

200

100

IGNITION

Operation without Load

Operation with Load

PRE Run

and

RUN Mode

After

IGNITION

Pre Heating

0

10000

100000

Frequency [Hz]

After Ignition

Before Ignition

Figure 7

Lamp Voltage versus Frequency during the different Startup Phases

Preliminary Data Sheet

18

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

2.3

Filament Detection during Start-Up and Run Mode

The low and high side filament detection is sensed via the RES and the LVS pins. The low side filament detection

during start-up and run mode is detected via the RES pin only. An open high side filament during start-up will be

sensed via the LVS and the RES pins.

2.3.1

Start-Up with broken Low Side Filament

A source current of I_RES3= -21.3 µA from the RES pin (13) monitors the existence of a low side filament during a

start-up (also in run mode). In the case of an open low side filament during the start-up hysteresis (10.6 V < V_CC

< 14.0 V) a capacitor (C19 in Figure 3) will be charged up via I_RES3= -21.3 µA. When the voltage at the RES pin

(13) exceeds V_RES1= 1.6 V, the controller prevents a power up and clamps the RES voltage internally at V_RES

= 5.0 V. The gate drives of the PFC and inverter stage do not start working.

V_CC

Start UP with open LOW Side Filament

17.5 V

16.0 V

Chip Supply Voltage

14.0 V

10.6 V

Time

Start Up

Hysteresis

UVLO

V_RES

5.0 V

No Power UP

1.6 V

1.3 V

I_RES

21.3µA

17.7µA

Time

V_Lamp

Figure 8

Start-Up with Open Low Side Filament

Restart from open LOW Side Filament

17.5 V

16.0 V

Chip Supply Voltage

PFC Gate Drive

10.0 V

Time

Timer t = 100ms

V_RES

5.0 V

Latch Mode

1.6 V

1.3 V

Power UP into RUN Mode

1

2

3

I_RES

21.3µA

17.7µA

Time

V_Lamp

Figure 9

Restart from Open Low Side Filament

Preliminary Data Sheet

19

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

The IC comparators are then set to a threshold of V_RES1= 1.3 V and to I_RES4= - 17.7µA, the controller waits until

the voltage at the RES pin drops below V_RES1= 1.3 V.

When a filament is present (Figure 9, section 2), the voltage drops below 1.3 V and the value of the source current

out of the RES pin is set from I_RES4= -17.7 µA up to I_RES3= -21.3 µA. The controller then powers up the system,

including soft start and preheating, into the run mode.

2.3.2

Low Side Filament Detection during Run Mode

In the case of an open low side filament during run mode, the current flowing out of the RES pin I_RES3= -21.3 µA

charges up the capacitor C19 in Figure 3. If the voltage at the RES pin exceeds the V_RES3= 3.2 V threshold, the

controller detects an open low side filament and stops the gate drives after a delay of t = 620 µs of an internal timer.

Open LOW Side Filament during Run Mode

V_CC/ V_PFCGD

17.5 V

16.0 V

Chip Supply Voltage

PFC Gate Drive

10.0 V

Time

V_RES

5.0 V

3.2 V

1.6 V

1.3 V

Latch Mode

I_RES

21.3µA

17.7µA

Time

V_Lamp

Delay t = 620µs

Figure 10 Open Low Side Filament Run Mode

Restart from open LOW Side Filament

17.5 V

16.0 V

Chip Supply Voltage

PFC Gate Drive

10.0 V

Time

Timer t = 100ms

V_RES

5.0 V

Latch Mode

1.6 V

1.3 V

Power UP into RUN Mode

1

2

3

I_RES

21.3µA

17.7µA

Time

V_Lamp

Figure 11 Restart from Open LS Filament

Preliminary Data Sheet

20

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

A restart is initiated when a filament is detected e.g. in the case of a lamp removal. If a filament is present

(Figure 11, section 2), the voltage drops below 1.3 V and the value of the source current flowing out of the RES

pin is set from I_RES4= -17.7 µA up to I_RES3= -21.3 µA. The controller powers up the system, including soft start and

preheating, into the run mode (Figure 11, section 3).

2.3.3

Start-Up with Broken High Side Filament

An open high side filament during the start-up hysteresis (10.6 V < V_CC< 14.0 V) is detected when the current into

the LVS pin 12 is below I_LVS= 12 µA (typically). In that case, the current flowing out of the RES pin 13 rises up to

I_RES1= -42.6 µA. This causes the voltage at the RES pin to cross V_RES1= 1.6 V. The source current is now set to

I_RES2= -35.4 µA and another threshold of V_RES2= 1.3 V is active. The controller prevents a power-up (see

Figure 12), and the gate drives of the PFC and inverter stage do not start working.

V_CC

Start UP with OPEN HIGH Side Filament

17.5 V

16.0 V

Chip Supply Voltage

14.0 V

10.6 V

Time

Start Up

Hysteresis

V_RES

UVLO

2.0 V

1.6 V

1.3 V

No Power UP

I_RES

42.6µA

35.4µA

21.3µA

17.7µA

Time

I_LVS

12µA

V_Lamp

I_LVS

Time

Figure 12 Start-Up with Open High Side Filament

Preliminary Data Sheet

21

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

V_CC

Restart from open HIGH Side Filament

17.5 V

16.0 V

Chip Supply Voltage

14.0 V

10.6 V

Time

V_RES

No Power Up

2.0 V

1.6 V

1.3 V

Power UP (into RUN Mode)

I_RES

Time

42.6µA

35.4µA

I_RES

21.3µA

17.7µA

I_LVS

12µA

I_LVS

V_Lamp

Time

Figure 13 Restart from Open High Side Filament

When the high side filament is present, e.g. insertion of a lamp, the current of the active LVS pin exceeds I_LVS

>

12 µA (typically), the RES current drops from I_RES2= -35.4 µA down to I_RES4= -17.7 µA (Figure 13). The controller

then senses the low side filament. If a low side filament is also present, and the controller drops (after a short delay

due to a capacitor at the RES pin) below V_RES2= 1.3 V, the RES current is set to I_RES3= -21.3 µA, and the controller

powers up the system.

Preliminary Data Sheet

22

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

2.4

PFC Preconverter

2.4.1

Discontinuous Conduction and Critical Conduction Mode Operation

The digitally controlled PFC preconverter starts with an internally fixed ON time of typically t_ON= 4.0 µs and a

variable frequency. The ON time is increased every 280 µs (typical) up to a maximum ON time of 24 µs. The

control switches practically immediately from the discontinuous conduction mode (DCM) to critical conduction

mode (CritCM) as soon as a sufficient ZCD signal becomes available. The frequency range in CritCM is 22 kHz

to 500 kHz depending on the power (Figure 14), with a variation of the ON time from 24 µs > t_ON> 0.5µs.

Discontinuous Conduction Mode (DCM) <> Critical Condution Mode (CritCM)

1000,00

100,00

10,00

1,00

100,00

Frequency @ CritCM Operation

Frequency @ DCM Operation

10,00

Nominal Load

ON Time Hysteresis

PRE HEATING

Light Load

ON Time @ CritCM Operation

Increasing Power

1,00

ON Time @ DCM Operation

Decreasing Power

0,10

ON Time Hysteresis

in RUN MODE

0,01

0,10

100,00

0,01

0,10

1,00

10,00

Normalized Output Power [%]

Frequency CritCM Ton DCM

Frequency DCM

Ton CritCM

Figure 14 Operating Frequency and ON Time versus Power in DCM and CritCM Operation

For lower loads (P_OUTNorm< 8 % from the normalized load¹⁾) the control operates in discontinuous conduction mode

(DCM) with an ON time from 4.0 µs and increasing OFF time. The frequency during DCM is variable in a range

from 144 kHz down to typically 22 kHz @ 0.1 % load (Figure 14). With this control method, the PFC converter

enables stable operation from 100 % load down to 0.1 %. Figure 14 shows the ON time range in DCM and CritCM

(Critical Conduction Mode) operation. In the overlapping area of CritCM and DCM there is a hysteresis of the ON

time which causes a negligible frequency change.

2.4.2

PFC Bus Voltage Sensing

Overvoltage, open loop, bus 95 % and undervoltage states (Figure 15) of the PFC bus voltage are sensed at the

PFCVS pin via the network R14, R15, R20 and C11 – Figure 3 (C11 acts as a spike suppression filter).

1) Normalized power @ low line input voltage and maximum load

Preliminary Data Sheet

23

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

2.4.2.1

Bus Overvoltage and PFC Open Loop

The bus voltage loop control is completely integrated (Figure 16) and provided by an 8-bit sigma/delta A/D

converter with a typical sampling rate of 280 µs and resolution of 4 mV/bit. After leaving phase 2 (monitoring), the

IC starts power-up (V_CC> 14.0 V). After power-up, the IC senses the bus voltage below 12.5 % (open loop) or

above 105 % (bus overvoltage) for 130 µs. In the case of bus overvoltage (V_BUSrated> 109 %) or open loop

(V_BUSrated< 12.5 %) in phases 3 to 8, the IC shuts off the gate drives of the PFC within 5 µs or 1 µs respectively.

In this case, the PFC restarts automatically when the bus voltage is within the corridor (12.5 % < V_BUSrated< 105 %)

again. Is the bus voltage valid after 130 µs, the bus voltage sensing is set to 12.5 % < V_BUSrated< 109 %. If these

thresholds are exceeded for longer than 1 µs (open loop) or 5 µs (overvoltage), the PFC gate drive stops working

until the voltage drops below 105 % or exceeds the 12.5 % level. If the bus overvoltage (> 109 %) lasts for longer

than 625 ms in run mode, the inverter gates also shut off and a power-down with complete restart is attempted

(Figure 15).

Rated BUS

6

Voltage V_BR

1

2

3

4

5

7

8

V_PFCVS= 2.725V

V_PFCVS= 2.625V

BUS Over Voltage: Stops PFC Gate Drive within 5µs Auto Restart when V_BR< 109% / t > 625ms PD V_BR< 105% Æ Fault U

109 %

105 %

Typical rated Bus Voltage Level

V_PFCVS= 2.500V

100 %

95 %

V

_PFCVS= 2.375V

V

_PFCVS= 1.875V

75 %

30 %

Under Voltage V _BR< 75%

t < 800ms AR without Preheating

t > 800ms AR with Preheating

V_PFCVS= 0.313V

12.5 %

0%

PFC Open Loop / keeps all Gate Drives within 1µs Auto Restart / t > 1µs Stops PFC FET till V_BR> 12.5%Æ AR

Mode /

Time

V_CC< 10.6 VV_CC< 14.1 V

60ms 35ms

V_BUS>95%

80ms

Preheating

0 - 2500ms

Ignition

Pre-Run

625ms

Soft Start

11ms

Run Mode into normal Operation

40 - 237ms

130µs

AR = Auto Restart

ERROR Corridor

PD = Power Down

CbC = Cycle by Cycle

Figure 15 PFC Bus Voltage Operating Level and Error Detection

2.4.2.2

Bus Voltage 95 % and 75 % Sensing

When the rated bus voltage is in the corridor of 12.5 % < V_BUSrated< 109 %, the IC will check whether the bus

voltage exceeds the 95 % threshold (Figure 15, phase 3) within 80 ms before entering the soft start phase 4.

Another threshold is activated when the IC enters the run mode (phase 8). If the rated bus voltage drops below

75 % for longer than 84 µs, a power-down with a complete restart is attempted when a counter exceeds 800 ms.

In the case of short-term bus undervoltage (the bus voltage reaches its working level in run mode before exceeding

typically 800 ms (min. 500 ms)) the IC skips phases 1 to 5 and starts with ignition (see Section 2.7.1 for conditions

for emergency lighting). The internal reference level of the bus voltage sense V_PFCVSis 2.5 V (100 % of the rated

bus voltage) with a high accuracy. A surge protection is activated in the case of a rated bus voltage of V_BUS

>

109 % and a low side current sense voltage of V_LSCS> 1.6 V in pre-run mode, or V_LSCS> 0.8 V in run mode for

longer than 500 ns.

Preliminary Data Sheet

24

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

2.4.3

PFC Structure of Mixed Signals

A digital NOTCH filter eliminates the input voltage ripple independently of the mains frequency. A subsequent error

amplifier with PI characteristic ensures stable operation of the PFC preconverter (Figure 16).

Over Voltage

109%

Open Loop

12.5%

PFCGD

PFCVS

Σ∆-ADC

Notch Filter

PI Loop Control

PWM

Gate Drive

PFCCS

Under Voltage

75%

Over Current

1V ± 5.0%

ZCD Start Up

1.5V / 0.5V

Bus Voltage

95%

PFCZCD

THD

Correction

Int. Reference

V_PFCVS= 2.5 V

Clock 870 kHz

Figure 16 Structure of the Mixed Digital and Analog Control of the PFC Preconverter

The zero current detection (ZCD) is sensed by the PFCZCD pin via R13 (Figure 3). Notification of finished current

flow during demagnetization is required in CritCM and in DCM also. The input is equipped with a special filtering

system, including blanking of typically 500 ns and a large hysteresis of typically 0.5 V and 1.5 V V_PFCZCD

(Figure 16).

2.4.4

THD Correction via ZCD Signal

An additional feature is the THD correction (Figure 16). In order to optimize the improved THD (especially in the

zones A shown in Figure 17 ZCD @ AC Input Voltage), there is a possibility to extend the pulse width of the gate

signal (blue part of the PFC gate signal in Figure 17) with the variable PFC ZCD resistor (see resistor R13 in

Figure 3) in addition to the gate signal controlled by the V_PFCVSsignal (gray part of the PFC gate signal in

Figure 17).

Preliminary Data Sheet

25

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

ZCD @ AC Input Voltage

ZCD @ DC Input Voltage

Rectified

AC Input Voltage

DC Input Voltage

A

B

A

0

Voltage at

ZCD-Winding

PFC Gate

Drive Voltage

0

PFC gate signal (gray) controlled by the V_PFCVS

PFC gate signal (blue) controlled by the ZCD

Figure 17 THD Optimization using adjustable Pulse Width Extension

In the case of DC input voltage (see DC input voltage in Figure 17), the pulse width gate signal is fixed as a

combination of the gate signal controlled by the V_PFCVSpin (gray) and the additional pulse width signal controlled

by the ZCD pin (blue) shown in Figure 17 ZCD @ DC input voltage.

The PFC current limitation at pin PFCCS interrupts the ON time of the PFC MOSFET if the voltage drop at the

shunt resistors R18 (Figure 3) exceeds V_PFCCS= 1.0 V (Figure 16). This interrupt will restart after the next

sufficient signal from ZCD becomes available (Auto Restart). The first value of the resistor can be calculated by

the ratio of the PFC mains choke and ZCD winding by the bus voltage and a current of typically 1.5 mA (see

equation below for a good practical value of resistance of ZCD). An adjustment of the ZCD resistor causes an

optimized THD.

N

^ZCD*V_BUS

N_PFC

R_ZCD

=

1.5mA

2.5

Detection of End-of-Life and Rectifier Effect

Two effects are present by End of Life (EOL): lamp overvoltage (EOL1) and a rectifier effect (EOL2).

After ignition (see 1 in Figure 18), the lamp voltage breaks down to its run voltage level with decreasing frequency.

On reaching the run frequency, the IC enters the pre-run mode for 625 ms. During this period, the EOL detection

is still disabled. In the subsequent run mode (2 in Figure 18) the detection of EOL1 (lamp overvoltage; see 3,

Figure 18) and EOL2 (rectifier effect; see 4, Figure 18) is enabled completely.

Preliminary Data Sheet

26

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

Lamp voltage

Pos. Ignition Level

Pos. AC Level

for EOL1 Detection

1

2

3

4

Positive DC Level

for EOL2 Detection

0

t

Negative DC Level

for EOL2 Detection

t

Neg. AC Level

for EOL 1 Detection

Neg. Ignition Level

EOL2

Rectifier Effect

EOL1

Lamp Overvoltage

Ignition

Normal Operation

Figure 18 End of Life and Rectifier Effect

2.5.1

Detection of End of Life 1 (EOL1) – Lamp Overvoltage

The event of EOL1 is detected by measuring the positive and negative peak levels of the lamp voltage via an AC

current fed into the pin LVS (Figure 19). This AC current is fed into the LVS pins via the network R41, R42, R43,

R44 and the low pass filter C40 and R45 – see Figure 3. If the sensed AC current exceeds 210 µA_PPfor longer

than 620 µs, the status of end-of-life (EOL1) is detected (lamp overvoltage/overload; see Figure 19 LVSAC

current). The EOL1 fault results in a latched power-down mode (after trying a single restart). The controller

continuously monitors the status until the EOL1 status changes – e.g. a new lamp is inserted.

Lamp Voltage

Pos. AC Level

for EOL1 Detection

3

2

0

t

Neg. AC Level

for EOL1 Detection

EOL1

Lamp Overvoltage

LVSAC Current

Normal Operation

105µA_Peak

3

2

t

0

- 105µA_Peak

t = 620 µs

EOL1 Detection

Figure 19 End of Life (EOL1) Detection, Lamp Voltage versus AC LVS Current

Preliminary Data Sheet

27

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

2.5.2

Detection of End of Life 2 (EOL2) – Rectifier Effect

The rectifier effect (EOL2) is detected by measuring the positive and negative DC levels of the lamp voltage via a

current fed into the LVS pin (Figure 20). This current is fed into the LVS pin via the network R41, R42, R43 and

R44 (see Figure 3). If the sensed DC current exceeds ± 42 µA (Figure 20 LVSDC current) for longer than

2500 ms, the status of end-of-life (EOL2) is detected. The EOL2 fault results in a latched power-down mode (after

trying a single restart) and the controller is continuously monitoring. The insertion of a new lamp or an interruption

of the input voltage resets the status of the IC.

Lamp Voltage

2

4

Pos. DC Level

for EOL2 Detection

0

t

Neg. DC Level

for EOL2 Detection

EOL2

Rectifier Effect

Normal Operation

LVSDC Current

42 µA

0

t

- 42 µA

EOL2 Detection

t = 2500 ms

Figure 20 End of Life (EOL2) Detection, Lamp Voltage versus DC LVS Current

2.6

Detection of Capacitive Load

In order to prevent a malfunction in the area of capacitive load (see Figure 21) during run mode due to certain

deviations from the normal load (e.g. harmed lamp, sudden break of the lamp tube …), the IC has three integrated

thresholds – sensed only via the LSCS (pin 2). The controller distinguishes between two different states of

capacitive load: detection of working without load (idling detection, CapLoad 1) and working with short overcurrent

(CapLoad 2). This state (CapLoad 2) affects operation below the resonance in the capacitive load area

(Figure 23). In both cases, the IC results in a latched power-down mode after a single restart. After latching the

power-down mode, the controller continuously monitors the input voltage and lamp filaments, and restarts after

interruption of the input voltage or insertion of a new lamp.

Preliminary Data Sheet

28

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

Lamp Voltage vs Frequency @ different Modes

1000

900

800

700

600

500

400

300

200

100

0

1000

900

800

700

600

500

400

300

200

100

Area of Inductive

Load Behavior

IGNITION

Area of Capacitive

Load Behavior

Load

PRE Run

and

RUN Mode

After

IGNITION

Pre Heating

0

10000

100000

Frequency [Hz]

After Ignition

Before Ignition

Figure 21 Capacitive and Inductive Operation

2.6.1

Capacitive Load 1 (Idling Detection – Current Mode Preheating)

A capacitive load 1 operation (idling) is detected when the voltage at the LSCS pin is below +50 mV during the

second 50 % ON time of the low side MOSFET (see capacitive load 1 (idling) in Figure 22). If this status is present

for longer than 2500 ms, the controller triggers a latched power-down mode after trying a single restart. The

controller keeps monitoring the status continuously until an adequate load is present (e.g. lamp removal); then the

IC changes to normal operation.

Capacitive Load 1 Operation (Ballast with Current Mode Preheating)

Normal Operation

Capacitive Load 1 (Idling)

V_DSLS

I_DSLS

V_GateHS

V_GateLS

V_LSCS

V_GateLS

V_LSCS

2nd 50%

ON Time

+ 50 mV

t_{CAPLOAD 1}

t_{CAPLOAD 2}

t_{CAPLOAD 1}

Figure 22 Capacitive Mode 1 Operation without Load during Run Mode

Preliminary Data Sheet 29

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

2.6.2

Capacitive Load 2 (Overcurrent / Operation below Resonance)

A capacitive load 2 operation is detected if the voltage at the LSCS pin drops below a second threshold of

_LSCS= –50 mV directly before the high side MOSFET is turned on or exceeds a third threshold of V_LSCS= 2.0 V

V

during ON switching of the high side MOSFET. If this overcurrent is present for longer than 620 µs, the IC triggers

a latched power-down mode after trying a single restart. The controller keeps monitoring the status continuously

until an adequate load is present e.g. a new lamp is inserted; then the IC changes to normal operation.

Normal Operation

Capacitive Load 2 (Over Current)

V_DSLS

I_DSLS

V_GateHS

V_GateLS

V_LSCS

+ 2.0 V

- 50 mV

t_{CAPLOAD 2}

Figure 23 Capacitive Mode 2 – Operation with Overcurrent

2.6.3

Adjustable Self-adapting Dead Time

The dead time between the turn OFF and turn ON of the half-bridge drivers is adjustable (C16, see Figure 3) and

is detected via a second threshold (–50 mV) of the LSCS voltage. The range of the dead time adjustment is 1.05 µs

up to 2.1 µs during all operating modes. The start of the dead time measurement is the OFF switching of the high

side MOSFET. The end of the dead time measurement is when V_LSCSdrops for longer than typically 200 ns

(internal fixed propagation delay) below –50 mV. This time will be stored (stored dead time) and the low side gate

driver switches ON. The high side gate driver turns ON again after OFF switching of the low side switch and the

stored dead time.

Normal Operation in RUN Mode

V_DSLS

V_LSCS

V_LSCS= -50mV

END of Dead Time

Measurement

Gate LS

Gate HS

Dead Time

START of Dead Time

Measurement

200 ns

Propagation Delay

Stored Dead Time

Figure 24 Dead Time of ON and OFF of the Half-Bridge Drivers

Preliminary Data Sheet 30

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

2.7

Emergency Lighting

Line interruptions (bus voltage drops) are detected by the PFCVS. If the rated PFC bus voltage drops below

_BUSRated< 75 % during run mode, the controller detects PFC bus undervoltage. In order to meet the emergency

V

lighting standards, the controller distinguishes between two different states of PFC bus undervoltage: short- and

a long-term PFC bus undervoltage. A timer increases the time as long as bus undervoltage is present. Short-term

bus undervoltage is detected if the timer value stays below t < 800 ms typical (500 ms min.) after the bus voltage

reaches the nominal level again. This causes a restart without preheating (emergency standard of VDE0108) –

see Figure 25. If the timer exceeds t > 800 ms, the controller forces a complete restart of the system due to long-

term bus undervoltage (Figure 26).

2.7.1

Short-term PFC Bus Undervoltage

Short-term PFC bus undervoltage (Figure 25) is detected if the duration of the undervoltage does not exceed

800 ms (timer stays below t < 800 ms, see Figure 25). In that case, the PFC and inverter drivers are immediately

switched off and the controller continuously monitors the status of the bus voltage in a latched power-down mode

(I_CC< 170 µA). If the signal at the LVS pin exceeds 18 µA and the rated bus voltage is above 12.5 % while the

timer is below t < 800 ms, the controller restarts from power up without preheating. The timer resets to 0 when

entering run mode.

Bus Voltage Drop for t < 800 ms

Restart without Preheating

Interrupt for

t < 800 ms

V_BUSRated

100%

75%

Power Down

Mode

RUN Mode

Pre Run

Run Mode

V_CC

16V

I_CC

< 6 mA +

I_QGate

< 6 mA + I_QGate

< 160 µA

Timer

t = 800ms

I_Preheating

V_Lamp

Figure 25 BUS Voltage Drop below 75% (rated Bus Voltage) for t < 800 ms during RUN Mode

Preliminary Data Sheet

31

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

2.7.2

Long-term PFC Bus Undervoltage

If the duration of the bus undervoltage exceeds t > 800 ms (see Figure 26), the controller forces an undervoltage

lockout (UVLO). The chip supply voltage drops below V_CC= 10.6 V and the chip supply current is below I_CC

< 130 µA. When the Vcc voltage exceeds the 10.6 V threshold again, the IC current consumption is below I_CC

< 160 µA. In that case, the controller resets the timer and restarts with the full start-up procedure, including

monitoring, power-up, start-up, soft start, preheating, ignition, pre-run and run modes, as shown in Figure 26.

Bus Voltage Drop for t > 800 ms

Restart with full Start Procedure

V_BUSRated

Interrupt for t> 800 ms

95%

75%

RUN Mode

Power Down Mode

Run Mode

V_CC

16V

UVLO @ 10.6V

I_CC

< 6 mA +

I_Gate

< 6 mA + I_Gate

<160 µA

< 160 µA

t = 800ms

Timer

I_Preheating

V_Lamp

Figure 26 BUS Voltage Drop below 75% (rated Bus Voltage) for t > 800 ms during RUN Mode

2.8

Built-in Customer Test Mode Operation

In order to decrease the final ballast testing time for customers, the 2nd generation of ballast IC supports an

integrated built-in Customer Test Mode and several functions to disable some features and states of the IC.

2.8.1

Preheating Test Mode

This feature forces the IC to stay in the preheating mode (see Section 2.8.1.2) or to start ignition immediately

without any preheating (see Section 2.8.1.1). A resistor at this pin defines the duration of the preheating phase.

Normally, the preheating phase is in a range of 0 ms up to 2500 ms set via a resistor R_RTPH= 0 ꢀ up to 25 kꢀ from

the RTPH pin to GND. The preheating phase is skipped when the RTHP pin is set to GND. If the signal at this pin

is V_RTPH> 5.0 V, the IC remains in the preheating mode.

Preliminary Data Sheet

32

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

2.8.1.1

Skip the Preheating Phase – Set RTPH Pin to GND

Figure 27 shows a standard start-up with a preheating time set via resistor at the RTPH pin 11 to GND (e.g. 8.2 kꢀ

– this is equal to a preheating phase of approx. 820 ms). The preheating phase can be skipped by setting the

RTPH pin 11 directly to GND. In this case, ignition takes place directly after the soft start phase (see Figure 28).

V_CC

Standard Start UP with Pre Heating

17.5 V

16.0 V

Chip Supply Voltage

14.0 V

10.6 V

Time

Start Up

Hysteresis

UVLO

V_RTPH

5.0 V

Duration of Pre Heating

is set by Resistor only

2.5 V

V_LSGD

10.0 V

Time

V_Lamp

PRE HEATING

t = 820 ms when using

R

_RTPH= 8.2kOhm

Figure 27 Start-Up WITH Preheating

V_CC

Start UP without Pre Heating

17.5 V

16.0 V

Chip Supply Voltage

14.0 V

10.6 V

Time

Start Up

UVLO

Hysteresis

V_RTPH

5.0 V

2.5 V

Set RTPH Resistor to GND

Time

V_LSGD

10.0 V

Time

V_Lamp

INGNITION directly

Figure 28 Start-Up WITHOUT Preheating

Preliminary Data Sheet

33

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

2.8.1.2

IC Remains in Preheating Phase

This feature gives the customer the flexibility to align the preheating frequency to the filament power in the

preheating phase. Figure 29 shows a standard start-up with the set preheating time of, for example, 820 ms with

an 8.2 kꢀ resistor at the RTPH pin 11. To force the IC to remain in preheating, the voltage level at the RTPH pin 11

has to be set to 5.0 V. The duration of this 5.0 V signal defines the time of the preheating (see I_PreHeatin Figure 30).

V_CC

17.5 V

16.0 V

Chip Supply Voltage

14.0 V

10.6 V

Time

Start Up

UVLO

V_RTPH

Hysteresis

5.0 V

2.5 V

Duration is set by

Resistor only

Time

I_PreHeat

Preheating

t = 820 ms when using

RRTPH = 8.2kOhm

V_Lamp

IGNITION

Time

Figure 29 Start-Up WITH Preheating

V_CC

17.5 V

16.0 V

Chip Supply Voltage

14.0 V

10.6 V

Time

Start Up

UVLO

V_RTPH

Hysteresis

Set by external 5.0V Signal

IC remains in Preheating

NO Ignition

5.0 V

2.5 V

Time

I_PreHeat

V_Lamp

Time

Figure 30 Start-Up WITHOUT Preheating

Preliminary Data Sheet

34

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

2.8.2

Deactivation of the Filament Detection

In order to deactivate the filament detection of the low or high side filament, set the RES pin 13 or the LVS pin to

GND. In this case, the IC starts up in normal operation without checking the filaments – e.g. when using an

equivalent lamp resistive load instead of a load.

V_CC

17.5 V

16.0 V

Chip Supply Voltage

14.0 V

10.6 V

Time

Start Up

Hysteresis

UVLO

V_RES

5.0 V

1.6 V

1.3 V

RES PIN set to GND

V_LSGD

10V

Time

V_Lamp

Figure 31 Deactivation via RES PIN

V_CC

17.5 V

16.0 V

Chip Supply Voltage

14.0 V

10.6 V

Time

Start Up

UVLO

V_RES

Hysteresis

5.0 V

LVS PIN set to GND

1.6 V

1.3 V

Time

V_LSGD

10V

Time

V_Lamp

Figure 32 Deactivation via LVS PIN

Figure 31 shows the deactivation of the low and high side filament via set the RES pin 13 to GND. Figure 32

shows the deactivation of the high side filament detection via set the LVS pin to GND.

Note:An unused LVS pin has to be set to GND.

Preliminary Data Sheet

35

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Functional Description

2.8.3

Built-in Customer Test Mode (Clock Acceleration)

The built-in customer test mode, supported by this IC, saves testing time for customers in terms of ballast end test.

In this mode, the IC accelerates the internal clock in order to reduce the time of the 4 different procedures by the

following factors (see Table 2).

Table 2

Phase

Specified Acceleration Factors

Duration for Test [ms]

625

Acceleration Factor

Nominal Duration [ms]

Preheating

4

2

2500 (max)

237

Time Out Ignition

Pre Run Mode

EOL2

118.5

41.7

15

60

625

2500

2.8.3.1

Enabling of the Clock Acceleration

The clock acceleration (Built-in Customer Test Mode) is activated when the chip supply voltage exceeds V_CC

> 14.0 V and the voltages at the run and preheating frequency pins are set to V_RFRUN= V_RFPH= 5.0 V (± 5 %) –

see Figure 33. A RES pin voltage of V_RES> 3.5 V up to 5.0 V (± 5 %) prevents a power-up of the IC, the IC remains

in a mode before powering up as long as the voltage at the RES pin is V_RES> 3.5 V up to 5.0 V (± 5 %) – no power-

up.

Note:After the activation of the clock acceleration mode, the voltage level of 5.0 V at the run and preheating

frequency pins (V_RFRUN= V_RFPH) can be released.

2.8.3.2

Starting the Chip with Accelerated Clock

In order to start the IC with an accelerated clock, set the voltage at the RES pin to GND (V_RES= 0 V), see

Figure 33. The IC powers up the system and starts working with an accelerated clock. The duration of the different

modes are accelerated by the factors shown in Table 2.

Accelerated

Ign. Time OUT

by Factor 2

Accelerated

Pre Heating

by Factor 4

Propagation

Delay

IC Powers UP

Accelerated

Pre RUN

by Factor 15

Filament

Detection

IC Remains

in Power UP

V_CC

Accelerated

EOL2

V_CCNom

by Factor 60

in Run Mode

14.0 V

10.6 V

Enabling of

Clock

Acceleration

Time

V_RFRUN

5.0 V

2.5 V

V_RFPH

5.0 V

2.5 V

Starting the Chip with

an accelerated Clock

Time

V_RES

3.5 V

Figure 33 Clock Acceleration (Built in Customer Test Mode)

Preliminary Data Sheet 36

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

State Diagram

3

State Diagram

3.1

Features during Different Operating Modes

10.6V < Vcc < 17.5V;

I_RES= 21.3µA; f= F_RUN

Mains Switch turned on; 0V < Vcc < 10.6V; I_VCC < 130µA; I_RES= 0µA

10.6V < Vcc < 14.0V; I_VCC < 160µA; I_RES= 21.3µA

Vcc > 14.0V & Filament detected; 12,5%< VBUS <105% => Start

after 130µs

F_START= 135kHz as long as VBUS < 95%

10.6V < Vcc < 17.5V

f= F_RUN

10.6V < Vcc < 17.5V

VBUS > 95%

F_START > f > F_PH

10.6V < Vcc < 17.5V

f= F_PH

10.6V < Vcc < 17.5V

F_PH > f > F_RUN

Typ. 60ms Typ. 35ms 0...80ms

10ms

0...2500ms

Preheating

40...237ms

Ignition

625ms

Pre-Run Run

UVLO

Monitoring Start-up Softstart

enabled PFC 5µs

enabled Inv 625ms

U

enabled PFC

BUS Overvoltage > 109%

BUS Overvoltage > 105%

BUS Undervoltage < 95%

enabled PFC enabled PFC

enabled PFC

A

U

N

F

enabled 130µs

enabled

enabled 84µs

BUS Undervoltage < 75%

BUS Open Loop < 12,5%

enabled PFC 5µs

enabled Inv 625ms

enabled 200ns

Threshold 1.0V

enabled 500ns

Threshold 0.8V

enabled PFC

enabled

enabled PFC

enabled

enabled PFC

enabled

enabled PFC

enabled

enabled PFC

enabled

Overcurrent PFC

Overcurrent Inverter

Capacitive Load 2

EOL 1, Overload

enabled 1,6V enabled 1,6V

enabled 0,8V

enabled 1,6V

enabled 620µs

enabled 2,5s

EOL 2, Rectifier Effect

Capacitive Load 1

A

N

U

F

= Auto Restart

= No Fault

= Undervoltage

Fault: 10.6V < Vcc < 17.5V; I_VCC < 170µA; I_RES= 21.3µA

disabled by Lamp Removal or UVLO

F= A single Restart is possible after delay of 200ms by internal Timer

Minimum

Duration

of Effect

= Fault, a single Restart

Figure 34 Monitoring Features during Different Operating Modes

Preliminary Data Sheet

37

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

State Diagram

3.2

Operating Flow of the Start-Up Procedure into Run Mode

UVLO

Vcc < 10.6V

Icc < 130µA

Vcc < 10.6V

Vcc > 10.6V

Monitoring

Vcc > 10.6V

Icc < 160µA

Vcc > Vccon(14.0V)

& Filament detected

Power-up

Gate Drives off

14.1V < Vcc

See

V_BUS< 12,5%

or V_BUS> 105%

Timing and Handling of

Fault Conditions

Icc approx 6.0mA

after 130µs

& V_BUS> 12,5%

& V_BUS< 105%

Start-up

Inverter Gates on

PFC Gate on

See

Protection

Functions

17.5V> Vcc >10.6V

f_Inv = f_START

Fault

17.5V> Vcc >10.6V

Icc < 170µA

V_BUS> 95%

within 80ms

Gate Drives off

Softstart

17.5V> Vcc >10.6V

f_START=> f_PH

after 10ms

& Flag Skip Preheat

= Reset

& Flag Skip Preheat = Set

// Reset Flag

Skip Preheat

& Counter Skip PH //

Preheat

17.5V> Vcc >10.6V

f = f_PH

after t_PH= 0...2500ms

Time set by R_TPH

Ignition*

Timeout 237ms

17.5V> Vcc >10.6V

f_PH => f_RUN

f_Inv= f_RUN within

t_IGN= 40...237ms

Pre-Run

17,5V> Vcc >10.6V

f = f_RUN

Reduced Monitoring

after

t_PRERUN= 625ms

Run

* NOTE:

Ignition will reset the

Flag Skip Preheating

17.5V> Vcc >10.6V

f = f_RUN

Complete Monitoring

Figure 35 Operating Flow during Start-Up Procedure

Preliminary Data Sheet

38

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

State Diagram

3.3

Auto Restart and Latched Fault Condition Mode

Fault U

BUS Voltage

Fault A

Fault F

Fault, single Restart

Auto Restart

BUS Undervoltage

(VBUS < 75%

during Run Mode

for t > 84µs);

BUS Overvoltage

(VBUS > 109%

for t > 625ms);

Open Filament LS;

Inverter Overcurrent;

Capacitive Load 1;

Capacitive Load 2;

Timeout Ignition;

Surge;

Time OUT Start Up

(VBUS < 95% for t >

80 ms)

EOL 1 (Overload);

EOL 2 (Rectifier Effect);

Increment

Fault Counter

NOTE

Set Flag

Skip Preheat

to Set Flag Skip Preheat:

When using external Vcc

Supply, no reset of Set Flag

Skip Preheat. 1st Restart

without Preheating while

Vcc > UVLO. When LVS

deactivated or not from Line.

INVERTER and PFC Gate OFF

Only at Inverter Over current PFC Gate

OFF appr. 150µs Delayed

Power down Icc< 160µA

Gate drives off

Power down

Icc < 160µA

Wait 200ms

Delay Timer A

Wait 100ms

Delay Timer A

Increment

Counter Skip PH

Fault Counter

< 2

Y

N

Counter

Skip Preheat

>7?

Reset

Fault Counter

Y

N

Wait for

Lamp Removal

Start

Start-up

Gate drives off

IC remains

in active mode

Lamp removed

for min 100ms

Inverter Gates on

PFC Gate on

17.5V> Vcc >10.6V

f_Inv = f_START

NOTE

For external Vcc

Supply, set Vcc

below UVLO.

Lamp inserted &

Wait for

Lamp inserted

Lamp

inserted?

I_LVSSink> 12µA typ.

N

Y

Lamp inserted

for min 100ms

Wait for

UVLO

N

t > 80ms?

from Power-Up

N

V_BUS> 95%?

Reset

Flag Skip Preheat

& Counter Skip PH

Vcc > 14.0V?

Vcc < 10.6V?

Y

N

Fault A

Timeout 80ms

Start-up

Y

End

Start-up

Note:

Fault Counter reset

after 40s in Run Mode

Reset of Flag Skip

Power-up

Gate Drives off

UVLO

Reset all Latches

Preheat after Ignition

Figure 36 Operating Process during Start-Up Mode and Handling of Fault Conditions

Preliminary Data Sheet

39

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Protection Functions Matrix

4

Protection Functions Matrix

Table 3

Protection Functions Matrix

Characteristics of Fault

Operating Mode Detection Active

Consequence

Description of Fault

Supply voltage V_cc< 14.0 V Below start-

before power-up up threshold

S

F

1µs

5µs

X

Prevents power-up

Supply voltage V_cc< 10.6 V Below UVLO

after power-up threshold

X

Power-down, reset

failure latch

Current into LVS pin < 12µA Open

100µs

620µs

1µs

Prevents power-up

(typ.) before power-up

filament HS

Voltage at RES pin > 1.6 V Open

Prevents power-up

before power-up

filament LS

Voltage at RES pin > 3.2 V Open

Power down, latched

fault mode, 1 restart

filament LS

Bus voltage < 12.5% of rated Open loop

S

N

U

X

Keep Gate drives off, re-

start after V_cchysteresis

level 10 µs after power-up

detection

Bus voltage < 12.5 %

of rated level

Open loop

detection

1µs

X

Stops PFC FET until

V_BUS> 12.5%

Bus voltage < 12.5%

of rated level

Shut-down

option

625ms

84µs

Power down, restart

when V_BUS> 12.5%

Bus voltage < 75%

of rated level

Under-

voltage

Power down, 100ms

delay, restart, skip pre-

heating max 7 times

add. shut down delay 120µs

Bus voltage < 95% of rated Timeout max

level during start-up start-up time

A

S

N

U

F

80ms

5µs

X

Power down, 200ms

delay, restart

Bus voltage > 105% of rated Over-

level 10µs after power-up voltage

X

Keep Gate drives off, re-

start after Vcc hysteresis

Bus voltage > 109% of rated PFC

5µs

X

Stops PFC FET until

V_BUS< 105%

level in active operation

overvoltage

Bus voltage > 109% of rated Inverter

625ms

620µs

2500ms

620µs

Power down, restart

when V_BUS<105%

level in active operation

overvoltage

+/- peak level of lamp voltage EOL 1

at pin LVS above threshold overvoltage

Power down, latched

fault mode, 1 restart

DC level of lamp voltage

above +/- threshold

EOL 2

rect. effect

Power down, latched

fault mode, 1 restart

Capacitive load 1

Cap load 1

idling

Power down, latched

fault mode, 1 restart

Capacitive load 2,

Cap. load 2

Power down, latched

fault mode, 1 restart

operation below resonance overload

Preliminary Data Sheet

40

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Protection Functions Matrix

Table 3

Protection Functions Matrix (cont’d)

Characteristics of Fault

Operating Mode Detection Active

Consequence

Description of Fault

Run frequency cannot be

achieved

Timeout

ignition

F

N

F

A

237ms

200ns

500ns

X

Power down, latched

fault mode, 1 restart

Voltage at PFCCS pin > 1.0V PFC

overcurrent

X

Stops on-time of PFC

FET immediately

Voltage at LSCS pin > 0.8V Inverter

current lim

Activates ignition control

Voltage at LSCS pin > 0.8V Inverter

overcurrent

Power down, latched

fault mode, 1 restart

Voltage at LSCS pin > 1.6V Inverter

overcurrent

X

Power down, latched

fault mode, 1 restart

Inverter overcurrent

& VBUS > 109% (Surge)

Surge

Power-down, restart

when V_BUS< 109 %

After jump into latched fault mode F wait

Reset of failure latch in run mode after

200ms A single restart attempt after delay of internal timer

40s Reset of failure latch by UVLO or 40 s in run mode

S = Start-up condition, N = No fault, A = Auto restart , U = Undervoltage

F = Fault with a single restart; a second F leads to a latched fault

Note: All values @ typical 50 Hz mains frequency

Preliminary Data Sheet

41

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Electrical Characteristics

5

Electrical Characteristics

All voltages without the high side signals are measured with respect to ground (pin 4). The high side voltages are

measured with respect to pin 17. The voltage levels are valid if other ratings are not violated.

5.1

Absolute Maximum Ratings

Absolute maximum ratings are defined as ratings, which when exceeded may lead to destruction of the integrated

circuit. For the same reason, ensure that any capacitor to be connected to pin 3 (V_CC) or pin 15 (HSV_CC) is

discharged before assembling the application circuit.

Parameter

Symbol

Limit Values

Unit

Remarks

min.

–5

max.

LSCS Voltage

V_LSCS

6

3

V

mA

V

LSCS Current

I_LSCS

–3

LSGD Voltage

V_LSGD

–0.3

–75

–50

–0.3

–5

V_cc+0.3

5

Internally clamped to 11 V

LSGD Peak Source Current

LSGD Peak Sink Current

VCC Voltage

I_LSGDsomax

I_LSGDsimax

V_VCC

mA < 500 ns

400

18.0

5

mA < 100 ns

V

VCC Zener Clamp Current

PFCGD Voltage

PFCGD Peak Source Current

PFCGD Peak Sink Current

PFCCS Voltage

I_VCCzener

V_PFCGD

I_PFCGDsomax

I_PFCGDsimax

V_PFCCS

I_PFCCS

mA IC in Power Down Mode

–0.3

–150

–100

–5

V_cc+0.3

5

V

mA < 500 ns

700

6

mA < 100 ns

V

PFCCS Current

–3

3

mA

PFCZCD Voltage

PFCZCD Current

PFCVS Voltage

V_PFCZCD

I_PFCZCD

V_PFCVS

V_RFRUN

V_RFPH

–3

6

V

–5

5

mA

–0.3

–6

5.3

7

V

RFRUN Voltage

RFPH Voltage

V

RTPH Voltage

V_RTPH

V

RES Voltage

V_RES

V

LVS Voltage

V_LVS

V

LVS Current1

I_{LVS_1}

–1

1

mA IC in Power Down Mode

mA IC in active Mode

LVS Current2

I_{LVS_2}

–3

3

HSGND Voltage

HSGND Voltage Transient

HSVCC Voltage

HSGD Voltage

V_HSGND

dV_HSGND/dt

V_HSVCC

V_HSGD

–650

–40

–0.3

650

40

V

V/ns

V

Referring to GND¹⁾

18.0

Referring to HSGND

V_HSVCC

+

V

Internally clamped to 11V

0.3

HSGD Peak Source Current

HSGD Peak Sink Current

Junction Temperature

I_HSGDsomax

I_HSGDsimax

T_J

–75

0

mA < 500 ns

mA < 100 ns

°C

400

150

–25

Preliminary Data Sheet

42

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Electrical Characteristics

Parameter

Symbol

Limit Values

Unit

Remarks

min.

–55

–

max.

150

1

Storage Temperature

T_S

°C

W

Maximum Power Dissipation

P_TOT

PG_DSO-16-20

_amb=25°C

K/W PG_DSO-16-20

PCB area > 30mmx20mm

K/W PG_DSO-16-20

PCB area > 30mmx20mm

K/W PG_DSO-16-20

PCB area > 30mmx20mm

Wave Soldering²⁾

T

Thermal Resistance (2 Chips)

Thermal Resistance (HS Chip)

Thermal Resistance (LS Chip)

R_thJA

–

120

240

R_thJAHS

R_thJALS

Soldering Temperature Wave

Soldering Temperature Reflow

ESD Capability HBM

–

260

3)

°C

kV

V

Reflow Soldering

V_{ESD_HBM}

V_{ESD_CDM}

V_PFCVS95

–

2

1

Human Body Model⁴⁾

Charged Device Model⁵⁾

ESD Capability CDM

–

Rated Bus Voltage (95%)

2.33

2.43

1) Limitation due to voltage capability in end test

2) According to JESD22A111

3) According to J-STD-020D

4) According to EIA/JESD22-A114-B

5) According to JESD22-C101

Preliminary Data Sheet

43

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Electrical Characteristics

5.2

Operating Range

The IC operates as described in the functional description once the values listed here lie within the operating

range.

Parameter

Symbol

Limit Values

Unit

Remarks

min.

V_HSVCCOff

–650

V_VCCOff

–4

max.

17.5

650

17.5

18.0

5

HSVCC Supply Voltage

HSGND Voltage

V_HSVCC

V_HSGND

V_VCC

V

Referring to HSGND

Referring to GND¹⁾

T_J= 25°C

VCC Voltage @ 25°C

VCC Voltage @ 125°C

LSCS Voltage Range

PFCVS Voltage Range

PFCCS Voltage Range

PFZCD Current Range

LVS Voltage Range

V_VCC

T_J= 125°C

V_LSCS

V_PFCVS

V_PFCCS

I_PFCZCD

V_LVS

In active mode

0

4

–4

5

In active mode

–3

3

6²⁾

mA In active mode

V

–6

3)

LVS Current Range

I_LVS

210

2.5

150

0

µA

IC Power Down Mode

LVS Current Range

I_LVS

–2.5

F_RUN

–500

0

mA IC active mode

kHz

RFPH Frequency

F_RFPHrange

I_RFPH

RFPH Source Current Range

RTPH Voltage Range

Junction Temperature

Adjustable Preheating Freq.

Adjustable Run Frequency

Adjustable Preheating Time

Set Resistor for Run Feq.

Set Resistor for Preheat Feq.

Set Resistor for Preheat Time

Mains Frequency

µA

V

@ V_RFPH= 2.5 V

V_RTPH

T_j

2.5

125

150

120

2500

25

–25

F_RFRUN

20

°C

F_RFPH

F_RFRUN

t_RTPH

kHz Range set by RFPH

kHz Range set by RFRUN

0

ms

kꢀ

Hz

Range set by RTPH

R_RFRUN

R_RFPH

R_RTPH

f_Mains

4

–

R_RFRUNparallel to R_RFPH

NOTCH Filter Operation

0

25

45

65

1) Limitation due to creeping distance between the HS&LS Pins

2) Limited by Maximum of Current Range at LVS

3) Limited by Minimum of Voltage Range at LVS

Preliminary Data Sheet

44

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Electrical Characteristics

5.3

Characteristics

5.3.1

Power Supply Section

The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and

junction temperature range T_Jfrom –25 °C to +125 °C. Typical values represent the median values, which are

related to 25 °C. Unless otherwise stated, a supply voltage of 15V and V_HSVCC= 15 V is assumed and the IC

operates in active mode. Furthermore, all voltages refer to GND if not otherwise stated.

Parameter

Symbol

Limit Values

Unit

Test Conditions

min. typ. max.

VCC Quiescent Current1

VCC Quiescent Current2

VCC Supply Current ¹⁾

I_VCCqu1

–

90

120

4.2

110

130

160

6.0

µA

V_VCC= V_VCCOff– 0.5V

V_VCC= V_VCCOn– 0.5V

I_VCCqu2

I_VCCSupply

I_VCCLatch

mA V_PFCVS> 2.725V

VCC Supply Current in Latched

Fault Mode

170

µA

V_RES= 5V

LSVCC Turn-On Threshold

LSVCC Turn-Off Threshold

LSVCC Turn-On/Off Hyst.

V_VCCOn

V_VCCOff

V_VCCHys

13.5 14.0 14.5

10.0 10.6 11.0

V

Hysteresis

3.2

3.6

4.0

VCC Zener Clamp Voltage

VCC Zener Clamp Current

High Side Leakage Current

HSVCC Quiescent Current

HSVCC Quiescent Current¹⁾

V_VCCClamp

I_VCCZener

15.5 16.3 16.9

V

I_VCC= 2mA/V_RES= 5V

2.5

–

5

2

mA V_VCC= 17.5V/V_RES= 5V

I_HSGNDleak

0.01

190

0.65

µA

V_HSGND= 650V, V_GND=0V

V_HSVCC= V_HSVCCOn– 0.5V

2)

I_HSVCCqu1

–

270

1.2

2)

I_HSVCCqu2

0.3

mA V_HSVCC> V_HSVCCOn

2)

HSVCC Turn-On Threshold

HSVCC Turn-Off Threshold

HSVCC Turn-On/Off Hyst.

V_HSVCCOn

V_HSVCCOff

V_HSVCCHy

GND

9.9

8.1

1.4

10.4 11.0

V

Hysteresis

8.6

1.7

9.3

2.0

2)

Low Side Ground

1) With inactive gate

2) Referring to High Side Ground (HSGND)

Preliminary Data Sheet

45

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Electrical Characteristics

5.3.2

PFC Section

5.3.2.1

PFC Current Sense (PFCCS)

Parameter

Symbol

Limit Values

Unit

Test Conditions

min. typ. max.

Turn – Off Threshold

V_PFCCSOff

t_PFCCSOff

0.95

140

1.0

1.05

260

V

Over Current Blanking +

Propagation Delay¹⁾

200

ns

Leading Edge Blanking

t_Blanking

180

250

–

310

0.5

ns

Pulse width when V_PFCCS> 1.0 V

V_PFCCS= 1.5V

PFCCS Bias Current

I_PFCCSBias

–0.5

µA

1) Propagation delay = 50 ns

5.3.2.2

PFC Zero Current Detection (PFCZCD)

Parameter

Symbol

Limit Values

Unit

Test Conditions

min. typ. max.

Zero Crossing upper Thr.¹⁾

Zero Crossing lower Thr.²⁾

Zero Crossing Hysteresis

Clamping of pos. Voltages

Clamping of neg. Voltages

PFCZCD Bias Current

V_PFCZCDUp

V_PFCZCDLow

V_PFCZCDHys

V_PFCZCDpclp

V_PFCZCDnclp

I_PFCZCDBias

t_Ringsup

1.4

0.4

–

1.5

0.5

1.0

4.6

1.6

0.6

–

V

4.1

5.1

V

I_PFCZCDSink= 2mA

I_PFCZCDSource= –2mA

V_PFCZCD= 1.5V

–1.7 –1.4 –1.0

V

–0.5

350

500

–

5.0

0.5

µA

ns

pAxs

PFCZCD Bias Current

PFCZCD Ringing Su.³⁾Time

–

V_PFCZCD= 0.5V

500

700

650

900

Limit Value for ON Time

Extension

∆t x I_ZCD

1) Turn OFF threshold

2) Turn ON threshold

3) Ringing Suppression Time

Preliminary Data Sheet

46

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Electrical Characteristics

5.3.2.3

PFC Bus Voltage Sense (PFCVS)

Parameter

Symbol

Limit Values

Unit

Test Conditions

min. typ. max.

2.47 2.50 2.53

2.68 2.73 2.78

2.57 2.63 2.68

Trimmed Reference Voltage

Overvoltage turn Off (109%)

Overvoltage turn On (105%)

Overvoltage Hysteresis

Under voltage (75%)

V_PFCVSRef

V_PFCVSRUp

V_PFCVSLow

V_PFCVSHys

V_PFCVSUV

V_PFCVS95

I_PFCVSBias

V

± 1.2 %

70

100

130

mV 4 % rated bus voltage

1.835 1.88 1.915

0.237 0.31 0.387

2.325 2.38 2.425

V

Under voltage (12.5%)

Rated Bus Voltage (95%)

PFCVS Bias Current

–1.0

–

1.0

µA

V_PFCVS= 2.5V

5.3.2.4

PFC PWM Generation

Parameter

Symbol

Limit Values

Unit

Test Conditions

min. typ. max.

Initial ON – Time¹⁾

Max. ON – Time²⁾

t_{PFCON_initial}

t_{PFCON_max}

t_{PFCON_min}

–

4.0

–

µs

ns

V_PFCZCD= 0V

18.0 24.0 28.0

0.45V < VPFCVS < 2.45V

Switch Threshold from CritCM

into DCM

160

270

370

Repetition Time¹⁾

t_PFCRep

t_PFCOff

47

42

52

47

57

52

µs

V_PFCZCD= 0V

Off Time

1) When missing Zero Crossing Signal

2) At the maxima of the AC Line Input Voltage

Preliminary Data Sheet

47

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Electrical Characteristics

5.3.2.5

PFC gate Drive (PFCGD)

Parameter

Symbol

Limit Values

Unit

Test Conditions

min. typ. max.

PFCGD Low Voltage

PFCGD High Voltage

V_PFCGDLow

0.4

0.7

0.75

0.3

0.9

1.1

0.6

V

I_PFCGD= 5mA

I

_PFCGD= 20mA

_PFCGD= -20mA

–0.2

V

I

V_PFCGDHigh

10.0 11.0 11.6

V

I_PFCGD= -20mA

_PFCGD= -1mA / V_VCC

I_PFCGD= -5mA / V_VCC

1)

9.0

8.5

0.4

0.3

–

V

I

–

V

PFCGD active Shut Down

PFCGD UVLO Shut Down

PFCGD Peak Source Current

PFCGD Peak Sink Current

V_PFCGASD

V_PFCGDuvlo

I_PFCGDSouce

I_PFCGDSink

V_PFCGDHigh

0.75

1.0

1.1

1.5

–

V

I_PFCGD= 20mA V_VCC=5V

I_PFCGD= 5mA V_VCC=2V

V

2)

3)

–100

500

mA

V

+

2)

3)

–

PFCGD Voltage during sink

Current

11.0 11.7 12.3

I_PFCGDSinkH= 3mA

PFC Rise Time

V_PFCGDRise

V_PFCGDFall

105

20

245

45

405

70

ns

2V > V_LSGD> 8V ²⁾

8V > V_LSGD> 2V ²⁾

PFC Fall Time

1) V_VCC= V_VCCOff+ 0.3 V

2) R_Load= 4ꢀ and C_Load= 3.3 nF

3) The parameter is not subject to a production test – verified by design / characterization

Preliminary Data Sheet

48

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Electrical Characteristics

5.3.3

Inverter Section

5.3.3.1

Low Side Current Sense (LSCS)

Parameter

Symbol

Limit Values

min. typ. max.

Unit

Test Conditions

1)

2)

Overcurrent Shut Down Volt.

Duration of Overcurrent

V_LSCSOvC1

V_LSCSOvC2

t_LSCSOvC

1.5

0.75

450

30

1.6

0.8

600

50

1.7

0.85

700

73

V

ns

Capacitive Mode Det. Level 1

Capacitive Mode Duration 1

Capacitive Mode Det. Level 2

Capacitive Mode Duration 2

Capacitive Mode Det. Level 3

Capacitive Mode Duration 3

LSCS Bias Current

V_LSCSCap1

t_LSCSCap1

V_LSCSCap2

t_LSCSCap2

V_LSCSCap3

t_LSCSCap3

I_LSCSBias

mV During Run Mode

3)

–

280

2.0

50

–

ns

1.8

–

2.2

–

V

ns

During Run Mode

4)

–70

–

-50

280

–

-27

–

mV

ns

5)

–1.0

1.0

µA

@ V_LSCS= 1.5V

1) Overcurrent Voltage Threshold active during: Start Up, Soft start, Ignition and pre-run Mode

2) Overcurrent Voltage Threshold active during: Preheating and Run Mode

3) During 2nd 50% Duty Cycle of LSGD in Run Mode

4) Active during Turn ON of the HSGD in Run Mode

5) Active before Turn ON of the HSGD in Run Mode

Preliminary Data Sheet

49

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Electrical Characteristics

5.3.3.2

Low Side Gate Drive (LSGD)

Parameter

Symbol

Limit Values

Unit

Test Conditions

I_LSGD= 5mA¹⁾

min. typ. max.

LSGD Low Voltage

LSGD High Voltage

V_LSGDLow

0.4

0.7

0.8

0.2

1.0

1.2

0.5

V

I_LSGD= 20mA¹⁾

–0.3

V

I_LSGD= - 20mA (Source)

2)

V_LSGDHigh

10.0 10.8 11.6

V

3)

4)

9.0

8.5

0.4

0.3

–

V

–

V

LSGD active Shut Down

LSGD UVLO Shut Down

LSGD Peak Source Current

LSGD Peak Sink Current

LSGD Voltage during ¹⁾

LSGD Rise Time

V_LSGDASD

V_LSGDUVLO

I_LSGDSource

I_LSGDSink

0.75

1.0

–50

300

11.7

245

35

1.1

1.5

–

V

V_CC=5V / I_LSGD= 20mA¹⁾

V_CC=2V / I_LSGD= 5mA¹⁾

V

5)

6)

mA

V

+

5)

6)

–

V_LSGDHigh

t_LSGDRise

t_LSGDFall

–

I_LSGDsinkH= 3mA

2V < V_LSGD< 8V⁵⁾

8V > V_LSGD> 2V⁵⁾

105

20

405

60

ns

LSGD Fall Time

1) Sink Current

2) I_LSGD= - 20mA Source Current

3) V_CCOFF+ 0.3V and ILSGD = - 1mA Source Current

4) V_CCOFF+ 0.3V and ILSGD = - 5mA Source Current

5) Load: R_Load= 10ꢀ and C_Load= 1nF

6) The parameter is not subject to a production test – verified by design / characterization

5.3.3.3

Inverter Control Run (RFRUN)

Parameter

Symbol

Limit Values

Unit

Test Conditions

min.

typ.

max.

Fixed Start – Up Frequency

Duration of Soft Start

F_StartUp

121.5 135 148.5

kHz

ms

V

1)

t_SoftStart

9

–

11

2.5

50

13.5

–

RFRUN Voltage in Run Mode

Run Frequency

V_RFRUN

F_RFRUN

F_RFRUN1

F_RFRUN2

F_RFRUN3

I_RFRUNmax

@ 100µA<I_RFRUN<600µA

49

–

51

–

kHz R_RFRUN= 10kꢀ

kHz I_RFRUN= – 100 µA

kHz I_RFRUN= – 200 µA

kHz I_RFRUN= – 500 µA

Adjustable Run Frequency

20

–

40

–

100

–

RFRUN max. Current Range

–

–1000 – 650

µA

@ V_RFRUN= 0V

1) Shift Start Up Frequency to Preheating Frequency

Preliminary Data Sheet

50

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Electrical Characteristics

5.3.3.4

Inverter Control Preheating (RFPH, RTPH)

Parameter

Symbol

Limit Values

Unit

Test Conditions

min. typ. max.

RFPH Voltage Preheating

Preheating Frequency

RFPH max. Current Range

Current for set Preh. Time

Preheating Time

V_RFPH

–

97

–

2.5

–

V

V_RFPH= 0V in Run Mode

F_RFPH1

I_RFPHmax

I_RTPH

100

103

kHz R_RFPH= R_RFRUN= 10kꢀ

–1000 – 550

–100

µA

ms

@ V_RFPH= 0V

–

t_RTPH1

t_RTPH2

t_RTPH3

t_RTPH4

t_RTPH5

950 1000 1050

R_RTPH1= 10kꢀ

R_RTPH2= 1kꢀ

R_RTPH3= 5kꢀ

R_RTPH4= 20kꢀ

R_RTPH5= 25kꢀ

50

–

100

500

150

–

2000

2500

–

5.3.3.5

Restart after Lamp Removal (RES)

Parameter

Symbol

Limit Values

min. typ. max.

Unit

Test Conditions

High Side Filament In Det.

V_RES1

1.55

1.25

–

1.60

1.30

3.2

1.65

1.35

–

V

U_VLO, V_CC< V_CCON

V_RES2

V_RES3

I_RES1

I_RES2

I_RES3

I_RES4

V

Run Mode

RES Current Source

–53.2 –42.6 –32.0

–44.2 –35.4 –26.6

–26.6 –21.3 – 16.0

–22.1 –17.7 –13.3

µA

V_RES= 1V ;LVS = 5µA

V_RES= 2V ;LVS = 5µA

V_RES= 1V ;LVS = 30µA

V_RES= 2V ;LVS = 30µA

Preliminary Data Sheet

51

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Electrical Characteristics

5.3.3.6

Lamp Voltage Sense (LVS)

Parameter

Symbol

Limit Values

Unit

Test Conditions

min. typ. max.

–5.0 –3.0 –2.0

Source Current before Startup

Enable Lamp Monitoring

Sink Current for Lamp Det.

Positive Clamping Voltage

AC EOLCurrent Threshold

Positive EOL Current Thr.

Negative EOL Current Thr.

I_LVSSource

V_LVSEnable1

I_LVSSink

µA

mV

µA

V

V_LVS= 0V

1)

350

8.0

–

530

750

12.0 18.0

V_LVS> V_LVSClamp

@ I_LVS= 300µA

V_LVSClamp

I_LVSSourceAC

I_LVSDCPos

I_LVSDCNeg

6.5

210

42

–

190

34

230

50

µApp I_LVS> I_LVSEOLppEOL 1

µA

I_LVS> I_LVSDCPosEOL 2

I_LVS> I_LVSDCNegEOL 2

–50

–42

–34

1) If V_LVS< V_LVSEnable1monitoring is disabled

5.3.3.7

High Side Gate Drive (HSGD)

Parameter

Symbol

Limit Values

Unit

Test Conditions

min. typ. max.

HSGD Low Voltage

HSGD High Voltage

V_HSGDLow

0.02 0.05

0.5 1.1

0.1

2.5

V

I_HSGD= 5mA (sink)

I_HSGD= 100mA (sink)

–0.4 –0.2 –0.05

I_LSGD= - 20mA (source)

V_HSGDHigh

9.7

10.5 11.2

V_CCHS=15V

_HSGD= - 20mA (source)

_CCHSOFF+ 0.3V

_HSGD= - 1mA (source)

I

7.8

–

V

I

HSGD active Shut Down

V_HSGDASD

0.05 0.22

0.5

V_CCHS=5V

I_HSGD= 20mA (sink)

HSGD Peak Source Current

HSGD Peak Sink Current

HSGD Rise Time

I_HSGDSource

I_HSGDSink

–

–50

300

220

–

mA R_Load= 10ꢀ+C_Load= 1nF¹⁾

T_HSGDRise

140

300

ns

2V < V_LSGD< 8V

_Load= 10ꢀ+C_Load= 1nF

8V > V_LSGD> 2V

_Load= 10ꢀ+C_Load= 1nF

1) The parameter is not subject to a production test – verified by design / characterization

R

HSGD Fall Time

T_HSGDFall

20

35

70

ns

R

Preliminary Data Sheet

52

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Electrical Characteristics

5.3.3.8

Timer Section

Delay Timer 1

t_TIMER1

t_TIMER2

t_Inv

70

74

100

84

160 ms

94 ms

160 µs

2.40 µs

1.3 µs

200 ns

48 ms

236 ms

685 ms

For lamp detection

For V_BUS> 95%

Delay Timer 2

Inverter Time

100

1.75

0.8

130

2.1

1.05

–

Inverter Dead Time Max

Inverter Dead Time Min

∆ Inverter Dead Time Max

∆ Inverter Dead Time Min

Min. Duration of Ignition

Max. Duration of Ignition

Duration of Pre – Run

t_DeadMax

t_DeadMin

t_DeadMax

t_DeadMin

t_Ignition

–200

34

–

40

t_NOIgnition

t_PRERUN

197

565

–

625

5.3.3.9

Built-In Customer Test Mode

Voltage at RTPH Pin

Voltage at LVS

V_RTPH

V_LVS

0

V

V¹⁾

Preheating time = 0 ms (skipped preheating)

IC remains in Preheating

5.0

0

V

Disables Lamp Voltage Sense

Disable the Filament Detection

Voltage at RES Pin

V_RES

0

V

Voltage at RFPH Pin

Voltage at RFRUN Pin

Voltage at VCC Pin

Voltage at RES Pin

V_RFPH

V_RFRUN

V_CC

5.0

V¹⁾

Built-in Customer Test Mode - Clock

Acceleration. Decreasing time for the following

procedures: Preheating by factor 4

Timeout ignition by factor 2

> 14.0 V

V_RES

0

V

Pre-run by factor 15; EOL by 60

1) Tolerance for this voltage is ± 5%

Preliminary Data Sheet

53

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Application Example

6

Application Example

6.1

Schematic Ballast 54W T5 Single Lamp

Figure 37 Application Circuit of Ballast for Single Fluorescent Lamp Voltage Mode Preheating

Preliminary Data Sheet

54

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Application Example

6.2

Bill of Material

Figure 38 Bill of Material

Preliminary Data Sheet

55

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Application Example

6.3

Multi Lamp Ballast Topologies (Series Connection)

PFCZCD

PFCGD

90 ...

270 VAC

HSGD

HSVCC

HSGND

PFCVS

PFCCS

LSGD

LSCS

Figure 39 Application Circuit of Ballast for two Fluorescent Lamps Voltage Mode Preheating

Preliminary Data Sheet

56

V1.1, 2012-04-10

ICB2FL03G

Controller for Fluorescent Lamp Ballasts

Package Outline

7

Package Outline

7.1

Outline Dimensions of PG-DSO-16

Figure 40 Package Outline with Creepage Distance

Preliminary Data Sheet

57

V1.1, 2012-04-10

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	ICB2FL03G
厂家：	Infineon
描述：	Power Factor And Fluorescent Light Controller,
文件：	总58页 (文件大小：2687K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICB2FL03G [INFINEON]

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