ICE5QSBG [INFINEON]
英飞凌第五代准谐振反激式 PWM 控制器性能强大,具有全面的保护组合,有效提高了系统稳健性。;型号: | ICE5QSBG |
厂家: | Infineon |
描述: | 英飞凌第五代准谐振反激式 PWM 控制器性能强大,具有全面的保护组合,有效提高了系统稳健性。 控制器 |
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ICE5QSBG
Quasi-Resonant Controller
Product Highlights
Novel Quasi-resonant operation and proprietary implementation for low EMI
Enhanced Active Burst Mode with selectable entry and exit standby power
Active Burst Mode to reach the lowest standby power <100 mW
Fast startup achieved with cascode configuration
PG-DSO-8
Digital frequency reduction for better overall system efficiency
Robust line protection with input OVP and brownout
Comprehensive protection
Pb-free lead plating, halogen free mold compound, RoHS compliant
Features
Applications
Minimum switching frequency difference between low & high
line for higher efficiency & better EMI
Auxiliary power supply for Home Appliances/white Goods, TV,
PC & Server
Enhanced Active Burst Mode with selectable entry and exit
standby power
Blu-ray player, Set-top box & LCD/LED Monitor
Description
Active Burst Mode to reach the lowest standby power <100 mW
Fast startup achieved with cascode configuration
Digital frequency reduction up to 10 zero crossings
Built-in digital soft start
The Quasi-Resonant, ICE5QSBG is the 5th generation of quasi-
resonant controller optimized for off-line switch power supply in
cascode configuration. The improved digital frequency reduction
with proprietary novel Quasi-Resonant operation offers lower EMI
and higher efficiency for wide AC range by reducing the switching
frequency difference between low and high line. The enhanced
active burst mode enables flexibility in standby power range
selection. The product has a wide operating range (10~25.5 V) of
IC power supply and lower power consumption. The numerous
protection functions including the robust line protection (both
input OVP and brownout) to support the protections of the power
supply system in failure situations. All of these make the
ICE5QSBG an outstanding controller for Quasi-Resonant flyback
converter in the market.
Cycle-by-cycle peak current limitation
Maximum on/off time limitation to avoid audible noise during
start up and power down
Robust line protection with input OVP and brownout
Auto restart mode protection for VCC Over Voltage, VCC Under
Voltage, Over load/Open Loop, Output Over Voltage, Over
Temperature
Limited charging current for VCC short to GND
Pb-free lead plating, halogen free mold compound, RoHS
compliant
Wp
Wa
Lf1
DO1
Ws1
RSTARTUP
RVCC DVCC
Cbus
VO1
Snubber
Cf1
Cf2
CO1
85 ~ 300 VAC
CVCC
Lf2
DO2
Ws2
VO2
CO2
DZC
CZC
RZC
Dr1~Dr4
VCC ZCD
RI1
VIN
RI2
D
Power
MOSFET
CPS
Power Management
RZCD
GATE
PWM controller
Current Mode Control
# Rovs3
Rb1
Rb2
Rovs1
Cycle-by-Cycle
current limitation
SOURCE
Gate
Driver
GND
Digital Control
CS
FB
Rc1
Active Burst Mode
Zero Crossing
Detection
ICE5QSBG
Controller
# Optional
RSel (Burst mode level 2)
Cc1 Cc2
Rovs2
RCS
Optocoupler
TL431
Protections
Rovs3 (V02 feedback)
Figure 1
Table 1
Typical application
Output Power of 5th generation Quasi-Resonant Controller
1
Package
Marking
220VAC ±20%1
85-300 VAC
Type
ICE5QSBG
PG-DSO-8
5QSBG
109 W
60 W
1
Calculated maximum output power rating in an open frame design at Ta=50°C, TJ=125°C. The output power figure is for reference
purpose only. The actual power can vary depending on particular designs. Please contact to a technical expert from Infineon for more
information.
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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Quasi-Resonant Controller
Table of Contents
Table of Contents
Product Highlights.......................................................................................................................... 1
Features ........................................................................................................................................ 1
Applications................................................................................................................................... 1
Description .................................................................................................................................... 1
Table of Contents ........................................................................................................................... 2
1
2
Pin Configuration and Functionality......................................................................................... 4
Representative Block Diagram................................................................................................. 5
3
Functional Description............................................................................................................ 6
VCC Pre-Charging and Typical VCC Voltage during Start-up.....................................................................6
Soft-start..................................................................................................................................................6
Normal Operation ...................................................................................................................................7
Digital Frequency Reduction .............................................................................................................7
3.1
3.2
3.3
3.3.1
3.3.1.1
3.3.1.2
3.3.1.3
3.3.2
3.3.2.1
3.3.3
3.3.4
3.4
Minimum ZC Count Determination ..............................................................................................7
Up/down counter..........................................................................................................................7
Zero crossing (ZC counter) ...........................................................................................................8
Ringing suppression time ..................................................................................................................9
Switch on determination..............................................................................................................9
Switch off determination...................................................................................................................9
Modulated gate drive .......................................................................................................................10
Current limitation..................................................................................................................................10
Active Burst Mode with selectable power level....................................................................................11
Entering Active Burst Mode Operation............................................................................................12
During Active Burst Mode Operation...............................................................................................12
Leaving Active Burst Mode Operation .............................................................................................12
Protection Functions.............................................................................................................................13
Line Over Voltage .............................................................................................................................14
Brownout..........................................................................................................................................14
VCC Ovder Voltage or Under Voltage.................................................................................................14
Over Load .........................................................................................................................................14
Output Over Voltage ........................................................................................................................14
Over Temperature............................................................................................................................14
3.5
3.5.1
3.5.2
3.5.3
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
4
Electrical Characteristics .......................................................................................................17
Absolute Maximum Ratings ..................................................................................................................17
Operating Range....................................................................................................................................17
Operating Conditions............................................................................................................................18
Internal Voltage Reference....................................................................................................................18
Gate Driver.............................................................................................................................................18
PWM Section..........................................................................................................................................19
Current Sense ........................................................................................................................................19
Soft Start................................................................................................................................................19
Digital Zero Crossing .............................................................................................................................20
Active Burst Mode..................................................................................................................................20
Line Over Voltage Protection ................................................................................................................21
Brownout Protection.............................................................................................................................21
VCC Over Voltage Protection ..................................................................................................................21
Over Load Protection ............................................................................................................................21
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
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Table of Contents
4.15
4.16
4.17
Output Over Voltage Protection ...........................................................................................................22
Thermal Protection ...............................................................................................................................22
Low side MOSFET ..................................................................................................................................22
5
6
7
Output power curve ..............................................................................................................23
Outline Dimension.................................................................................................................24
Marking................................................................................................................................25
Revision history.............................................................................................................................26
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Pin Configuration and Functionality
1
Pin Configuration and Functionality
The pin configuration is shown in Figure 2 and the functions are described in Table 2.
PG-DSO-8
FB
VIN
CS
1
8
7
6
5
GND
2
VCC
3
4
SOURCE
GATE
ZCD
Figure 2
Pin Configuration
Pin Definitions and Functions
Table 2
Pin
Symbol
Function
Feedback & Burst entry/exit control
1
FB
FB pin combines the functions of feedback control, selectable burst entry/exit control
and overload/open loop protection.
Input Line OVP & Brownout
2
3
4
VIN
CS
VIN pin is connected to the bus via resistor divider (see Figure 1) to sense the line
voltage. This pin combines the functions of input Line OVP, Brownout, minimum
and maximum ZC count setting for low and high line.
Current Sense
The CS pin is connected to the shunt resistor for the primary current sensing
externally and to the PWM signal generator block for switch-off determination
(together with the feedback voltage) internally.
Zero Crossing Detection
ZCD
ZCD pin combines the functions of start up, zero crossing detection and output
over voltage protection. During the start up, it is used to provide a voltage level to
the gate of power switch Power MOSFET (see Figure 1) to charge VCC capacitor.
5
6
GATE
Gate Drive Output
This output signal drives the external main Power MOSFET (see Figure 1).
SOURCE
SOURCE
The SOURCE pin is connected to the source of external power switch Power
MOSFET (see Figure 1) which is in series connection with internal low side MOSFET
and internal VCC diode D3.
VCC(Positive Voltage Supply)
The VCC pin is the positive voltage supply to the IC. The operating range is
7
8
VCC
between VVCC_OFF and VVCC_OVP
.
Ground
GND
The GND pin is the common ground of the controller.
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Representative Block Diagram
2
Representative Block Diagram
VCC
ZCD
LOVP
Brown In / Out
Thermal Protection
250 µs
Blanking
time
50 µs
Blanking
time
VVIN_LOVP
250 µs
Blanking
time
VVIN_BO
C16a
OTP
Mode
Tj > Tjcon_OTP
Brown
Out
S
R
Q
C7a
Input
OVP
S
R
Q
S
R
Q
Mode
VIN
Mode
Autorestart
Protect
C16b
Tj < Tjcon_OTP-TjHYS_OTP
VVIN_BI
Autorestart
Protect
Autorestart
Protect
Power Management
Zero Crossing
ZC counter
VZCD_CT
D3
Internal
Bias
Undervoltage Lockout
16V
clk
C2
Voltage
Reference
10V
D1
&
G1
Protection
Comparator
S
R
Q
C12
50us
1
VVCC_OVP
Up/down counter
G7
Autorestart
Protect
RZCD
tVIN_REF
C8
VVIN_REF
S
Q
PWM Control
Counter
tCOUNT
Soft-start
1
R
G2
C6
Autorestart
Protect
Counter
PZCD_OVP_B
VZCD_OVP
C1
Ringing
Suppression
VZCD_RS
TOffMax
&
G9
Gate
Drive
&
1
GATE
C12
C5
tFB_OLP_B
VREF
VFB_OLP
VFB_LB
/
G5
G4
S
R
G8
Q
&
G6
1
SOURCE
RFB
Burst
Mode
detect
VFB_R
G3
TOnMax
Gate
Drive
fSB
enOSC
C3
VFB_HLC
Gate Driver
VCS_N
VCS_BL1
VCS_BL2
C4
FB
C13
C15
VFB_LHC
Regulation
Peak
Current
Limit
Burst Mode
Level Select
VCS_FB
Leading
Edge
Blanking
tCS_LEB
VFB_EBL1
VFB_EBL2
10kΩ
CS
VPWM
V1
C9
tFB_BEB
Active
Burst Mode
1pF
D2
GPWM
2pF
C20
PWM OP
C10
VFB_BOn
PWM
Comparator
Current Mode
Delay
tCS_STG_SAM
GND
C17
C11
VFB_BOff
VCS_STG
Current Limiting/ Current Sense short to Gnd Protection
Active Burst Block
Figure 3
Representative Block Diagram
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Functional Description
3
Functional Description
3.1
VCC Pre-Charging and Typical VCC Voltage during Start-up
As shown in Figure 1, once the line input voltage is applied, a rectified voltage appears across the capacitor
CBUS. The pull up resistor RSTARTUP provides a current to charge the Ciss (input capacitance) of CoolMOS™ and
gradually generate one voltage level. If the voltage over Ciss is high enough, CoolMOS™ on and VCC capacitor will
be charged through primary inductance of transformer LP, CoolMOS™ and internal diode D3 with two steps
1
constant current source IVCC_ Charge11 and IVCC_ Charge3
.
A very small constant current source (IVCC_Charge1) is charged to the VCC capacitor till VCC reach VCC_SCP to protect the
controller from VCC pin short to ground during the start up. After this, the second step constant current source
(IVCC_Charge3) is provided to charge the VCC capacitor further, until the VCC voltage exceeds the turned-on threshold
VVCC_ON. As shown in the time phase I in Figure 4, the VCC voltage increase almost linearly with two steps.
VVCC
I
II
III
(VVCC_ON )16V
(VVCC_OFF) 10V
tA
tB
(VVCC_SCP) 1.1V
IVCC
t
t
(IVCC_Normal) 0.9mA
0
(IVCC_Charge1) -0.2mA
t1
t2
IVCC_Charge2/3) -3/-3.2mA
-IVCC
Figure 4
VCC voltage and current at start up
The time taking for the VCC pre-charging can then be approximately calculated as:
푉ꢀ퐶퐶_푆퐶푃 ∙ ꢁꢀ퐶퐶 (푉ꢀ퐶퐶_푂푁 − 푉ꢀ퐶퐶_푆퐶푃) ∙ ꢁꢀ퐶퐶
(1)
푡1 = 푡A + 푡B =
+
퐼ꢀ퐶퐶_퐶ℎ푎푟ꢂ푒1
퐼ꢀ퐶퐶_퐶ℎ푎푟ꢂ푒3
When the VCC voltage exceeds the VCC turned on threshold VVCC_ON at time t1, the IC begins to operate with soft
start. Due to power consumption of the IC and the fact that there is still no energy from the auxiliary winding to
charge the VCC capacitor before the output voltage is built up, the VCC voltage drops (Phase II). Once the output
voltage is high enough, the VCC capacitor receives the energy from the auxiliary winding from the time t2 onward
and delivering the IVCC_ Normal2 to the controller. The VCC then will reach a constant value depending on output
load.
3.2
Soft-start
As shown in Figure 5, at the time ton, the IC begins to operate with a soft-start. By this soft-start the switching
stresses for the MOSFET, diode and transformer are minimized. The soft-start implemented in ICE5QSBG is a
digital time-based function. The preset soft-start time is tSS (12 ms) with 4 steps. If not limited by other
functions, the peak voltage on CS pin will increase step by step from 0.3 V to 1 V finally. During the first 3 ms of
1 IVCC_ Charge1/2/3 is charging current from the controller to VCC capacitor during start up
2 IVCC_ Normal is supply current from VCC capacitor or auxiliary winding to the controller during normal operation
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Functional Description
soft start, the ringing suppression time is set to 25 µsto avoid irregular switching due to switch off oscillation
noise.
Vcs (V)
VCS_Peak
0.75
0.60
0.45
0.30
ton
3
6
9
12
Time(ms)
Figure 5
Maximum current sense voltage during soft start
3.3
Normal Operation
During normal operation, the ICE5QSBG works with a digital signal processing circuit composing an up/down
counter, a zero-crossing counter (ZC counter) and a comparator, and an analog circuit composing a current
measurement unit and a comparator. The switch-on and -off time points are each determined by the digital
circuit and the analog circuit, respectively. The input information of the zero-crossing signal and the value of
the up/down counter are needed to determine the switch-on while the feedback signal VFB and the current
sensing signal VCS are necessary for the switch-off determination.
Details about the full operation of the controller in normal operation are illustrated in the following
paragraphs.
3.3.1
Digital Frequency Reduction
As mentioned above, the digital signal processing circuit consists of an up/down counter, a ZC counter and a
comparator. These three parts are the key to implement digital frequency reduction with decreasing load. In
addition, a ringing suppression time controller is implemented to avoid mis-triggering by the high frequency
oscillation, when the output voltage is very low under conditions such as soft start period or output short
circuit. Functionality of these parts is described as in the following.
3.3.1.1
Minimum ZC Count Determination
To reduce the switching frequency difference between low and high line, minimum ZC count determination is
implemented. Minimum ZC count is set to 1 if VIN less than VVIN_REF which represents for low line. For high line,
minimum ZC count is set to 3 after VIN higher than VVIN_REF. There is also a hysteresis VVIN_REF with certain blanking
time tVIN_REF for stable AC line selection between low and high line.
3.3.1.2
Up/down counter
The up/down counter stores the number of the zero crossing which determines valley numbers to switch-on
the main MOSFET after demagnetization of the transformer. This value is fixed according to the feedback
voltage, VFB, which contains information about the output power. Indeed, in a typical peak current mode
control, a high output power results in a high feedback voltage, and a low output power leads to a low
feedback voltage. Hence, according to VFB, the value in the up/down counter is changed to vary the Power
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Functional Description
MOSFET off-time according to the output power. In the following, the variation of the up/down counter value
according to the feedback voltage is explained.
The feedback voltage VFB is internally compared with three threshold voltages VFB_LHC, VFB_HLC and VFB_R at each
clock period of 48 ms. The up/down counter counts then upward, keep unchanged or count downward, as
shown in 0.
Table 3
VFB
Operation of up/down counter
up/down counter action
Always lower than VFB_LHC
Count upwards till n=8/101
Stop counting, no value changing
Count downwards till n=1/32
Set up/down counter to n=1/32
Once higher than VF_LHC, but always lower than VFB_HLC
Once higher than VFB_HLC, but always lower than VFB_R
Once higher than VFB_R
The number of zero crossing is limited and therefore, the counter varies among 1 to 8 (for low line) or 3 to 10
(for high line) and any attempt beyond this range is ignored. When VFB exceeds VFB_R voltage, the up/down
counter is reset to 1 (low line) and 3 (high line) in order to allow the system to react rapidly to a sudden load
increase. The up/down counter value is also reset to 1 (low line) and 3 (high line) at the start-up time, to ensure
an efficient maximum load start up. Figure 6 shows some examples on how up/down counter is changed
according to the feedback voltage over time.
The use of two different thresholds VFB_LHC and VFB_HLC to count upward or downward is to prevent frequency
jittering when the feedback voltage is close to the threshold point.
clock
T=48ms
clock
T=48ms
t
t
t
t
VFB
VFB,R1
VFB
VFB,R3
VFB,HLC
VFB,LHC
VFB,HLC
VFB,LHC
Up/down
Up/down
counter
counter
1
1
1
1
3
3
3
3
Case 1
Case 2
Case 3
5
2
8
6
3
8
7
4
8
8
5
8
8
5
8
8
5
8
7
6
3
6
5
2
5
Case 1
Case 2
6
4
7
5
8
6
9
7
9
7
9
8
7
5
8
6
4
7
4
7
7
6
9
Case 3 10 10 10 10 10 10
low line
Up/down counter operation
High line
Figure 6
3.3.1.3
Zero crossing (ZC counter)
In the system, the voltage from the auxiliary winding is applied to the ZCD pin through a RC network, which
provides a time delay to the voltage from the auxiliary winding. Internally this pin is connected to a clamping
network, a zero-crossing detector, an output overvoltage detector and a ringing suppression time controller.
During on-state of the power switch, a positive gate drive voltage is applied to the ZCD pin due to RZCD resistor,
hence external diode DZC (see Figure 1) is added to block the negative voltage from the auxiliary winding. The ZC
counter has a minimum value of 1 (for low line) or 3 (for high line) and maximum value of 8 (for low line) or 10
1 n=8 (for low line) and n=10 (for high line)
2 n=1 (for low line) and n=3 (for high line)
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Functional Description
(for high line). After the Power MOSFET (see Figure 1) is turned off, every time when the falling voltage ramp of
on ZCD pin crosses the VZCD_CT threshold, a zero crossing is detected and ZC counter will increase by 1. It is reset
every time after the DRIVER output is changed to high.
To achieve the switch on at voltage valley, the voltage from the auxiliary winding is fed to a time delay network
(the RC network consists of RZC and CZC as shown in Figure 1) before it is applied to the zero-crossing detector
through the ZCD pin. The needed time delay to the main oscillation signal Δt should be approximately one
fourth of the oscillation period, TOSC (by transformer primary inductor and drain-source capacitor) minus the
propagation delay from the detected zero-crossing to the switch-on of the main switch tdelay, theoretically:
푇푂푆퐶
(2)
Δt =
− 푡푑푒푙푎푦
4
This time delay should be matched by adjusting the time constant of the RC network which is calculated as:
푅푍퐶∙푅푍퐶퐷
휏ꢃd = ꢁ푍퐶.
(3)
푅푍퐶+푅푍퐶퐷
3.3.2
Ringing suppression time
After Power MOSFET (see Figure 1) is turned off, there will be some oscillation on VDS, which will also appear on
the VZCD. To avoid mis-triggering by such oscillations to turn on the Power MOSFET, a ringing suppression timer
is implemented. This suppression time is depended on the voltage VZCD. If the voltage VZCD is lower than the
threshold VZCD_RS, a longer preset time tZCD_RS2 is applied. However, if the voltage VZCD is higher than the threshold,
a shorter time tZCD_RS1 is set.
3.3.2.1
Switch on determination
After the gate drive goes to low, it cannot be changed to high during ring suppression time.
After ring suppression time, the gate drive can be turned on when the ZC counter value is equal to up/down
counter value.
However, it is also possible that the oscillation between primary inductor and drain-source capacitor damps
very fast and IC cannot detect zero crossings event. In this case, a maximum off time is implemented. After gate
drive has been remained off for the period of TOffMax, the gate drive will be turned on again regardless of the ZC
counter values and VZCD. This function can effectively prevent the switching frequency from going lower than 20
kHz. Otherwise it will cause audible noise.
3.3.3
Switch off determination
In the converter system, the primary current is sensed by an external shunt resistor, which is connected
between source terminal of the internal MOSFET and the common ground. The sensed voltage across the shunt
resistor VCS is applied to an internal current measurement unit, and its output voltage V1 is compared with the
feedback voltage VFB. Once the voltage V1 exceeds the voltage VFB, the output flip-flop is reset. As a result, the
main power switch is switched off. The relationship between the V1 and the VCS is described by (see Figure 3):
푉CS = 퐼D × 푅CS
(4)
푉 = 퐺푃푊푀 ∙ 푉퐶푆 + 푉푃푊푀
1
where, VCS
: CS pin voltage
ID
: power MOSFET current
RCS
V1
: resistance of the current sense resistor
: voltage level compared to VFB
GPWM : PWM-OP gain
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Functional Description
To avoid mis-triggering caused by the voltage spike across the shunt resistor at the turn on of the main power
switch, a leading edge blanking time, tLEB, is applied to the output of the comparator. In other words, once the
gate drive is turned on, the minimum on time of the gate drive is the leading edge blanking time.
In addition, there is a maximum on time, tOnMax, limitation implemented in the IC. Once the gate drive has been
in high state longer than the maximum ON time, it will be turned off to prevent the switching frequency from
going too low because of long on time.
In addition, there is a maximum on time, tOnMax, limitation implemented in the IC. Once the gate drive has been
in high state longer than the maximum on time, it will be turned off to prevent the switching frequency from
going too low because of long on time.
Also, if the voltage at the current sense pin is lower than the preset threshold VCS_STG after the time tCS_STG_SAM for
three consecutive pulses during on-time of the power switch, this abnormal VCS will trigger IC into auto restart
mode.
3.3.4
Modulated gate drive
The drive-stage is optimized for EMI consideration. The switch on speed is slowed down before it reaches the
Power MOSFET turn on threshold. That is a slope control of the rising edge at the output of driver (see Figure 7).
Thus the leading switch spike during turn on is minimized.
VGATE (V)
VGATE_HIGH
typ. t = 117ns
5V
t (ns)
Figure 7
Gate rising waveform
3.4
Current limitation
There is a cycle by cycle current limitation realized by the current limit comparator to provide over-current
detection. The source current of the Power MOSFET is sensed via a sense resistor RCS. By means of RCS the
source current is transformed to a sense voltage VCS which is fed into the pin CS. If the voltage VCS exceeds an
internal voltage limit, adjusted according to the Line voltage, the comparator immediately turns off the gate
drive.
When the main bus voltage increases, the switch on time becomes shorter and therefore the operating
frequency is also increased. As a result, for a constant primary current limit, the maximum possible output
power is increased which is beyond the converter design limit.
To compensate such effect, both the internal peak current limit circuit (VCS) and the ZC count varies with the
bus voltage according to Figure 8.
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Functional Description
VCS (V)
VCS_N, 1
0.9
Starting ZC = 1
Starting ZC = 3
VVIN (V)
0.83 1.29 VVIN_REF
Figure 8
Variation of the VCS limit voltage according to the VIN voltage
3.5
Active Burst Mode with selectable power level
At light load condition, the IC enters Active Burst Mode operation to minimize the power consumption. Details
about Active Burst Mode operation are explained in the following paragraphs.
The burst mode entry level can be selected by changing the different resistor RSel at FB pin. There are 2 levels to
be selected with different resistor which are targeted for low range of active burst mode power (Level 1) and
high range of active burst mode power (Level 2). The following table shows the control logic for the entry and
exit level with the FB voltage.
Table 4
Two levels entry and exit active burst mode power
Level VFB
VCS
Entry level
VFB_EBLX
Exit level
VFB_LB
1
2
VFB > VREF_B
VFB < VREF_B
VCS_BL1 = 0.31 V
VCS_BL2 = 0.35 V
0.90 V
2.75 V
1.05 V
2.75 V
During IC first startup, the internal RefGOOD signal is logic low when VCC < 4 V. It will reset the Burst Mode level
Detection latch. When the Burst Mode Level Detection latch is low and IC is in OFF state, the IC internal RFB
resistor is disconnected from the FB pin and a current source Isel is turned on instead.
From VCC=4 V to VCC on threshold, the FB pin will start to charge to a voltage level associated with RSel resistor.
When VCC reaches Vcc on threshold, the FB voltage is sensed. The burst mode thresholds are then chosen
according to the FB voltage level. The Burst Mode Level Detection latch is then set to high. Once the detection
latch is set high, any change of the FB level will not change the threshold selection. The current source Isel is
turned off in 2 μs after VCC reaches VCC on threshold and the RFB resistor is re-connected to FB pin (see Figure 9).
Vdd
Isel
S2
UVLO
S
2μs
delay
R
RFB
Refgood
S1
FB
Burst mode
detection latch
VCS_BLx
Selection
Logic
Compare
logic
VREF_B
VFB _EBL x
Control unit
Figure 9
Burst mode detect and adjust
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Functional Description
3.5.1
Entering Active Burst Mode Operation
For determination of entering Active Burst Mode operation, three conditions apply:
the feedback voltage is lower than the threshold of VFB_EBLX
the up/down counter is 8 for low line or 10 for high line and
the above two conditions remain after a certain blanking time tFB_BEB (20 ms).
Once all of these conditions are fulfilled, the Active Burst Mode flip-flop is set and the controller enters Active
Burst Mode operation. This multi-condition determination for entering Active Burst Mode operation prevents
mis-triggering of entering Active Burst Mode operation, so that the controller enters Active Burst Mode
operation only when the output power is really low during the preset blanking time.
3.5.2
During Active Burst Mode Operation
After entering the Active Burst Mode the feedback voltage rises as VO starts to decrease due to the inactive PWM
section. One comparator observes the feedback signal if the voltage level VFB_BOn is exceeded. In that case the
internal circuit is power up to restart with switching.
Turn-on of the Power MOSFET is triggered by ZC counter with a fixed value of 8 ZC for low line and 10 ZC for
high line. Turn-off is resulted if the voltage across the shunt resistor at CS pin hits the threshold VCS_BLX
.
If the output load is still low, the feedback signal decreases as the PWM section is operating. When feedback
signal reaches the low threshold VFB_BOff , the internal circuit is reset again and the PWM section is disabled until
next time VFB signal increases beyond the VFB_BOn threshold. In Active Burst Mode, the feedback signal is changing
like a saw tooth between VFB_BOff and VFB_BOn (see Figure 10).
3.5.3
Leaving Active Burst Mode Operation
The feedback voltage immediately increases if there is a high load jump. This is observed by a comparator with
threshold of VFB_LB. As the current limit is VCS_BLX (31% or 35%) during Active Burst Mode, a certain load is needed
so that feedback voltage can exceed VFB_LB. After leaving Active Burst Mode, Gate will only turn on if zero
crossing is detected (VZCD<VZCD_LB) to ensure full transformer demagnetization. This eases synchronous
rectification implementation by ensuring DCM operation upon exit of burst mode. Then, normal peak current
control through VFB is re-activated. In addition, the up/down counter will be set to 1 (low line) or 3 (high line)
immediately after leaving Active Burst Mode. This is helpful to minimize the output voltage undershoot.
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Functional Description
VFB
Entering Active Leaving Active
Burst Mode
Burst Mode
VFB_LB
VFB_BOn
VFB_BOff
VFB_EBx
Time to 8th/10th ZC and
t
Blanking time (tFB_BEB
)
VCS
Current limit level during
Active Burst Mode
VCS_N
VCS_BLx
t
VVCC
VVCC_OFF
t
t
VO
Max. Ripple < 1%
Figure 10
Signals in Active Burst Mode
3.6
Protection Functions
The ICE5QSBG provides numerous protection functions which considerably improve the power supply system
robustness, safety and reliability. The following table summarizes these protection functions. There are 3
different kinds of protection mode; non switch auto restart, auto restart and odd skip auto restart. The details
can refer to the Figure 11, Figure 12 and Figure 13.
Table 5
Protection functions
Protection Functions
Normal Mode
Burst Mode
Protection Mode
Burst ON
Burst OFF
√
√
√
√
√
√
√
√
√
Line Over Voltage
Brownout
Non switch Auto Restart
Non switch Auto Restart
√
NA1
√
VCC Over Voltage
VCC Under Voltage
Odd skip Auto Restart
Auto Restart
1 Not Applicable
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Functional Description
Protection Functions
Normal Mode
Burst Mode
Protection Mode
Burst ON
Burst OFF
Over Load
Odd skip Auto Restart
Odd skip Auto Restart
Non switch Auto Restart
√
√
√
NA1
NA1
NA1
Output Over Voltage
Over Temperature
√
√
√
3.6.1
Line Over Voltage
The AC Line Over Voltage Protection is detected by sensing bus capacitor voltage through VIN pin via 2 potential
divider resistors, Rl1 and Rl2 (see Figure 1). Once VVIN voltage is higher than the line over voltage threshold VVIN_LOVP, the
controller enters Line Over Voltage Protection and it releases the protection mode after VVIN is lower than VVIN_LOVP
.
3.6.2
Brownout
The Brownout protection is observed by VIN pin similar to line over voltage Protection method with a different
voltage threshold level. When VVIN voltage is lower than the brownout threshold (VVIN_BO), the controller enters
Brownout Protection and it releases the protection mode after VVIN higher than brownin threshold (VVIN_BI).
3.6.3
VCC Ovder Voltage or Under Voltage
During operation, the VCC voltage is continuously monitored. In case of a VCC Over Voltage or Under Voltage,
the IC is reset and the main power switch is then kept off. After the VCC voltage falls below the threshold VVCC_OFF
the new start up sequence is activated. The VCC capacitor is then charged up. Once the voltage exceeds the
threshold VVCC_ON, the IC begins to operate with a new soft-start.
,
3.6.4
Over Load
In case of open control loop or output Over Load, the feedback voltage will be pulled up and exceed VFB_OLP
.
After a blanking time of tFB_OLP_B, the IC enters auto restart mode. The blanking time here enables the converter
to operate for a certain time during a sudden load jump.
3.6.5
Output Over Voltage
During off-time of the Power MOSFET, the voltage at the ZCD pin is monitored for Output Over Voltage
detection. If the voltage is higher than the preset threshold VZCD_OVP for 10 consecutive pulses, the IC enters
Output Over Voltage Protection.
3.6.6
Over Temperature
If the junction temperature of controller chip exceeds Tjcon_OTP, the IC enters into Over Temperature protection
(OTP) Non switch auto restart mode. The controller implements with a 40°C hysteresis. In another word, the
controller/IC can only resume from OTP if its junction temperature drops 40°C from OTP trigger point. The over
temperature protection of the controller chip shall prevent turn-on of the power supply if the component
temperature is too high. For appropriate system protection, additional measures may have to be taken by the
designer.
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Functional Description
Fault
detected
Fault released
Switching start at the
following restart cycle
Start up and detect at
every charging cycle
VVCC
VCC_ON
VCC_OFF
t
t
VCS
No switching
Figure 11
Non switch Auto Restart Mode
Fault
Fault released
detected
Start up and detect at every
charging cycle
Switching start at the
following restart cycle
VVCC
VCC_ON
VCC_OFF
t
t
VCS
Figure 12
Auto Restart Mode
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Functional Description
Fault
detected
Fault released
Start up and detect at
every even charging
cycle
Switching start at the
following even restart
VVCC
No detect
No detect
cycle
VCC_ON
VCC_OFF
t
t
VCS
Figure 13
Odd skip Auto Restart Mode
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Electrical Characteristics
4
Electrical Characteristics
Attention: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings
are not violated.
4.1
Absolute Maximum Ratings
Attention: Stresses above the maximum values listed here may cause permanent damage to the device. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability. Maximum
ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the
integrated circuit. System design needs to ensure not to exceed the maximum limit. Ta=25°C unless
otherwise specified.
Table 6
Absolute Maximum Ratings
Symbol
Parameter
Limit Values
Unit Note / Test
Condition
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-
Max.
27
VCC Supply Voltage
GATE Voltage
SOURCE Voltage
FB Voltage
VCC
V
V
V
V
V
V
V
VGATE
VSOURCE
VFB
27
27
3.6
27
ZCD Voltage
VZCD
CS Voltage
VCS
3.6
3.6
0.9
VIN Voltage
VIN
Maximum DC current at SOURCE
pin
ISOURCE
A
Limited by Tj,Max
Single pulse source current at
SOURCE pin
IS_pulse
-
5.8
A
Pulse width tP=20 µs
and limited by Tj,Max
ESD robustness HBM
ESD robustness CDM
VESD_HBM
VESD_CDM
TJ
-
2000
500
150
150
185
V
According to
EIA/JESD22
-
V
Junction temperature range
Storage Temperature
-40
-55
-
°C
°C
TSTORE
RthJA
Thermal Resistance Junction-
Ambient
K/W Setup according to
the JESD51 standard
4.2
Operating Range
Note: Within the operating range the IC operates as described in the functional description.
Table 7
Operating Range
Parameter
Symbol
Limit Values
Min.
Unit Remark
Max.
VCC Supply Voltage
VVCC
VVCC_OFF
VVCC_OVP
V
Max value limited
Junction Temperature of controller TjCon_op
-40
TjCon_OTP
˚C
due to OTP of
controller chip
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Electrical Characteristics
4.3
Operating Conditions
Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction
temperature range TJ from – 40 °C to 125 °C. Typical values represent the median values, which are related to 25°C.
If not otherwise stated, a supply voltage of VCC = 18 V is assumed.
Table 8
Operating Conditions
Parameter
Symbol
Limit Values
Unit Note / Test Condition
Min.
Typ.
Max.
VCC Charge Current
-0.35
-0.2
-3.2
-3
-0.09
VVCC=0 V, RStartUp=50
mA
IVCC_Charge1
IVCC_Charge2
MΩ and VDRAIN=90 V
-
-
VVCC=3 V, RStartUp=50
MΩ and VDRAIN=90 V
mA
-5
-
-1
-
VVCC=15 V, RStartUp=50
MΩ and VDRAIN=90 V
IVCC_Charge3
IVCC_Startup
mA
Current Consumption, Startup
Current
0.19
0.9
mA
mA
VVCC=15 V
-
-
IFB=0 A (No gate
switching)
Current Consumption, Normal
IVCC_Normal
Current Consumption, Auto Restart IVCC_AR
-
320
0.5
16
-
µA
mA
V
Current Consumption, Burst Mode IVCC_Burst Mode
-
-
VFB=1.8 V
VCC Turn-on Threshold Voltage
VCC Turn-off Threshold Voltage
VVCC_ON
VVCC_OFF
15.3
9.5
16.5
10.5
10
V
VCC Short Circuit Protection
Voltage
VVCC_SCP
-
-
1.1
50
1.9
-
V
VCC Turn-off blanking
tVCC_OFF_B
µs
4.4
Internal Voltage Reference
Table 9
Internal Voltage Reference
Symbol
Parameter
Limit Values
Unit Note / Test
Condition
Min.
Typ.
Max.
Internal Reference Voltage
VREF
3.2
3.3
3.4
V
Measured at pin FB
IFB=0
4.5
Gate Driver
Table 10
Gate Driver
Parameter
Symbol
Limit Values
Unit Note / Test
Condition
Min.
Typ.
Max.
1.00
13
-
-
Output voltage at logic low
Output voltage at logic high
Rise Time
VGATE_LOW
VGATE_HIGH
tGATE_RISE
tGATE_FALL
V
V
7.5
-
10
117
27
-
-
ns
ns
Cout = 1nF
Cout = 1nF
-
Fall Time
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Electrical Characteristics
4.6
PWM Section
Table 11
PWM Section
Parameter
Symbol
Limit Values
Unit Note / Test
Condition
Min.
Typ.
Max.
Feedback Pull-Up Resistor
RFB
11
15
20
kΩ
PWM-OP Gain
GPWM
VPWM
tOnMax
1.95
0.42
20
2.05
0.5
35
2.15
0.58
60
-
Offset for Voltage Ramp
V
Maximum on time in normal
operation
µs
Maximumoff time in normal
operation
tOffMax
24
42.5
71
µs
4.7
Current Sense
Table 12
Current Sense
Parameter
Symbol
Limit Values
Unit Note / Test
Condition
Min.
Typ.
Max.
Peak current limitation in normal VCS_N
0.94
1.00
1.06
V
operation
Leading Edge Blanking time
tCS_LEB
VCS_BL1
VCS_BL2
VCS_STG
PCS_STG
118
0.26
0.3
0.06
-
220
0.31
0.35
0.10
3
462
0.36
0.4
0.15
-
ns
Peak Current Limitation in Active
Burst Mode – Level 1
Peak Current Limitation in Active
Burst Mode – Level 2
V
V
V
Abnormal CS voltage threshold
cycle
Abnormal CS voltage Consecutive
Trigger
Abnormal CS voltage Sample
period
tCS_STG_SAM
2.3
5
-
µs
4.8
Soft Start
Table 13
Soft Start
Parameter
Symbol
Limit Values
Unit Note / Test
Condition
Min.
8.5
-
Typ.
12
Max.
-
-
Soft-Start time
tSS
ms
ms
1
tSS_S
Soft-start time step
3
1 The parameter is not subjected to production test - verified by design/characterization
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Electrical Characteristics
1
Internal regulation voltage at first VSS1
step
-
-
0.30
0.15
-
-
V
V
CS peak voltage
CS peak voltage
1
Internal regulation voltage step at VSS_S
soft start
4.9
Digital Zero Crossing
Table 14
Digital Zero Crossing
Parameter
Symbol
VZCD_CT
Limit Values
Unit Note / Test
Condition
Min.
60
-
Typ.
100
0.45
Max.
150
-
Zero crossing threshold voltage
Zero crossing Ringing suppression VZCD_RS
threshold
mV
V
Minimum ringing suppression time tZCD_RS1
1.5
2.5
4.1
µs
VZCD > VZCD_RS (except
1st 3 ms of soft-start)
Maximum ringing suppression
time
Threshold to reset Up/Down
Counter
tZCD_RS2
VFB_R
-
-
25
-
-
µs
V
VZCD < VZCD_RS
2.80
Threshold for downward counting VFB_HLC
-
-
2.05
1.55
-
-
V
V
Threshold for upward counting
VFB_LHC
Counter Time
ZCD resistance
tCOUNT
RZCD
-
48
-
ms
2.5
3.0
3.5
kΩ
Internal resistor at
ZCD pin
VIN voltage threshold for line
selection
Blanking time for VIN voltage
threshold for line selection
VVIN_REF
tVIN_REF
1.48
-
1.52
16
1.58
-
V
ms
4.10
Active Burst Mode
Table 15
Active Burst Mode
Parameter
Symbol
Isel
Limit Values
Unit Note / Test
Condition
Min.
Typ.
Max.
3.9
2.1
3
µA
Charging current to select burst
mode
VREF_B
2.65
0.86
2.75
0.9
2.85
0.94
V
Burst mode selection reference
voltage
VFB_EBL1
V
Feedback voltage for entering
Active Burst Mode for level 1
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Electrical Characteristics
Feedback voltage for entering
Active Burst Mode for level 2
VFB_EBL2
1.0
-
1.05
20
1.1
-
V
Blanking time for entering Active tFB_BEB
ms
Burst Mode
Feedback voltage for leaving
Active Burst Mode
VFB_LB
2.65
60
2.75
100
2.85
150
V
ZCD voltage threshold for first
pulse after leaving Active Burst
Mode
VZCD_LB
mV
Feedback voltage for burst-on
VFB_BOn
VFB_BOff
2.3
1.9
2.4
2.0
2.5
2.1
V
V
Feedback voltage for burst-off
4.11
Line Over Voltage Protection
Table 16
Line OVP
Parameter
Symbol
Limit Values
Unit Note / Test
Condition
Min.
2.8
-
Typ.
Max.
3.0
-
Line Over Voltage threshold
Line Over Voltage Blanking
VVIN_LOVP
2.9
V
tVIN_LOVP_B
250
µs
4.12
Brownout Protection
Table 17
Brownout Protection
Symbol
Parameter
Limit Values
Unit Note / Test
Condition
Min.
0.63
-
Typ.
0.66
250
0.40
250
Max.
0.69
-
0.43
-
BrownIn threshold
BrownIn Blanking
BrownOut threshold
BrownOut Blanking
VVIN_BI
V
µs
V
tVIN_BI_B
VVIN_BO
tVIN_BO_B
0.37
-
µs
4.13
VCC Over Voltage Protection
Table 18
Vcc Over Voltage Protection
Symbol
Parameter
Limit Values
Unit
Note / Test
Condition
Min.
Typ.
Max.
VCC Over Voltage threshold
VCC Over Voltage blanking
VVCC_OVP
24
25.50
27
V
tVCC_OVP_B
-
50
-
µs
4.14
Over Load Protection
Table 19
Overload Protection
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Electrical Characteristics
Parameter
Symbol
Limit Values
Unit Note / Test
Condition
Min.
Typ.
Max.
Over Load Detection threshold for VFB_OLP
2.65
2.75
2.85
V
OLP protection at FB pin
Over Load Protection Blanking
Time
tFB_OLP_B
-
30
-
ms
4.15
Output Over Voltage Protection
Table 20
Output OVP
Parameter
Symbol
Limit Values
Unit Note / Test
Condition
Min.
1.9
-
Typ.
Max.
Output Over Voltage threshold
VZCD_OVP
2
2.1
-
V
Output Over Voltage Blanking
Pulse
PZCD_OVP_B
10
pulse Consecutive Pulse
4.16
Thermal Protection
Table 21
Thermal Protection
Parameter
Symbol
Limit Values
Unit Note / Test
Condition
Min.
129
-
-
Typ.
140
40
Max.
150
-
-
Over temperature protection1
Over temperature Hysteresis1
Over temperature Blanking Time
Tjcon_OTP
TjHYS_OTP
tjcon_OTP_B
°C
°C
Junction
temperature of the
controller chip
50
µs
4.17
Low side MOSFET
Table 22
Low side MOSFET
Parameter
Symbol
Limit Values
Unit Note / Test
Condition
Min.
Typ.
0.22
0.311
Max.
0.29
-
RDSon
-
-
Ω
Ω
Tj = 25°C
Tj = 125°C
Drain Source On-Resistance
1 The parameter is not subjected to production test - verified by design/characterization
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Output power curve
5
Output power curve
The calculated output power curves versus ambient temperature are shown below. The curves are derived
based on a typical DCM flyback in an open frame design setting the maximum TJ at 125 °C, using minimum pin
copper area in a 2 oz copper single sided PCB and steady state operation only (no design margins for abnormal
operation modes are included).
The output power figure is for reference only. The actual power can vary depending on a particular design. In a
power supply system, appropriate thermal design margins must be considered to make sure that the operation
of the device is within the maximum ratings given in section 4.1.
Figure 14
Output power curve of ICE5QSAG
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Outline Dimension
6
Outline Dimension
Figure 15
PG-DSO-8
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Quasi-Resonant Controller
Marking
7
Marking
Figure 16
Marking for ICE5QSBG
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Quasi-Resonant Controller
Revision history
Revision history
Document
version
Date of release
Description of changes
V 2.0
V 2.1
30 Aug 2019
3 Feb 2020
First release
Update of CS pin function and description
(refer to errata sheet ES_2001_PL83_2002_024629)
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IMPORTANT NOTICE
The information given in this document shall in no For further information on the product, technology,
Edition 2020-02-03
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
Published by
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contact your nearest Infineon Technologies office
(www.infineon.com).
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With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
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