IGI60F5050A1L_技术文档

CoolGaN^TMIntegrated Power Stage (IPS) IGI60F5050A1L

500 m / 600 V GaN half-bridge with fast accurate isolated gate drivers

Features

•

Two 500 m GaN switches in half-bridge configuration with dedicated high- and

low-side isolated gate drivers

Source / sink driving current up to 1 / 2 A

Application-configurable turn-on and turn-off speed

•

Fast input-to-output propagation (typ. 47 ns) with extremely small channel-to-

channel mismatch

•

PWM input signal (switching frequency up to 3 MHz)

Standard logic input levels compatible with digital controllers

Wide supply range

Single gate driver supply voltage possible (typ. 8 V) with fast UVLO recovery

Low-side open source for current sensing with external shunt resistor

Galvanic input-to-output isolation based on robust coreless transformer technology

Gate driver with very high common mode transient immunity (CMTI) > 300 V/ns

Thermally enhanced 8 x 8 mm QFN-28 package

Product is fully qualified acc. to JEDEC for Industrial Applications

Description

IGI60F5050A1L combines a half-bridge power stage consisting of two 500 m (typ. R_dson) / 600 V enhancement-

mode CoolGaN^TMHEMTs with dedicated gate drivers in a small 8 x 8 mm QFN-28 package. In the low-to-medium

power area (example application in Figure 1) it is thus ideally suited to support the design of high-density AC/DC

chargers and adapters utilizing the superior switching behavior of CoolGaN^TMHEMTs.

Infineon’s CoolGaN^TMand related power switches provide a very robust gate structure. When driven by a continuous

gate current of a few mA in the “on” state, a minimum on-resistance R_dsonis always guaranteed.

R_ss

V_in

V_out

C_C

V_DDL

R_tr

CoolGaN^TMIPS

OUTH

C_clmp

VDDH

DH

GH

R_VDDI

VDDI

C_out

Controller

UVLO

CT

C_VDDI

SLDON

RX

TX

SLDO

Logic

D_boot

C_boot

PWML

PWMH

GPIOx

INL

INH

Control

Logic

SW

CoolGaN^TM

VDDL

UVLO

V_DDL

TX

RX

ENABLE

C_VDDL

Logic

GND

GNDI

SL

R_sense

OUTL

GL

I_s

R_tr

C_C

R_ss

Figure 1

Typical application circuit (active clamp flyback converter)

Final Datasheet

Please read the Important Notice and Warnings at the end of this document

page 1 of 35

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

Due to the GaN-specific low threshold voltage and the fast switching transients, a negative gate drive voltage is

required in certain applications to both enable fast turn-off and avoid cross-conduction effects. This can be achieved

by the well-known RC interface between driver and switch. A few external SMD resistors and caps enable easy

adaptation to different power topologies.

The driver utilizes on-chip coreless transformer technology (CT) to achieve signal level-shifting to the high-side.

Further, CT guarantees robustness even for extremely fast switching transients above 300 V/ns.

Applications

•

Low power motor drive

LED lighting

Power Topologies

•

Digital controller based AC/DC, DC/DC and DC/AC topologies

Active clamp flyback or hybrid flyback converters

LLC or LCC resonant converters

Single or interleaved synchronous buck or boost converter

Single phase or multiphase two level inverters

Product Versions

Table 1

CoolGaN^TMintegrated power stage half bridge products overview

Part Number /

Ordering code

OPN

Package

Typ. R_dson

Marking

high- / low-side

IGI60F1414A1L

IGI60F2020A1L

IGI60F2727A1L

IGI60F5050A1L

IGI60F1414A1L

AUMA1

PG-TIQFN-28-1

8 x 8 mm

140 mΩ / 140 mΩ

200 mΩ / 200 mΩ

270 mΩ / 270 mΩ

500 mΩ / 500 mΩ

60F1414A

60F2020A

60F2727A

60F5050A

IGI60F2020A1L

AUMA1

PG-TIQFN-28-1

8 x 8 mm

IGI60F2727A1L

AUMA1

PG-TIQFN-28-1

8 x 8 mm

IGI60F5050A1L

AUMA1

PG-TIQFN-28-1

8 x 8 mm

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

Table of contents

Table of contents ........................................................................................................................... 3

1

Pin configuration and description ........................................................................................... 4

Functional description ........................................................................................................... 6

Block Diagram ........................................................................................................................................6

Power supply..........................................................................................................................................7

Driver input supply voltage...............................................................................................................7

Driver output supply voltages ..........................................................................................................7

Input configurations...............................................................................................................................8

Driver outputs.........................................................................................................................................8

Undervoltage Lockout (UVLO) ...............................................................................................................8

Start-up and active clamping ................................................................................................................9

CT Communication and Data Transmission..........................................................................................9

CoolGaN^TMoutput stage.........................................................................................................................9

Characteristics.....................................................................................................................10

Absolute maximum ratings..................................................................................................................10

Thermal characteristics .......................................................................................................................11

Recommended operating range..........................................................................................................11

Electrical characteristics......................................................................................................................12

Timing diagrams and test circuit.........................................................................................................17

Driving CoolGaN^TMHEMTs ......................................................................................................19

Typical characteristics ..........................................................................................................21

GaN switch characteristics...................................................................................................................21

Gate driver characteristics...................................................................................................................24

Application circuit ................................................................................................................27

Package information ............................................................................................................28

Layout guidelines .................................................................................................................29

Appendix .............................................................................................................................32

References...........................................................................................................................33

2

2.1

2.2

2.2.1

2.2.2

2.3

2.4

2.5

2.6

2.7

2.8

3

3.1

3.2

3.3

3.4

3.5

4

5

5.1

5.2

6

7

8

9

10

Revision history............................................................................................................................34

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

1

Pin configuration and description

SL

DH DH DH

13

14

15

16

17

18

19

20

21

SL

8

7

6

5

4

3

2

1

SW

SL

SW

SL

SW

GL

VDDL

OUTL

GNDI

INL

GH

VDDH

OUTH

NC

GNDI

1

Figure 2

Pin configuration and exposed pads for QFN-28 8 x 8 mm package, top view (not to scale)

Table 2

Pin description

Symbol

NC

Description

Pin No.

1

2

Not connected

OUTH

VDDH

GH

Driver output high-side

3

Supply voltage for high-side driver (typ. 8 V referred to SW)

Gate connection high-side switch

Half-bridge output (switching node)

Drain connection high-side switch

Source connection low-side switch

Gate connection low-side switch

Supply voltage for low-side driver (typ. 8 V referred to SL)

Driver output low-side

4

5 – 8, 28

9 - 11

12 - 16

17

SW

DH

SL

GL

18

VDDL

OUTL

GNDI

INL

19

20, 25

21

Ground connection of driver input stage

Input signal (default state “Low”); controls low-side switch

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

22

23

INH

Input signal (default state “Low”); controls high-side switch

Connected to VDDI (or not connected): VDDI directly supplies driver input

circuitry

SLDON

Connected to GNDI: Internal shunt regulator activated to generate VDDI (3.3 V)

Supply voltage driver input stage (+3.3 V); can be either applied directly or

generated by internal SLDO (e.g by connecting VDDI via resistor R_VDDIto VDDL)

24

26

27

VDDI

ENABLE

NC

Input signal (default state “Low” - both outputs set to low state); logic “High”

required to activate outputs

Not connected

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2

Functional description

2.1

Block Diagram

A simplified functional block diagram of the CoolGaN^TMPower Stage is given in Figure 3. For the level-shifting

function of the input signal to the high-side switch an on-chip coreless transformer (CT) is utilized. For symmetry

reasons a CT is also included in the low-side path, resulting in both a galvanic input-to-output and high-to-low-side

isolation. In addition, this CT separates the low-side gate driver reference (SL) from GNDI allowing to use a shunt

resistor for current sensing as shown in Figure 1.

VDDH

OUTH

GH

DH

CT

UVLO

VDDI

SLDON

INL

TX

RX

SLDO

Logic

SH

Control

Logic

SW

functional

isolation

INH

DL

UVLO

ENABLE

TX

RX

Logic

SL

GNDI

GL

SL

VDDL

OUTL

Figure 3

Block Diagram IGI60F5050A1L

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2.2

Power supply

Basically, the Power Stage requires 3 supply voltages: a ground-related 3.3 V (V_DDI) for the driver input circuitry,

another ground-related 8 V (V_DDL) for the low-side driver and a floating 8 V (V_DDH) for the high-side driver. However,

in most applications a single 8 V supply is sufficient, as V_DDIand V_DDHcan be simply generated from V_DDL

.

Independent Undervoltage Lockout (UVLO) functions for all supply voltages ensure a defined start-up and robust

functionality under all operating conditions.

All driver supply currents stay in the few mA range, as described in Table 9, resp. However, in particular applications

a further power reduction in stand-by mode might be beneficial. Then a complete elimination of the supply currents

can be achieved by implementing a simple circuit with a bipolar transistor as a supply switch controlled by the Enable

signal.

2.2.1

Driver input supply voltage

The driver input die is supplied via V_DDIwith a nominal voltage of 3.3 V. The Undervoltage Lockout threshold, defining

the minimum V_DDI, is set to typically 2.85 V. Power consumption to some extent depends on switching frequency, as

the input signal is converted into a train of repetitive current pulses to drive the CT. Due to the chosen robust encoding

scheme the average repetition rate of these pulses and thus the average supply current depends on the switching

frequency f_sw. However, for f_sw< 500 kHz this effect is very small.

If no separate 3.3 V supply is available, the input side can also be operated with V_DDL(typically 8 V). Then the shunt

LDO voltage regulator (SLDO) has to be enabled by connecting pin SLDON (pin#23) to GNDI. The SLDO regulates

the current through an external resistor R_VDDIconnected between V_DDLand pin VDDI as depicted in Figure 1 to

generate the required voltage drop. For proper operation it has to be ensured that the current through R_VDDIalways

exceeds the maximum supply current I_VDDIof the input chip. R_VDDIthus has to fulfil:

ꢀ_{퐷퐷퐿,푚ꢁ푛}− 3.3 ꢀ

푅_푉퐷퐷퐼

<

(1)

ꢂ_{푉퐷퐷퐼,푚푎푥}

However, R_VDDIshould not be chosen too small to avoid any additional power dissipation. A typical choice for

V_DDL= 8 V would be R_VDDI= 1 k, resulting in sufficient margin between resistor current and maximum operating

current. Dynamic current peaks are provided by a blocking cap (10 to 22 nF) between V_DDIand GNDI. Table 3 shows

proper R_VDDIvalues for different supply voltages V_{DDL .}

.

Table 3

V_DDL

Proper R_VDDIvalues for different V_DDL

R_VDDI

SLDO

3.3 V

5.0 V

8.0 V

12.0 V

no resistor (connect VDDL to VDDI pin)

Disabled

Enabled

360 

1.0 k

1.8 k

2.2.2

Driver output supply voltages

Both output dice have to be supplied by a voltage of typically 8 V related to the source of the respective GaN switch.

In many applications the floating high-side supply V_DDHcan be generated from the ground-related V_DDLby means of

bootstrapping (components D_boot, C_bootand R_bootin Figure 1). A ceramic bypass capacitance C_VDDLof typically

100 nF has to be placed close to pin V_DDL

.

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

For both driver output stages the minimum operating supply voltage is set by independent undervoltage lockout

functions (UVLO_out).

2.3

Input configurations

The inputs INL and INH are two independent logic (PWM) channels. The input signal is transferred non-inverted to

the corresponding gate driver outputs OUTL and OUTH. All inputs are compatible with LV-TTL threshold levels with

a hysteresis of typ. 0.8 V. The hysteresis is independent of the supply voltage VDDI.

The PWM inputs are internally pulled down to a logic low voltage level (GNDI). In case the PWM-controller signals

have an undefined state during the power-up sequence, the gate driver outputs are forced to the "off"-state (low). If

the Enable input is low, both channel outputs are driven to “low”, regardless of the state of INL or INH. Table 4 shows

the logic table in normal operation.

Table 4

Logic table (UVLO input inactive, both output side UVLO inactive; normal operation)

Inputs

Gate Drive Ouput

Enable

INL

x

INH

x

OUTL

OUTH

L

H

L

H

L

H

L

H

L

H

2.4

Driver outputs

The rail-to-rail gate driver output stage realized with complementary MOS transistors is able to provide a typical 1 A

sourcing and 2 A sinking current. This is by far sufficient when driving the GaN HEMTs due to their low gate charge.

In addition, the relatively low driver output resistance is beneficial, too. With an R_onof 3.1  for the sourcing pMOS

and 1.2  for the sinking nMOS transistor the driver can be considered as nearly ideal. The gate drive parameters

can thus be determined easily and accurately by the external components as described in chapter 4. The p-channel

sourcing transistor allows real rail-to-rail behavior without suffering from a source follower's voltage drop.

2.5

Undervoltage Lockout (UVLO)

The Undervoltage Lockout function ensures that the gate drive outputs can be switched to their high level only, if

both input and output supply voltages exceed the corresponding UVLO threshold voltages. Thus it can be

guaranteed, that the GaN switches are in “off” state, if the driving voltage is too low for complete and fast switching

on, thereby avoiding excessive power dissipation and keeping the switch transistors within their safe operating area

(SOA).

The UVLO levels for the output supplies V_DDLand V_DDHare set to a typical “on”-value of 4.2 V (with 0.3 V hysteresis),

whereas UVLO_infor V_DDIis set to 2.85 V with 0.15 V hysteresis. Table 5 shows the logic table in the condition that

input or outputs are in UVLO active or inactive condition.

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Table 5

Enable

Logic table (dependence on UVLO status)

Inputs

Gate Drive Ouput

INL

INH

UVLO input

UVLO output L UVLO output H

OUTL

OUTH

x

L

H

x

Active

Inactive

x

L

H

L

H

L

H

Active

Inactive

Active

x

L

H

x

2.6

Start-up and active clamping

Special attention has been paid to cover all possible operating conditions, like start-up or arbitrary supply voltage

situations:

-

if V_DDIdrops below UVLO_in, a “switch-to-low” command is sent to both outputs OUTL and OUTH

for V_DDLand/or V_DDHlower than the respective UVLO levels, a new fast active clamping circuit provides a

low-impedance path from the gate driver outputs OUTL and OUTH to their respective grounds SL and SW.

As soon as the output voltage exceeds a low threshold level (typically below 1 V), the clamp is activated

within approximately 20 ns.

As the result, safe operation of the GaN Power Stage can be guaranteed under any circumstances.

2.7

CT Communication and Data Transmission

A Coreless Transformer (CT) based communication module is used for PWM signal transfer between input and

outputs. A proven high-resolution pulse repetition scheme in the transmitter combined with a watchdog time-out at

the receiver side enables recovery from communication fails and ensures safe system shut-down in failure cases.

2.8

CoolGaN^TMoutput stage

The output stage consists of two CoolGaN^TM600V switches in half-bridge configuration. The switches are

characterized by a typical R_dsonof 500 m @ 25 °C. And thanks to the current driving concept, this value increases

by a comparably moderate 85 % @ 150 °C. As typical for GaN, gate and output charges are very small and there is

no reverse recovery charge due to the lack of a physical body diode (for more information please refer to [1]).

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

3

Characteristics

3.1

Absolute maximum ratings

The absolute maximum ratings are listed in Table 6. Stresses beyond these values may cause permanent damage

to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 6

Absolute maximum ratings

Parameter

Symbol

Values

Unit

Note or Test Conditions

Min.

Max.

Voltage between output pins

DH, SW and SL

V_DHSW

V_SWSL

-

600

V

V_GHSH= 0 V, V_GLSL= 0 V

Drain-to-source voltage pulsed V_DS,pulse

-

750¹

650

V

T_J= 25°C, V_GS≤ 0 V,

cumulated stress time ≤ 1h

T_J= 125°C, V_GS≤ 0 V,

cumulated stress time ≤ 1h

Continuous drain current²

Pulsed drain current³

I_D

-

3.8

2.8

6.4

3.5⁴

3.7

A

V

T_Case= 25°C

-

T_Case= 125°C

I_D,pulse

-

T_Case= 25°C (see Figure 13)

T_Case= 125°C (see Figure 13)

Note⁵

Supply voltage input chip

V_DDI

V_DDL/H

V_IN

-0.3

Supply voltage output chips

-0.3

22

17

V

with respect to SW/SL

Voltage at pins INL, INH and

ENABLE

Voltage at pin SLDO

V_SLDO

V_OUTL/H

T_J

-0.3

- 40

- 55

-

V_DDI+ 0.3

V_DDL/H+ 0.3

150

V

Voltage at pins OUTL, OUTH

Junction temperature

Storage temperature

V

°C

T_S

150

reflow/wave soldering⁶

Soldering temperature

T_sold

260

¹Acc to JEDEC-JEP180

²Limited by T_jmax. Maximum Duty Cycle D=0.5

³Limits derived from product characterization, parameter not measured during production

⁴Parameter is influenced by reliability requirements. Please contact the local Infineon Sales Office to get an assessment of your application

⁵If the SLDO is activated (SLDON pin tied to GNDI), the input-side supply voltage (VDDL) does not correspond to VDDI and can be higher

⁶Acc. to JESD22A111

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Parameter

Symbol

Values

Unit

Note or Test Conditions

Min.

Max.

ESD capability

V_{ESD_HBM}

V_{ESD_CDM}

-

1.5

1.0

kV

Human Body Model¹

Charged Device Model²

3.2

Thermal characteristics

Table 7 Thermal characteristics

Parameter

Symbol

Values

Unit

Note or Test

Conditions

Min.

Typ.

Max.

Thermal resistance junction-case

R_thJC

R_thJA

-

5.5

°C/W

Thermal resistance junction-

ambient

35

-

°C/W Device mounted on

four-layer PCB with

600 mm²total cooling

area

3.3

Recommended operating range

Table 8 Recommended operating range

Parameter

Symbol

Values

Typ.

3.3

Unit

Note or Test

Conditions

Min.

Max.

Input supply voltage

V_DDI

3

3.5

V

if operated directly

without SLDO

Driver output supply voltages

V_DDL/H

5.5

8

12

min. defined by

UVLO_out

VDDI blocking capacitance

C_VDDI

V_IN

10

0

-

22

nF

V

SLDO active

Logic input voltage at pins INL,

INH and ENABLE

6.5

Voltage at pin SLDO

V_SLDO

I_{G, avg}

T_J

0

-

3.5

2.6

V

Gate current, continuous^{3 4}

Junction temperature

mA

-40

125 ⁵°C

¹Acc. to EIA/JESD22-A114-B (discharging 100 pF capacitor through 1.5 kΩ resistor)

²Acc. to JESD22-002

³Parameter is influenced by rel-requirements. Contact the local Infineon Sales Office to get an assessment of your application.

⁴We recommend to use RC interface gate drive to optimize the device performance. Please see gate drive application note for details.

⁵Continuous operation above 125°C may reduce lifetime

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3.4

Electrical characteristics

Unless otherwise noted, min/max values of characteristics are the lower and upper limits, resp. They are valid within

the full operating range. All values are given at T_J= 25 °C with V_DDI= 3.3 V and V_DDL/H= 8 V.

Table 9

Power supply

Parameter

Symbol

Values

Typ.

1.4

Unit

Note or Test

Conditions

Min.

Max.

V_DDIquiescent current¹

V_DDLquiescent current¹

V_DDHquiescent current¹

I_VDDIqu

-

mA

V

no switching

I_VDDLqu

-

0.7

-

I_VDDHqu

UVLO_VDDI

0.7

Undervoltage Lockout input

(UVLO_VDDI) turn-on threshold

2.75

2.85

2.95

UVLO_VDDIturn-off threshold

UVLO_VDDI-

UVLO_VDDI

UVLO_outLH

-

2.7

0.15

4.2

-

V

UVLO_VDDIthreshold hysteresis

0.1

4.0

0.2

4.4

Undervoltage Lockout outputs

(UVLO_VDDL/H) turn-on threshold

UVLO_VDDL/Hturn-off threshold

UVLO_{VDDL/H -}

-

3.9

0.3

-

V

UVLO_VDDL/Hthreshold hysteresis

0.2

0.4

UVLO_VDDL/H

Table 10

Logic inputs INL, INH and ENABLE

Parameter

Symbol

Values

Typ.

2.0

Unit

Note or Test

Conditions

Min.

Max.

Input voltage threshold for

transition LH

V_IN+

1.7

2.3

V

independent of V_DDI

Input voltage threshold for

transition HL

V_IN-

-

1.2

-

Input voltage threshold hysteresis V_{IN_hys}

Input pull down resistor R_IN

0.4

-

0.8

1.2

-

V

150

k

¹Can be completely eliminated in stand-by mode by utilizing external supply switch (see chapter 2.2)

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Table 11

Static gate driver output characteristics

Parameter

Symbol

Min.

Values

Typ.

Unit Note or Test Conditions

Max.

High-level (sourcing) output

resistance

R_on

1.4

3.1

5.8



Peak sourcing output current¹

I_src,pk

R_off

-

1

-

A

actively limited to 1.3 A

actively limited to -2.6 A

Low-level (sinking) output

resistance

0.6

1.2

2.5



Peak sinking output current¹

I_snk,pk

-

-2

1

-

A

V

Active clamp threshold voltage V_clmp

Table 12

Output characteristics GaN switches

Parameter

Symbol

Min.

Values

Typ.

Unit Note or Test Conditions

Max.

R_dsonhigh-side

R_dshs

-

500

650

I_G= 2.6 mA, I_D= 0.8 A,

T_J= 25°C

m

µA

1000

500

1000

0.1

-

I_G= 2.6 mA, I_D= 0.8 A,

T_J= 150°C

R_dsonlow-side

R_dsls

650

I_G= 2.6 mA, I_D= 0.8 A,

T_J= 25°C

-

I_G= 2.6 mA, I_D= 0.8 A,

T_J= 150°C

Drain-source leakage current

I_DSShs,I_DSSls

V_DS= 600 V, V_GS= 0 V,

T_J= 25°C

2.0

µA

V_DS= 600 V, V_GS= 0 V,

T_J= 25°C

Total gate charge (per switch) ¹Q_G

0.58

nC

I_G= 0 to 1.0 mA,

V_DH= 400 V, I_D= 0.8 A

1

Verified by design / characterization, not tested in production

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Table 13

Static characteristics GaN switches

Parameter

Symbol

Min.

Values

Unit Note or Test Condition

Typ. Max.

Gate threshold voltage

V_GS(th)

V_{GS, clamp}

R_G,int

0.9

0.7

1.2

1.0

1.6

1.4

V

I_DS= 0.26 mA, V_DS= 10 V, T_j=25 °C

I_DS= 0.26 mA, V_DS= 10 V, T_j=125°C

Gate-source reverse clamping

voltage

-

-8

V

I_GSS¹= -1 mA, T_j=25 °C

-

Gate resistance

-

1.31

-

Ω

LCR impedance measurement

Table 14

Dynamic characteristics GaN switches

Symbol

Parameter

Values

Min. Typ. Max.

Unit Note or Test Condition

Input capacitance

C_iss

-

37.8

-

pF

nC

V_GS= 0 V, V_DS= 400 V; f = 1MHz

V_GS= 0 V, V_DS= 0 to 400 V

V_DS= 0 to 400 V

Output capacitance

C_oss

7.2

Reverse transfer capacitance

C_rss

0.03

8.0

Effective output capacitance, energy

related²

C_o(er)

C_o(tr)

Q_oss

Effective output capacitance, time

related³

10.2

4.1

Output charge

1 Gate-Source leakage current

2 C_o(er)is a fixed capacitance that gives the same stored energy as C_osswhile V_DSis rising from 0 to 400 V

3 C_o(tr)is a fixed capacitance that gives the same charging time as C_osswhile V_DSis rising from 0 to 400 V

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

Table 15

Reverse conduction characteristics

Symbol

Parameter

Values

Typ.

2.2

Unit

Note/Test Condition

Min.

Max.

Source-Drain reverse voltage V_SD

-

2.5

V

A

V_GS= 0V, I_SD= 0.8 A

I_G= 2.6 mA

Pulsed current, reverse

I_S,pulse

-

6.0

1

Reverse recovery charge

Reverse recovery time

Q_rr

t_rr

-

0

-

nC I_SD= 0.8 A, V_DS= 400V

ns

A

Peak reverse recovery current I_rrm

Table 16

Dynamic Characteristics²(see Figure 4, Figure 5)

Parameter

Symbol

Values

Typ.

Unit

Note or Test

Conditions

Min.

Max.

INL to SW propagation delay “on” t_PDonL

INL to SW propagation delay “off” t_PDoffL

-

47

-

ns

R_tr= 50 

I_load= 2 A

Propagation delay matching

high/low-side

-5

-

5

ns

t_PDonLH

t_PDoffLH

ENABLE to SW propagation

delay

t_{PD_DIS_ON}

,

-

70

-

ns

t_{PD_DIS_OFF}

Rise time SW

Fall time SW

t_rise

-

6

5

-

ns

10 % to 90 %

90 % to 10 %

t_fall

Minimum input pulse width that

changes output state

t_PW

-

18

-

ns

-

Input-side start-up time²

t_START,VDDI

t_STOP,VDDI

t_START,VDDL/H

t_STOP,VDDL/H

-

7

-

µs

ns

see Figure 6

Input-side deactivation time²

Output-side deactivation time²

255

5

110

¹Excluding Q_oss

²Verified by design / characterization, not tested in production

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

Table 17

Isolation specifications

Parameter

Symbol

Value

Unit Note or Test Conditions

Max. Input-to-DH voltage

V_InDH

V_InSW

>1200

>600

V_DC

production test > 10 ms

Max. Input-to-SW

voltage

Functional isolation

Max. Input-to-SL voltage

V_InSL

CLR

>100

1.9

V_DC

Nominal package

clearance

mm

shortest distance over air, from

any input pin to any high-side

output pin

Nominal package

creepage

CRP

1.9

mm

V

shortest distance over surface,

from any input pin to any high-

side output pin

Package

characteristics

Comparative Tracking

Index of package mold

CTI

>400

according to DIN EN 60112

(VDE 0303-11)

Material group

-

II

-

according to IEC 60112

Static Common Mode

Transient Immunity¹²

V_CM= 1500 V; INL, INH

tied to V_DDI(logic

|CM_Static,H

|

300

V/ns

high inputs)

V_CM= 1500 V; INL, INH

tied to GNDI (logic

Common Mode

Transient Immunity

(CMTI)

|CM_Static,L

|

300

V/ns

high inputs)

Dynamic Common

Mode Transient

Immunity^{1 3}

|CM_Dynamic

|

V/ns V_CM= 1500 V; dynamic INL,

INH (10 MHz square wave)

¹minimum slew rate of a common mode voltage at which the output signal is disturbed

²parameters verified by characterization according to VDE0884-11 standard definitions and test-methods

³verified by characterization with ground reference for the common mode pulse generator connected to the coupler intput-side ground to reflect

real applications requirements

Final Datasheet

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3.5

Timing diagrams and test circuit

Figure 4 depicts rise, fall and delay times measured at the GaN half-bridge output SW. Figure 5 shows the

associated test circuit. The power stage is operated in a boost configuration at a constant current I_load. In this so-

called double-pulse arrangement I_loadis determined by the high-voltage supply (400 V), the output inductance and

the length of the first “on”-phase of the INL-signal. The specified delay and transient times are related to an I_loadvalue

of 2 A (particularly the “off” transient strongly depends on this current). INH need not be switched for this

measurement.

INL

V_INH

V_INL

90%

10%

SW

10%

t_PDon

t_PDoff

t_fall

t_rise

Figure 4

Propagation delay, rise and fall time

+400 V

1k

1.5n

VDDL

33

OUTH

DH

GH

1k

VDDH

100n

VDDI

22n

2 A

+8 V

SLDON

INL

INH

SW

VDDL

+8 V

100n

ENABLE

GNDI

SL

OUTL

GL

33

1k

1.5n

Figure 5

Test circuit

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

High logic level

INL/INH

High logic level

INL/INH

High logic level

ENABLE

High logic level

ENABLE

High level ( > UVLO_{VDDI,on )}

VDDI

High level ( > UVLO_{VDDL/H,on )}

VDDL/H

UVLO_VDDL/H,on

UVLO_VDDI,on

UVLO_VDDL/H,off

UVLO_VDDI,off

VDDL/H

OUTL/H

VDDI

OUTL/H

t_{STAR T,VDDI}

t_{STAR T,VDDL/H}

t_STOP,VDDI

t_STOP,VDDL/H

Figure 6

UVLO behavior, start-up and deactivation time (unloaded output)

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

4

Driving CoolGaN^TMHEMTs

Although Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) with ohmic connection to a pGaN gate are

robust enhancement-mode (“normally-off”) devices, they differ significantly from MOSFETs. The gate module is not

isolated from the channel, but behaves like a diode with a forward voltage V_Fof 3 to 4 V. Equivalent circuit and typical

gate input characteristic are given in Figure 7. In the steady “on” state a continuous gate current is required to achieve

stable operating conditions. The switch is “normally-off”, but the threshold voltage V_this rather low (~ +1 V). This is

why in many applications a negative gate voltage -V_N, typically in the range of several Volts, is required to safely

keep the switch “off” (Figure 7b).

Figure 7

Equivalent circuit (a) and gate input characteristics (b) of typical normally-off GaN HEMT

Obviously the transistor in Figure 7 cannot be driven like a conventional MOSFET due to the need for a steady-state

“on” current I_ssand a negative “off” voltage –V_N. While an I_ssof a few mA is sufficient, fast switching transients require

gate charging currents I_onand I_offin the 1 A range. To avoid a dedicated driver with 2 separate “on” paths and bipolar

supply voltage, the solution depicted in Figure 8 is usually chosen, combining a standard gate driver with a passive

RC circuit to achieve the intended behavior. The high-current paths containing the small gate resistors R_onand R_off,

respectively, are connected to the gate via a coupling capacitance C_C. C_Cis chosen to have no significant effect on

the dynamic gate currents I_onand I_off. In parallel to the high-current charging path the much larger resistor R_ssforms

a direct gate connection to continuously deliver the small steady-state gate current I_ss. In addition, C_Ccan be used to

generate a negative gate voltage. Obviously, in the “on”-state C_Cis charged to the difference of driver supply V_DD

and diode voltage V_F. When switching off, this charge is redistributed between C_Cand C_GSand causes an initial

negative V_GSof value:

퐶_ꢃ∙ (ꢀ_퐷퐷− ꢀ ) − 푄_퐺

퐹

ꢀ_푁=

(2)

퐶_ꢃ+ 퐶_퐺푆

with Q_Gdenoting the total gate charge. V_Ncan thus be controlled by proper choice of V_DDand C_C. During the „off“

state the negative V_GSdecreases, as C_Cis discharged via R_SS. The associated time constant cannot be chosen

independently, but is related to the steady-state current and is typically in the 1 s range. The negative gate voltage

at the end of the “off” phase (V_Nfin Figure 8b) thus depends on the “off” duration. It lowers the effective driver voltage

for the following switching-on event, resulting in a slight dependence of switching dynamics on frequency and duty

cycle. However, in most applications the impact of this effect is negligible.

Another situation requires attention, too. If there is by any reason a longer period with both switches of a half-bridge

in “off”-state (e.g. during system start-up, burst mode operation etc.), both capacitors C_Cwill be discharged. That

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

means, for the first switching pulse after such an extended non-switching period no negative voltage is available. To

avoid instabilities due to spurious turn-on effects in such a situation, C_Cshould not be chosen lower than 1 nF.

GaNswitch

D

R_ssI_ss

I_on

V_GS

V_DD

Driver

R_tr

R_off

I_off

C_GD

OUT

G

VDD

3.5V

C_DS

C_C

V_F

0

S₁

S₂

on

off

+

t

C_GS

-V_Nf

-V_N

S

a)

b)

Figure 8

Equivalent circuit of GaN switch with RC gate drive (a) and gate-to-source voltage V_GS(b)

In the topology of Figure 8 often a single resistor R_trcan be used for setting the maximum transient charging and

discharging current. If this is not acceptable by any reason, an additional resistor R_offwith series diode in parallel with

R_trcan be used to realize independent gate impedances for the “on” and “off” transient, respectively.

All relevant driving parameters are easily programmable by choosing V_DD, R_ss, R_tr, R_offand C_Caccording to the

relations

퐶_ꢃ∙ (ꢀ_퐷퐷− ꢀ ) − 푄_퐺

퐹

ꢀ_푁=

퐶_ꢃ+ 퐶_퐺푆

(3)

ꢀ_퐷퐷− ꢀ

ꢀ_퐷퐷− ꢀ_푁푓

푅_푡푟

(ꢀ + ꢀ_푁) ∙ (푅_표푓푓+ 푅_푡푟)

퐹

푡ℎ

ꢂ_푠푠

=

,

ꢂ_{표푛,푚푎푥}

~

,

ꢂ_{표푓푓,푚푎푥}~

푅_푠푠

푅_표푓푓∙ 푅_푡푟

The main guidelines for dimensioning gate drive parameters are as follows:

-

V_Nmust always be positive; a target value of 2 V in soft-switching and 4 V to 5 V in hard-switching systems

is recommended

-

The target value of I_ssis 2.5 mA, R_sshas to be chosen accordingly

R_trsets the transient speed for a hard switching “on” event. Due to the low gate charge, values above 50 

typically do not result in significant benefits. For soft switching systems R_tris anyway uncritical.

If a separate R_offis used, it should guarantee sufficient damping of oscillations in the gate loop.

-

For a given driving voltage the values for the gate drive components can now be derived from equations (3).

V_DD= 8 V, for example, yields

-

C_C= 330 pF

R_ss= 3.3 k

R_tr= 50 … 120 

R_off= 15 (if used)

For more information regarding how to drive GaN HEMT refer to [2][3].

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

5

Typical characteristics

5.1

GaN switch characteristics

The following graphs refer to a single GaN switch.

10

9

8

7

6

5

4

3

2

1

0

10

9

I

= 2.6 mA

G

I

= 1.3 mA

G

8

7

6

5

4

3

2

1

0

I

= 0.26 mA

G

I

= 0.13 mA

G

I

= 2.6 mA

G

I

= 0.026 mA

G

I

= 1.3 mA

G

I

= 0.26 mA

G

I

= 0.013 mA

G

I

= 0.13 mA

G

I

= 0.026 mA

G

I

= 0.013 mA

G

0

2

4

6

8

10

0

2

4

6

8

10

V_DS[V]

I_D=f(V_DS,I_GS); T_j=25°C

I_D=f(V_DS,I_GS); T_j=125°C

Figure 9

1500

1400

1300

1200

1100

1000

900

Typical output characteristics

I

= 0.013 mA

G

I

= 0.026 mA

G

I

= 0.13 mA

G

I

= 0.26 mA

G

I

= 1.3 mA

G

I

= 2.6 mA

G

800

0

2

4

6

8

I_D[A]

R_DS(on)=f(I_D,I_G); T_j=125°C

R_DS(on)=f(T_j); I_D=0.8 A

Figure 10 Typical drain-source on-resistance

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

I_GS=f(V_GS,T_j); Open Drain

I_GS=f(V_GS,T_j); T_j=25°C

Figure 11 Typical gate characteristics forward and reverse

V_DS(V)

-6

-10

-8

-6

-4

-2

0

-12

-10

-8

-4

-2

0

-1

-2

-3

-4

-5

-6

-1

-2

-3

-4

-5

-6

V_GS

0V

-4V -3V

-5V

-2V -1V

0V

-1V

V_GS

-4V -3V

-2V

-5V

V_DS=f(V_GS,T_j); T_j=25°C

Figure 12 Typical channel reverse characterisitics

V_DS=f(V_GS,T_j); T_j=125°C

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

10.00

1.00

0.10

0.01

10.00

1.00

0.10

0.01

tp = 20ns

tp = 500ns

tp = 10us

tp = 100us

tp = 1ms

DC

tp = 500ns

tp = 10us

tp = 100us

tp = 1ms

limited by

R_DS(on)

DC

limited by

R_DS(on)

limited by thermals

limited by

thermals

limited by Vdsmax

limited by

Vdsmax

1

10

100

1000

1

10

100

1000

V_DS[V]

I_D=f(V_DS); T_c=25°C

I_D=f(V_DS); T_c=125°C

Figure 13

Safe Operating Area (SOA)

Typical V_DS-dependence of

terminal capacitances

Typical V_DS-dependence of

Output charge

Figure 14

Terminal capacitances and output charge (single switch)

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

3

2

1

0

200

400

600

V_DS[V]

Figure 15 Typical output energy (single switch)

5.2

Gate driver characteristics

Typical V_DDIquiescent current

vs. temperature

Typical V_DDIcurrent vs.

temperature and frequency

Figure 16 Supply current V_DDI

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

Typical V_DDL/Hquiescent current

vs. temperature

Typical V_DDL/Hcurrent vs.

switching frequency

Figure 17

Supply current V_DDL/H

Typical input voltage thresholds

vs. temperature

Typical undervoltage lockout thresholds

V_DDIvs. temperature

Figure 18 Logic input thresholds and V_DDIUVLO

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

Typical undervoltage lockout thresholds

V_DDL/Hvs. temperature

Figure 19 V_DDL/HUVLO

Typical propagation delays

vs. temperature

Typical rise and fall time vs. temperature

Figure 20 Propagation delay and rise / fall times

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

6

Application circuit

In Figure 21 a typical application example is given with IGI60F5050A1L operated in an actively clamped flyback

topology.

In this application the recommended values for the gate drive circuit are as follows:

V_DD= 8 V

C_C= 330 pF

R_ss= 3.3 k

R_tr= 50 … 120 

R_ss

V_in

V_out

C_C

V_DDL

R_tr

CoolGaN^TMIPS

OUTH

C_clmp

VDDH

DH

GH

R_VDDI

VDDI

C_out

Controller

UVLO

CT

C_VDDI

SLDON

RX

TX

SLDO

Logic

D_boot

C_boot

PWML

PWMH

GPIOx

INL

INH

Control

Logic

SW

CoolGaN^TM

VDDL

UVLO

V_DDL

TX

RX

ENABLE

C_VDDL

Logic

GND

GNDI

SL

R_sense

OUTL

GL

I_s

R_tr

C_C

R_ss

Figure 21 Application Circuit (active clamp flyback converter)

Final Datasheet

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7

Package information

Figure 22 TIQFN-28-1 8x8 package outline and footprint

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

8

Layout guidelines

Figure 23 shows the suggested arrangement of the power stage and the external components on the PCB based

on the schematic shown in the Figure 24.

Figure 25 and Figure 26 show the top and bottom layer of the PCB. The following layout recommendations should

be considered:

1. On the exposed pads’ landing area place vias with 0.3mm hole size with <0.7mm space (center to center)

2. Use solder mask expansion of 0.05~0.075mm for the chipset footprint pins and pads

3. Place and align the GND trace (PGND node for power return) beneath the DC bus trace on the top layer to

minimize the inductance loop in the power path.

4. For the low voltage controller reference (DGND) on the PGND trace select a location free of any switching

current to avoid switching-induced noise in DGND (do not connect the DGND trace to any trace which

connects the bypass cap to CoolGaN^TM).

Figure 23 CoolGaN^TMIPS external component placement on the PCB

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

Figure 24 CoolGaN^TMIPS circuitry with external passive components

Refer to Appendix (I) to download the footprint and the PCB example for Altium. Also, a complete PCB project with

this product is available in the CoolGaN^TMHalf-Bridge IPS Evaluation Board project.

Figure 25 Top layer of the PCB (trace on the left and top solder paste layer on the right)

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

Figure 26 Bottom layer of the PCB - top view (Trace on the left and silk mask on the right)

Final Datasheet

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IGI60F5050A1L CoolGaN^TMIntegrated Power Stage

9

Appendix

I.

PCB footpriont and Altium file for the reference PCB design can be found in the CoolGaN^TMHalf-bridge

IPS webpage (product registration is needed to access the design files)

II.


型号：	IGI60F5050A1L
厂家：	Infineon
描述：	CoolGaN™ IPS
文件：	总35页 (文件大小：1258K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IGI60F5050A1L [INFINEON]

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