IP1001PBF [INFINEON]
DC-DC Regulated Power Supply Module, 1 Output, Hybrid, SSBGA-218;
| 型号： | IP1001PBF |
| 厂家： | 
Infineon |
| 描述： | DC-DC Regulated Power Supply Module, 1 Output, Hybrid, SSBGA-218 电源电路 |
| 文件： | 总18页 (文件大小：506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 94336c
iP1001
Full Function Synchronous Buck Power Block
Integrated Power Semiconductors, Control IC & Passives
Features
• 3.3V to 12V input voltage1
• 20A maximum load capability, with no derating up to TPCB = 90°C
• 5 bit DAC settable, 0.925V to 2V output voltage range 2
• Configurable down to 3.3Vin & up to 3.3Vout with simple external circuit 3
• 200kHz or 300kHz nominal switching frequency
• Optimized for very low power losses
• Over & undervoltage protection
• Adjustable lossless current limit
• Internal features minimize layout sensitivity *
• Very small outline 14mm x 14mm x 3mm
iP1001 Power Block
Description
The iP1001 is a fully optimized solution for high current synchronous buck applications requiring up to 20A.
The iP1001 is optimized for single-phase applications, and includes a full function fast transient response
PWM control, with an optimized power semiconductor chip-set and associated passives, achieving benchmark
power density. Very few external components are required, including output inductor, input & output capacitors.
Further range of operation to 3.3Vin can be achieved with the addition of a simple external boost circuit, and
operation up to 3.3Vout can be achieved with a simple external voltage divider.
iPOWIR technology offers designers an innovative board space-saving solution for applications requiring high
power densities. iPOWIR technology eases design for applications where component integration offers
benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout,
heat transfer and component selection.
iP1001 Internal Block Diagram
VIN
D0
D1
5 Bit
D2
DAC
D3
D4
VSW
PWM
& Driver
ENABLE
PGOOD
ILIM
FREQ
VDD
PGND
VFS VF
SGND
GNDS
* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be
applied for the design of the power supply board. There are no concerns about unwanted shutdowns common to switching power supplies, if operated as specified. The
iPOWIR block will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable
and reliable long term operation. No additional bypassing is required on the Vdd pin. See layout guidelines in datasheet for more detailed information.
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1
05/20/03
All specifications @ 25°C (unless otherwise specified)
iP1001
Absolute Maximum Ratings
Parameter
Conditions
Symbol
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-
Typ
Max
16.0
6.0
Units
VIN to PGND
-
-
-
-
-
-
-
-
-
-
-
VDD to PGND
VFS
VF
V
V
V
DD+0.3
DD+0.3
DD+0.3
6.0
V
D0-D4
PGOOD to PGND
ENABLE to PGND
ILIM
6.0
VDD+0.3
V
DD+0.3
20
125
FREQ
Output RMS Current
Block Temperature
A
°C
TBLK
-40
Recommended Operating Conditions
Conditions
Parameter
Supply Voltage
Input Voltage Range 1
Output RMS Current from VSW 4
Symbol
Min
4.5
3.3
-
Typ
Max
5.5
12
Units
VDD
-
-
-
V
With 4.5V<VDD<5.5V
VIN
IoutVSW
20
A
V
DAC Setting
see VID code, Table1.
VOUT
Output Voltage Range 2
0.925
-
2.0
Electrical Specifications @ VDD = 5V & TPCB 0°C - 90°C (Unless otherwise specified)
Conditions
Parameter
Symbol
Min
Typ
Max
Units
300kHz, 12VIN, 1.3Vout, 20A
PLOSS
Power Loss
-
3.1
3.9
W
VIN=12V, VOUT=1.3V,
FREQ=300KHz, RLIM=340k
Over Current Shutdown
Soft Start Time
-
-
25
1.8
-
-
-
A
ms
%
All DAC codes
BLK = -40°C to 125°C
Output Voltage Accuracy
VF Input Resistance
Frequency
-2
2
T
-
-
-
-
181
200
300
4.2
-
-
-
-
kΩ
kHz
freq pin connected to VDD
freq pin floating
200mV hysteresis
FREQ
VDD Undervoltage Lockout
Output Undervoltage Shutdown
Threshold
Output Undervoltage Protection
Blanking Time
V
V
-
0.8
-
ENABLE going high on start-up
-
20
-
ms
Output Overvoltage Shutdown
Threshold at VF
PGOOD Trip Threshold
See OVP note in Design
Guidelines
At VF
PGOOD output high
Forced to 5.5V
-
-
-
2.25
VDAC -5%
1
-
-
-
V
V
PGOOD
PGOOD Leakage Current
µA
Isink = 1mA
D0-D4, Enable
D0-D4, Enable
PGOOD Output Low Voltage
Logic Input High Voltage
Logic Input Low Voltage
-
2.4
-
-
-
-
0.4
-
0.8
V
V
V
2
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iP1001
Electrical Specifications (continued)
Conditions
Parameter
Symbol
Min
Typ
25
600
-
Max
Units
mA
µA
mA
kΩ
VDD Operating Current
VDD Quiescent Current
VIN Quiescent Current
IVDD
IQVDD
IQVIN
Enable High, 300kHz
Shutdown mode
Enable Low, VIN = 12V
Measured ILIM pin to SGND
-
-
-
-
-
-
1
-
300
ILIM to SGND Internal Resistance
Notes :
1
2
For Vin less than 4.5V requires external 5VDD supply.
Can be modified to operate up to 3.3VOUT, outside of DAC settable range. See Design Guidelines on how to set
output voltage greater than 2V.
See design guidelines.
See Fig. 5 for Recommended Operating Area
3
4
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3
iP1001
Guaranteed Performance Curves
22
5.0
20
18
4.5
VIN = 12V
OUT = 1.3V
BLK=125°C
sw set to 300kHZ
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
Maximum
16
14
12
10
8
T
f
Safe Operating Area
Typical
VIN = 12V
VOUT = 1.3V
6
f
sw set to 300kHZ
4
2
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130
0
2
4
6
8
10
12
14
16
18
20
PCB Temperature (°C)
Output Current (A)
Fig 1. Power Loss vs Current
Fig 2. Safe Operating Area (SOA) vs TPCB
Adjusting the Power Loss and SOA curves for different operating conditions
To make adjustments to the power loss curves in Fig. 1, multiply the normalized value obtained from the curves in Figs. 3,
or 4 by the value indicated on the power loss curve in Fig. 1. If multiple adjustments are required, multiply all of the
normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 1. The resulting
product is the final power loss based on all factors.
To make adjustments to the SOA curve in Fig. 2, determine the maximum allowed PCB temperature in Fig. 2 at the required
operating current. Then, add the correction temperature from the normalized curves in Figs. 3 or 4 to find the final maximum
allowable PCB temperature. When multiple adjustments are required, add all of the temperatures together, then add the sum
to the PCB temperature indicated on the SOA graph to determine the final maximum allowable PCB temperature based on
all factors.
Note: If input voltage <5Vin nominal operation is required then first see Fig. 5 for maximum current capability limit.
Operating Conditions for the examples below:
Output Current = 20A
Output Voltage = 2.5V
Input Voltage = 7V
Adjusting for Maximum Power Loss:
(Fig. 1) Maximum power loss =5 W
(Fig. 3) Normalized power loss for output voltage ≈1.14
(Fig. 4) Normalized power loss for input voltage ≈0.89
Adjusted Power Loss = 5W x 0.89 x 1.14 ≈ 5.07W
Adjusting for SOA Temperature:
(Fig. 2) SOA PCB Temperature = 90°C
(Fig. 3) Normalized SOA PCB Temperature for output voltage ≈ -4.5°C
(Fig. 4) Normalized SOA PCB Temperature for input voltage ≈ 4°C
Adjusted SOA PCB Temperature = 90°C + 4°C -4.5°C ≈ 89.5°C
4
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iP1001
Typical Performance Curves
1.36
1.30
1.24
1.18
1.12
1.06
1.00
0.94
0.88
-13
-11
-9
-6
-4
-2
0
1.00
0.97
0.94
0.91
0.89
0.86
0.83
0
1
2
3
4
5
6
VIN = 12V
VOUT = 1.3V
IOUT = 20A
IOUT = 20A
fsw set to 300kHz
TBLK = 125°C
f
sw set to 300kHz
TBLK = 125°C
2
4
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3
4
5
6
7
8
9
10 11 12
Output Voltage (V)
Input Voltage (V)
Fig 4. Normalized Power Loss vs VIN
Fig 3. Normalized Power Loss vs VOUT
25
20
15
10
5
VIN = 5V to 12V
200kHz/300kHz
For 200kHz frequency setting there will be a
10% power loss reduction and a positive PCB
temperature adjustment of 3°C.
VIN = 3.3V,
200kHz
0
0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
Output Voltage (V)
Fig 5. Recommended Operating Area
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5
iP1001
D4
D3
D2
D1
D0
OUTPUT
VOLTAGE(V)
2.00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
Shutdown*
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
Shutdown*
* Shutdown : Upon receipt of the shutdown code (per VID code table above), both FETs are turned OFF and
the output is discharged as the undervoltage protection is activated.
Table 1. VID Code Table2
900
800
700
600
500
400
300
200
100
0
6
11
16
21
26
31
36
Typical Current Limit Setting in Amps
Fig 6. Overcurrent adjustment settings using RLIM
6
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iP1001
Pin Name
VIN
Ball Designator
Pin Description
A9-A12, B9-B12, C9-
C14, D9-D14, E9-E16,
F9-F16, G9-G16
Input voltage connection node.
A1, A6-A7, A13-A15,
B1, B6-B7, B13-B16,
C3, C6-C7, C15-C16,
D3-D4, D6, D15-D16
E3-E6, F1-F5, G1-G5,
H1-H5, J1-J2, J6-J8,
K6-K8, L6-L8, M 6-M8,
N4-N5, N7-N8, P4-P5,
P7-P8, R6-R8, S6-S8
H9-H14, J11-J14, K11-
K14, L11-L14, N11-
N14, M11-M 14, P11-
P14, R11-R14, S11-S14
H15-H16, J15-J16, K9-
K10, K15-K16, L9-
NC
No electrical connection.
VSW
Output inductor connection node.
Power ground.
L10, L15-L16, M 9-
PGND
M 10, M15-M 16, N9-
N10, N15-N16, P9-P10,
P15-P16, R9-R10, R15-
R16, S9-S10, S15-S16
R4-R5, S4-S5
A2-A3, B2-B3
VDD
SGND
Control Power connection node
Signal ground.
Rem ote Ground Sense Pin. Connect to PGND for
GNDS
ENABLE
NC
E1
VOU T >2V
Com m ands output ON or OFF. Active floating
(internally pulled high). When logic low, the
synchronous M OSFET is turned ON.
No electrical connection, internally pulled high,
must leave floating.
Internally pulled-up to VDD.
Output voltage feedback local sense.
R3, S3
R2, S2
PGOOD
VF
R1, S1
C1-C2
Output voltage rem ote sense feedback signal. For
greater than 2VOUT, disconnect from rem ote load
and connect to VF.
VFS
D1-D2
D0
D1
D2
D3
D4
P1-P2
N1-N2
M 1-M 2
L1-L2
K1-K2
VID code setting D/A inputs. Internally pulled high.
Current lim it threshold setting pin. See ILIM curve
for external resistor values.
Switching frequency selector pin. Floating selects
300kHz, tied to VDD selects 200kHz.
ILIM
A5, B5, C5
A4, B4
FREQ
Table 2. Pin Description
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7
iP1001
P = VIN Average x I Average
PIN = VDD Average xINIDD Average
PODDUT = V Average x IOUT Average
PLOSS = (OPUITN + PDD) - POUT
Average
VDD
Current
Average
Input
Current
A
A
Average
VDD
Voltage
Average
Input
Voltage
V
V
DC
DC
Average Output
Current
VO
VOS
VSW
A
PGOOD
D4
D3
Averaging
Circuit
D2
D1
D0
FREQ
Average
Output
Voltage
V
iP1001
ENABLE
ILIM
VF
VFS
GNDS
Fig 7. Power loss test circuit
8
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iP1001
FREQ
SGND
NC
NC
NC NC
NC
ILIM
NC
NC
V
F
NC
NC
NC
V
FS
NC NC
V
IN
GNDS
NC
NC
NC
NC
NC
NC
NC
NC NC NC
NC
NC NC
NC
D4
D3
NC
V
NC NC
NC
D2
D1
D0
SW
PGND
PGND
NC
NC
NC
NC
V
NC NC
DD
PGOOD
ENABLE
Fig 8. Recommended PCB Footprint (Top View)
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9
iP1001
PGOOD
iP1001 User’s Design Guidelines
The PGOOD comparator constantly monitors VF for
undervoltage. A 5% drop in output voltage can cause
PGOOD to go low. PGOOD pin is internally pulled-
up to V through a 100K, 5% resistor. If it is desired
to use DthDe PGOOD signal to enable another stage
using iP1001, then it is recommended to filter and
buffer PGOOD to prevent transients appearing at
The iP1001 is a 20A power block that consists of
optimized power semiconductors, PWM control and
its associated passive components. It is based on
a synchronous buck topology and offers an optimized
solution where space, efficiency and noise caused
by stray parasitics are of concern. The iP1001 com-
ponents are integrated in a ball grid array (BGA) pack-
age where the electrical and thermal conduction is
accomplished through solder balls.
the output from pulling PGOOD low.
OVP (Output Overvoltage Protection)
If the overvoltage trip 2.25V threshold is reached, the
OVP is triggered, the circuit is shutdown and the
bottom FET is latched on discharging the output filter
capacitor. Pulling ENABLE low resets the latch. The
overvoltage trip threshold is scaled accordingly, if
output voltages greater than 2V are set through
voltage dividers.
FUNCTIONAL DESCRIPTION
VIN
The standard iP1001 operating input voltage range
is 5V to 12V. The input voltage can also be easily
configured to run at voltages down to 3.3V.
UVP (Output Undervoltage Protection)
FREQ
The Output Undervoltage Protection trip threshold is
fixed at 0.8V. If ENABLE is pulled up and VF is below
0.8V for a duration of 10-20ms, the PWM will be in a
latched state, with the bottom FET latched on, and
will not restart until ENABLE is recycled.
The PWM control is pseudo current mode. The ESR
of the output filter capacitor is used for current sens-
ing and the output voltage ripple developed across
the ESR provides the PWM ramp signal.
iP1001 offers two switching frequency settings,
200kHz and 300kHz. At a given setting the switching
frequency will remain relatively constant indepen-
dent of load current.
DAC Converter (D0-D4)
The output voltage is programmed through a 5-bit
DAC (see the VID code in table 1). The output volt-
age can be programmed from 0.925V to 2V. To elimi-
nate external resistors, the DAC pins are internally
pulled up. To set for output voltages above 2V, the
DAC must be set to 2V and a resistor divider,
R3 & R4 (see Fig 10.), is used. The values of the
resistors are selected using equation 1.
VDD (+5V bias)
An external 5V bias supply is required to operate the
iP1001. In applications where input voltages are
lower than 4.5V, and where 5V is not available, a
special boost circuit is required to supply VDD with 5V
(as shown in the reference design).
Equation 1 : Vout = VF x (1 + R3/R4)
where VF is equal to the DAC setting
and R4 is recommended to be ~1kΩ
Soft Start, VDD Undervoltage Lockout
When V rises above 4.2V a soft start is initiated by
rampingDDthe maximum allowable current limit. The
ramp time is typically 1.8ms. An external capacitor
can be added across the current limit resistor from
ILIM to PGND to provide up to 5ms ramp time. Select
the capacitor according to the 10nf/ms rule.
Bottom
ENABLE
Low
Mode
Shutdown
Comments
FET
ON
DAC code = X1111, Both FETs
are turned OFF.
High
OFF
Shutdown
High
Switching
PWM (Running)
Fault latch set by OVP or UVP.
This mode will sustain until VDD
is cycled or ENABLE is reset.
High
ON
Fault
Table 3 - iP1001 Operating Truth Table
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10
iP1001
DESIGNPROCEDURE
Inductor Selection
A 470µF POSCAP capacitor has a maximum 35mΩ
of ESR which provides 9.7kHz zero frequency.
The ESR zero frequency must be set below 12kHz.
This value is calculated assuming the capacitor
datasheet maximum ESR value.
The inductor is selected according to the following
expression.
L = VOUT x (1-D) / (fsw x ∆IL)
where, D = V / V
OUT
IN
Example:
To determine the amount of capacitance
to meet a 30mVp-p output ripple, with 4A
inductor current ripple requirement.
V
is the output voltage in Volts,
fsOwUTis the switching frequency in kHz,
∆IL is the output inductor ripple current.
The calculated ESR will be = 30mV/4A =
7.5mΩ. This will require 5 x 470uF POSCAP
capacitors. The total ESR will result in a
9.7kHz zero frequency.
The inductor value should be selected from 0.8µH
to 2.0µH range.
Output Capacitor Selection
For stable operation:
• Set the resonant frequency fo of the output
inductor and capacitor between 2kHz and 4kHz.
The resonant frequency is calculated using the
following expression:
Use tantalum or POSCAP type capacitors for iP1001.
Selection of the output capacitors depends on
several factors.
• Low effective ESR for ripple and load transient
requirements.
fo = 1/ (2π x (√LC))
• Stability.
To support the load transients and to stay within a
specified voltage dip ∆V due to the transients, ESR
selection should satisfy the following equation:
• Select the output inductor value between 0.8µH
to 2.0µH and the output capacitance between
1880µF (4x 470µF) and 5600µF (12x470µF)
R
ESR ≤ ∆V/∆I
• Set the minimum output ripple voltage to be
greater than 0.5% of the output voltage. Select the
capacitor by ESR and by voltage rating rather than
capacitance.
where, ∆I is the transient load step
If output voltage ripple is required to be maintained
at specified levels then, the following expression
should be used to select the output capacitors.
External Input Capacitor Selection
The switching currents impose RMS current
requirements on the input capacitors. The following
expression allows the selection of the input
capacitors, based on the input RMS current:
RESR ≤ Vp-p / ∆IL
where, Vp-p is the peak to peak output voltage ripple.
IRMS = ILOAD x ( √D x (1-D))
The value of the output capacitor ESR zero frequency
also determines stability. The value of the ESR zero
frequency is calculated by the expression:
where, D = VOUT/VIN
RESR = 1 / (2π x fESR x COUT
)
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iP1001
Application Issues
Setting VOUT above 2V
In certain applications where the output voltage is
required to be set higher than the maximum DAC
code setting of 2V, it is possible to use an external
resistive voltage divider which, for accuracy, needs
to have 1% or better tolerance. The switching
frequency should be set at 200kHz by connecting
the FREQ pin to VDD. Also, the output voltage should
never be set higher than 3.3V with a VIN minimum of
5V, or 2.5V with a VIN minimum of 3.3V. The DAC
code should be set to 2V and the following equation
used to select the resistors:
VOUT = VF x (1 + R3/R4)
See the reference design for reference designators.
Note that the impedance at V is 180KΩ ±35%. It is
recommended that R3 be cFalculated assuming a
value of 1kΩ for R4. Connect VFS to VF and GNDS to
PGND.
Duty Cycle D = VOUT / VIN >50%
For duty cycles >50% the switching frequency should
be set at 200kHz. 300kHz switching frequency can
be selected if the output is less than 2V and the duty
cycle is <50%.
For duty cycles >50%, add external compensation
ramp from the Vsw terminal of the iP1001 device as
shown in the reference design through R9 resistor
and C21 capacitor (Fig 10a.). For optimum perfor-
mance maintain a RC time constant of approximately
5µs.
12
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iP1001
Layout Guidelines
For stable and noise free operation of the whole
power system it is recommended that the designer
uses to the following guidelines.
5. Although there is a certain degree of VIN
bypassing inside the iP1001, the external input
decoupling capacitors should be as close to the
device as possible.
1. Follow the layout scheme presented in Fig.9.
Make sure that the output inductor L1 is placed as
close to the iP1001 as possible to prevent noise
propagation that can be caused by switching of
power at the switching node VSW, to sensitive circuits.
6. In situations where the load is located at an
appreciable distance from the iP1001 block, it is
recommended that at least one or two capacitors
be placed close to the iP1001 to derive the VF
signal.
2. Provide a mid-layer solid ground with connections
to the top layer through vias. The two PGND pads of
the iP1001 also need to be connected to the same
ground plane through vias.
7. The VF connection to the output capacitors should
be as short as possible and should be routed as
far away from noise generating traces as possible.
3. Do not connect SGND pins of the iP1001 to PGND.
8. V & GNDS pins need to be connected at the
loadFSfor remote sensing. If remote sensing is not
used connect VFS to VF and GNDS to PGND.
4. To increase power supply noise immunity, place
input and output capacitors close to one another, as
shown in the layout diagram. This will provide short
high current paths that are essential at the ground
terminals.
9. Refer to IR application noteAN-1029 to determine
what size vias and what copper weight and
thickness to use when designing the PCB.
iP1001 Block
Input Caps (CIN)
V
IN
Input
Terminal
PGND
VSW
Load
Terminal
PGND
Output Caps (COUT
)
VOUT
Output Inductor (L1)
Fig 9. iP1001 suggested layout
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13
iP1001
iP1001 Reference Design
The schematics in Fig.10a & 10b and complete Bill
of Materials in Table 4 are provided as a reference
design to enable a preliminary evaluation of iP1001.
They represent a simple method of applying the
iP1001 solution in a synchronous buck topology.
Fig. 10a shows the implementation for <5V
nominal applications, and Fig. 10b shows thIeN
implementation for 5VIN
applications.
-
12VIN nominal
The connection pins are provided through the solder
balls on the bottom layer of the package. A total
power supply solution is presented with the addition
of inductor L1 and the output capacitors C11-C14.
Input capacitors C1-C10 are for bypassing in the
5V - 12VIN application, but only C1-C3 are required
forIN<5VIN applications (refer to the BOM for values).
Switches 1-5 of SW1 are used to program the output
voltage. Refer to the VID table provided in this
datasheet for the code that corresponds to the
desired output voltage. Resistors R2 & R4 need to
be removed for operation at standard VID levels
(0.925V - 2.0V, leave R3 = 0Ω). Switch 8 of SW1
enables the output when floating (internally pulled
high). The 5V VDD power terminal and input power
terminals are provided as separate inputs. They
can be connected together if the application
requires only 5V nominal input voltage.
The reference design also offers a higher output
voltage option for greater than 2.0V, up to 3.3V. For
output voltages above 2V, the DAC setting must be
set to 2V, and then select resistors R3 & R4 per
Equation 1 on page 10 for the desired output volt-
age. Remove R5 and connect VF to VFS through R2,
where R2=0Ω. In this case, GNDS should be refer-
enced to PGND. Tighter regulation can be achieved
by using resistors with less than 1% tolerance. For
Vin < 5V and Vout > 2V, the frequency select pin
(FREQ) must be set to 200kHz (connected to VDD).
For applications with VIN < 5V and where there is no
auxiliary 5V available, connections JP2 and JP3
must be provided in order to enable the boost cir-
cuit. This will provide 5V V necessary for the
iP1001 internal logic to functiDoDn. The boost circuit
will convert 3.3V input voltage to 5V, to power the
V , and will provide enough power to supply the
inDteD rnal logic for up to five iP1001 power blocks.
14
www.irf.com
iP1001
Optional
U2
1
2
3
4
8
7
6
5
FB
OUT
LX
L2
C17
10µF
C18
10µF
LBI
LBO
REF
22µH
GND
C20
1µF
SHDN
C19
0.1µF
MAX1675
JP3
JP2
R8
100K
VIN
3.3-4.5V
JP1
1
2
C1
C2
C3
100uF 100uF 100uF
6.3V
6.3V
6.3V
+5V
TP1
U1
TP4
VO
VOS
L1
1.06uH
R1
VSW
VOUT
0
TP3
C11
470uF 470uF 470uF 470uF
6.3V 6.3V 6.3V 6.3V
C12
C13
C14
PGOOD
D1
C16
0.1µF
10MQ040N
SW1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGND
D4
D3
D2
D1
D0
FREQ
PGND
+5V
R9
R3
R4
iP1001
TP5
91K
ENABLE
ILIM
C21
47pF
R6
0
R5
R7
340K, 1%
VF
R2
VFS
GNDS
TP2
Fig 10a. - Reference Design Schematic For <4.5VIN
VIN
5-12V
C1
C2
C3
C4
C5
C6
C7
10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
C8
C9
C10
25V
25V
25V
25V
25V
25V
25V
25V
25V 25V
+5V
TP1
U1
TP4
VO
VOS
L1
1.06uH
R1
VSW
VOUT
0
TP3
C11
470uF 470uF 470uF 470uF
6.3V 6.3V 6.3V 6.3V
C12
C13
C14
PGOOD
D1
C16
0.1µF
10MQ040N
SW1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGND
D4
D3
D2
D1
D0
FREQ
PGND
+5V
R3
R4
iP1001
TP5
ENABLE
ILIM
R6
0
R5
R7
340K, 1%
VF
R2
VFS
GNDS
TP2
Fig 10b. - Reference Design Schematic For 5VIN - 12VIN Nominal
www.irf.com
15
iP1001
Designator
C1, C3, C5
IRDCiP1001-A (For operation <4.5VIN)
Value
100uF
-
Part Type
Capacitor, 6.3V, 20%, X5R
Not Installed
Footprint
1812
-
Mfr.
TDK
Mfr. P/N
C4532X5R0J107MT
-
C2, C4, C6, C7, C8, C9, C10, C15
C11, C12, C13, C14
-
Sanyo
470uF
0.100uF
10.0uF
1.00uF
47.0pF
40V
Capacitor, 6.3V, 20%, Tantalum
Capacitor, 50V, 10%, X7R
Capacitor, 16V, 10%, X5R
Capacitor, 10V, 10%, X7R
Capacitor, 50V, 5%, C0G
Schottky Diode, 40V, 2.1A
Test Point
7343
1206
1210
0805
1206
D-64
-
6TPB470M
C16, C19
C17, C18
Novacap
TDK
1206B104K500N
C3225X5R1C106KT
GRM40X7R105K010
GRM42-6C0G470J050A
10MQ040N
C20
C21
MuRata
MuRata
International Rectifier
Samtec
D1
JP1, JP2, JP3
JP1-1, JP2-1, JP3-1
-
TSW-102-07-LS
SNT-100-BKT
ETQP6F1R1BFA
CR43-220
-
Shunt
-
Samtec
Panasonic
Sumida
L1
L2
R1
1.06uH
22uH
0:
Inductor, 16A, 20%, Ferrite
Inductor, 0.68A, 20%, Ferrite
Resistor, 0: Jumper
SMT
SMT
2716
Isotek Corp
SMT-R000
For <2Vout, Not installed
For >2Vout, Resistor, 0: Jumper
For <2Vout, Resistor, 0: Jumper
For >2Vout see formula for value
For <2Vout, Not installed
For >2Vout recommend 1k:
see formula for detail
R2
R3
-
SMT
SMT
-
-
-
-
-
-
SMT
-
-
R4
R5
R6
For <2Vout, Resistor, 0: Jumper
For >2Vout, Not installed
Resistor, 0: Jumper
-
1206
1206
Panasonic
-
ERJ-8GEY0R00
-
0:
Resistor, 340k:, 1%
R7
340k:
1206
ROHM
MCR18EZHF3403
340k: sets for 20A limit.
See ILIM formula for other values
Resistor, 100k:, 5%
R8
R9
1206
1206
SMT
ROHM
ROHM
MCR18EZHJ104
MCR18EZHJ913
SD08H0SK
-
100k:
91k:
-
-
-
Resistor, 91k:, 5%
8-position DIP switch
SW1
TP1, TP3
TP2, TP4, TP5
C&K Components
-
Keystone
Not Installed
Test Point
-
-
1502-2
SSBGA
14mmx14mm
8uMAX
U1
U2
-
-
Power Block
International Rectifier
Maxim
iP1001
IC, Step-Up DC-DC Converter, 0.5A
MAX1675EUA
IRDCiP1001-B (For operation 5VIN to 12VIN)
Designator
Value
Part Type
Footprint
Mfr.
Mfr. P/N
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 10.0uF
Capacitor, 25V, 10%, X5R
1812
MuRata
GRM43-2X5R106K25A
C11 C12 C13 C14
470uF
Capacitor, 6.3V, 20%, Tantalum
Capacitor, 50V, 10%, X7R
Not Installed
7343
Sanyo
6TPB470M
C16
0.100uF
1206
Novacap
1206B104K500N
C15, C17, C18, C19, C20, C21
-
-
-
-
D1
40V
Schottky Diode, 40V, 2.1A
Not Installed
D-64
International Rectifier
10MQ040N
JP1, JP2, JP3
-
-
-
-
JP1-1, JP2-1, JP3-1
-
1.06uH
-
Not Installed
-
-
-
ETQP6F1R1BFA
-
L1
L2
R1
Inductor, 16A, 20%, Ferrite
Not Installed
SMT
-
Panasonic
-
2716
Isotek Corp
SMT-R000
0:
Resistor, 0: Jumper
For <2Vout, Not installed
For >2Vout, Resistor, 0: Jumper
For <2Vout, Resistor, 0: Jumper
For >2Vout see formula for value
For <2Vout, Not installed
For >2Vout recommend 1k:
see formula for detail
For <2Vout, Resistor, 0: Jumper
For >2Vout, Not installed
Resistor, 0: Jumper
R2
R3
-
SMT
SMT
-
-
-
-
-
R4
-
SMT
-
-
R5
R6
-
1206
1206
Panasonic
-
ERJ-8GEY0R00
-
0:
Resistor, 340k:, 1%
R7
340k:
1206
ROHM
MCR18EZHF3403
340k: sets for 20A limit.
See ILIM formula for other values
Not Installed
R8, R9
SW1
-
-
-
-
-
-
-
SD08H0SK
1502-2
-
8-position DIP switch
Test Point
SMT
C&K Components
TP1 TP2 TP4 TP5
TP3
-
-
Keystone
-
Not Installed
SSBGA
U1
U2
-
-
Power Block
Not Installed
International Rectifier
-
iP1001
-
14mmx14mm
-
Table 4 - Reference Design Bill of Materials
16
www.irf.com
iP1001
0.15 [.006]
2X
C
14.00
[.551]
B
A
6
5
C
0.45 [.0177]
0.35 [.0138]
BALL A1
CORNER ID
0.12 [.005]
C
14.00
[.551]
NOTES:
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
3. CONTROLLING DIMENSION: MILLIMETER
4. SOLDER BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
5
6
7
PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE
PACKAGE BODY.
0.15 [.006]
2X
C
TOP VIEW
6
SOLDER BALL DIAMETER IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER, IN A PLANE PARALLEL TO DATUM C.
0.55 [.0216]
0.45 [.0178]
218X Ø
7
0.15 [.006]
0.08 [.003]
C
C
A B
2.66 [.1047]
2.46 [.0969]
0.40
[.016]
(4X 1.0 [.039])
0.80
[.032]
3.11 [.1224]
2.81 [.1107]
4X
30X
BOTTOM VIEW
SIDE VIEW
Mechanical Drawing
Refer to the following application notes for detailed guidelines and suggestions when implementing
iPOWIR Technology products:
AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier’s
iPOWIR Technology BGA Packages
This paper discusses the assembly considerations that need to be taken when mounting iPOWIR BGA’s
on printed circuit boards. This includes soldering, pick and place, reflow, inspection, cleaning and
reworking recommendations.
AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design
This paper describes how to optimize the PCB layout design for both thermal and electrical performance.
This includes placement, routing, and via interconnect suggestions.
AN-1030:Applying iPOWIR Products in Your Thermal Environment
This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the
operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product.
www.irf.com
17
iP1001
0123
XXXX
iP1001
TOP
Part Marking
24mm
0123
0123
XXXX
iP1001
XXXX
iP1001
FEED DIRECTION
20mm
NOTES:
1. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Tape & Reel Information
Data and specifications subject to change without notice.
This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.03/02
18
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