IPD50N10S3L-16 [INFINEON]

OptiMOS-T Power-Transistor; 的OptiMOS -T电源晶体管
IPD50N10S3L-16
型号: IPD50N10S3L-16
厂家: Infineon    Infineon
描述:

OptiMOS-T Power-Transistor
的OptiMOS -T电源晶体管

晶体 晶体管 功率场效应晶体管 脉冲
文件: 总9页 (文件大小:185K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
IPD50N10S3L-16  
OptiMOS®-T Power-Transistor  
Product Summary  
VDS  
100  
15  
V
R DS(on),max  
I D  
m  
A
50  
Features  
• N-channel - Enhancement mode  
PG-TO252-3-11  
• Automotive AEC Q101 qualified  
• MSL1 up to 260°C peak reflow  
• 175°C operating temperature  
• Green product (RoHS compliant)  
• 100% Avalanche tested  
Type  
Package  
Marking  
IPD50N10S3L-16  
PG-TO252-3-11 QN10L16  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol  
Conditions  
Unit  
I D  
T C=25°C, VGS=10V  
Continuous drain current  
50  
A
T C=100°C, VGS=10V1)  
38  
Pulsed drain current1)  
Avalanche energy, single pulse1)  
I D,pulse  
EAS  
T C=25°C  
I D=25A  
200  
330  
mJ  
A
I AS  
Avalanche current, single pulse  
50  
Gate source voltage2)  
VGS  
±20  
V
Ptot  
T C=25 °C  
Power dissipation  
100  
W
°C  
T j, T stg  
Operating and storage temperature  
IEC climatic category; DIN IEC 68-1  
-55 ... +175  
55/175/56  
Rev. 1.1  
page 1  
2008-04-09  
IPD50N10S3L-16  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics1)  
R thJC  
R thJA  
Thermal resistance, junction - case  
SMD version, device on PCB  
-
-
-
-
-
-
1.5  
62  
40  
K/W  
minimal footprint  
6 cm2 cooling area3)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V(BR)DSS  
VGS(th)  
V
V
GS=0V, I D= 1mA  
DS=VGS, I D=60µA  
Drain-source breakdown voltage  
Gate threshold voltage  
100  
1.2  
-
-
V
1.7  
2.4  
V
DS=80V, VGS=0V,  
I DSS  
Zero gate voltage drain current  
-
-
0.01  
1
0.1  
10  
µA  
T j=25°C  
V
DS=80V, VGS=0V,  
T j=125°C1)  
I GSS  
V
V
V
GS=16V, VDS=0V  
GS=4.5V, I D=50A  
GS=10 V, I D=50 A  
Gate-source leakage current  
-
-
-
-
100 nA  
R DS(on)  
Drain-source on-state resistance  
15.3  
12.5  
19.9  
15.0  
mΩ  
Rev. 1.1  
page 2  
2008-04-09  
IPD50N10S3L-16  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Dynamic characteristics1)  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t r  
-
-
-
-
-
-
-
3215  
730  
63  
10  
5
4180 pF  
950  
V
GS=0V, VDS=25V,  
f =1MHz  
95  
-
-
-
-
ns  
V
DD=20V, VGS=10V,  
I D=50A, R G=3.5Ω  
t d(off)  
t f  
Turn-off delay time  
Fall time  
29  
5
Gate Charge Characteristics1)  
Gate to source charge  
Gate to drain charge  
Gate charge total  
Q gs  
-
-
-
-
9
8
12  
12  
64  
-
nC  
Q gd  
V
V
DD=80V, I D=50A,  
GS=0 to 10V  
Q g  
49  
3.7  
Vplateau  
Gate plateau voltage  
V
A
Reverse Diode  
Diode continous forward current1)  
Diode pulse current1)  
I S  
-
-
-
-
50  
T C=25°C  
I S,pulse  
200  
V
GS=0V, I F=50A,  
VSD  
Diode forward voltage  
Reverse recovery time1)  
Reverse recovery charge1)  
0.6  
1
1.2  
V
T j=25°C  
VR=50V, I F=I S,  
diF/dt =100A/µs  
t rr  
-
-
97  
-
-
ns  
nC  
Q rr  
178  
1) Defined by design. Not subject to production test.  
2) Qualified with VGS = +20/-5V.  
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
Rev. 1.1  
page 3  
2008-04-09  
IPD50N10S3L-16  
1 Power dissipation  
2 Drain current  
P
tot = f(T C); VGS 6 V  
I D = f(T C); VGS 6 V  
120  
100  
80  
60  
40  
20  
0
60  
50  
40  
30  
20  
10  
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T
C [°C]  
T
C [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
thJC = f(t p)  
I D = f(VDS); T C = 25 °C; D = 0  
parameter: t p  
Z
parameter: D =t p/T  
101  
1000  
100  
10  
1 µs  
100  
0.5  
10 µs  
0.1  
100 µs  
10-1  
0.05  
0.01  
10-2  
1 ms  
single pulse  
10-3  
1
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
0.1  
1
10  
100  
t p [s]  
V
DS [V]  
Rev. 1.1  
page 4  
2008-04-09  
IPD50N10S3L-16  
5 Typ. output characteristics  
I D = f(VDS); T j = 25 °C  
parameter: VGS  
6 Typ. drain-source on-state resistance  
DS(on) = f(I D); T j = 25 °C  
R
parameter: VGS  
200  
50  
10 V  
5 V  
4 V  
3 V  
3.5 V  
4.5 V  
160  
120  
80  
40  
0
40  
4.5 V  
30  
20  
4 V  
5 V  
3.5 V  
3 V  
10 V  
10  
0
0
1
2
3
4
5
6
40  
80  
D [A]  
120  
160  
V
DS [V]  
I
7 Typ. transfer characteristics  
I D = f(VGS); VDS = 6V  
parameter: T j  
8 Typ. drain-source on-state resistance  
R
DS(on) = f(T j); I D = 50 A; VGS = 10 V  
160  
120  
80  
40  
0
30  
-55 °C  
25 °C  
25  
20  
15  
10  
5
175 °C  
1
2
3
4
5
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
V
GS [V]  
Rev. 1.1  
page 5  
2008-04-09  
IPD50N10S3L-16  
9 Typ. gate threshold voltage  
GS(th) = f(T j); VGS = VDS  
10 Typ. capacitances  
V
C = f(VDS); VGS = 0 V; f = 1 MHz  
parameter: I D  
2.5  
104  
103  
102  
Ciss  
2
1.5  
1
300 µA  
60 µA  
Coss  
Crss  
0.5  
101  
0
0
5
10  
15  
20  
25  
30  
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
V
DS [V]  
11 Typical forward diode characteristicis  
12 Typ. avalanche characteristics  
A S= f(t AV  
IF = f(VSD)  
I
)
parameter: T j  
parameter: Tj(start)  
103  
102  
101  
100  
25 °C  
100 °C  
150 °C  
10  
1
25 °C  
175 °C  
100  
0.1  
0.1  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1
10  
AV [µs]  
100  
1000  
V
SD [V]  
t
Rev. 1.1  
page 6  
2008-04-09  
IPD50N10S3L-16  
13 Typical avalanche energy  
AS = f(T j)  
14 Typ. drain-source breakdown voltage  
E
V
BR(DSS) = f(T j); I D = 1 mA  
parameter: I D  
115  
600  
12.5 A  
500  
110  
105  
100  
95  
400  
300  
25 A  
200  
50 A  
100  
90  
0
-55  
-15  
25  
65  
105  
145  
25  
75  
125  
175  
T j [°C]  
T j [°C]  
15 Typ. gate charge  
16 Gate charge waveforms  
V
GS = f(Q gate); I D = 50 A pulsed  
parameter: VDD  
10  
9
8
7
6
5
4
3
2
1
V GS  
Q g  
20 V  
80 V  
V gs(th)  
Q g(th)  
Q sw  
Q gd  
Q gate  
Q gs  
0
0
10  
20  
Q
30  
gate [nC]  
40  
50  
Rev. 1.1  
page 7  
2008-04-09  
IPD50N10S3L-16  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© Infineon Technologies AG 2008  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions  
or characteristics. With respect to any examples or hints given herein,  
any typical values stated herein and/or any information regarding the application of the device,  
Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including  
without limitation warranties of noninfringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices please  
contact your nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements components may contain dangerous substances. For information  
on the types in question please contact your nearest Infineon Technologies Office.  
Infineon Technologies Components may only be used in life-support devices or systems with the  
express written approval of Infineon Technologies, if a failure of such components can reasonably  
be expected to cause the failure of that life-support device or system, or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be  
implanted in the human body, or to support and/or maintain and sustain and/or protect human life.  
If they fail, it is reasonable to assume that the health of the user or other persons may be  
endangered.  
Rev. 1.1  
page 8  
2008-04-09  
IPD50N10S3L-16  
Revision History  
Version  
Date  
Changes  
Page 1: VGS changed from ±16V  
08.04.2008 to ±20V  
1.1  
1.1  
08.04.2008 Page 3: Footnote 2) added  
Page 1: EAS changed from 264mJ  
09.04.2008 to 330mJ  
1.1  
Rev. 1.1  
page 9  
2008-04-09  

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