IPS075N03LG [INFINEON]
OptiMOS Power-Transistor Feature Enhancement mode Logic Level Avalanche rated; 的OptiMOS功率三极管特性增强模式的逻辑电平额定雪崩
| 型号： | IPS075N03LG |
| 厂家： | 
Infineon |
| 描述： | OptiMOS Power-Transistor Feature Enhancement mode Logic Level Avalanche rated |
| 文件： | 总12页 (文件大小：550K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IPD075N03L G
IPS075N03L G
IPF075N03L G
IPU075N03L G
OptiMOS®3 Power-Transistor
Product Summary
Features
V DS
30
7.5
50
V
• Fast switching MOSFET for SMPS
• Optimized technology for DC/DC converters
• Qualified according to JEDEC1) for target applications
R DS(on),max
I D
mΩ
A
• N-channel, logic level
• Excellent gate charge x R DS(on) product (FOM)
• Very low on-resistance R DS(on)
• Avalanche rated
• Pb-free plating; RoHS compliant
Type
IPD075N03L G
IPF075N03L G
IPS075N03L G
IPU075N03L G
Package
Marking
PG-TO252-3-11
075N03L
PG-TO252-3-23
075N03L
PG-TO251-3-11
075N03L
PG-TO251-3-21
075N03L
Maximum ratings, at T j=25 °C, unless otherwise specified
Value
Parameter
Symbol Conditions
Unit
I D
V
V
V
GS=10 V, T C=25 °C
Continuous drain current
50
43
49
A
GS=10 V, T C=100 °C
GS=4.5 V, T C=25 °C
V
GS=4.5 V,
35
T C=100 °C
Pulsed drain current2)
I D,pulse
I AS
T C=25 °C
350
50
Avalanche current, single pulse3)
Avalanche energy, single pulse
Gate source voltage
T C=25 °C
E AS
V GS
I D=12 A, R GS=25 Ω
50
mJ
V
±20
1) J-STD20 and JESD22
Rev. 1.1
page 1
2009-01-14
IPD075N03L G
IPS075N03L G
IPF075N03L G
IPU075N03L G
Maximum ratings, at T j=25 °C, unless otherwise specified
Value
47
Parameter
Symbol Conditions
Unit
P tot
T C=25 °C
Power dissipation
W
T j, T stg
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
-55 ... 175
55/175/56
°C
Values
typ.
Parameter
Symbol Conditions
Unit
min.
max.
Thermal characteristics
R thJC
Thermal resistance, junction - case
SMD version, device on PCB
-
-
-
-
-
-
3.2
75
50
K/W
R thJA
minimal footprint
6 cm² cooling area4)
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
V (BR)DSS
V GS(th)
V
V
V
GS=0 V, I D=1 mA
DS=V GS, I D=250 µA
DS=30 V, V GS=0 V,
Drain-source breakdown voltage
Gate threshold voltage
30
1
-
-
-
V
2.2
I DSS
Zero gate voltage drain current
-
-
0.1
10
1
µA
T j=25 °C
V
DS=30 V, V GS=0 V,
100
T j=125 °C
I GSS
V
V
V
GS=20 V, V DS=0 V
GS=4.5 V, I D=30 A
GS=10 V, I D=30 A
Gate-source leakage current
Drain-source on-state resistance5)
-
-
-
-
10
9.1
6.3
1.3
100 nA
R DS(on)
11.4
7.5
-
mΩ
R G
g fs
Gate resistance
Ω
|V DS|>2|I D|R DS(on)max
I D=30 A
,
Transconductance
30
61
-
S
2) See figure 3 for more detailed information
3) See figure 13 for more detailed information
4) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
5) Measured from drain tab to source pin
Rev. 1.1
page 2
2009-01-14
IPD075N03L G
IPS075N03L G
IPF075N03L G
IPU075N03L G
Values
Parameter
Symbol Conditions
Unit
min.
typ.
max.
Dynamic characteristics
C iss
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
-
-
-
-
-
-
-
1400
580
29
1900 pF
770
V
GS=0 V, V DS=15 V,
C oss
Crss
t d(on)
t r
f =1 MHz
44
4.3
3.6
17
-
-
-
-
ns
V
DD=15 V, V GS=10 V,
I D=30 A, R G=1.6 Ω
t d(off)
t f
Turn-off delay time
Fall time
2.8
Gate Charge Characteristics6)
Gate to source charge
Gate charge at threshold
Gate to drain charge
Switching charge
Q gs
-
-
-
-
-
-
4.6
2.2
2.1
4.4
8.7
3.3
-
-
-
-
-
-
nC
Q g(th)
Q gd
V
V
DD=15 V, I D=30 A,
GS=0 to 4.5 V
Q sw
Q g
Gate charge total
V plateau
Gate plateau voltage
V
V
V
DD=15 V, I D=30 A,
GS=0 to 10 V
Q g
Gate charge total
-
18
-
V
V
DS=0.1 V,
Q g(sync)
Q oss
Gate charge total, sync. FET
Output charge
-
-
7.6
15
-
-
nC
GS=0 to 4.5 V
V
DD=15 V, V GS=0 V
Reverse Diode
I S
Diode continuous forward current
Diode pulse current
-
-
-
-
42
A
T C=25 °C
I S,pulse
350
V
GS=0 V, I F=30 A,
V SD
Q rr
Diode forward voltage
-
-
0.89
-
1.1
10
V
T j=25 °C
V R=15 V, I F=I S,
di F/dt =400 A/µs
Reverse recovery charge
nC
6) See figure 16 for gate charge parameter definition
Rev. 1.1
page 3
2009-01-14
IPD075N03L G
IPS075N03L G
IPF075N03L G
IPU075N03L G
1 Power dissipation
2 Drain current
P
tot=f(T C)
I D=f(T C); V GS≥10 V
50
60
50
40
30
20
10
0
40
30
20
10
0
0
50
100
150
200
0
50
100
150
200
T
C [°C]
T
C [°C]
3 Safe operating area
I D=f(V DS); T C=25 °C; D =0
parameter: t p
4 Max. transient thermal impedance
thJC=f(t p)
Z
parameter: D =t p/T
103
10
limited by on-state
resistance
1 µs
102
0.5
10 µs
1
100 µs
0.2
DC
0.1
101
0.05
0.02
1 ms
10 ms
0.1
0.01
100
single pulse
10-1
0
0
0
0
0
0
1
0.01
10-1
100
101
102
10-6
10-5
10-4
10-3
p [s]
10-2
10-1
100
t
V
DS [V]
Rev. 1.1
page 4
2009-01-14
IPD075N03L G
IPS075N03L G
IPF075N03L G
IPU075N03L G
5 Typ. output characteristics
I D=f(V DS); T j=25 °C
6 Typ. drain-source on resistance
R
DS(on)=f(I D); T j=25 °C
parameter: V GS
parameter: V GS
120
20
5 V
4.5 V
3.2 V
100
80
60
40
20
0
16
10 V
3.5 V
4 V
12
8
4 V
4.5 V
5 V
10 V
3.5 V
3.2 V
11.5 V
4
3 V
2.8 V
0
0
1
2
3
0
20
40
60
80
100
V
DS [V]
I
D [A]
7 Typ. transfer characteristics
I D=f(V GS); |V DS|>2|I D|R DS(on)max
parameter: T j
8 Typ. forward transconductance
g fs=f(I D); T j=25 °C
100
100
80
60
40
20
0
80
60
40
20
175 °C
25 °C
0
0
1
2
3
4
5
0
20
40
60
80
100
V
GS [V]
ID [A]
Rev. 1.1
page 5
2009-01-14
IPD075N03L G
IPS075N03L G
IPF075N03L G
IPU075N03L G
9 Drain-source on-state resistance
10 Typ. gate threshold voltage
R
DS(on)=f(T j); I D=30 A; V GS=10 V
V
GS(th)=f(T j); V GS=V DS; I D=250 µA
16
14
12
10
2.5
2
1.5
1
98 %
8
typ
6
4
2
0
0.5
0
-60
-20
20
60
100
140
180
-60
-20
20
60
100
140
180
T j [°C]
T j [°C]
11 Typ. capacitances
12 Forward characteristics of reverse diode
I F=f(V SD
C =f(V DS); V GS=0 V; f =1 MHz
)
parameter: T j
104
103
25 °C
175 °C, 98%
103
102
101
100
Ciss
102
Coss
175 °C
z
Crss
25 °C, 98%
101
100
0
0
10
20
30
0.5
1
1.5
2
V
DS [V]
V SD [V]
Rev. 1.1
page 6
2009-01-14
IPD075N03L G
IPS075N03L G
IPF075N03L G
IPU075N03L G
13 Avalanche characteristics
AS=f(t AV); R GS=25 Ω
14 Typ. gate charge
GS=f(Q gate); I D=30 A pulsed
V
I
parameter: T j(start)
parameter: V DD
100
12
15 V
24 V
6 V
10
8
25 °C
100 °C
150 °C
10
6
4
2
1
0
0
10-1
100
101
102
103
4
8
12
16
20
24
t
AV [µs]
Q
gate [nC]
15 Drain-source breakdown voltage
16 Gate charge waveforms
V
BR(DSS)=f(T j); I D=1 mA
34
32
30
28
26
24
22
20
V GS
Q g
V gs(th)
Q g(th)
Q sw
Q gd
Q gate
Q gs
-60
-20
20
60
100
140
180
T j [°C]
Rev. 1.1
page 7
2009-01-14
IPD075N03L G
IPS075N03L G
IPF075N03L G
IPU075N03L G
Package Outline
PG-TO252-3-11
Rev. 1.1
page 8
2009-01-14
IPD075N03L G
IPS075N03L G
IPF075N03L G
IPU075N03L G
Package Outline
PG-TO252-3-23
Rev. 1.1
page 9
2009-01-14
IPD075N03L G
IPS075N03L G
IPF075N03L G
IPU075N03L G
Package Outline
PG-TO251-3-11
Rev. 1.1
page 10
2009-01-14
IPD075N03L G
IPS075N03L G
IPF075N03L G
IPU075N03L G
Package Outline
PG-TO251-3-21
Rev. 1.1
page 11
2009-01-14
IPD075N03L G
IPS075N03L G
IPF075N03L G
IPU075N03L G
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of
conditions or characteristics. With respect to any examples or hints given herein, any typical
values stated herein and/or any information regarding the application of the device,
Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind,
including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please
contact the nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information
on the types in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with
the express written approval of Infineon Technologies, if a failure of such components can
reasonably be expected to cause the failure of that life-support device or system or to affect
the safety or effectiveness of that device or system. Life support devices or systems are
intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user
or other persons may be endangered.
Rev. 1.1
page 12
2009-01-14
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