IPT026N10N5 [INFINEON]
Infineon’s OptiMOS™ 5 100V n-channel power MOSFET IPT026N10N5 in TO-Leadless (TOLL) package is ideally suited for high switching frequencies. This package is especially designed for high current applications such as POL (point-of-load), forklift, light electric vehicles (LEV) and telecom power supply. With a 60% space reduction compared to D2PAK 7pin package, TOLL is the perfect solution where highest efficiency, outstanding EMI behavior as well as best thermal behavior and space reduction are required.;
| 型号： | IPT026N10N5 |
| 厂家： | 
Infineon |
| 描述： | Infineon’s OptiMOS™ 5 100V n-channel power MOSFET IPT026N10N5 in TO-Leadless (TOLL) package is ideally suited for high switching frequencies. This package is especially designed for high current applications such as POL (point-of-load), forklift, light electric vehicles (LEV) and telecom power supply. With a 60% space reduction compared to D2PAK 7pin package, TOLL is the perfect solution where highest efficiency, outstanding EMI behavior as well as best thermal behavior and space reduction are required. |
| 文件： | 总11页 (文件大小：1015K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IPT026N10N5
MOSFET
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV
HSOF
Features
Tab
•ꢀIdealꢀforꢀhighꢀfrequencyꢀswitchingꢀandꢀsync.ꢀrec.
•ꢀExcellentꢀgateꢀchargeꢀxꢀRDS(on)ꢀproductꢀ(FOM)
•ꢀVeryꢀlowꢀon-resistanceꢀꢀRDS(on)
1
•ꢀN-channel,ꢀnormalꢀlevel
2
3
4
5
•ꢀ100%ꢀavalancheꢀtested
6
7
8
•ꢀPb-freeꢀplating;ꢀRoHSꢀcompliant
•ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21
Productꢀvalidation
FullyꢀqualifiedꢀaccordingꢀtoꢀJEDECꢀforꢀIndustrialꢀApplications
Drain
Tab
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters
Gate
Pin 1
Parameter
Value
100
2.6
Unit
Source
Pin 2-8
VDS
V
RDS(on),max
ID
mΩ
A
202
123
96
Qoss
nC
nC
QG(0V..10V)
Typeꢀ/ꢀOrderingꢀCode
Package
Marking
RelatedꢀLinks
IPT026N10N5
PG-HSOF-8
026N10N5
-
Final Data Sheet
1
Rev.ꢀ2.1,ꢀꢀ2019-03-28
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV
IPT026N10N5
TableꢀofꢀContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Final Data Sheet
2
Rev.ꢀ2.1,ꢀꢀ2019-03-28
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV
IPT026N10N5
1ꢀꢀꢀꢀꢀMaximumꢀratings
atꢀTA=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
VGS=10ꢀV,ꢀTC=25ꢀ°C
VGS=10ꢀV,ꢀTC=100ꢀ°C
-
-
-
-
-
-
202
143
27
Continuous drain current
ID
A
VGS=10ꢀV,ꢀTA=25ꢀ°C,
RTHJA=40ꢀ°C/W1)
Pulsed drain current2)
Avalanche energy, single pulse3)
Gate source voltage
ID,pulse
EAS
-
-
-
-
-
808
250
20
A
TA=25ꢀ°C
-
mJ
-
ID=150ꢀA,ꢀRGS=25ꢀΩ
VGS
Ptot
-20
-
-
Power dissipation
214
W
TC=25ꢀ°C
IEC climatic category; DIN IEC 68-1:
55/175/56
Operating and storage temperature
Tj,ꢀTstg
-55
-
175
°C
2ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Values
Typ.
0.4
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Thermal resistance, junction - case
RthJC
RthJA
-
0.7
°C/W -
°C/W -
Device on PCB,
minimal footprint
-
-
-
-
62
40
Device on PCB,
RthJA
°C/W -
6 cm² cooling area1)
1) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
2) See Diagram 3 for more detailed information
3) See Diagram 13 for more detailed information
Final Data Sheet
3
Rev.ꢀ2.1,ꢀꢀ2019-03-28
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV
IPT026N10N5
3ꢀꢀꢀꢀꢀElectricalꢀcharacteristics
atꢀTj=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics
Values
Typ.
-
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
100
2.2
Max.
-
Drain-source breakdown voltage
Gate threshold voltage
V(BR)DSS
VGS(th)
V
V
VGS=0ꢀV,ꢀID=1ꢀmA
3.0
3.8
VDS=VGS,ꢀID=158ꢀµA
-
-
0.1
10
5
100
VDS=100ꢀV,ꢀVGS=0ꢀV,ꢀTj=25ꢀ°C
VDS=100ꢀV,ꢀVGS=0ꢀV,ꢀTj=125ꢀ°C
Zero gate voltage drain current
Gate-source leakage current
Drain-source on-state resistance
IDSS
µA
nA
IGSS
-
10
100
VGS=20ꢀV,ꢀVDS=0ꢀV
-
-
2.2
2.7
2.6
3.5
VGS=10ꢀV,ꢀID=150ꢀA
VGS=6ꢀV,ꢀID=75ꢀA
RDS(on)
mΩ
Gate resistance1)
Transconductance
RG
gfs
-
1.3
1.95
-
Ω
-
105
210
S
|VDS|≥2|ID|RDS(on)max,ꢀID=100ꢀA
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Input capacitance1)
Output capacitance1)
Reverse transfer capacitance1)
Ciss
Coss
Crss
-
-
-
6800 8800 pF
1000 1300 pF
VGS=0ꢀV,ꢀVDS=50ꢀV,ꢀf=1ꢀMHz
VGS=0ꢀV,ꢀVDS=50ꢀV,ꢀf=1ꢀMHz
VGS=0ꢀV,ꢀVDS=50ꢀV,ꢀf=1ꢀMHz
46
17
80
-
pF
ns
VDD=50ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,
RG,ext=1.8ꢀΩ
Turn-on delay time
Rise time
td(on)
tr
td(off)
tf
-
-
-
-
VDD=50ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,
RG,ext=1.8ꢀΩ
11
38
13
-
-
-
ns
ns
ns
VDD=50ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,
RG,ext=1.8ꢀΩ
Turn-off delay time
Fall time
VDD=50ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,
RG,ext=1.8ꢀΩ
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics2)ꢀ
Values
Typ.
32
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Gate to source charge
Gate charge at threshold
Gate to drain charge1)
Switching charge
Qgs
-
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
V
VDD=50ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=50ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=50ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=50ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=50ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=50ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDS=0.1ꢀV,ꢀVGS=0ꢀtoꢀ10ꢀV
Qg(th)
Qgd
20
-
20
30
Qsw
31
-
Gate charge total1)
Qg
96
120
Gate plateau voltage
Gate charge total, sync. FET
Output charge1)
Vplateau
Qg(sync)
Qoss
4.7
83
-
-
nC
nC
123
164
VDS=50ꢀV,ꢀVGS=0ꢀV
1) Defined by design. Not subject to production test.
2) See ″Gate charge waveforms″ for parameter definition
Final Data Sheet
4
Rev.ꢀ2.1,ꢀꢀ2019-03-28
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV
IPT026N10N5
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode
Values
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Typ.
-
Max.
159
808
1.2
Diode continuous forward current
Diode pulse current
IS
-
-
-
-
-
A
TC=25ꢀ°C
IS,pulse
VSD
trr
-
A
TC=25ꢀ°C
Diode forward voltage
0.89
40
52
V
VGS=0ꢀV,ꢀIF=100ꢀA,ꢀTj=25ꢀ°C
VR=50ꢀV,ꢀIF=100ꢀA,ꢀdiF/dt=100ꢀA/µs
VR=50ꢀV,ꢀIF=100ꢀA,ꢀdiF/dt=100ꢀA/µs
Reverse recovery time1)
Reverse recovery charge1)
80
ns
nC
Qrr
104
1) Defined by design. Not subject to production test.
Final Data Sheet
5
Rev.ꢀ2.1,ꢀꢀ2019-03-28
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV
IPT026N10N5
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams
Diagramꢀ1:ꢀPowerꢀdissipation
Diagramꢀ2:ꢀDrainꢀcurrent
240
240
200
160
120
80
200
160
120
80
40
40
0
0
0
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
TCꢀ[°C]
TCꢀ[°C]
Ptot=f(TC)
ID=f(TC);ꢀVGS≥10ꢀV
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance
103
100
1 µs
single pulse
0.01
0.02
10 µs
0.05
0.1
0.2
0.5
102
101
100 µs
1 ms
10 ms
DC
10-1
100
10-1
10-2
10-2
10-1
100
101
102
103
10-5
10-4
10-3
10-2
10-1
100
VDSꢀ[V]
tpꢀ[s]
ID=f(VDS);ꢀTC=25ꢀ°C;ꢀD=0;ꢀparameter:ꢀtp
ZthJC=f(tp);ꢀparameter:ꢀD=tp/T
Final Data Sheet
6
Rev.ꢀ2.1,ꢀꢀ2019-03-28
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV
IPT026N10N5
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
1000
7
10 V
8 V
7 V
6
800
600
400
200
0
5
4.5 V
5 V
4
6 V
3
6 V
7 V
8 V
2
10 V
1
5 V
4.5 V
0
0
1
2
3
4
5
0
100
200
300
400
500
VDSꢀ[V]
IDꢀ[A]
ID=f(VDS),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS
RDS(on)=f(ID),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS
Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics
Diagramꢀ8:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
1000
7
25 °C
6
5
4
3
2
1
0
800
600
400
200
0
175 °C
175 °C
25 °C
0
1
2
3
4
5
6
7
0
2
4
6
8
10
VGSꢀ[V]
VGSꢀ[V]
ID=f(VGS),ꢀ|VDS|>2|ID|RDS(on)max;ꢀparameter:ꢀTj
RDS(on)=f(VGS),ꢀID=150ꢀA;ꢀparameter:ꢀTj
Final Data Sheet
7
Rev.ꢀ2.1,ꢀꢀ2019-03-28
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV
IPT026N10N5
Diagramꢀ9:ꢀNormalizedꢀdrain-sourceꢀonꢀresistance
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage
2.4
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.0
1.6
1.2
0.8
0.4
0.0
1580 µA
158 µA
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
Tjꢀ[°C]
Tjꢀ[°C]
RDS(on)=f(Tj),ꢀID=150ꢀA,ꢀVGS=10ꢀV
VGS(th=f(Tj),ꢀVGS=VDS;ꢀparameter:ꢀID
Diagramꢀ11:ꢀTyp.ꢀcapacitances
Diagramꢀ12:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode
104
103
25 °C
25 °C, max
175 °C
Ciss
175 °C, max
103
102
101
102
101
100
Coss
Crss
0
20
40
60
80
100
0.00
0.25
0.50
0.75
1.00
1.25
1.50
VDSꢀ[V]
VSDꢀ[V]
C=f(VDS);ꢀVGS=0ꢀV;ꢀf=1ꢀMHz
IF=f(VSD);ꢀparameter:ꢀTj
Final Data Sheet
8
Rev.ꢀ2.1,ꢀꢀ2019-03-28
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV
IPT026N10N5
Diagramꢀ13:ꢀAvalancheꢀcharacteristics
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge
103
10
20 V
50 V
80 V
8
6
4
2
0
102
25 °C
101
100 °C
150 °C
100
100
101
102
103
0
20
40
60
80
100
tAVꢀ[µs]
Qgateꢀ[nC]
IAS=f(tAV);ꢀRGS=25ꢀΩ;ꢀparameter:ꢀTj,start
VGS=f(Qgate),ꢀID=100ꢀAꢀpulsed,ꢀTj=25ꢀ°C;ꢀparameter:ꢀVDD
Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage
Diagram Gate charge waveforms
108
106
104
102
100
98
96
-80
-40
0
40
80
120
160
200
Tjꢀ[°C]
VBR(DSS)=f(Tj);ꢀID=1ꢀmA
Final Data Sheet
9
Rev.ꢀ2.1,ꢀꢀ2019-03-28
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV
IPT026N10N5
5ꢀꢀꢀꢀꢀPackageꢀOutlines
1) partially covered with Mold Flash
MILLIMETERS
INCHES
DIM
MIN
2.20
0.70
9.70
0.42
0.40
10.28
MAX
2.40
0.90
9.90
0.50
0.60
10.58
MIN
MAX
0.094
0.035
0.390
0.020
0.024
0.416
DOCUMENT NO.
Z8B00169619
A
b
0.087
0.028
0.382
0.017
0.016
0.405
b1
b2
c
0
SCALE
D
2
D2
E
3.30
0.130
9.70
10.10
0.382
0.398
0
2
E1
E4
E5
e
7.50
8.50
0.295
0.335
4mm
9.46
1.20 (BSC)
0.372
0.047 (BSC)
EUROPEAN PROJECTION
H
11.48
6.55
11.88
6.75
0.452
0.258
0.468
0.266
H1
H2
H3
H4
N
7.15
3.59
3.26
8
0.281
0.141
0.128
8
ISSUE DATE
20-02-2014
K1
L
4.18
0.165
1.60
1.00
2.10
1.30
0.063
0.039
0.083
0.051
L1
L2
L4
0.70
0.60
0.028
0.024
REVISION
02
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀPG-HSOF-8,ꢀdimensionsꢀinꢀmm/inches
Final Data Sheet
10
Rev.ꢀ2.1,ꢀꢀ2019-03-28
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV
IPT026N10N5
RevisionꢀHistory
IPT026N10N5
Revision:ꢀ2019-03-28,ꢀRev.ꢀ2.1
Previous Revision
Revision Date
Subjects (major changes since last revision)
2.0
2.1
Release of final version
Addition max values
2019-02-21
2019-03-28
Trademarks
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warrantiesꢀofꢀnon-infringementꢀofꢀintellectualꢀpropertyꢀrightsꢀofꢀanyꢀthirdꢀparty.
Inꢀaddition,ꢀanyꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀisꢀsubjectꢀtoꢀcustomer’sꢀcomplianceꢀwithꢀitsꢀobligationsꢀstatedꢀinꢀthis
documentꢀandꢀanyꢀapplicableꢀlegalꢀrequirements,ꢀnormsꢀandꢀstandardsꢀconcerningꢀcustomer’sꢀproductsꢀandꢀanyꢀuseꢀofꢀthe
productꢀofꢀInfineonꢀTechnologiesꢀinꢀcustomer’sꢀapplications.
Theꢀdataꢀcontainedꢀinꢀthisꢀdocumentꢀisꢀexclusivelyꢀintendedꢀforꢀtechnicallyꢀtrainedꢀstaff.ꢀItꢀisꢀtheꢀresponsibilityꢀofꢀcustomer’s
technicalꢀdepartmentsꢀtoꢀevaluateꢀtheꢀsuitabilityꢀofꢀtheꢀproductꢀforꢀtheꢀintendedꢀapplicationꢀandꢀtheꢀcompletenessꢀofꢀtheꢀproduct
informationꢀgivenꢀinꢀthisꢀdocumentꢀwithꢀrespectꢀtoꢀsuchꢀapplication.
Information
Forꢀfurtherꢀinformationꢀonꢀtechnology,ꢀdeliveryꢀtermsꢀandꢀconditionsꢀandꢀpricesꢀpleaseꢀcontactꢀyourꢀnearestꢀInfineon
TechnologiesꢀOfficeꢀ(www.infineon.com).
Warnings
Dueꢀtoꢀtechnicalꢀrequirements,ꢀcomponentsꢀmayꢀcontainꢀdangerousꢀsubstances.ꢀForꢀinformationꢀonꢀtheꢀtypesꢀinꢀquestion,
pleaseꢀcontactꢀtheꢀnearestꢀInfineonꢀTechnologiesꢀOffice.
TheꢀInfineonꢀTechnologiesꢀcomponentꢀdescribedꢀinꢀthisꢀDataꢀSheetꢀmayꢀbeꢀusedꢀinꢀlife-supportꢀdevicesꢀorꢀsystemsꢀand/or
automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa
failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand
aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare
intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis
reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.
Final Data Sheet
11
Rev.ꢀ2.1,ꢀꢀ2019-03-28
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