IR1167ASPBF [INFINEON]
SmartRectifier CONTROL IC; 智能整流控制IC
| 型号： | IR1167ASPBF |
| 厂家： | 
Infineon |
| 描述： | SmartRectifier CONTROL IC |
| 文件： | 总15页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Data Sheet PD60254A
IR1167ASPbF
IR1167BSPbF
SmartRectifierTM CONTROL IC
Features
50ns turn-off propagation delay
Vcc range from 11.3V to 20V
Direct sensing of MOSFET drain voltage
Minimal component count
Secondary side high speed SR controller
DCM, CrCM and CCM flyback topologies
200V proprietary IC technology
Max 500KHz switching frequency
Anti-bounce logic and UVLO protection
7A peak turn off drive current
Simple design
Lead-free
Compatible with 1W Standby, Energy Star, CECP, etc.
Micropower start-up & ultra low quiescent current
10.7/14.5V gate drive clamp
Description
Package
IR1167S is a smart secondary side driver IC designed to drive N-Channel power MOSFETs
used as synchronous rectifiers in isolated Flyback converters.
The IC can control one or more paralleled N-MOSFETs to emulate the behavior of Schottky
diode rectifiers. The drain to source voltage is sensed differentially to determine the polarity
of the current and turn the power switch on and off in proximity of the zero current transi-
tion.
Ruggedness and noise immunity are accomplished using an advanced blanking scheme
and double-pulse suppression which allow reliable operation in continuous, discontinuous
8-Lead SOIC
and critical current mode operation and both fixed and variable frequency modes.
IR1167 Application Diagram
Vin
Rs
Cs
Rdc
U1
XF M
Cdc
1
2
3
4
8
7
6
5
VCC VGATE
Ci
OVT
GND
VS
Co
MOT
RMOT
EN
VD
Rg
Q1
IR1167S
Rtn
*Please note that this data sheet contains advanced information that could change before the product is released to production.
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1
IR1167AS/BS
PRELIMINARY
Absolute Maximum Ratings
Stress beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.All voltages are absolute voltages referenced
to GND. Thermal resistance and power dissipation are measured under board mounted and still air conditions.
Parameters
Symbol Min.
Max. Units
Remarks
Supply Voltage
Enable Voltage
VCC
VEN
VD
-0.3
-0.3
-3
20
V
20
V
Cont. Drain Sense Voltage
Pulse Drain Sense Voltage
Source Sense Voltage
Gate Voltage
200
200
20
V
VD
-5
V
VS
-3
V
VGATE
TJ
-0.3
-40
-55
20
V
VCC=20V, Gate off
Operating Junction Temperature
Storage Temperature
Thermal Resistance
150
150
128
970
2
°C
°C
TS
RθJA
PD
°C/W SOIC-8
mW SOIC-8, TAMB=25°C
Package Power Dissipation
ESD Protection
VESD
fsw
kV
Human Body Model*
Switching Frequency
500
kHz
Recommended Operating Conditions
Recommended operating conditions for reliable operation with margin
Parameters Symbol Min. Max. Units
Remarks
Supply Voltage
VCC
TJ
12
-25
-25
40
18
125
85
V
°C
Operating Junction Temperature
Ambient Temperature
TA
°C
Switching Frequency
fsw
400
kHz
* Per EIA/JESD22-A114-B( discharging a 100pF capacitor through a 1.5kΩ series resistor).
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2
IR1167AS/BS
PRELIMINARY
Electrical Characteristics
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and
junction temperature range TJ from 25° C to 125°C. Typical values represent the median values, which are
related to 25°C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition.
Supply Section
Parameters
VCC Turn On Threshold
VCC Turn Off Threshold
Symbol Min.
Typ.
10.5
Max.
11.3
Units
V
Remarks
VCC ON
9.8
VCC UVLO
8.4
9
9.7
V
V
(Under Voltage Lock Out)
VCC Turn On/Off Hysteresis
VCC HYST
1.4
1.55
1.7
CLOAD=1nF, fsw = 400kHz
8.5
50
10
65
IR1167A
IR1167B
C
LOAD=10nF, fSW = 400kHz
ICC
Operating Current
mA
CLOAD=1nF, fsw = 400kHz
10.3
66
12
C
LOAD=10nF, fSW = 400kHz
- 0.1V
80
Quiescent Current
Start-up Current
IQCC
ICC START
ISLEEP
VENHI
1.8
100
150
2.75
1.6
1.5
2.2
200
200
mA
µA
µA
V
VCC=VCC
ON
Sleep Current
V
EN=0V, VCC =15V
Enable Voltage High
Enable Voltage Low
Enable Pull-up Resistance
V
VENLO
REN
MΩ
GBD
Comparator Section
Parameters
Symbol Min.
Typ.
-3.5
Max.
0
Units
Remarks
-7
OVT = 0V, VS=0V
OVT floating, VS=0V
OVT = VCC, VS=0V
Turn-off Threshold
VTH1
-15
-23
-10.5
-19
-7
mV
-15
-50
Turn-on Threshold
Hysteresis
VTH2
VHYST
IIBIAS1
IIBIAS2
VOFFSET
VCM
-150
mV
mV
µA
µA
mV
V
55
VD = -50mV
1
7.5
100
2
Input Bias Current
V
D = 200V
30
Input Bias Current
Comparator Input Offset
Input CM Voltage Range
GBD
-0.15
2
One-Shot Section
Parameters
Blanking pulse duration
Symbol Min.
tBLANK
Typ.
15
Max.
20
Units
µs
Remarks
10
V
CC=10V - GBD
VCC=20V - GBD
CC=10V - GBD
2.5
5.4
40
V
V
Reset Threshold
Hysteresis
VTH3
V
mV
VHYST3
Minimum On Time Section
Parameters
Symbol Min.
Typ.
Max.
Units
Remarks
190
240
290
ns
RMOT =5kΩ, VCC=12V
TONmin
Minimum on time
2.4
3
3.6
µs
RMOT =75kΩ, VCC=12V
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3
IR1167AS/BS
PRELIMINARY
Gate Driver Section
Parameters
Gate Low Voltage
Gate High Voltage
Gate High Voltage
Rise Time
Symbol Min.
VGLO
Typ. Max. Units
Remarks
0.3
10.7
14.5
30
180
10
30
60
40
4
0.5
V
IGATE = 200mA
VGTH
VGTH
tr1
9.5
12.5
16.5
V
IR1167A - VCC=12V-18V (internally clamped)
IR1167B - VCC=12V-18V (internally clamped)
CLOAD = 1nF, VCC=12V
12.5
V
ns
ns
ns
ns
ns
ns
Ω
tr2
CLOAD = 10nF, VCC=12V
Fall Time
tf1
CLOAD = 1nF, VCC=12V
tf2
CLOAD = 10nF, VCC=12V
Turn on Propagation Delay
Turn off Propagation Delay
Pull up Resistance
tDon
tDoff
rup
80
60
VDS to VGATE -100mV overdrive
VDS to VGATE -100mV overdrive
IGATE = 1A - GBD
Pull down Resistance
rdown
IO source
IO sink
0.7
2
Ω
I
GATE = -200mA
LOAD = 10nF - GBD
CLOAD = 10nF - GBD
Output Peak Current (source)
Output Peak Current (sink)
A
C
7
A
** Guaranteed by Design
STATE AND TRANSITIONS DIAGRAM
POWER ON
Gate Inactive
UVLO MODE
VCC < VCCon
Gate Inactive
ICC max = 200uA
VCC > VCCon
VCC < VCCuvlo
and
or
ENABLE HIGH
ENABLE LOW
NORMAL
Gate Active
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IR1167AS/BS
PRELIMINARY
Block Diagram
MOT
VCC
VDD
UVLO
&
ENA
REGULATOR
VDD
VD
Min ON Time
RESET
VTH1
VGATE
VS
DRIVER
COM
OVT
Min OFF Time
RESET
Vgate
VTH3
VTH1
VDS
VTH2
VTH3
Lead Assignments & Definitions
Lead Assignment
Pin#
Symbol
VCC
Description
Supply Voltage
1
Offset Voltage Trimming
Minimum On Time
Enable
2
3
4
5
6
7
8
OVT
MOT
EN
1
2
3
4
VCC
OVT
MOT
EN
8
7
6
5
VGATE
GND
VS
VD
FET Drain Sensing
FET Source Sensing
Ground
VS
VD
GND
GATE
Gate Drive Output
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IR1167AS/BS
PRELIMINARY
Detailed Pin Description
kelvin contact as close as possible to the power
MOSFET source pin.
GND: Ground
This is ground potential pin of the integrated control
circuit. The internal devices and gate driver are
referenced to this point.
VD: Drain Voltage Sense
VD is the voltage sense pin for the power MOSFET
Drain. This is a high voltage pin and particular care
must be taken in properly routing the connection to
the power MOSFET drain.
Additional filtering and or current limiting on this pin is
not recommended as it would limit switching perfor-
mance of the IC.
MOT: Minimum On Time
The MOT programming pin controls the amount of
minimum on time. Once VTH2 is crossed for the first
time, the gate signal will become active and turn on
the power FET. Spurious ringings and oscillations can
trigger the input comparator off. The MOT blanks the
input comparator keeping the FET on for a minimum
time.
VCC: Power Supply
This is the supply voltage pin of the IC and it is
monitored by the under voltage lockout circuit. It is
possible to turn off the IC by pulling this pin below the
minimum turn off threshold voltage, without damage
to the IC.
The MOT is programmed between 200ns and 3us
(typ.) by using a resistor referenced to GND.
OVT: Offset Voltage Trimming
The OVT pin will program the amount of input offset
To prevent noise problems, a bypass ceramic
capacitor connected to Vcc and GND should be placed
as close as possible to the IR1167S.
voltage for the turn-off threshold VTH1
.
The pin can be optionally tied to ground, to VCC or
left floating, to select 3 ranges of input offset trimming.
This programming feature allows for accomodating
different RDSon MOSFETs.
This pin is internally clamped.
EN: Enable
GATE: Gate Drive Output
This pin is used to activate the IC sleep mode by
pulling the voltage level below 2.5V (typ). In sleep
mode the IC will consume a minimum amount of cur-
rent. However all switching functions will be disabled
and the gate will be inactive.
This is the gate drive output of the IC. Drive voltage
is internally limited and provides 2A peak source and
5A peak sink capability. Although this pin can be
directly connected to the power MOSFET gate, the
use of minimal gate resistor is recommended,
expecially when putting multiple FETs in parallel.
Care must be taken in order to keep the gate loop as
short and as small as possible in order to achieve
optimal switching performance.
VS: Source Voltage Sense
VS is the differential sense pin for the power MOSFET
Source. This pin must not be connected directly to
the power ground pin (7) but must be used to create a
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6
IR1167AS/BS
PRELIMINARY
STATES OF OPERATION
GENERAL DESCRIPTION
The IR1167 Smart Rectifier IC can emulate the
operation of diode rectifier by properly driving a
Synchronous Rectifier (SR) MOSFET.
UVLO/Sleep Mode
The IC remains in the UVLO condition until the voltage
on the VCC pin exceeds the VCC turn on threshold
The direction of the rectified current is sensed by the
voltage, VCC ON
.
input comparator using the power MOSFET R
as a shunt resistance and the GATE pin of the
MOSFET is driven accordingly.
Internal blanking logic is used to prevent spurious
transitions and guarantee operation in continuous
(CCM), discountinuous (DCM) and critical (CrCM)
conduction mode.
During the time the IC remains in the UVLO state, the
gate drive circuit is inactive and the IC draws a
quiescent current of ICC START. The UVLO mode is
accessible from any other state of operation whenever
the IC supply voltage condition of VCC < VCC UVLO
occurs.
The sleep mode is initiated by pulling the EN pin below
2.5V (typ). In this mode the IC is essentially shut down
and draws a very low quiescent supply current.
DSon
VGate
Normal Mode
The IC enters in normal operating mode once the
UVLO voltage has been exceeded. At this point the
gate driver is operating and the IC will draw a
maximum of ICC from the supply voltage source.
VDS
VTH2
VTH1
VTH3
Input comparator thresholds
The modes of operation for a Flyback circuit differ
mainly for the turn-off phase of the SR switch, while
the turn-on phase of the secondary switch (which
correspond to the turn off of the primary side switch)
is identical.
Turn-on phase
When the conduction phase of the SR FET is initiated,
current will start flowing through its body diode,
generating a negative VDS voltage across it. The body
diode has generally a much higher voltage drop than
the one caused by the MOSFET on resistance and
therefore will trigger the turn-on threshold V
.
TH2
At that point the IR1167 will drive the gate of MOSFET
on which will in turn cause the conduction voltage VDS
to drop down. This drop is usually accompained by some
amount of ringing, that can trigger the input comparator
to turn off; hence, a Minimum On Time (MOT) blanking
period is used that will maintain the power MOSFET on
for a minimum amount of time.
The programmed MOT will limit also the minimum duty
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7
IR1167AS/BS
PRELIMINARY
cycle of the SR MOSFET and, as a consequence, the
max duty cycle of the primary side switch.
is blanked for a certain amount of time (TBLANK) after
VTH1 has been triggered.
The blanking time is internally set. As soon as VDS
crosses the positive threshold VTH3 also the blanking
time is terminated and the IC is ready for next
conduction cycle.
DCM/CrCM Turn-off phase
Once the SR MOSFET has been turned on, it will
remain on until the rectified current will decay to the
level where V will cross the turn-off threshold VTH1
.
DS
CCM Turn-off phase
This will happen differently depending on the mode
of operation.
In DCM the current will cross the threshold with a
relatively low dI/dt. Once the threshold is crossed, the
current will start flowing again through the body diode,
In CCM mode the turn off transition is much steeper
and dI/dt involved is much higher. The turn on phase
is identical to DCM or CrCM and therefore wont be
repeated here.
During the SR FET conduction phase the current will
decay linearly, and so will VDS on the SR FET.
IPRIM
VPRIM
IPRIM
VPRIM
time
T3
T1
T2
ISEC
VSEC
time
T2
T1
ISEC
VSEC
time
Primary and secondary currents and
voltages for DCM mode
Primary and secondary currents and time
voltages for CCM mode
IPRIM
VPRIM
Once the primary switch will start to turn back on, the
SR FET current will rapidly decrease crossing VTH1
and turning the gate off.
The turn off speed is critical to avoid cross conduction
on the primary side and reduce switching losses.
also in this case a blanking period will be applied, but
given the very fast nature of this transition, it will be
time
T2
T1
ISEC
VSEC
reset as soon as VDS crosses VTH3
.
time
Primary and secondary currents and
voltages for CrCM mode
causing the VDS voltage to jump negative. Depending
on the amount of residual current, VDS may trigger
once again the turn on threshold: for this reason VTH2
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8
IR1167AS/BS
PRELIMINARY
VTH3
ISEC
VDS
T1
T2
time
VTH1
VTH2
Gate Drive
Blanking
time
time
MOT
Secondary side CCM operation
VTH3
ISEC
VDS
T1
T2
time
time
9
VTH1
VTH2
Gate Drive
Blanking
MOT
10us blanking
Secondary side DCM/CrCM operation
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IR1167AS/BS
PRELIMINARY
11
10
9
10
1
0.1
0.01
V
CC ON
V
CC UVLO
8
-50
0
50
100
150
5
10
15
20
Temperature ( °C )
Supply Voltage (V)
Fig 1. Supply Current vs. Supply Voltage
Fig 2. Under Voltage Lockout
vs. Temp.
0
-5
0
-10
-15
-20
-25
-30
-50
-100
-150
OVT = GND
OVT = Floating
OVT = V
CC
-50
0
50
100
150
-50
0
50
100
150
Temperature ( °C )
Temperature ( °C )
Fig 4. VTH2 vs. Temp.
Fig 3. VTH1 vs. Temp.
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10
IR1167AS/BS
PRELIMINARY
100
50
0
0
-3
-6
-9
VS = -150mV
VS= 0V
VS= +2V
-50
0
50
100
150
-50
0
50
100
150
Temperature ( °C )
Temperature ( °C )
Fig 5. Comparator Hysteresis vs.
Fig 6. VTH1 vs. Temp. and Common
Temp.
Mode (OVT=GND)
-50
-100
-150
-50
-100
-150
VS = -150mV
VS= 0V
VS= +2V
VS = -150mV
VS= 0V
VS= +2V
-50
0
50
100
150
-50
0
50
100
150
Temperature ( °C )
Temperature ( °C )
Fig 7. VTH2 vs. Temp. and Common
Fig 8. Comparator Hysteresis vs. Temp. and
Mode (OVT=GND)
Common Mode (OVT=GND)
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11
IR1167AS/BS
PRELIMINARY
4
3
2
1
0
100
80
60
40
20
0
T = -25°C
J
RMOT = 5k
RMOT= 75k
T = 25°C
J
T = 125°C
J
-50
0
50
Temperature ( °C )
100
150
0
50
100
150
200
Drain Sense Voltage (V (V)
D)
Fig 9. MOT vs. Temp.
Fig 10. Input Bias Current vs. VD.
20
19
18
17
16
15
14
13
12
11
20
Csync = 2nF
Csync = 5nF
Csync = 8nF
Csync = 15nF
Csync = 20nF
Csync = 2nF
Csync = 5nF
Csync = 8nF
Csync = 15nF
Csync = 20nF
19
18
17
16
15
14
13
12
11
50 100 150 200 250 300 350 400 450 500
50 100 150 200 250 300 350 400 450 500
Max. Synchronous HEXFET Switching Frequency (kHz)
Max. Synchronous HEXFET Switching Frequency (kHz)
Fig 12. Max. VCC Voltage vs. Synchronous Rectifier
Switching Freq, TJ=125°C, TIC = 85°C, external RG=2W,
1ΩHEXFET Gate Resistance included
Fig 11. Max. VCC Voltage vs. Synchronous Rectifier
Switching Freq, TJ=125°C, TIC = 85°C, external RG=1W,
1ΩHEXFET Gate Resistance included
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12
IR1167AS/BS
PRELIMINARY
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
Csync = 2nF
Csync = 5nF
Csync = 8nF
Csync = 15nF
Csync = 20nF
Csync = 2nF
Csync = 5nF
Csync = 8nF
Csync = 15nF
Csync = 20nF
50 100 150 200 250 300 350 400 450 500
50 100 150 200 250 300 350 400 450 500
Maximum Synchronous HEXFET Switching Frequency (kHz)
Max. Synchronous HEXFET Switching Frequency (kHz)
Fig 13. Max. VCC Voltage vs. Synchronous Rectifier
Switching Freq, TJ=125°C, TIC = 85°C, external RG=4W,
1ΩHEXFET Gate Resistance included
Fig 14. Max VCC Voltage vs. Synchronous Rectifier
Switching Freq, TJ=125°C, TIC = 85°C, external RG=6W,
1ΩHEXFET Gate Resistance included
Figures 11-14 shows the maximum allowable VCC voltage vs. maximum switching frequency for
different loads which are calculated using the design methodology discussed in AN1087.
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13
IR1167AS/BS
PRELIMINARY
VCC
VCC ON
VCC UVLO
t
UVLO
NORMAL
UVLO
Fig. 14 - V Under Voltage Lockout
cc
VTH1
VDS
VTH2
tDon
tDoff
VGate
90%
50%
10%
trise
tfall
Fig. 15 - Timing Diagrams
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IR1167AS/BS
PRELIMINARY
Case outline
INCHES
MIL L IME T ERS
DIM
A
D
B
MIN
.0532
MAX
.0688
.0098
.020
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
FOOTPRINT
8X 0.72 [.028]
5
A
A1 .0040
b
c
D
E
.013
.0075
.189
.0098
.1968
.1574
8
1
7
2
6
3
5
6
H
E
.1497
0.25 [.010]
A
e
.050 BASIC
1.27 BASIC
6.46 [.255]
4
e1 .025 BASIC
0.635 BASIC
H
K
L
.2284
.0099
.016
0°
.2440
.0196
.050
8°
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
3X 1.27 [.050]
e
6X
8X 1.78 [.070]
y
K x 45°
e1
A
A
C
y
0.10 [.004]
8X c
8X L
A1
B
8X b
7
0.25 [.010]
C
5
6
7
DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
NOTES:
1. DIMENSIONING& TOLERANCING PER ASME Y14.5M-1994.
2. CONT ROLLING DIME NS ION: MILLIME T ER
DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
4. OU T L INE CONF OR MS T O JE DE C OU T L INE MS -012AA.
DIMENSION IS THE LENGTH OF LEAD FOR SOLDERINGTO
ASUBSTRATE.
01-6027
01-0021 11 (MS-012AA)
8-Lead SOIC
1167ASPbF
Data and specifications subject to change without notice.
Qualification Standards can be found on IRs Web site.
WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105
http://www.irf.com/ Data and specifications subject to change without notice. 4/2006
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15
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