IR21091PBF [INFINEON]
HALF-BRIDGE DRIVER; 半桥驱动器
| 型号： | IR21091PBF |
| 厂家： | 
Infineon |
| 描述： | HALF-BRIDGE DRIVER |
| 文件： | 总8页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD60191 revD
( ) & (PbF)
S
IR21091
HALF-BRIDGE DRIVER
Product Summary
Features
Floating channel designed for bootstrap operation
•
V
600V max.
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
OFFSET
I +/-
120 mA / 250 mA
10 - 20V
O
Gate drive supply range from 10 to 20V
Undervoltage lockout for both channels
3.3V, 5V and 15V input logic compatible
Cross-conduction prevention logic
Matched propagation delay for both channels
High side output in phase with IN input
Logic and power ground +/- 5V offset.
Internal 500ns dead-time, and programmable
•
V
OUT
•
•
ton/off (typ.)
Dead time
680 & 170 ns
500 ns
•
•
•
(programmable up to 5uS)
•
•
up to 5us with one external R resistor
DT
Lower di/dt gate driver for better noise immunity
The dual function DT/SD pin input turns off both
channels.
•
•
Packages
Available in Lead-Free
•
Description
The IR21091(S) are high voltage, high speed power
MOSFET and IGBT drivers with dependant high and
low side referenced output channels.Proprietary HVIC
and latch immune CMOS technologies enable rugge-
8 Lead SOIC
8 Lead PDIP
dized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to
3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-
conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high
side configuration which operates up to 600 volts.
Typical Connection
up to 600V
VCC
VCC
VB
HO
VS
IN
IN
TO
LOAD
SD
DT/SD
COM
LO
IR21091(S)
(Refer to Lead Assignments for correct configuration).This/These diagram(s) show electrical connections
only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
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IR21091
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Definition
High side floating absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Min.
Max.
Units
V
V
-0.3
625
B
S
V
B
- 25
V
B
V
B
+ 0.3
+ 0.3
25
V
HO
V
CC
V
S
- 0.3
-0.3
-0.3
V
V
LO
V
V
V
+ 0.3
+ 0.3
+ 0.3
CC
CC
CC
DT/SD
Programmable dead-time and shut-down pin voltage
Logic input voltage
V
- 0.3
SS
SS
V
IN
V
- 0.3
dV /dt
Allowable offset supply voltage transient
—
50
V/ns
W
S
P
Package power dissipation @ T ≤ +25°C (8 Lead PDIP)
—
—
—
—
—
-50
—
1.0
0.625
125
200
150
150
300
D
A
(8 Lead SOIC)
Rth
Thermal resistance, junction to ambient
(8 Lead PDIP)
(8 Lead SOIC)
JA
°C/W
°C
T
T
Junction temperature
J
Storage temperature
S
T
L
Lead temperature (soldering, 10 seconds)
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The V offset rating are tested with all supplies biased at 15V differential.
S
Symbol
Definition
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating output voltage
Min.
Max.
Units
VB
V
+ 10
V + 20
S
S
V
Note 1
600
S
V
HO
V
V
B
S
V
Low side and logic fixed supply voltage
10
0
20
CC
V
V
Low side output voltage
V
LO
CC
CC
CC
V
Logic input voltage
V
V
V
IN
SS
SS
DT/SD
Programmable dead-time and shut-down pin voltage
Ambient temperature
V
T
A
-40
125
°C
Note 1: Logic operational for V of -5 to +600V. Logic state held for V of -5V to -V (Please refer to the Design Tip
BS.
S
S
DT97-3 for more details).
2
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S
IR21091
Dynamic Electrical Characteristics
V (V , V ) = 15V, C = 1000 pF, T = 25°C, DT = VSS unless otherwise specified.
BIAS CC BS L A
Symbol
Definition
Min. Typ. Max. Units Test Conditions
t
Turn-on propagation delay
—
—
—
—
—
750
200
0
950
280
70
V = 0V
S
on
off
t
Turn-off propagation delay
V
S
= 0V or 600V
MT
Delay matching, HS & LS turn-on/off
Turn-on rise time
t
150
50
220
80
V
V
= 0V
= 0V
nsec
r
S
t
Turn-off fall time
f
S
DT
Deadtime: LO turn-off to HO turn-on(DT
400
4
540
5
680
6
RDT= 0
LO-HO) &
HO turn-off to LO turn-on (DT
usec
nsec
RDT = 200k
HO-LO)
MDT
tsd
Deadtime matching = DT
- DT
—
—
0
0
60
RDT=0
LO - HO
HO-LO
600
RDT = 200k
Shut down propagation delay
215
—
615
Static Electrical Characteristics
V
(V , V ) = 15V, DT= V
CC BS
and T = 25°C unless otherwise specified. The V , V and I parameters are
SS A IL IH IN
BIAS
referenced to V /COM and are applicable to the respective input leads: IN and DT. The V , I and Ron parameters are
SS
O O
referenced to COM and are applicable to the respective output leads: HO and LO.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
V
Logic “1” input voltage for HO & logic “0” for LO
2.9
—
—
0.8
14.5
1.4
0.6
50
V
= 10V to 20V
IH
CC
CC
V
Logic “0” input voltage for HO & logic “1” for LO
—
—
V
= 10V to 20V
IL
V
11.5
—
13
0.8
0.3
—
SD,TH
DT/SD pin shutdown input threshold
V
V
OH
High level output voltage, V
- V
I
I
= 20 mA
= 20 mA
BIAS
O
O
O
V
OL
Low level output voltage, V
—
O
I
LK
Offset supply leakage current
Quiescent V supply current
—
V
= V = 600V
B
S
µA
I
20
60
1.0
150
1.6
V
= 0V or 5V
= 0V or 5V
QBS
QCC
BS
IN
IN
I
Quiescent V
supply current
0.4
mA
V
CC
RDT = 0
I
Logic “1” input bias current
Logic “0” input bias current
—
—
5
1
20
2
IN = 5V, SD = 0V
IN = 0V, SD = 5V
IN+
µA
V
I
IN-
V
V
and V supply undervoltage positive going
8.0
8.9
9.8
CCUV+
CC
BS
V
threshold
BSUV+
V
V
and V supply undervoltage negative going
7.4
0.3
8.2
0.7
9.0
—
CCUV-
CC
BS
V
threshold
BSUV-
V
Hysteresis
CCUVH
V
BSUVH
I
Output high short circuit pulsed vurrent
Output low short circuit pulsed current
120
250
200
350
—
—
V
= 0V, PW ≤ 10 µs
=15V,PW ≤ 10 µs
O+
O
mA
I
V
O
O-
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IR21091
Functional Block Diagrams
VB
UV
DETECT
IR21091(S)
HO
R
R
Q
PULSE
FILTER
HV
LEVEL
S
SHIFTER
VSS/COM
LEVEL
SHIFT
IN
VS
PULSE
GENERATOR
VCC
LO
DEADTIME
DT/SD
UV
DETECT
VSS/COM
LEVEL
SHIFT
DELAY
COM
4
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IR21091
Lead Definitions
Symbol Description
IN
Logic input for high and low side gate driver outputs (HO and LO), in phase with HO
DT/SD
Programmable dead-time lead, referenced to VSS. Disables input/output logic when tied to VCC
V
High side floating supply
High side gate drive output
High side floating supply return
Low side and logic fixed supply
Low side gate drive output
Low side return
B
HO
V
V
S
CC
LO
COM
Lead Assignments
V
V
1
2
3
4
V
1
2
3
4
B
8
7
B
8
V
CC
CC
HO
HO
IN
7
6
5
IN
V
S
V
S
DT/SD
COM
6
5
DT/SD
COM
LO
LO
8 Lead PDIP
8 Lead SOIC
IR21091
IR21091(S)
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IR21091
Case Outlines
01-6014
01-3003 01 (MS-001AB)
8 Lead PDIP
INCHES
MILLIMETERS
DIM
A
D
B
MIN
.0532
MAX
.0688
.0098
.020
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
FOOTPRINT
8X 0.72 [.028]
5
A
A1 .0040
b
c
.013
.0075
.189
.0098
.1968
.1574
8
1
7
2
6
3
5
6
D
E
e
H
E
.1497
0.25 [.010]
A
.050 BASIC
1.27 BASIC
6.46 [.255]
4
e 1 .025 BASIC
0.635 BASIC
H
K
L
y
.2284
.0099
.016
0°
.2440
.0196
.050
8°
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
3X 1.27 [.050]
e
6X
8X 1.78 [.070]
e1
K x 45°
A
C
y
0.10 [.004]
8X c
8X L
A1
B
8X b
7
0.25 [.010]
C A
NOT ES :
5
6
7
DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS .
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS .
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
3. DIMENS IONS ARE S HOWN IN MILLIME TE RS [INCHES ].
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
01-6027
01-0021 11 (MS-012AA)
8 Lead SOIC
6
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IR21091
IN(LO)
IN
50%
50%
t
IN(HO)
t
DT/SD
t
t
f
on
off
r
HO
LO
90%
90%
LO
HO
10%
10%
Figure 2. Switching Time Waveform Definitions
Figure 1. Input/Output Timing Diagram
50%
50%
50%
tsd
IN
DT/SD
90%
90%
HO
LO
DT
10%
HO
LO
LO-HO
DT
HO-LO
10%
90%
Figure 3. Shutdown Waveform Definitions
MDT=
DT
- DT
LO-HO
HO-LO
Figure 4. Deadtime Waveform Definitions
IN(LO)
50%
50%
IN(HO)
LO
HO
10%
MT
MT
90%
LO
HO
Figure 5. Delay Matching Waveform Definitions
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S
IR21091
Basic Part (Non-Lead Free)
Lead-Free Part
8-Lead PDIP IR21091 order IR21091
8-Lead SOIC IR21091S order IR21091S
8-Lead PDIP IR21091 order IR21091PBF
8-Lead SOIC IR21091S order IR21091SPBF
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Website.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 7/19/2005
8
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