IR21362JTRPBF [INFINEON]

MOSFET Driver, CMOS, PQCC44;
IR21362JTRPBF
型号: IR21362JTRPBF
厂家: Infineon    Infineon
描述:

MOSFET Driver, CMOS, PQCC44

文件: 总36页 (文件大小:891K)
中文:  中文翻译
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
Data Sheet No. PD60166 revU  
IR2136/IR21362/IR21363/IR21365/  
IR21366/IR21367/IR21368 (J&S) & (PbF)  
3-PHASE BRIDGE DRIVER  
Packages  
Features  
Floating channel designed for bootstrap operation  
Fully operational to +600 V  
Tolerant to negative transient voltage, dV/dt immune  
Gate drive supply range from 10 V to 20 V (IR2136/  
IR21368), 11.5 V to 20 V (IR21362D), or 12 V to 20 V  
(IR21363/IR21365/IR21366/IR21367)  
28-Lead SOIC  
28-Lead PDIP  
Undervoltage lockout for all channels  
Over-current shutdown turns off all six drivers  
Independent 3 half-bridge drivers  
Matched propagation delay for all channels  
Cross-conduction prevention logic  
Low side output out of phase with inputs. High side outputs  
out of phase (IR213(6,63, 65, 66, 67, 68)), or in phase  
(IR21362) with inputs  
44-Lead PLCC w/o 12 Leads  
3.3 V logic compatible  
Lower di/dt gate drive for better noise immunity  
Externally programmable delay for automatic fault clear  
All parts are LEAD-FREE  
Feature Comparison: IR213(6,62,63,65,66,67,68)  
Description  
Part  
IR2136  
IR21362  
IR21363  
IR21365  
IR21366  
IR21367  
IR21368  
The IR2136x (J&S) are high voltage, high  
speed power MOSFET and IGBT drivers with  
three independent high and low side  
referenced output channels for 3-phase  
applications. Proprietary HVIC technology  
enables ruggedized monolithic construction.  
Logic inputs are compatible with CMOS or  
LSTTL outputs, down to 3.3 V logic. A current  
trip function which terminates all six outputs  
___ ___  
HIN, LIN  
___  
HIN, LIN  
___ ___  
HIN, LIN  
___ ___  
HIN, LIN  
___ ___  
HIN, LIN  
___ ___  
HIN, LIN  
___ ___  
HIN, LIN  
Input Logic  
Ton (typ.)  
Toff (typ.)  
400 ns  
380ns  
400 ns  
380 ns  
400 ns  
380 ns  
400 ns  
380 ns  
250 ns  
180 ns  
250 ns  
180 ns  
400 ns  
380 ns  
VIH (typ.)  
VIL (typ.)  
2.7 V  
1.7 V  
0.46 V  
8.9 V  
8.2 V  
2.7 V  
1.7 V  
2.7 V  
1.7 V  
2.7 V  
1.7 V  
2.0 V  
1.3 V  
2.0 V  
1.3 V  
2.0 V  
1.3 V  
4.3 V  
8.9 V  
8.2 V  
Vitrip+  
0.46 V  
10.4 V  
9.4 V  
0.46 V  
11.2 V  
11.0 V  
4.3 V  
0.46 V  
11.2 V  
11.0 V  
4.3 V  
UVCC/BS+  
UVCC/BS-  
11.2 V  
11.0 V  
11.2 V  
11.0 V  
can be derived from an external current sense resistor. An enable function is available to terminate all six outputs simultaneously. An  
open-drain FAULT signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred. Overcurrent fault  
conditions are cleared automatically after a delay programmed externally via an RC network connected to the RCIN input. The output  
drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to  
simplify use in high frequency applications. The floating channels can be used to drive N-channel power MOSFETs or IGBTs in the  
high side configuration which operates up to 600 V.  
Typical Connection  
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1
IR213(6,62,63,65,66,67,68)(J&S) & PbF  
Absolute Maximum Ratings  
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage  
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are  
measured under board mounted and still air conditions.  
Symbol  
Definition  
Min  
Max  
Units  
VS  
High side offset voltage  
VB 1,2,3 - 25 VB 1,2,3 + 0.3  
-0.3 625  
VS1,2,3 - 0.3 VB 1,2,3 + 0.3  
VB  
VHO  
High side floating supply voltage  
High side floating output voltage  
Low side and logic fixed supply voltage  
Logic ground  
VCC  
-0.3  
VCC - 25  
-0.3  
25  
VSS  
VCC + 0.3  
VCC + 0.3  
Lower of  
V
VLO1,2,3  
Low side output voltage  
VIN  
Input voltage LIN, HIN, ITRIP, EN  
VSS -0.3 (VSS + 15) or  
VCC + 0.3)  
VRCIN  
VFLT  
RCIN input voltage  
FAULT output voltage  
VSS -0.3  
VSS -0.3  
VCC + 0.3  
VCC + 0.3  
50  
Allowable offset voltage slew rate  
dV/dt  
V/ns  
W
(28 lead PDIP)  
-55  
1.5  
1.6  
2.0  
83  
Package power dissipation  
@ TA +25 °C  
(28 lead SOIC)  
(44 lead PLCC)  
(28 lead PDIP)  
(28 lead SOIC)  
(44 lead PLCC)  
PD  
Thermal resistance, junction to  
ambient  
RthJA  
°C/W  
°C  
78  
63  
TJ  
TS  
TL  
Junction temperature  
Storage temperature  
150  
150  
300  
Lead temperature (soldering, 10 seconds)  
Recommended Operating Conditions  
The input/output logic-timing diagram is shown in Fig. 1. For proper operation the device should be used within the  
recommended conditions. All voltage parameters are absolute referenced to COM. The VS offset ratings are tested  
with all supplies biased at a 15 V differential.  
Symbol  
Definition  
Min  
Max  
Units  
IR213(6,68)  
IR21362  
VS1,2,3 +10  
VS1,2,3 + 20  
VB1,2,3  
High side floating supply voltage  
VS1,2,3 +11.5 VS1,2,3 + 20  
IR213(6,63,65,66,67) VS1,2,3 +12  
VS1,2,3 + 20  
600  
VB1,2,3  
VCC  
VS 1,2,3  
VHO 1,2,3  
VLO1,2,3  
High side floating supply offset voltage  
High side output voltage  
Note 1  
VS1,2,3  
0
Low side output voltage  
V
IR213(6,68)  
10  
20  
Low side and logic fixed supply  
voltage  
VCC  
IR21362  
11.5  
12  
20  
IR213(6,63,65,66,67)  
20  
VSS  
VFLT  
VRCIN  
Logic ground  
-5  
5
FAULT output voltage  
VSS  
VSS  
VCC  
RCIN input voltage  
VCC  
Note 1: Logic operational for VS of (COM - 5 V) to (COM + 600 V). Logic state held for VS of (COM - 5 V) to (COM – VBS).  
(Please refer to the Design Tip DT97-3 for more details).  
Note 2: All input pins and the ITRIP and EN pins are internally clamped with a 5.2 V zener diode.  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
Recommended Operating Conditions - (Continued)  
The input/output logic-timing diagram is shown in Fig. 1. For proper operation the device should be used within the  
recommended conditions. All voltage parameters are absolute referenced to COM. The VS offset ratings are tested  
with all supplies biased at a 15 V differential.  
Symbol  
Definition  
Min  
Max Units  
VITRIP  
ITRIP input voltage  
VSS  
VSS + 5  
V
Logic input voltage LIN, HIN (IR213(6,63,65,66,67,68)),  
HIN (IR21362), EN  
VIN  
VSS  
VSS + 5  
TA  
Ambient temperature  
-40  
125  
°C  
Note 2: All input pins and the ITRIP and EN pins are internally clamped with a 5.2 V zener diode.  
Static Electrical Characteristics  
VBIAS (VCC,VBS1,2,3) = 15 V unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to VSS and are  
applicable to all six channels (HIN1,2,3 and LIN1,2,3). The VO and IO parameters are referenced to COM and VS1,2,3  
and are applicable to the respective output leads: HO1,2,3 and LO1,2,3.  
Symbol  
Definition  
Min Typ Max Units Test Conditions  
Logic “0” input voltage LIN1,2,3, HIN1,2,3  
IR213(6,63,65)  
Logic “1” input voltage HIN1,2,3 IR21362  
Logic “0” input voltage LIN1,2,3, HIN1,2,3  
IR213(66,67,68)  
3.0  
2.5  
VIH  
Logic “1” input Voltage LIN1,2,3, HIN1,2,3  
IR213(6,63,65)  
Logic “0” input voltage HIN1,2,3 IR21362  
VIL  
0.8  
Logic “0” input voltage LIN1,2,3, HIN1,2,3  
IR213(66,67,68)  
VEN,TH+  
VEN,TH-  
Enable positive going threshold  
Enable negative going threshold  
3
0.8  
IR2136(2)(3)(6) 0.37 0.46 0.55  
V
ITRIP positive going  
threshold  
VIT,TH+  
IR21365(7)(8)  
3.85 4.30 4.75  
IR2136(2)(3)(6)  
IR21365(7)(8)  
0.07  
.15  
8
VIT,HYS  
ITRIP input hysteresis  
VRCIN, TH+  
VRCIN, HYS  
VOH  
RCIN positive going threshold  
RCIN input hysteresis  
3
High level output voltage, VBIAS - VO  
Low level output voltage, VO  
0.9  
0.4  
1.4  
0.6  
9.8  
Io = 20 mA  
VOL  
IR2136(8)  
IR21362  
IR21363(5)(6)(7) 10.6 11.1 11.6  
8.0 8.9  
9.6 10.4 11.2  
VCC and VBS supply  
undervoltage positive going  
threshold  
VCCUV+  
VBSUV+  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
Static Electrical Characteristics - (Continued)  
VBIAS (VCC,VBS1,2,3) = 15 V unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to VSS and are  
applicable to all six channels (HIN1,2,3 and LIN1,2,3). The VO and IO parameters are referenced to COM and VS1,2,3 and  
are applicable to the respective output leads: HO1,2,3 and LO1,2,3.  
Symbol  
Definition  
Min Typ Max Units Test Conditions  
IR2136(8)  
IR21362  
IR2136(3,5,6,7) 10.4 10.9 11.4  
7.4 8.2  
8.6 9.4 10.2  
9.0  
V
CC and VBS supply  
VCCUV-  
VBSUV-  
undervoltage negative going  
threshold  
V
IR2136  
0.3 0.7  
0.5 1.0  
V
CC and VBS supply  
VCCUVH  
VBSUVH  
undervoltage lockout  
hysteresis  
IR21362  
IR2136(3,5)  
0.2  
VB1,2,3 = VS1,2,3  
600 V  
=
ILK  
Offset supply leakage current  
50  
µA  
IQBS  
IQCC  
Quiescent VBS supply current  
Quiescent VCC supply current  
70  
120  
2.3  
5.5  
V
IN = 0 V or 5 V  
1.6  
mA  
V
VIN,CLAMP  
Input clamp voltage (HIN, LIN, ITRIP and EN)  
4.9 5.2  
IIN =100 µA  
VLIN = 5 V  
IR2136(2,3,5)  
Input bias current (LOUT = HI)  
IR2136(6,7,8)  
IR2136(2,3,5)  
Input bias current (LOUT = LO)  
IR2136(6,7,8)  
200 300  
30 100  
100 220  
ILIN+  
ILIN-  
VLIN = 0 V  
VHIN = 5 V  
VHIN = 0 V  
0
1
IR2136(3,5)  
IR21362  
IR2136(6,7,8)  
IR2136(3,5)  
IR2136(2,6,7,8)  
200 300  
30  
30  
100 220  
0
IHIN+  
Input bias current (HOUT = HI)  
100  
100  
µA  
IHIN-  
Input bias current (HOUT = LO)  
1
IITRIP+  
IITRIP-  
IEN+  
“High” ITRIP input bias current  
“Low” ITRIP input bias current  
30  
100  
VITRIP = 5 V  
VITRIP = 0 V  
0
30  
0
1
100  
1
“High” ENABLE input bias current  
“Low” ENABLE input bias current  
VENABLE = 5 V  
VENABLE =0 V  
IEN-  
Vrcin= 0 V or  
15 V  
Vo =0 V,  
PW 10 µs  
Vo =15 V,  
PW 10 µs  
IRCIN  
IO+  
RCIN input bias current  
0
1
Output high short circuit pulsed current  
Output low short circuit pulsed current  
120 200  
250 350  
mA  
IO-  
Ron_RCIN  
RCIN low on resistance  
FAULT low on resistance  
50  
50  
100  
100  
Ron_FAULT  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
Dynamic Electrical Characteristics  
VCC = VBS = VBIAS = 15 V, VS1,2,3 = VSS = COM, TA = 25 °C and CL = 1000 pF unless otherwise specified.  
Test  
Conditions  
Symbol  
Definition  
Min Typ Max Units  
IR2136(2,3,5,8) 300 425 550  
IR2136(6,7) 250  
IR2136(2,3,5,8) 250 400 550  
ton  
toff  
Turn-on propagation delay  
Turn-off propagation delay  
VIN = 0 V & 5 V  
IR2136(6,7)  
180  
125 190  
50 75  
tr  
tf  
Turn-on rise time  
Turn-off fall time  
IR2136(2,3,5,8) 300 450 600  
ns  
ENABLE low to output shutdown  
propagation delay  
VIN, VEN = 0 V  
or 5 V  
tEN  
IR2136(6,7)  
100 250 400  
500 750 1000  
tITRIP  
tbl  
ITRIP to output shutdown propagation delay  
ITRIP blanking time  
VITRIP = 5 V  
100 150  
VIN = 0 V or 5 V  
VITRIP = 5 V  
ITRIP to FAULT propagation delay  
tFLT  
400 600 800  
Input filter time (HIN, LIN)  
(IR213(6,62,63,65,68) only)  
tFILIN  
100 200  
1.3 1.65  
2
VIN = 0 V & 5 V  
VIN = 0 V or 5 V  
VITRIP = 0 V  
tFLTCLR  
FAULT clear time RCIN: R = 2 M, C = 1 nF  
ms  
ns  
DT  
MT  
Deadtime  
220 290 360  
VIN = 0 V & 5 V  
Matching delay ON and OFF  
40  
25  
40  
75  
70  
75  
External dead  
time >400 ns  
Matching delay, max (ton, toff) – min (ton, toff),  
(ton, toff are applicable to all 3 channels)  
MDT  
PM  
Output pulse width matching (pwin-pwout) (Fig.2)  
Note: For high side PWM, HIN pulse width must be 1 µs.  
VCC  
<UVCC  
15 V  
15 V  
15 V  
VBS  
X
<UVBS  
15 V  
15 V  
15 V  
ITRIP  
X
0 V  
0 V  
>VITRIP  
0 V  
ENABLE  
X
FAULT  
LO1,2,3  
HO1,2,3  
0 (note 1)  
high imp  
high imp  
0 (note 2)  
high imp  
0
0
0
5 V  
5 V  
5 V  
0 V  
LIN1,2,3  
LIN1,2,3  
HIN1,2,3  
0
0
0
0
15 V  
Note 1: A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously.  
Note 2: UVCC is not latched, when VCC > UVCC, FAULT returns to high impedance.  
Note 3: When ITRIP < VITRIP, FAULT returns to high-impedance after RCIN pin becomes greater than 8 V (@ VCC = 15 V).  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
Functional Block Diagram  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
Functional Block Diagram  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
Functional Block Diagram  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
Lead Definitions  
Symbol  
Description  
VCC  
VSS  
Low side and logic fixed supply  
Logic ground  
HIN1,2,3  
HIN1,2,3  
LIN1,2,3  
Logic inputs for high side gate driver outputs (HO1,2,3), out of phase [IR213(6,63,65,66,67,68)]  
Logic inputs for high side gate driver outputs (HO1,2,3), in phase (IR21362)  
Logic input for low side gate driver outputs (LO1,2,3), out of phase  
Indicates over-current (ITRIP) or low-side undervoltage lockout has occurred. Negative logic, open-  
drain output  
Logic input to enable I/O functionality. I/O logic functions when ENABLE is high (i.e., positive logic)  
No effect on FAULT and not latched  
FAULT  
EN  
Analog input for overcurrent shutdown. When active, ITRIP shuts down outputs and activates FAULT  
and RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally set time  
ITRIP  
T
FLTCLR, then automatically becomes inactive (open-drain high impedance).  
External RC network input used to define FAULT CLEAR delay, TFLTCLR, approximately equal to R*C.  
When RCIN>8 V, the FAULT pin goes back into open-drain high-impedance  
RCIN  
COM  
VB1,2,3  
Low side gate drivers return  
High side floating supply  
HO1,2,3  
VS1,2,3  
High side gate driver outputs  
High voltage floating supply return  
Low side gate driver outputs  
LO1,2,3  
Note: All input pins and the ITRIP pin are internally clamped with a 5.2 V zener diode.  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
Lead Assignments  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
HIN1,2,3  
HIN1,2,3  
LIN1,2,3  
EN  
ITRIP  
FAULT  
RCIN  
HO1,2,3  
LO1,2,3  
Fig. 1. Input/Output Timing Diagram  
LIN1,2,3  
50%  
50%  
50%  
HIN1,2,3  
EN  
PWIN  
ten  
LIN1,2,3  
HIN1,2,3  
50%  
50%  
90%  
HO1,2,3  
LO1,2,3  
ton  
tr  
toff  
tf  
PWOUT  
90%  
90%  
HO1,2,3  
LO1,2,3  
10%  
10%  
Fig. 2. Switching Time Waveforms  
Fig. 3. Output Enable Timing Waveform  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
L I N 1 , 2 , 3  
H I N 1 , 2 , 3  
5 0 %  
5 0 %  
L I N 1 , 2 , 3  
H I N 1 , 2 , 3  
5 0 %  
5 0 %  
5 0 %  
5 0 %  
L O 1 , 2 , 3  
H O 1 , 2 , 3  
D T  
D T  
5 0 %  
5 0 %  
Fig. 4. Internal Deadtime Timing Waveforms  
Fig. 5. ITRIP/RCIN Timing Waveforms  
tin,fil  
tin,fil  
n
off  
on  
on  
on  
off  
off  
HIN/LIN  
HO/LO  
high  
low  
Fig. 6. Input Filter Function  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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25  
IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
Case Outlines  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
Case Outlines  
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IR213(6,62,63,65,66,67,68)(J&S) & PbF  
ORDER INFORMATION  
Basic Part  
Order IR2136(3,5,6,7,8)  
28-Lead PDIP IR2136(3,5,6,7,8)  
28-Lead SOIC IR2136(3,5,6,7,8)S  
44-Lead PLCC IR2136(3,5,6,7,8)J  
28-Lead PDIP IR21362  
Order IR2136(3,5,6,7,8)S  
Order IR2136(3,5,6,7,8)J  
Order IR21362  
Order IR21362S  
Order IR21362J  
28-Lead SOIC IR21362S  
44-Lead PLCC IR21362J  
Lead-Free Part  
Order IR2136(3,5,6,7,8)PbF  
Order IR2136(3,5,6,7,8)(S)PbF  
Order IR2136(3,5,6,7,8)(J)PbF  
Order IR21362PbF  
28-Lead PDIP IR2136(3,5,6,7,8)  
28-Lead SOIC IR2136(3,5,6,7,8)S  
44-Lead PLCC IR2136(3,5,6,7,8)J  
28-Lead PDIP IR21362  
Order IR21362SPbF  
28-Lead SOIC IR21362S  
44-Lead PLCC IR21362J  
Order IR21362JPbF  
WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 90245 Tel: (310) 252-7105  
This part has been qualified per industrial level  
http://www.irf.com Data and specifications subject to change without notice. 7/08/2008  
www.irf.com  
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