IR21364JTRPBF_技术文档

Data Sheet No. PD PD60342A

November 13, 2009

IR21364(S&J)PbF

3-PHASE BRIDGE DRIVER

Features

Product Summary

•

Floating channel designed for bootstrap operation

3 phase bridge

driver

Tolerant to negative transient voltage – dV/dt immune

Gate drive supply range from 11.5 V to 20 V

Undervoltage lockout for all channels

Over-current shutdown turns off all six drivers

Independent 3 half-bridge drivers

Topology

V_OFFSET

V_OUT

≤ 600 V

11.5 V – 20 V

Matched propagation delay for all channels

Cross-conduction prevention logic

I_o+& I _o-

(typical)

200 mA & 350 mA

500 ns & 530 ns

Low side and High side outputs in phase with inputs.

3.3 V logic compatible

Lower di/dt gate drive for better noise immunity

Externally programmable delay for automatic fault clear

RoHS Compliant

t_ON& t_OFF

(typical)

Package Options

Typical Applications

•

Motor Control

Air Conditioners/ Washing Machines

General Purpose Inverters

Micro/Mini Inverter Drivers

28-Lead SOIC

44-Lead PLCC

w/o 12 Leads

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1

IR21364(S&J)PbF

Description

The IR21364(S&J)PBF is a high voltage, high speed power MOSFET and IGBT drivers with three

independent high and low side referenced output channels for 3-phase applications. Proprietary HVIC

technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL

outputs, down to 3.3V logic. A current trip function which terminates all six outputs can be derived from an

external current sense resistor. An enable function is available to terminate all six outputs simultaneously. An

open-drain FAULT signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred.

Overcurrent fault conditions are cleared automatically after a delay programmed externally via an RC

network connected to the RCIN input. The output drivers feature a high pulse current buffer stage designed

for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency

applications. The floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side

configuration which operates up to 600 V.

Qualification Information^†

Industrial^††

Comments: This family of ICs has passed JEDEC’s

Qualification Level

Industrial qualification. IR’s Consumer qualification

level is granted by extension of the higher Industrial

level.

MSL3^†††, 260°C

SOIC28W

(per IPC/JEDEC J-STD-020)

Moisture Sensitivity Level

MSL3^†††, 245°C

PLCC44

(per IPC/JEDEC J-STD-020)

Class 2

Human Body Model

(per JEDEC standard JESD22-A114)

ESD

Class B

Machine Model

(per EIA/JEDEC standard EIA/JESD22-A115)

Class I, Level A

(per JESD78)

Yes

IC Latch-Up Test

RoHS Compliant

†

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

†† Higher qualification ratings may be available should the user have such requirements. Please contact

your International Rectifier sales representative for further information.

Higher MSL ratings may be available for the specific package types listed here. Please contact your

†††

International Rectifier sales representative for further information.

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2

IR21364(S&J)PbF

Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are

measured under board mounted and still air conditions.

Symbol

Definition

Min

V_{B 1,2,3}- 25 V_{B 1,2,3}+ 0.3

-0.3 625

V_S1,2,3- 0.3 V_{B 1,2,3}+ 0.3

Max

Units

V_S

High side offset voltage

V_B

V_HO

High side floating supply voltage

High side floating output voltage

Low side and logic fixed supply voltage

Logic ground

V_CC

-0.3

V_CC- 25

-0.3

25

V

V_SS

V_CC+ 0.3

lower of

V_LO1,2,3

Low side output voltage

V_IN

Input voltage LIN, HIN, ITRIP, EN, RCIN

V_SS-0.3 V_CC+ 0.3 or

Vss+15

V_FLT

FAULT output voltage

V_SS-0.3

—

V_CC+ 0.3

50

dV/dt

Allowable offset voltage slew rate

V/ns

W

(28 lead SOIC)

(44 lead PLCC)

(28 lead SOIC)

(44 lead PLCC)

—

1.6

Package power dissipation

@ T_A≤ +25 °C

P_D

—

2.0

—

78

Thermal resistance, junction to

ambient

°C/W

°C

Rth_JA

—

63

T_J

T_S

T_L

Junction temperature

—

150

300

Storage temperature

-55

—

Lead temperature (soldering, 10 seconds)

Recommended Operating Conditions

The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the

recommended conditions. All voltage parameters are absolute referenced to COM. The V_S& V_SSoffset rating are

tested with all supplies biased at a 15 V differential.

Symbol

Definition

High side floating supply voltage

Min.

Max.

Units

V_B1,2,3

V_{S 1,2,3}

V_CC

IR21364

V_S1,2,3+11.5 V_S1,2,3+ 20

High side floating supply voltage

Low side supply voltage

High side output voltage

Low side output voltage

Logic ground

Note 1

11.5

V_S1,2,3

0

600

20

V_{HO 1,2,3}

V_LO1,2,3

V_SS

V_B1,2,3

V_CC

V

-5

5

V_FLT

FAULT output voltage

RCIN input voltage

V_SS

-40

V_CC

V_RCIN

V_ITRIP

V_IN

V_CC

ITRIP input voltage

V_SS+ 5

125

Logic input voltage LIN, HIN, EN

Ambient temperature

T_A

°C

Note 1: Logic operational for

V_Sof COM -5 V to COM + 600 V. Logic state held for V_Sof COM -5 to COM – V_BS.

(Please refer to the Design Tip DT97 -3 for more details).

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3

IR21364(S&J)PbF

Static Electrical Characteristics

V_BIAS(V_CC, V_{BS 1,2,3}) = 15 V, TA = 25°C unless otherwise specified. The V_IN, V_THand I_INparameters are referenced to

V_SSand are applicable to all six channels (HIN1,2,3 and LIN1,2,3). The V_Oand I_Oparameters are referenced to COM

and V_S1,2,3and are applicable to the respective output leads: HO1,2,3 and LO1,2,3.

Test

Conditions

Symbol

Definition

Logic “0” input voltage

Min Typ Max Units

V_IH

V_IL

—

2.5

—

0.8

—

Logic “1” input voltage

V_EN,TH+

V_EN,TH-

V_IT,TH+

V_IT,HYS

V_{RCIN, TH+}

V_{RCIN, HYS}

V_OH

Enable positive going threshold

Enable negative going threshold

ITRIP positive going threshold

ITRIP hysteresis

2.5

—

0.8

0.37 0.46 0.55

—

0.07

8

—

RCIN positive going threshold

RCIN hysteresis

3

—

High level output voltage, V_BIAS- V_O

0.9

1.4

Io = 20 mA

V

V_OL

Low level output voltage, V_O

—

0.4

0.6

V_CCsupply undervoltage positive going

threshold

V_CCUV+

IR21364

9.6 10.4 11.2

V_CCsupply undervoltage negative going

threshold

V_CCUV-

V_CCUVHY

V_BSUV+

IR21364

8.6

—

9.4 10.2

V_CCsupply undervoltage hysteresis

1

—

V_BSsupply undervoltage positive going

threshold

9.6 10.4 11.2

V_BSsupply undervoltage negative going

threshold

V_BSUV-

IR21364

8.6

9.4 10.2

V_BSsupply undervoltage

hysteresis

V_BSUVHY

llk

—

1

—

50

Offset supply leakage current

—

V_B= V_S= 600 V

µA

V

_B1,2,3= V_S1,2,3

600 V

=

I_QBS

Quiescent V_BSsupply current

70

120

I_QCC

Quiescent V_CCsupply current

Input bias current (LOUT = HI)

Input bias current (LOUT = LO)

Input bias current (HOUT = HI)

Input bias current (HOUT = LO)

“High” ITRIP input bias current

“Low” ITRIP input bias current

“High” ENABLE input bias current

“Low” ENABLE input bias current

—

-1

—

-1

—

-1

—

-1

0.6

1.3

mA V_IN= 0 V or 5 V

V_LIN= 3.3 V

I_LIN

I_HIN

+

100 195

-

—

V_LIN= 0 V

+

100 195

V_HIN= 3.3 V

V_HIN= 0 V

-

—

3.3

—

6

I_ITRIP+

I_ITRIP-

I_EN+

V_ITRIP= 3.3 V

µA

—

V_ITRIP= 0 V

V_EN= 3.3 V

V_EN= 0 V

100

—

I_EN-

Vrcin = 0 V or 15

V

I_RCIN

Io+

Io-

RCIN input bias current

—

1

Vo = 0 V,

PW ≤ 10 µs

Vo = 15 V,

Output high short circuit pulsed current

Output low short circuit pulsed current

120 200

250 350

—

mA

PW ≤ 10 µs

R_{on_RCIN}

RCIN low on resistance

FAULT low on resistance

—

50

100

Ω

I = 1.5 mA

R_{on_FAULT}

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IR21364(S&J)PbF

Dynamic Electrical Characteristics

Dynamic Electrical Characteristics V_CC= V_BS= V_BIAS= 15 V, V_S1,2,3= V_SS= COM, TA = 25°C and CL = 1000 pF

unless otherwise specified

.

Symbol

Definition

Min Typ Max Units Test Conditions

t_on

t_off

t_r

Turn-on propagation delay

Turn-off propagation delay

Turn-on rise time

350

375

—

500

530

125

50

650

685

190

75

V_IN= 0 V & 5 V

t_f

Turn-off fall time

—

ENABLE low to output shutdown propagation

delay

t_EN

300

450

600

V_IN,V_EN= 0 V or 5 V

V_ITRIP= 5 V

t_ITRIP

t_bl

ITRIP to output shutdown propagation delay

ITRIP blanking time

500

100

400

750 1000

150

600

—

V_IN= 0 V or 5 V

V_ITRIP= 5 V

ns

t_FLT

ITRIP to FAULT propagation delay

800

t_FILIN

t_filterEn

DT

Input filter time (HIN, LIN)

100

220

—

200

290

—

V_IN= 0 V & 5 V

Enable input filter time

Deadtime

360

75

70

75

MT

Ton, off matching time (on all six channels)

DT matching (Hi->Lo & Lo->Hi on all channels)

pulse width distortion (pwin-pwout)

External dead time

>450 nsec

MDT

PM

—

PW input =10 µs

V_IN= 0 V or 5 V

V_ITRIP= 0 V

t_FLTCLR

FAULT clear time RCIN: R = 2 MΩ, C = 1 nF

1.3 1.65

2

ms

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IR21364(S&J)PbF

HIN1,2,3

LIN1,2,3

EN

ITRIP

FAULT

RCIN

HO1,2,3

LO1,2,3

Fig. 1. Input/Output Timing Diagram

LIN1,2,3

HIN1,2,

50%

EN

PW

IN

ten

90%

HO1,2,3

LO1,2,3

ton

t

tof

t

PW

50

90%

HO1,2,3

LO1,2,3

10%

Fig. 2. Switching Time Waveforms

Fig. 3. Output Enable Timing Waveform

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IR21364(S&J)PbF

Fig. 4. Internal Deadtime Timing Waveforms

RCIN

50%

ITRIP

50%

tflt

FAULT

90%

tfltclr

Any

Ouput

titrip

Fig. 5. ITRIP/RCIN Timing Waveforms

t_in,fi

off

on

off

on

off

on

HIN/LI

high

lo

Fig. 6. Input Filter Function

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7

IR21364(S&J)PbF

Lead Definitions

Symbol

Description

V_CC

V_SS

Low side supply voltage

Logic ground

HIN1,2,3

LIN1,2,3

Logic inputs for high side gate driver outputs (HO1,2,3), in phase

Logic input for low side gate driver outputs (LO1,2,3), in phase

Indicates over-current (ITRIP) or low-side undervoltage lockout has occurred. Negative logic, open-drain

output

FAULT

EN

Logic input to enable I/O functionality. Positive logic, i.e. I/O logic functions When ENABLE is high. No

effect on FAULT and not latched

Analog input for overcurrent shutdown. When active, ITRIP shuts down outputs and activates FAULT and

RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally set time T_FLTCLR, then

automatically becomes inactive (open-drain high impedance).

ITRIP

External RC network input used to define FAULT CLEAR delay, T_FLTCLR,approximately equal to R*C.

When RCIN > 8 V, the FAULT pin goes back into open-drain high-impedance

RCIN

COM

V_B1,2,3

Low side gate drivers return

High side floating supply

HO1,2,3

V_S1,2,3

High side gate driver outputs

High voltage floating supply return

Low side gate driver outputs

LO1,2,3

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8

IR21364(S&J)PbF

Functional Block Diagram

VCC

<UV_CC

15 V

VBS

X

<U_VBS

15 V

ITRIP

X

0 V

>V_ITRIP

0 V

ENAB LE

X

5 V

0 V

FAULT

0 (note 1)

high imp

0 (note 2)

high imp

LO1,2,3

0

LIN1,2,3

0

HO1,2,3

0

HIN1,2,3

0

Note 1: A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously.

Note 2: U_VCCis not latched, when V_CC> U_VCC, FAULT return to high impedance.

Note 3: When ITRIP <V_ITRIP, FAULT returns to high-impedance after RCIN pin becomes greater than 8 V (@ V_CC= 15 V)

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9

IR21364(S&J)PbF

Parameter Temperature Trends

Figures 7-39 provide information on the experimental performance of the IR21364 HVIC. The line plotted

in each figure is generated from actual lab data. A small number of individual samples were tested at

three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The

line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have

been connected together to illustrate the understood temperature trend. The individual data points on the

curve were determined by calculating the averaged experimental value of the parameter (for a given

temperature).

800

700

600

500

400

300

200

100

0

1000

800

600

400

200

0

Exp.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 8. (Toff_Ls1) Turn-off Propagation Delay

vs. Temperature

Fig. 7. (Ton_Ls1 ) Turn-on Propagation Delay

vs. Temperature

800

700

600

800

700

600

Exp.

500

400

300

200

100

0

400

300

200

100

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 9. (Ton_Hs11) Turn-on Propagation Delay

vs. Temperature

Fig. 10. (Toff_Hs21) Turn-off Propagation

Delay vs. Temperature

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10

IR21364(S&J)PbF

250

200

150

100

50

120

100

80

60

40

20

0

Exp.

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 11. Turn-on Rise Time vs. Temperature

Fig. 12. Turn-off Fall Time vs. Temperature

100

80

60

40

20

0

60

Exp.

40

20

0

Exp.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 13. Ton, off matching time vs.

Temperature

Fig. 14. DT matching time vs. Temperature

100

80

60

40

20

0

1000

800

Exp.

600

400

200

0

Exp.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 16. ITRIP to Output Shutdown Propagation

Delay vs. Temperature

Fig. 15. Pulse Width Distortion vs.

Temperature

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11

IR21364(S&J)PbF

1200

1000

800

600

400

200

0

1000

800

600

400

200

0

Exp.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 17. Dead Time vs. Temperature

Figure 18. EN to Output Shutdown Time vs.

Temperature

1000

900

800

700

600

500

400

300

200

100

0

5.0

4.0

3.0

2.0

1.0

0.0

Exp.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 19. ITRIP to FAULT Indication Delay vs.

Temperature

Fig. 20. FAULT Clear Time vs. Temperature

6.0

2.5

2.0

4.5

1.5

Exp.

3.0

Exp.

1.0

0.5

0.0

1.5

0.0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 21. Input Positive Going Threshold vs.

Temperature

Fig. 22. Input Negative Going Threshold vs.

Temperature

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12

IR21364(S&J)PbF

800

700

600

500

400

300

200

100

0

800

700

600

500

400

300

200

100

0

EXP.

Exp.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 24. ITRIP Input Negative Going Threshold

vs. Temperature

Fig. 23. ITRIP Input Positive Going Threshold

vs. Temperature

600

500

400

1600

1200

300

800

Exp.

200

100

0

400

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 25. Low Level Output Voltage vs.

Temperature

Fig. 26. High Level Output Voltage vs.

Temperature

2.5

2.0

1.5

1.0

0.5

0.0

120

100

80

60

40

20

0

Exp.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 28. Offset Supply Leakage Current vs.

Temperature

Fig. 27. FAULT Low On-Resistance vs.

Temperature

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13

IR21364(S&J)PbF

2.0

1.5

1.0

0.5

0.0

2.0

1.5

1.0

0.5

0.0

Exp.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 29. Quiescent V_CCSupply Current vs.

Temperature

Fig. 30. Quiescent V_CCSupply Current vs.

Temperature

80

70

60

50

40

30

20

10

0

140

120

100

80

60

40

20

0

Exp.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 31. Quiescent V_BSSupply Current vs.

Temperature

Fig. 32. Quiescent V_BSSupply Current vs.

Temperature

18.0

15.0

12.0

9.0

12.0

9.0

6.0

3.0

0.0

Exp.

6.0

3.0

0.0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 34. V_CCSupply Undervoltage Positive

Going Threshold vs. Temperature

Fig. 33. V_CCSupply Undervoltage Negative

Going Threshold vs. Temperature

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14

IR21364(S&J)PbF

15.0

12.0

9.0

15.0

12.0

9.0

Exp.

6.0

3.0

0.0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 35. V_BSSupply Undervoltage Negative

Going Threshold vs. Temperature

Fig. 36. V_BSSupply Undervoltage Positive

Going Threshold vs. Temperature

0.0

-0.1

-0.2

-0.3

-0.4

-0.5

0.5

-50

-25

0

25

50

75

100

125

0.4

Exp.

0.3

0.2

0.1

0.0

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 37. Output High Short Circuit Pulsed

Current vs. Temperature

Fig. 38. Output Low Short Circuit Pulsed Current

vs. Temperature

0

-50

-25

0

25

50

75

100

125

-2

-4

Exp.

-6

-8

-10

-12

-14

Temperature (^oC)

Fig. 39. Max -VS vs. Temperature

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IR21364(S&J)PbF

Case Outlines

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IR21364(S&J)PbF

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IR21364(S&J)PbF

LOADED TAPE FEED DIRECTION

A

B

H

D

F

C

NOTE : CONTROLLING

DIMENSION IN MM

E

G

CARRIER TAPE DIMENSION FOR 28SOICW

Metric

Imperial

Code

A

B

C

D

E

F

G

Min

11.90

3.90

23.70

11.40

10.80

18.20

1.50

Max

12.10

4.10

24.30

11.60

11.00

18.40

n/a

Min

Max

0.476

0.161

0.956

0.456

0.433

0.724

n/a

0.468

0.153

0.933

0.448

0.425

0.716

0.059

H

1.50

1.60

0.062

F

D

B

C

A

E

G

H

REEL DIMENSIONS FOR 28SOICW

Metric

Imperial

Min

Code

A

Min

329.60

20.95

12.80

1.95

Max

330.25

21.45

13.20

2.45

102.00

30.40

29.10

26.40

Max

13.001

0.844

0.519

0.096

4.015

1.196

1.145

1.039

12.976

0.824

0.503

0.767

3.858

n/a

B

C

D

E

98.00

n/a

F

G

26.50

24.40

1.04

0.96

H

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IR21364(S&J)PbF

LOADED TAPE FEED DIRECTION

A

B

H

D

F

C

NOTE : CONTROLLING

DIMENSION IN MM

E

G

CARRIER TAPE DIMENSION FOR 44PLCC

Metric

Imperial

Code

A

Min

23.90

3.90

Max

24.10

4.10

Min

0.94

Max

0.948

0.161

1.271

0.562

0.712

n/a

B

0.153

1.248

0.555

0.704

0.078

0.059

C

31.70

14.10

17.90

2.00

32.30

14.30

18.10

n/a

D

E

F

G

H

1.50

1.60

0.062

F

D

B

C

A

E

G

H

REEL DIMENSIONS FOR 44PLCC

Metric

Imperial

Max

Code

A

Min

329.60

20.95

12.80

1.95

Max

330.25

21.45

13.20

2.45

Min

12.976

0.824

0.503

0.767

3.858

n/a

13.001

0.844

0.519

0.096

4.015

1.511

1.409

1.303

B

C

D

E

98.00

n/a

34.7

102.00

38.4

35.8

F

G

1.366

1.283

H

32.6

33.1

www.irf.com

19

IR21364(S&J)PbF

ORDER INFORMATION

28-Lead SOIC Tape & Reel IR21364STRPbF

44-Lead PLCC Tape & Reel IR21364JTRPbF

28-Lead SOIC IR21364SPbF

44-Lead PLCC IR21364JPbF

The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility

for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other

rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or

patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document

supersedes and replaces all information previously supplied.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technical-info/

WORLD HEADQUARTERS:

233 Kansas St., El Segundo, California 90245

Tel: (310) 252-7105

www.irf.com

20


型号：	IR21364JTRPBF
厂家：	Infineon
描述：	3-PHASE BRIDGE DRIVER 3相桥式驱动器驱动器
文件：	总20页 (文件大小：361K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IR21364JTRPBF [INFINEON]

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