IR21571STRPBF [INFINEON]
Fluorescent Light Controller, 0.5A, 50.5kHz Switching Freq-Max, PDSO16, MS-012AC, SOIC-16;
| 型号： | IR21571STRPBF |
| 厂家： | 
Infineon |
| 描述： | Fluorescent Light Controller, 0.5A, 50.5kHz Switching Freq-Max, PDSO16, MS-012AC, SOIC-16 光电二极管 |
| 文件： | 总18页 (文件大小：446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet PD No. 60179 revL
IR21571(S)&(PbF)
FULLY INTEGRATED BALLAST CONTROL IC
Features
Programmable preheat time & frequency
Programmable ignition ramp
Thermal overload protection
•
•
•
•
•
•
•
•
•
•
•
•
•
Programmable deadtime
Protection from failure-to-strike
Integrated 600V level-shifting gate driver
Internal 15.6V zener clamp diode on VCC
Micropower startup (150uA)
Lamp filament sensing & protection
Protection from operation below resonance -
0.2V CS threshold sync’d to falling edge on LO
Protection from low-line condition
Automatic restart for lamp exchange
Latch immunity protection on all leads
ESD protection on all leads
•
•
Parts also available LEAD-FREE
Packages
Description
The IR21571 is a fully integrated, fully protected 600V ballast control IC designed
to drive virtually all types of rapid start fluorescent lamp ballasts. Externally pro-
grammable features such as preheat time & frequency, ignition ramp characteris-
tics, and running mode operating frequency provide a high degree of flexibility for
the ballast design engineer. Comprehensive protection features such as protec-
tion from failure of a lamp to strike, filament failures, low dc bus conditions, thermal
overload, or lamp failure during normal operation, as well as an automatic restart
function, have been included in the design. The heart of this control IC is a variable
frequency oscillator with externally programmable deadtime. Precise control of a
50% duty cycle is accomplished using a T-flip-flop. The IR21571 is available in both
16 pin DIP and 16 pin narrow body SOIC packages.
16 Lead SOIC
(narrow body)
16 Lead PDIP
Typical Connection
+ Rectified AC Line
+ VBUS
R2
R1
C1
RSupply
VDC
CPH
RPH
RT
HO
VS
VB
1
2
3
4
5
6
7
8
16
15
14
RGHS
CBLOCK LRES
CPH
CBS
CSNUBBER
DBOOT
CRAMP RPH
13 VCC
12 COM
RT
RRUN
CVCC
D1
R5
RUN
CT
CSTART RSTART
D2
CRES
LO
11
RGLS
R4
CT
RDT
R3
DT
CS
10
ROC
OC
SD
9
C2
RCS
VBUS return
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1
IR21571
(S)&(PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol Definition
Min.
Max.
Units
V
B
High side floating supply voltage
-0.3
625
V
High side floating supply offset voltage
High side floating output voltage
Low side output voltage
V
- 25
V
+ 0.3
+ 0.3
+ 0.3
S
B
B
V
V
HO
V
S
- 0.3
V
B
V
LO
-0.3
V
CC
I
Maximum allowable output current (either output) due to
external power transistor miller effect
OMAX
-500
500
mA
I
R
C
V
pin current
pin voltage
pin voltage
-5
-0.3
-0.3
-5
5
RT
T
T
V
5.5
CT
V
V
V
+ 0.3
DC
DC
CC
I
CPH pin current
5
5
CPH
I
RPH pin current
-5
RPH
mA
I
RUN pin current
-5
5
RUN
I
DT
Deadtime pin current
-5
5
V
Current sense pin voltage
Current sense pin current
Over-current threshold pin current
Shutdown pin current
-0.3
-5
5.5
5
V
CS
I
CS
I
-5
5
OC
mA
I
-5
5
SD
I
Supply current (note 1)
Allowable offset voltage slew rate
-20
-50
—
20
50
1.60
1.00
75
115
150
150
300
CC
dV/dt
V/ns
W
P
D
Package power dissipation @ T ≤ +25°C (16 lead PDIP)
A
P
= (T -T )/Rth
JMAX A JA
(16 lead SOIC)
(16 lead PDIP)
(16 lead SOIC)
—
D
Rth
JA
Thermal resistance, junction to ambient
—
°C/W
—
T
J
Junction temperature
-55
-55
—
T
S
Storage temperature
°C
T
L
Lead temperature (soldering, 10 seconds)
Note 1:
This IC contains a zener clamp structure between the chip V
and COM which has a nominal breakdown
CC
voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source
greater than the V specified in the Electrical Characteristics section.
CLAMP
2
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IR21571
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol Definition
Min.
Max.
Units
V
High side floating supply voltage
Steady state high side floating supply offset voltage
Supply voltage
V
- 0.7
V
BS
CC
CLAMP
V
V
-3.0
600
S
V
CC
V
V
CCUV+
CLAMP
I
Supply current
Note 2
0
10
mA
V
CC
V
V
DC
lead voltage
VCC
DC
C
C
lead capacitance
T
220
1.0
—
—
50
pF
T
R
DT
Deadtime resistance
Over-current (CS+) threshold programming resistance
lead current (Note 3)
kΩ
R
OC
—
I
RT
R
-500
-50
T
I
RPH lead current (Note 3)
0
0
450
450
1
uA
RPH
I
RUN lead current (Note 3)
RUN
I
Shutdown lead current
-1
-1
-40
—
SD
mA
I
Current sense lead current
1
CS
o
C
T
J
Junction temperature
125
5
VBSMIN
Minimum required VBS voltage for proper HO functionality
V
Electrical Characteristics
V
= V
= V
= 14V +/- 0.25V, R = 40.0kΩ, C = 470 pF, RPH and RUN leads no connection, V
= 0.0V,
CPH
CC
BS
BIAS
T
T
o
R
= 6.1kΩ, R
= 20.0kΩ, V
= 0.5V, V
= 0.0V, C = 1000pF, T = 25 C unless otherwise specified.
SD L
A
DT
OC
CS
Supply Characteristics
Symbol Definition
Min. Typ.
Max. Units Test Conditions
V
V
CC
supply undervoltage positive going
10.5
11.4
12.4
V
CC
rising from 0V
CCUV+
V
threshold
V
V
supply undervoltage lockout hysteresis
1.5
50
75
1.8
2.2
UVHYS
CC
I
UVLO mode quiescent current
150
200
300
300
V < V
CC CCUV-
QCCUV
I
Fault-mode quiescent current
SD=5V, CS = 2V or
µA
QCCFLT
Tj > T
SD
I
Quiescent V
supply current
2.9
4.0
3.8
4.3
R
no connection, C
T
QCC
CC
T
connected to COM
mA
I
V
CC
supply current, f= 50kHz
zener clamp voltage
5.5
7.0
R
=36kΩ, R
=
DT
CC50K
T
5.6kΩ, C =220pF
T
V
V
14.5
15.6
16.5
V
I
= 10mA
CC
CLAMP
CC
Note 2: Enough current should be supplied into the VCC lead to keep the internal 15.6V zener clamp diode on this lead
regulating its voltage.
Note 3: Due to the fact that the RT input is a voltage-controlled current source, the total RT lead current is the sum of all
the parallel current sources connected to that lead. For optimum oscillator current mirror performance, this total
current should be kept between 50µA and 500µA. During the preheat mode, the total current flowing out of the RT
lead consists of the RPH lead current plus the current due to the RT resistor. During the run mode, the total RT lead
current consists of the RUN lead current plus the current due to the RT resistor.
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IR21571
(S)&(PbF)
Electrical Characteristics (cont.)
V
= V
= V
= 14V +/- 0.25V, R = 40.0kΩ, C = 470 pF, RPH and RUN leads no connection, V
= 0.0V,
CPH
CC
BS
BIAS
T
T
o
R
= 6.1kΩ, R
= 20.0kΩ, V
= 0.5V, V
= 0.0V, C = 1000pF, T = 25 C unless otherwise specified.
SD L
A
DT
OC
CS
Floating Supply Characteristics
Symbol Definition
Min.
Typ.
Max. Units Test Conditions
I
Quiescent V supply current
BS
0
0
15
65
µA
V
= V
S
QBS0
HO
µA
I
Quiescent V
supply current
5
V
HO
= V
B
35
50
QBS1
BS
I
LK
Offset supply leakage current
—
—
V = V = 600V
B S
Oscillator I/O Characteristics
Symbol Definition
Min. Typ.
Max. Units Test Conditions
fosc
d
Oscillator frequency
Oscillator duty cycle
45.5
48
50.5
RT = 16.9kΩ, RDT =
kHz
6.1kΩ, C =470pF
T
49.5
3.7
50.5
4.3
50
%
V
V
Upper C ramp voltage threshold
T
4.0
2.0
CT+
CT-
1.85
—
2.15
50
V
Lower C ramp voltage threshold
T
mV
SD = 5V, CS = 2V,
or Tj > TSD
V
Fault-mode C lead voltage
T
0
CTFLT
1.85
—
2.0
0
2.15
50
V
V
V
R lead voltage
T
RT
SD = 5V, CS = 2V,
or Tj > TSD
Fault-mode R lead voltage
T
mV
RTFLT
2
2
2.3
2.3
2.5
2.5
tdlo
tdho
LO output deadtime
HO output deadtime
µsec
Preheat Characteristics
Symbol Definition
Min. Typ.
Max. Units Test Conditions
I
CPH lead charging current
0.72
3.7
0.85
4.0
0.98
4.3
µA
V
= 5.3V
CPH
CPH
V
CPH lead lgnition mode threshold voltage
CPH lead run mode threshold voltage
CPHIGN
V
4.7
5.45
10.5
300
V
CPHRUN
5.15
9.5
0
V
I
= 1mA
CPH lead clamp voltage
9.0
—
CPHCLMP
CPH
V
Fault-mode CPH lead voltage
mV
SD = 5V, CS = 2V,
or Tj > TSD
CPHFLT
RPH Characteristics
Symbol Definition
Min. Typ.
Max. Units Test Conditions
I
Open circuit RPH lead leakage current
Fault-mode RPH lead voltage
—
0.01
0.1
50
µA
mV
V
RPH
= 5V,V
= 6V
RPHLK
RPH
V
—
0
SD = 5V, CS = 2V,
or Tj > TSD
RPHFLT
4
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IR21571
Electrical Characteristics (cont.)
V
= V
= V
= 14V +/- 0.25V, R = 40.0kΩ, C = 470 pF, RPH and RUN leads no connection, V
= 0.0V,
CPH
CC
BS
BIAS
T
T
o
R
= 6.1kΩ, R
= 20.0kΩ, V
= 0.5V, V
= 0.0V, C = 1000pF, T = 25 C unless otherwise specified.
SD L
A
DT
OC
CS
RUN Characteristics
Symbol Definition
Min. Typ.
Max.
Units Test Conditions
I
Open circuit RUN lead leakage current
Fault-mode RUN lead voltage
—
0.01
0.1
50
µA
mV
V
= 5V
RUN
RUNLK
V
—
0
SD = 5V, CS = 2V,
or Tj > TSD
RUNFLT
Protection Circuitry Characteristics
Symbol Definition
Min. Typ.
Max.
Units Test Conditions
V
Rising shutdown lead threshold voltage
Shutdown pin threshold hysteresis
Over-current sense threshold voltage
Under-current sense threshold voltage
Over-current sense propogation delay
1.9
100
2.1
150
1.10
0.2
2.3
200
1.21
0.26
400
5.6
V
SD+
V
mV
SDHYS
V
CS+
0.99
0.15
V
V
T
V
CS-
100
250
5.20
3.3
nsec
Delay from CS to LO
CS
Low V
/rectified line input upper threshold 5.0
BUS
DC+
V
V
DC-
Low V
/rectified line input lower threshold
BUS
2.85
150
3.3
160
170
oC
Note 4
T
SD
Thermal shutdown junction temperature
Gate Driver Output Characteristics
Symbol Definition
Min. Typ.
Max.
Units Test Conditions
VOL
Low-level output voltage
High level output voltage
Turn-on rise time
—
—
55
35
0
100
100
150
100
I
= 0
o
mV
V
OH
0
V
- V I = 0
O, o
BIAS
t
r
85
45
nsec
t
f
Turn-off fall time
Note 4: When the IC senses an overtemperature condition (Tj > 160ºC), the IC is latched off. In order to reset this
Fault Latch, the SD lead must be cycled high and then low, or the V supply to the IC must be cycled below
CC
the falling undervoltage lockout threshold (V
).
CCUV-
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5
IR21571
(S)&(PbF)
Functional Block Diagram
3.0V
14
16
15
VB
HO
VS
1
VDC
CPH
S
R
Q
Q
PULSE
FILTER &
LATCH
LEVEL
SHIFT
5.1V
1.0uA
2
10V
5.1V
4.0V
S
R1
R2
Q
Q
T
Q
Q
4.0V
2.0V
13
11
VCC
LO
R
3
4
5
RPH
RT
R
T
I
15.6V
2.0V
12
COM
RUN
0.2V
Q
D
CLK
R
C
T
R
I
= I
T
10
7.6V
9
CS
6
7
CT
DT
Q
Q
S
R
Q
OVER-
TEMP
50uA
UNDER-
VOLTAGE
DETECT
DETECT
8
OC
SD
7.6V
7.6V
2.0V
Lead Assignments & Definitions
Pin # Symbol
Description
1
2
VDC
CPH
RPH
RT
DC Bus Sensing Input
Preheat Timing Capacitor
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDC
CPH
RPH
RT
HO
VS
3
4
Preheat Frequency Resistor & Ignition Capacitor
Oscillator Timing Resistor
RUN
CT
5
Run Frequency Resistor
VB
6
Oscillator Timing Capacitor
7
DT
Deadtime Programming
Over-current (CS+) Threshold Programming
Shutdown Input
Current Sensing Input
Low-Side Gate Driver Output
IC Power & Signal Ground
Logic & Low-Side Gate Driver Supply
High-Side Gate Driver Floating Supply
High Voltage Floating Return
High-Side Gate Driver Output
VCC
COM
LO
8
OC
9
SD
RUN
CT
10
11
12
13
14
15
16
CS
LO
COM
VCC
VB
DT
CS
OC
SD
VS
HO
6
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IR21571
IR21571 State Diagram
Power Turned On
UVLO Mode
1/2-Bridge Off
IQCC 150µA
CPH = 0V
Oscillator Off
VCC < 9.5V
VCC > 11.4V(UV+)
SD > 2.0V
(VCC Fault or Power Down)
and
(Lamp Removal)
or
or
VDC > 5.1V(Bus OK)
VDC < 3.0V
and
VCC < 9.5V
(Power Turned Off)
(dc Bus/ac Line Fault or Power Down)
SD < 1.7V(Lamp OK)
and
or
SD > 2.0V
TJ < 160C(T
)
jmax
(Lamp Fault or Lamp Removal)
FAULT Mode
Fault Latch Set
1/2-Bridge Off
IQCC 150µA
TJ > 160C
PREHEAT Mode
(Over-Temperature)
1/2-Bridge @PfH
CPHCharging @ I = 1µA
PH
RPH = 0V
RUN = Open Circuit
CS Disabled
CPH = 0V
VCC = 15.6V
Oscillator Off
CPH > 4.0V
(End of PREHEAT Mode)
CS > CS+ Threshold
(Failure to Strike Lamp
or Hard Switching)
or
IGNITION RAMP Mode
TJ > 160C
fPH ramps toMfIN
(Over-Temperature)
CPHCharging @ I = 1µA
RPH = OpenPCHircuit
RUN = Open Circuit
CS+ Threshold Enabled
CS > CS+ Threshold
CPH > 5.1V
(Over-Current or Hard Switching)
(End of IGNITION RAMP)
or
CS < 0.2V
(No-Load or Below Resonance)
or
RUN Mode
fMIN Ramps toRfUN
TJ > 160C
(Over-Temperature)
CPHCharges to 7.6V Clamp
RPH = Open Circuit
RUN = 0V
CS- Threshold Enabled
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IR21571
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Description of Operation & Component Selection Tips
Supply Bypassing and PC Board
Layout Rules
Connecting the IC Ground (COM)
to the Power Ground
Component selection and placement on the pc
board is extremely important when using power
control ICs. VCC should be bypassed to COM as close
to the IC terminals as possible with a low ESR/ESL
capacitor, as shown in Figure 1 below.
Both the low power control circuitry and low side
gate driver output stage grounds return to this lead
within the IC. The COM lead should be connected to
the bottom terminal of the current sense resistor in
the source of the low side power MOSFET using an
individual pc board trace, as shown in Figure 2. In
addition, the ground return path of the timing
components and VCC decoupling capacitor should
be connected directly to the IC COM lead, and not
via separate traces or jumpers to other ground traces
on the board.
CVCC (surface mount)
IR21571
C
BOOT (surface mount)
pin 1
DBoot (surface mount)
CVCC (through hole)
IR21571 pin 1
CVCC (surface mount)
CVCC (through hole)
Figure 1: Supply bypassing PCB layout example
timing
components
A rule of thumb for the value of this bypass capacitor
is to keep its minimum value at least 2500 times the
value of the total input capacitance (Ciss) of the
power transistors being driven. This decoupling
capacitor can be split between a higher valued
electrolytic type and a lower valued ceramic type
connected in parallel, although a good quality
electrolytic (e.g., 10µF) placed immediately adjacent
to the VCC and COM terminals will work well.
RCS (through hole)
VBUS return
Figure 2: COM lead connection PCB layout example
This connection technique prevents high current
ground loops from interfering with the sensitive timing
component operation, and allows the entire control
circuit to reject common-mode noise due to output
switching.
In a typical application circuit, the supply voltage to
the IC is normally derived by means of a high value
startup resistor (1/4W) from the rectified line voltage,
in combination with a charge pump from the output
of the half-bridge. With this type of supply
arrangement, the internal 15.6V zener clamp diode
from VCC to COM will determine the steady state IC
supply voltage.
8
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IR21571
The heart of this controller is an oscillator which
resembles those found in many popular PWM voltage
regulator ICs. In its simplest form, this oscillator
consists of a timing resistor and capacitor connected
to ground. The voltage across the timing capacitor
CT is a sawtooth, where the rising portion of the ramp
is determined by the current in the RT lead, and the
falling portion of the ramp is determined by an external
deadtime resistor RDT. The oscillograph in Figure 4
illustrates the relationship between the oscillator
capacitor waveform and the gate driver outputs.
The Control Sequence & Timing
Component Selection
The IR21571 uses the following control sequence
(Figure 3) to drive rapid start fluorescent lamps.
fStart
fPH
fRun
fmin
t
5V
VCPH
2V
VRPH
2V
VRUN
Ignition
Ramp
mode
Preheat mode
Run mode
Figure 3: IR21571 control sequence
Figure 4
The control sequence used in the IR21571 allows
the Run Mode operating frequency of the ballast to
be higher than the ignition frequency (i.e., fstart >
fph > frun > fign). This control sequence is
recommended for lamp types where the ignition
frequency is too close to the run frequency to ensure
proper lamp striking for all production resonant LC
component tolerances (please note that it is possible
to use the IR21571 in systems where fstart > fph >
fign > frun, simply by leaving the RUN lead open).
The deadtime can be programmed by means of the
external RDT resistor, given a certain range of CT
capacitor values, using the graph shown in Figure 5.
The RT input is a voltage-controlled current source,
where the voltage is regulated to be approximately
2.0V. In order to maintain proper linearity between
the RT lead current and the CT capacitor charging
current, the value of the RT lead current should be
kept between 50µA and 500µA. The RT lead can
also be used as a feedback point for closed loop
control.
Six leads in the IC are used to control the Startup,
Preheat, Ignition Ramp, and Run modes of
operation, and to allow ballast and lamp engineers
the flexibility to optimize their designs for virtually
any lamp type.
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IR21571
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During the Startup Mode, the operating frequency is
determined by the parallel combination of RPH
START, and RT, combined with the values of CSTART
10
,
R
,
CT and RDT , as shown in Figure 6. This frequency is
normally chosen to ensure that the instantaneous
voltage across the lamp during the first few cycles of
operation does not exceed the strike potential of the
lamp. As the voltage across CSTART charges up to the
RT lead voltage, the output frequency exponentially
decays to the preheat frequency.
tDEAD
(usec)
CT = 220 pF
CT = 470 pF
CT = 1 nF
1
During the Preheat Mode, the operating frequency
is determined by the parallel combination of RPH and
RT, combined with the value of CT and RDT. This
frequency, along with the Preheat Time, is normally
chosen to ensure that adequate heating of the lamp
filaments occur. Typically, a 4.5:1 ratio of the hot
filament-to-cold filament resistance is desired for
maximum lamp life, as shown in Figure 7.
0.1
1
10
100
RDT (Kohms)
Figure 5: Deadtime versus R
DT
1.0uA
CPH
2
7.6V
CPH
5.1V
4.0V
S
R1
R2
Q
Q
4.0V
2.0V
RPH
3
CIGN
RT
RPH
RT
IRT
4
5
2.0V
RRUN
RUN
CSTART RSTART
ICT = IRT
CT
DT
6
7
CT
RDT
UNDER-
VOLTAGE
DETECT
Figure 6: Oscillator section block diagram with external component connection
10
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IR21571
The following graphs, Figures 8 and 9, illustrate the
relationship between the effective RT resistance (i.e.,
the parallel combination of resistors which programs
the CT capacitor charging current) and the operating
frequency.
Ignition
Ramp
Preheat
Run
150
FREQ
(KHz)
CT=220pF,RDT=11K
CT=470pF,RDT=6.2K
CT=1nF,RDT=3K
100
50
0
Figure 7: Lamp filament voltage during the
preheat, ignition ramp and run modes.
The Preheat Time is programmed by means of the
preheat capacitor, CPH, an internal 1µA current
source, and an internal threshold on the CPH lead of
4.0V, according to the following formula:
0
5
10
15
20
25
30
35
40
RT (K ohms)
Figure 8: fosc versus effective RT (tDEAD = 2.0 usec)
tPH = 4.7E6 CPH, or
CPH = 213E-9 tPH
250
200
At the end of the Preheat Time, the internal, open-
drain transistor holding the RPH lead to ground turns
off, and the voltage on this lead charges exponentially
up to the RT lead potential. During this Ignition Ramp
Mode, the output frequency exponentially decays to
a minimum value. The rate of decay of this frequency
is a function of the RPH * CPH time constant. Because
the Ignition Ramp Mode ends when the voltage on
the CPH lead reaches 5.15V, the Ignition Ramp Mode
is always 1/4th as long as the preheat time.
CT=220pF, RDT=5.6K
CT=470pF, RDT=2.7K
CT=1nF, RDT=1.2K
150
FREQ
(KHz)
100
50
0
When the CPH lead reaches 5.15V, an open-drain
transistor on the RUN lead turns on, and the external
RRUN resistor is then in parallel with the RT resistor.
The Run Mode operating frequency is therefore a
function of the parallel combination of RRUN and RT,
and this means that the operating power of the lamp
0
5
10
15
20
25
30
35
40
RT (K ohms)
can be programmed by means of RRUN
.
Figure 9: fosc versus effective RT (tDEAD = 1.0 usec)
www.irf.com
11
IR21571
(S)&(PbF)
Lamp Protection & Automatic Restart Circuitry Operation
Three leads on the IR21571 are used for protection, as shown in Figure 10 below. These are VDC (dc bus
monitor), SD (unlatched shutdown), CS (latched shutdown) and OC (CS+ threshold programming).
+VBUS
3.0V
VDC
R2
R1
1
2
S
R
Q
Q
5.1V
C1
from oscillator
section
1.0uA
T
Q
Q
CPH
R
Q2
7.6V
5.1V
4.0V
R3
0.2V
Q
Q
D
CLK
R
CS
SD
RCS
10
DT
Q
Q
S
R
7
8
VCC
7.6V
OVER-
TEMP
50uA
R5
OC
UNDER-
VOLTAGE
DETECT
R4
DETECT
9
7.6V
2.0V
ROC
7.6V
C2
from lower
lamp cathode
Figure 10: Lamp protection & automatic restart circuitry block diagram with external component connection.
Sensing the DC Bus Voltage
pump off of the output of the half-bridge). In this
The first of these protection leads senses the voltage
case, the voltage on the VDC lead will shut the oscillator
on the DC bus by means of an external resistor
off, thereby protecting the power transistors from
divider and an internal comparator with hysteresis.
potentially hazardous hard switching. Approximately
When power is first supplied to the IC at system
2V of hysteresis has been designed into the internal
startup, 3 conditions are required before oscillation
comparator sensing the VDC lead, in order to account
is initiated: 1.) the voltage on the VCC lead must exceed
for variations in the dc bus voltage under varying
the rising undervoltage lockout threshold (11.5V),
load conditions. When the dc bus recovers, the chip
2.) the voltage at the VDC lead must exceed 5.1V, and
restarts from the beginning of the control sequence,
3.) the voltage on the SD lead must be below
as shown in timing diagram Figure 11.
approximately 1.85V. If a low dc bus condition occurs
during normal operation, or if power to the ballast is
shut off, the dc bus will collapse prior to the VCC of the
chip (assuming the VCC is derived from a charge
12
www.irf.com
(S)&(PbF)
IR21571
+ rectified
+ VBUS
AC Line
5
3
VDC
CPH
RPH
RT
HO
1
2
3
4
5
6
7
8
16
15
14
VDC
RGHS
CBLOCK LRES
VS
VB
CBS
RSupply
CSNUBBER
DBOOT
13 VCC
12 COM
4
CVCC
D1
RUN
CT
CT
D2
CRES
LO
11
RGLS
R4
R3
DT
CS
10
R5
8
OC
SD
9
CPH
C2
RCS
15
VBUS return
Figure 12: Lamp presence detection circuit
LO
connection (shaded area)
15
HO-VS
2
SD
Restart
RUN mode
Low VDC
4
CT
Figure 11: VDC lead fault and auto restart
8
CPH
Lamp Presence Detection and
Automatic Restart
15
The second protection lead, SD, is used for both
unlatched shutdown and automatic restart functions.
The SD lead would normally be connected to an
external circuit which senses the presence of the
lamp (or lamps), as shown in Figure 12.
LO
15
HO-VS
When the SD lead exceeds 2.0V (approximately
150mV of hysteresis is included to increase noise
immunity), signaling either a lamp fault or lamp
removal, the oscillator is disabled, both gate driver
outputs are pulled low, and the chip is put into the
micropower mode. Since a lamp fault would normally
lead to a lamp exchange, when a new lamp is
inserted into the fixture, the SD lead would be pulled
back to near the ground potential. Under these
Restart
RUN mode
SD mode
Figure 13: SD lead fault and auto restart
conditions a reset signal would restart the chip from
the beginning of the control sequence, as shown in
the timing diagram in Figure 13.
www.irf.com
13
IR21571
(S)&(PbF)
enabled at the end of the preheat time. The level of
this positive-going threshold is determined by the
value of the resistor ROC. The value of the resistor
ROC is determined by the following formula:
Thus, for a lamp removal and replacement, the ballast
automatically restarts the lamp in the proper manner,
maximizing lamp life and minimizing stress on the
power MOSFETs or IGBTs. The SD lead contains an
internal 7.5V zener diode clamp, thereby reducing
the number of external components required.
V
CS+
R
OC
=
or
50E - 6
Half-Bridge Current Sensing and
Protection
V
CS+
=
50E -6 - R
OC
The third lead used for protection is the CS lead,
which is normally connected to a resistor in the source
of the lower power MOSFET, as shown in Figure 14.
For the under-current and under-resonance
conditions, there is a negative-going CS- threshold
of 0.2V which is enabled at the onset of the run mode.
The sensing of this CS- threshold is synchronized
with the falling edge of the LO output.
The CS lead is used to sense fault conditions such
as failure of a lamp to strike, over-current during
normal operation, hard switching, no load, and
operation below resonance. If any one of these
conditions is sensed, the fault latch is set, the oscillator
is disabled, the gate driver outputs go low, and the
chip is put into the micropower mode. The CS lead
performs its sensing functions on a cycle-by-cycle
basis in order to maximize ballast reliability.
Figures 15, 16 and 17 are oscillographs of fault
conditions. Figure 15 shows a failure of the lamp to
strike, Figure 16 shows a hard switching condition
and Figure 17 shows an under-current condition.
For the over-current, failure-to-strike, and hard
switching fault conditions, an externally
programmable, positive-going CS+ threshold is
rectifie
d
+VBUS
AC line
VDC
CPH
RPH
RT
HO
VS
VB
1
2
3
4
5
6
7
8
16
15
14
Q1
RGHS
CBOOT
DBOOT
Bridge
output
1
/
2
RSUPPLY
D1
CSNUBBER
13 VCC
12 COM
RUN
CT
CVCC
LO
11
Q2
D2
RGLS
DT
CS
10
R3
OC
SD
9
RCS
ROC
VBUS return
Figure 15: Lamp failure to strike
Figure 14: Half-bridge current sensing circuit
connection (shaded area)
14
www.irf.com
(S)&(PbF)
IR21571
Figure 16: Hard switching condition
Figure 18: Auto restart for lamp replacement
Recovery from such a fault condition is accomplished
by cycling either the SD lead or the VCC lead. When
a lamp is removed, the SD lead goes high, the fault
latch is reset, and the chip is held off in an unlatched
state. Lamp replacement causes the SD lead to go
low again, reinitiating the startup sequence. The fault
latch can also be reset by the undervoltage lockout
signal, if VCC falls below the lower undervoltage
threshold.
Bootstrap Supply Considerations
Power is normally supplied to the high-side circuitry
by means of a simple charge pump from VCC, as
shown in Figure 19.
Figure 17: Operation below resonance
www.irf.com
15
IR21571
(S)&(PbF)
power supply to the upper gate driver CMOS circuitry.
Since the quiescent current in this CMOS circuitry is
very low (typically 45µA in the on-state), the majority
of the drop in the VBS voltage when Q1 is on occurs
due to the transfer of charge from the bootstrap
capacitor to the gate of the power MOSFET.
rectifie
d
+VBUS
AC line
VDC
CPH
RPH
RT
HO
VS
VB
1
2
3
4
5
6
7
8
16
15
14
Q1
RGHS
CBOOT
DBOOT
Bridge
output
1
/
2
RSUPPLY
D1
CSNUBBER
VB should be bypassed to VS as close as possible to
the leads of the IC with a low ESR/ESL capacitor. A
PCB layout example is shown in figure 20. A rule of
thumb for the value of this capacitor is to keep its
minimum value at least 50 times the value of the total
input capacitance (Ciss) of the MOSFET or IGBT being
driven. In addition, the VS lead should be connected
directly to the high side power MOSFET source.
13 VCC
12 COM
RUN
CT
CVCC
LO
11
Q2
D2
RGLS
DT
CS
10
R3
OC
SD
9
RCS
VBUS return
CVCC (surface mount)
IR21571
pin 1
CBOOT (surface mount)
Figure 19: Typical bootstrap supply connection
with VCC charge pump from half-bridge output
(shaded area)
DBoot (surface mount)
A high voltage, fast recovery diode DBOOT (the so-
called bootstrap diode) is connected between VCC
(anode) and VB (cathode), and a capacitor CBOOT
(the so-called bootstrap capacitor) is connected
between the VB and VS leads. During half-bridge
switching, when MOSFET Q2 is on and Q1 is off, the
bootstrap capacitor CBOOT is charged from the VCC
decoupling capacitor, through the bootstrap diode
CVCC (through hole)
Figure 20: Supply bypassing PCB layout example
D
BOOT, and through Q2. Alternately, when Q2 is off
and Q1 is on, the bootstrap diode is reverse-biased,
and the bootstrap capacitor (which ‘floats’ on the
source of the upper power MOSFET) serves as the
16
www.irf.com
(S)&(PbF)
IR21571
Case outlines
01-6015
16-Lead PDIP
01-3065 00 (MS-001A)
01-6018
16-Lead SOIC (narrow body)
01-3064 00 (MS-012AC)
www.irf.com
17
IR21571
(S)&(PbF)
LEADFREE PART MARKING INFORMATION
Part number
Date code
IRxxxxxx
YWW?
IR logo
?XXXX
Pin 1
Identifier
Lot Code
?
(Prod mode - 4 digit SPN code)
MARKING CODE
P
Lead Free Released
Non-Lead Free
Released
Assembly site code
ORDER INFORMATION
Leadfree Part
Basic Part (Non-Lead Free)
16-Lead PDIP IR21571 order IR21571PbF
16-Lead PDIP IR21571 order IR21571
16-Lead SOIC IR21571S order IR21571S
16-Lead SOIC IR21571S order IR21571SPbF
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice.
5/5/2005
18
www.irf.com
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