IR2166 [INFINEON]
PFC & BALLAST CONTROL IC; PFC和镇流器控制IC
| 型号： | IR2166 |
| 厂家： | 
Infineon |
| 描述： | PFC & BALLAST CONTROL IC |
| 文件： | 总29页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD60198-C
IR2166(S)
PFC & BALLAST CONTROL IC
Features
PFC, Ballast control and half-bridge driver in one IC
Programmable dead time
Internal ignition ramp
Internal fault counter
DC bus under-voltage reset
Shutdown pin with hysteresis
Internal 15.6V zener clamp diode on Vcc
Micropower startup (150µA)
Latch immunity and ESD protection
•
•
Critical conduction mode boost type PFC
No PFC current sense resistor required
Programmable preheat frequency
Programmable preheat time
Programmable run frequency
Programmable over-current protection
•
•
•
•
•
•
•
•
•
•
•
•
Programmable end-of-life protection
•
•
Description
Packages
The IR2166 is a fully integrated, fully protected 600V ballast control IC designed to
drive all types of fluorescent lamps. PFC circuitry operates in critical conduction mode
and provides for high PF, low THD and DC Bus regulation. The IR2166 features in-
clude programmable preheat and run frequencies, programmable preheat time, pro-
grammable dead-time, programmable over-current protection, and programmable end-
of-life protection. Comprehensive protection features such as protection from failure of
a lamp to strike, filament failures, end-of-life protection, DC bus undervoltage reset as
well as an automatic restart function, have been included in the design. The IR2166 is
available in both 16-lead PDIP and 16-lead (narrow body) SOIC packages.
16-Lead SOIC
(narrow body)
16-Lead PDIP
IR2166 Application Diagram
D BUS
+ Rectified AC Line
R BUS
RSUPPLY
CVDC
RGHS
VBUS
CPH
HO
VS
VB
1
2
3
4
5
6
7
8
16
15
14
M1
RVDC
CPH
CBLOCK LRES
+
CBOOT
DBOOT
CVCC2
RGLS
RT
CBUS
RT
RPH
CSNUB
VCC
DCP1
13
12
R5
RPH
CT
CVCC1
COM
CT
R3
CRES
R6
CCOMP
COMP
LO
M2
11
10
9
DCP2
R7
R2
D1
R1
ZX
CS
DZCOMP
R4
PFC
SD/EOL
M3
RGPFC
RCS
CSD1
CCS CSD2
D2 D3
CEOL
R8
- Rectified AC Line
*Please note that this data sheet contains advanced information that could change before the product is released to production.
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1
IR2166
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
V
High side floating supply voltage
High side floating supply offset voltage
High side floating output voltage
Low side output voltage
-0.3
625
B
V
S
V
V
- 25
V
V
+ 0.3
+ 0.3
+ 0.3
+ 0.3
B
B
B
V
- 0.3
V
HO
S
V
-0.3
V
LO
CC
CC
V
PFC gate driver output voltage
-0.3
V
PFC
I
Maximum allowable output current (HO, LO, PFC)
due to external power transistor miller effect
-500
500
OMAX
mA
V
V
pin voltage
-0.3
-0.3
-5
V
V
+ 0.3
+ 0.3
BUS
BUS
CC
V
V
CT pin voltage
CT
CPH
RPH
CC
I
I
CPH pin current
5
mA
RPH pin current
-5
5
V
RPH pin voltage
-0.3
-5
V
CC
+ 0.3
V
RPH
I
RT pin current
5
mA
RT
V
RT pin voltage
-0.3
-0.3
-5
V
CC
+ 0.3
RT
V
V
CS
Current sense pin voltage
Current sense pin current
Shutdown pin current
5.5
5
I
CS
SD/EOL
I
-5
5
I
Supply current (Note 1)
PFC inductor current, zero crossing detection input current
PFC error compensation current
Allowable offset voltage slew rate
-20
-5
20
CC
mA
I
5
ZX
I
-5
5
COMP
dV/dt
-50
—
50
V/ns
W
P
Package power dissipation @ T ≤ +25°C
(16-Pin PDIP)
(16-Pin SOIC)
(16-Pin PDIP)
(16-Pin SOIC)
1.80
1.40
70
D
A
P
= (T
-T )/Rth
JA
—
D
JMAX
A
Rth
Thermal resistance, junction to ambient
—
JA
oC/W
oC
—
86
T
T
T
Junction temperature
-55
-55
—
150
150
300
J
Storage temperature
S
L
Lead temperature (soldering, 10 seconds)
Note 1:
This IC contains a zener clamp structure between the chip V
and COM which has a nominal breakdown
CC
voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source
greater than the V specified in the Electrical Characteristics section.
CLAMP
2
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IR2166
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol
Definition
Min.
Max.
Units
V
High side floating supply voltage
Steady state high side floating supply offset voltage
Supply voltage
V
- 0.7
V
BS
CC
CLAMP
600
V
V
-1
S
V
V
V
CC
CC
CCUV+
CLAMP
10
I
Supply current
Note 2
mA
pF
C
CT lead capacitance
—
1
T
220
-1
I
End-of-life lead current
SD/EOL
I
Current sense lead current
Zero crossing detection pin current
Junction temperature
-1
-1
1
mA
oC
CS
I
1
ZX
T
-25
125
J
Note 2: Enough current should be supplied into the VCC lead to keep the internal 15.6V zener clamp diode on this lead
regulating its voltage, V
.
CLAMP
Electrical Characteristics
V
V
= V = V
= 14V +/- 0.25V, V
= Open, R = 39.0kΩ, R = 100kΩ C = 470 pF, V
= 0.0V, V = 0.0V,
CPH SD
CC
BS
BIAS
BUS
T
PH
,
T
= 0.0V, V = 0.0V, C
C
= 1000pF, T = 25oC unless otherwise specified.
LO = HO
A
COMP
CS
Symbol Definition
Min.
Typ.
Max.
Units Test Conditions
Supply Characteristics
V
V
supply undervoltage positive going
10.0
8.5
11.5
9.5
12.5
10.7
V
rising from 0V
CCUV+
CC
CC
threshold
V
V
supply undervoltage negative going
V
falling from 14V
CC
CCUV-
CC
V
threshold
V
V
supply undervoltage lockout hysteresis
1.5
120
—
2.0
170
2.3
3.0
280
4.0
UVHYS
CC
I
UVLO mode quiescent current
Quiescent V supply current
µA
V
CC
= 8V
QCCUV
I
mA
CT connected toCOM
VCC =14V
QCC
CC
V
V
zener clamp voltage
14.3
15.6
16.5
V
I
= 10mA
CC
CLAMP
CC
Floating Supply Characteristics
I
V
HO
V
HO
V
= (CT = 0V)
S
Quiescent VBS supply current
-1
5
0
30
2.5
5
60
QBS0
µA
I
Quiescent V supply current
= V (C = 14V)
QBS1
BS
B T
—
—
V
Minimum required VBS voltage for proper
HO functionality
V
BSMIN
µA
I
LK
Offset supply leakage current
—
—
50
V = V = 600V
B S
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3
IR2166
Electrical Characteristics cont.
V
CC
V
= V = V
= 14V +/- 0.25V, V
= Open, R = 39.0kΩ, R = 100kΩ C = 470 pF, V
= 0.0V, V = 0.0V,
CPH SD
BS
BIAS
BUS
T
PH
,
T
= 0.0V, V = 0.0V, C
C
= 1000pF, T = 25oC unless otherwise specified.
LO = HO
A
COMP
CS
Symbol Definition
Min. Typ.
Max. Units Test Conditions
PFC Error Amplifier Characteristics
I
V
V
V
V
V
= 14V
= 3.5V
= 14V
= 4.5V
= 3.0V
55
COMP
Error amplifier output current sourcing
5
35
-30
CPH
BUS
CPH
BUS
BUS
SOURCE
µA
I
-18
14.5
4
COMP
Error amplifier output current sinking
-50
10.5
—
SINK
V
COMPOH Error amplifier output voltage swing
(high state)
13.5
0.25
V
V
V
= 5.0V
COMPOL Error amplifier output voltage swing
(low state)
BUS
PFC DC Bus Regulation
V
Overvoltage comparator threshold
3.8
75
4.3
100
4.7
300
V
mV
V
V
= 4.0V
= 4V
BUSOV
COMP
V
Overvoltage comparator
hysterisis
BUSOV
COMP
HYS
V
VBUS internal reference voltage
3.7
4.0
4.2
V
V
= 4V
VBUS
COMP
REG
PFC Zero Current Detector
V
V
V
1.1
75
2
800
9.1
V
V
I
= 4V
= 4V
ZX pin comparator threshold voltage
1.65
300
7.5
V
mV
V
ZX
COMP
ZX pin comparator hysterisis
ZXhys
ZXclamp
COMP
= 5mA
ZX pin clamp voltage (high state)
6.3
ZX
PFC Watch-dog
t
Watch-dog pulse interval
90
400
810
µS
= 0V, V
=2V
WD
ZX
COMP>
Ballast Control Oscillator Characteristics
f
Oscillator frequency
38.5
71
42
47.5
81
Run mode
osc
kHz
%
75
50
Preheat mode
—
—
d
Oscillator duty cycle
C
C
6.8
1.8
—
10.7
5.6
—
V
Upper
Lower
ramp voltage threshold
ramp voltage threshold
8.4
4.6
0
1.0
1.0
CT+
T
V
= 14V
CC
V
CT-
V
T
C
>
or CS >
1.3V
V
Fault-mode
LO output deadtime
HO output deadtime
lead voltage
T
SD 5.0V
CTFLT
DLO
0.7
0.7
1.5
1.5
t
t
usec CT = 470pF
DHO
Ballast Control Preheat Characteristics
CPH
V
=5V,CT=0V, V =0V
I
CPH pin charging current
2.6
—
3.2
0
4.3
—
µA
mV
CPH BUS
> or CS >
SD 5.0V 1.3V
V
Fault-mode pin voltage
CPHFLT
CPH
RPH Characteristics
µA
I
Open circuit RPH pin leakage current
—
—
0.1
0
—
—
RPHLK
> or CS >
SD 5.0V 1.3V
V
Fault-mode pin voltage
mV
RPHFLT
RPH
4
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IR2166
Electrical Characteristics cont.
V
CC
V
= V = V
= 14V +/- 0.25V, V
= Open, R = 39.0kΩ, R = 100kΩ C = 470 pF, V
= 0.0V, V = 0.0V,
CPH SD
BS
BIAS
BUS
T
PH
,
T
= 0.0V V = 0.0V, C
C
= 1000pF, T = 25oC unless otherwise specified.
LO = HO
A
COMP
CS
Symbol Definition
RT Characteristics
Min. Typ.
Max. Units Test Conditions
µA
I
Open circuit RT pin leakage current
—
—
0.1
0
—
—
CT = 10V
RTLK
> or CS >
SD 5.0V 1.3V
V
Fault-mode pin voltage
mV
RTFLT
RT
Protection Circuitry Characteristics
V
V
V
V
V
Rising shutdown pin reset threshold voltage
Shutdown pin 5.0V threshold hysteresis
Rising shutdown pin end-of-life threshold volt.
4.7
100
2.4
5.2
150
3.0
1.0
1.2
75
5.7
350
3.6
1.6
1.3
90
V
SDTH+
SDHYS
SDEOL+
mV
V
>12V
CPH
-
Falling shutdown pin end-of-life threshold volt. 0.7
V
SDEOL
Over-current sense threshold voltage
1.0
25
V
>7.5V
CPH
CSTH+
-
Cycles
V
>7.5V, CYCLES
CPH
Number of sequential over-current fault
cycles before IC shuts down
#FAULT
CS > 1.3V
V
V
BUSUV- The VBUS threshold below which the IC
shuts down
2.6
3.0
12
3.3
V
CPH
CPH pin end-of-life enable threshold
10.3
13.2
Gate Driver Output Characteristics (HO, LO and PFC pins)
VOL
VOH
Low-level output voltage
High-level output voltage
—
—
0
0
100
100
Io = 0
mV
V
- Vo, Io = 0
BIAS
tr
Turn-on rise time
Turn-off fall time
—
—
110
55
300
400
210
160
—
C
= 1nF
= C = C
LO PFC
HO
nsec
mA
tf
—
—
I0+
I0-
HO, LO, PFC source current
HO, LO, PFC sink current
—
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5
IR2166
Block Diagram
13
Vcc
S1
R
14
16
15
3
VB
HO
VS
RT
CT
Soft
Start
S2
40K
Driver
Logic
High-
Side
Driver
R
Comp
1
5
T
Q
Q
VTH
R
RDT
3.0K
R
S3
Fault
Logic
S4
S6
R
R
Fault
Counter
4
RPH
Low-
Side
Driver
Schmitt
1
3uA
11
LO
2
CPH
12
COM
S
Q
Q
R1
R2
Comp
3
10
9
CS
1.3V
3V
1V
Under-
Voltage
Detect
2.0V
1.0M
CPH>12V
SD/EOL
PFC
CPH>12V
7.6V
1
6
VBUS
Over-Voltage
Protection
Gain
5.2V
OTA1
4.0V
VCC
4.3V
8
COMP
S
R
Q
Q
VCC
Under-Voltage
Reset
Watch
Dog
Timer
S
R
Q
Q
3.0V
S
Q
R1
R2
Q
7
ZX
1.0V
7.6V
6
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IR2166
State Diagram
Power Turned On
UVLO Mode
1/2-Bridge Off
IQCC 400µA
CPH = 0V
CT = 0V (Oscillator Off)
VCC < 9.5V
(VCC Fault or Power Down)
or
SD/EOL > 5.0V
VCC > 11.5V (UV+)
and
SD/EOL < 5.0V
SD/EOL > 5.0V
(Lamp Removal)
or
(Lamp Fault or Lamp Removal)
VCC < 9.5V (UV-)
(Power Turned Off)
PREHEAT Mode
FAULT Mode
1/2-Bridge oscillating @ fPH
RPH // RT
Fault Latch Set
1/2-Bridge Off
IQCC 180µA
CPH = 0V
VCC = 15.6V
CPH Charging @ ICPH = 5 µA
PFC Enabled (High Gain)
CS Enabled
CS > 1.3V for 25
cycles
Fault Counter Enabled
CT = 0V (Oscillator Off)
CPH > 10V
(End of PREHEAT Mode)
Ignition Ramp
Mode
CS > 1.3V for 25 cycles
(Failure to Strike Lamp)
RPH!Open
fPH ramps to fRUN
CPH charging
CPH > 12V
CS > 1.3V
(Lamp Fault)
or
RUN Mode
SD/EOL<1.0V or SD/EOL>3.0V
(End-of-Life)
RPH = Open
Discharge
VCC
VBUS<3.0V
1/2-Bridge Oscillating @fRUN
EOL Thresholds Enabled
PFC = Low Gain Mode
VBUS UV Threshold Enabled
Fault Counter Disabled
to UVLO-
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7
IR2166
Lead Assignments & Definitions
VBUS
HO
Pin # Symbol
Description
1
2
3
4
5
6
7
8
16
VBUS
CPH
RT
DC Bus Sensing Input
1
2
CPH
VS
Preheat Timing Capacitor
15
14
13
12
3
Minimum Frequency Timing Resistor
Preheat Frequency Timing Resistor
Oscillator Timing Capacitor
VB
RT
4
RPH
CT
5
RPH
VCC
COM
6
PFC Error Amplifier Compensation
COMP
ZX
7
PFC Zero-Crossing Detection
PFC Gate Driver Output
CT
COMP
ZX
8
PFC
SD/EOL
CS
9
Shut-Down/End of Life Sensing Circuit
Current Sensing Input
10
11
12
13
14
15
16
LO
11
10
9
LO
Low-Side Gate Driver Output
IC Power & Signal Ground
COM
VCC
VB
CS
Logic & Low-Side Gate Driver Supply
High-Side Gate Driver Floating Supply
High Voltage Floating Return
High-Side Gate Driver Output
PFC
SD/EOL
VS
HO
8
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IR2166
BALLAST TIMING DIAGRAMS
NORMAL OPERATION
VCC
15.6V
UVLO+
UVLO-
VCC
7.5V
CPH
frun
fph
FREQ
HO
LO
CS
Over-Current Threshold
1.3V
UVLO
PH
RUN
UVLO
RT
RT
RT
RPH
CT
RPH
CT
RPH
CT
HO
LO
HO
LO
HO
LO
CS
CS
CS
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9
IR2166
BALLAST TIMING
DIAGRAMS
FAULT CONDITION
VCC
15.6V
UVLO+
UVLO-
VCC
7.5V
CPH
frun
p
h
f
FREQ
SD
HO
LO
CS
1.3V
UVLO
PH
RUN
UVLO
PH
RT
RT
RT
RPH
CT
RPH
CT
RPH
CT
HO
LO
HO
LO
HO
LO
CS
CS
CS
10
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IR2166
14
12
10
8
1600
1400
1200
1000
800
600
400
200
0
UVLO+
UVLO-
6
4
2
0
-25
0
25
50
75
100
125
0
0.5
1
1.5
2
2.5
3
DeadTime( S)
Temperature (°C)
µ
Graph 1. VCCUV+, VCCUV- vs TEMP
Graph 2. CT vs Dead Time
1000000
100000
10000
1000
9
8
7
6
5
4
3
2
1
0
CT+
CT-
-25
0
25
50
75
100
125
5
25
45
65
85
RT(K
)
Ω
Temperature (°C)
Graph 3: CT+, CT- vs TEMP
Graph 4: Frequency vs RT
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11
IR2166
8
7
6
5
4
3
2
1
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
0
0
3
6
9
12
15
40
80
120
160
200
VCPH (V)
FREQUENCY (KHz)
Graph 6: ICPH vs VCPH
Graph 5: ICC vs Frequency
50
40
30
20
10
2.5
2
ZX+
1.5
1
ZX-
0.5
0
0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Graph 7. ILK vs TEMP
Graph 8: ZX+, ZX- vs TEMP
12
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IR2166
325
315
305
295
285
275
9
8.5
8
7.5
7
6.5
6
-25
0
25
50
75
100
125
-25
0
25
50
75
100 125
Temperature (°C)
Temperature (°C)
Graph 9: IZX (ZX Input Bias) vs TEMP
Graph 10: VZX (ZX Clamp Voltage) vs TEMP
5
5
4.5
4
4.5
VBUS+
4
VBUS-
3.5
3
3.5
3
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Graph 12: VBUS+, VBUS- vs TEMP
Graph 11: VBUS Sense Thresh vs TEMP
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13
IR2166
63
61
59
57
55
53
150
125
100
75
Trise
Tfall
50
25
0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Graph 14: Frequency vs TEMP
Graph 13: PFC Trise, Tfall vs TEMP
2.5
200
175
150
125
100
75
2.3
2.1
1.9
1.7
1.5
t
DEAD HO
t
RISE
t
DEAD LO
50
t
FALL
25
0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Graph 15: tDEAD HO, tDEAD LO vs TEMP
Graph 16: tRISE, tFALL vs TEMP
14
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IR2166
5
4
3
2
1
0
50
40
30
20
10
0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Graph 17: CS Pulses vs TEMP
Graph 18: CS Threshold vs TEMP
3.5
3
6
EOL+
5.5
5
2.5
2
SD+
SD-
1.5
1
EOL-
4.5
4
0.5
0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Graph 19: EOL+,EOL- vs TEMP
Graph 20: SD+, SD- vs TEMP
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15
IR2166
3
2.5
2
15
14
13
12
11
10
1.5
1
0.5
0
-25
0
25
50
75
100
125
8
9
10
11
12
13
Temperature (°C)
VCC (V)
Graph 22: IQCC vs VCC UVLO Hysteresis
Graph 21: VCPH (EOL/RUN) Threshold vs TEMP
16
14
12
10
8
90
80
70
60
50
40
30
20
10
0
6
4
2
-10
0
0
3
6
9
12
15
0
5
10
PFC ON TIME ( S)
15
20
VBS (V)
µ
Graph 23: VCOMP vs PFC ON TIME
Graph 24: I
(1) vs V
vs Temp
CC
QBS
16
www.irf.com
IR2166
20
16
12
8
20
16
12
8
-25
25
-25
25
75
125
75
125
4
4
0
0
0
5
10
15
20
15
15.5
16
16.5
VCC (V)
V
CC (V)
Graph 25. IQCC vs VCC vs Temp
Graph 26. IQCC vs VCC vs Temp
Internal Zener Diode Curve
2.5
2
0.3
0.25
0.2
-25
25
-25
25
75
75
125
1.5
1
125
0.15
0.1
0.5
0
0.05
0
10
10.5
11
11.5
12
12.5
13
0
3
6
9
12
15
VC C (V)
V
CC (V)
Graph 27. IQCC vs VCC vs Temp
Micropower Startup Mode
Graph 28: I
vs V
vs Temp V
+
QCC
CC
CCUV
www.irf.com
17
IR2166
3
2.5
2
-25
25
75
125
1.5
1
0.5
0
8.5
9
9.5
10
10.5
VCC (V)
Graph 29: I
vs V
vs Temp V
-
QCC
CC
CCUV
18
www.irf.com
IR2166
I. Ballast Section
VC1
Functional Description
CVCC
DISCHARGE
INTERNAL VCC
ZENER CLAMP VOLTAGE
Under-voltage Lock-Out Mode (UVLO)
VUVLO+
VHYST
The under-voltage lock-out mode (UVLO) is
defined as the state the IC is in when VCC is
below the turn-on threshold of the IC. To identify
the different modes of the IC, refer to the State
Diagram shown on page 7 of this document. The
IR2166 undervoltage lock-out is designed to
maintain an ultra low supply current of less than
400uA, and to guarantee the IC is fully functional
before the high and low side output drivers are
activated. Figure 1 shows an efficient supply
voltage using the start-up current of the IR2166
together with a charge pump from the ballast
output stage (RSUPPLY, CVCC, DCP1 and DCP2).
VUVLO-
DISCHARGE
TIME
CHARGE PUMP
OUTPUT
RSUPPLY & CVCC
TIME
CONSTANT
t
Figure 2, Supply capacitor (C
) voltage.
VCC
During the discharge cycle, the rectified current
from the charge pump charges the capacitor above
the IC turnoff threshold. The charge pump and
the internal 15.6V zener clamp of the IC take over
as the supply voltage. The start-up capacitor and
snubber capacitor must be selected such that
enough supply current is available over all ballast
operating conditions. A bootstrap diode (DBOOT)
and supply capacitor (CBOOT) comprise the
supply voltage for the high side driver circuitry.
To guarantee that the high-side supply is charged
up before the first pulse on pin HO, the first pulse
from the output drivers comes from the LO pin.
During under-voltage lockout mode, the high-
and low-side driver outputs HO and LO are both
low, pin CT is connected internally to COM to
disable the oscillator, and pin CPH is connected
internally to COM for resetting the preheat time.
VBUS(+)
R SUPPLY
D BOOT
HO
M1
16
Half-Bridge
Output
VS
15
14
13
12
VB
C BOOT
CVCC
VCC
CSNUB
IR2166
COM
LO
11
M2
D CP1
RCS
D CP2
VBUS(-)
Figure 1, Start-up and supply circuitry.
The start-up capacitor (CVCC) is charged by
current through supply resistor (RSUPPLY)
minus the start-up current drawn by the IC. This
resistor is chosen to set the line input voltage
turn-on threshold for the ballast . Once the
capacitor voltage on VCC reaches the start-up
threshold, and the SD pin is below 5.0 volts, the
IC turns on and HO and LO begin to oscillate.
The capacitor begins to discharge due to the
increase in IC operating current (Figure 2).
Preheat Mode (PH)
The preheat mode is defined as the state the IC
is in when the lamp filaments are being heated to
their correct emission temperature. This is
necessary for maximizing lamp life and reducing
the required ignition voltage. The IR2166 enters
preheat mode when VCC exceeds the UVLO
positive-going threshold. HO and LO begin to
www.irf.com
19
IR2166
oscillate at the preheat frequency with 50% duty
cycle and with a dead-time which is set by the
value of the external timing capacitor, CT, and
internal deadtime resistor, RDT. Pin CPH is
disconnected from COM and an internal 3µA
current source (Figure 3)
VCC is the dead-time (both off) of the output
gate drivers, HO and LO. The selected value of
CT together with RDT therefore program the
desired dead-time (see Design Equations, page
26, Equations 1 and 2). Once CT discharges
below 1/3 VCC, MOSFET S3 is turned off,
disconnecting RDT from COM, and MOSFET
S1 is turned on, connecting RT and RPH again
to VCC. The frequency remains at the preheat
frequency until the voltage on pin CPH exceeds
10V and the IC enters Ignition Mode. During the
preheat mode, the over-current protection
together with the fault counter are enabled. The
peak ignition current must not exceed the
maximum allowable current ratings of the output
stage MOSFETs. Should this voltage exceed the
internal threshold of 1.3V, the internal FAULT
Counter begins counting the sequential over-
current faults (See Timing Diagram). If the
number of over-current faults exceed 25, the IC
will enter FAULT mode and gate driver outputs
HO, LO and PFC will be latched low.
VBUS (+)
HO
RT
M1
16
3
OSC.
RT
Half-
Bridge
Output
S4
Half-
Bridge
Driver
RPH
CT
4
5
VS
LO
R PH
15
11
ILOAD
CT
M2
3uA
CPH
RCS
2
CCPH
COM
12
IR2166
Load
Return
VBUS (-)
Figure 3, Preheat circuitry.
charges the external preheat timing capacitor
on CPH linearly. The over-current protection on
pin CS is disabled during preheat. The preheat
frequency is determined by the parallel
combination of resistors RT and RPH, together
with timing capacitor CT. CT charges and
discharges between 1/3 and 3/5 of VCC (see
Timing Diagram, page 9). CT is charged
exponentially through the parallel combination
of RT and RPH connected internally to VCC
through MOSFET S1. The charge time of CT
from 1/3 to 3/5 VCC is the on-time of the
respective output gate driver, HO or LO. Once
CT exceeds 3/5 VCC, MOSFET S1 is turned
off, disconnecting RT and RPH from VCC. CT is
then discharged exponentially through an
internal resistor, RDT, through MOSFET S3 to
COM. The discharge time of CT from 3/5 to 1/3
V
BUS (+)
VCC
13
3
S1
HO
VS
RT
16
15
M1
OSC
RT
Half-
Bridge
Output
S4
RPH
Half-
Bridge
Driver
4
5
RPH
ILOAD
CT
Fault
Logic
CT
LO
CS
11
10
M2
S3
1.3V
3uA
R1
CCS
Comp 4
CPH
2
RCS
CCPH
12
COM
IR2166
Load
Return
VBUS (-)
Figure 4, Ignition circuitry.
20
www.irf.com
IR2166
Ignition Mode (IGN)
RT and timing capacitor CT (see Design
Equations, page 26, Equations 3 and 4). Should
The ignition mode is defined as the state the IC hard-switching occur at the half-bridge at any
is in when a high voltage is being established time due to an open-filament or lamp removal,
across the lamp necessary for igniting the lamp. the voltage across the current sensing resistor,
The IR2166 enters ignition mode when the RCS, will exceed the internal threshold of 1.3 volts
voltage on pin CPH exceeds 10V.
and the IC will enter FAULT mode and gate driver
outputs HO, LO and PFC will be latched low.
Pin CPH is connected internally to the gate of a
P-channel MOSFET (S4) (see Figure 4) that DC Bus Under-voltage Reset
connects pin RPH with pin RT. As pin CPH
exceeds 10V, the gate-to-source voltage of Should the DC bus decrease too low during a
MOSFET S4 begins to fall below the turn-on brownout line condition or overload condition,
threshold of S4. As pin CPH continues to ramp the resonant output stage to the lamp can shift
towards VCC, switch S4 turns off slowly. This near or below resonance. This can produce
results in resistor RPH being disconnected hard-switching at the half-bridge which can
smoothly from resistor RT, which causes the damage the half-bridge switches or, the DC bus
operating frequency to ramp smoothly from the can decrease too far and the lamp can
preheat frequency, through the ignition frequency, extinguish. To protect against this, the VBUS pin
to the final run frequency. The over-current includes a 3.0V under-voltage threshold. Should
threshold on pin CS will protect the ballast the voltage at the VBUS pin decrease below 3.0V,
against a non-strike or open-filament lamp fault VCC will be discharged to the UVLO- threshold
condition. The voltage on pin CS is defined by and all gate driver outputs will be latched low.
the lower half-bridge MOSFET current flowing
through the external current sensing resistor For proper ballast design, the designer should
RCS. The resistor RCS therefore programs the design the PFC section such that the DC bus
maximum allowable peak ignition current (and does not drop until the AC line input voltage falls
therefore peak ignition voltage) of the ballast below the rated input voltage of the ballast (See
output stage. If the number of over current pulses PFC section). When correctly designed, the
exceed 25, the IC will enter fault mode and gate voltage measured at the VBUS pin will decrease
driver outputs HO, LO and PFC will be latched below the internal 3.0V threshold and the ballast
low.
will turn off cleanly. The pull-up resistor to VCC
( SUPPLY) will then turn the ballast on again
R
Run Mode (RUN)
with the AC input line voltage increasing to the
minimum specified value causing VCC to exceed
UVLO+.
Once the lamp has successfully ignited, the
ballast enters run mode. The run mode is defined
as the state the IC is in when the lamp arc is
established and the lamp is being driven to a
given power level. The run mode oscillating
frequency is determined by the timing resistor
R
SUPPLY should be set to turn the ballast on at
the minimum specified ballast input voltage. The
PFC should then be designed such that the DC
bus decreases at an input line voltage that is
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21
IR2166
II. PFC Section Functional Description
lower than the minimum specified ballast input
voltage. This hysteresis will result in clean turn-
on and turnoff of the ballast.
In most electronic ballasts it is necessary to
have the circuit act as a pure resistive load to
the AC input line voltage. The degree to which
the circuit matches a pure resistor is measured
by the phase shift between the input voltage
and input current and how well the shape of the
input current waveform matches the shape of
the sinusoidal input voltage. The cosine of the
phase angle between the input voltage and input
current is defined as the power factor (PF), and
how well the shape of the input current waveform
matches the shape of the input voltage is
determined by the total harmonic distortion
(THD). A power factor of 1.0 (maximum)
corresponds to zero phase shift and a THD of
0% represents a pure sinewave (no distortion).
For this reason it is desirable to have a high PF
and a low THD. To achieve this, the IR2166
includes an active power factor correction (PFC)
circuit which, for an AC line input voltage,
produces an AC line input current. The control
method implemented in the IR2166 is for a boost-
type converter (Figure 6) running in critical-
conduction mode (CCM). This means that during
each switching cycle of the PFC MOSFET, the
circuit waits until the inductor current discharges
to zero before turning the PFC MOSFET on again.
The PFC MOSFET is turned on and off at a
much higher frequency (>10KHz) than the line
input frequency (50 to 60Hz).
CS and EOL Fault Mode (FAULT)
Should the voltage at the SD/EOL pin exceed 3V
or decrease below 1V during RUN mode, the IC
enters fault mode and all gate driver outputs, HO,
LO and PFC, are latched off in the 'low' state.
CPH is discharged to COM for resetting the
preheat time, and CT is discharged to COM for
disabling the oscillator. To exit fault mode, VCC
must be recycled back below the UVLO negative-
going turn-off threshold, or, the shutdown pin, SD,
must be pulled above 5.2 volts. Either of these
will force the IC to enter UVLO mode (see State
Diagram, page 7). Once VCC is above the turn-
on threshold and SD is below 5.0 volts, the IC
will begin oscillating again in the preheat mode.
The current sense function will force the IC to
enter FAULT mode only after the voltage at the
current sense pin has been pulsed about 25 times
with a voltage greater than 1.3 volts during preheat
and ignition modes only. These over-currents must
occur during the on-time of LO. During run mode,
a single pulse on the CS pin above 1.3V will force
the IC to enter FAULT mode.
25 Pulses
LO
DPFC
LPFC
DC Bus
(+)
CS
2.0V
+
CBUS
MPFC
(-)
Run Mode
Fault Mode
Figure 6: Boost-type PFC circuit
Figure 5: FAULT counter during preheat and ignition
22
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IR2166
When the switch MPFC is turned on, the inductor
LPFC is connected between the rectified line
input (+) and (-) causing the current in LPFC to
charge up linearly. When MPFC is turned off,
LPFC is connected between the rectified line
input (+) and the DC bus capacitor CBUS
(through diode DPFC) and the stored current in
LPFC flows into CBUS. As MPFC is turned on
and off at a high-frequency, the voltage on CBUS
charges up to a specified voltage. The feedback
loop of the IR2166 regulates this voltage to a
fixed value by continuously monitoring the DC
voltage and adjusting the on-time of MPFC
accordingly. For an increasing DC bus the on-
time is decreased, and for a decreasing DC bus
the on-time is increased. This negative feedback
control is performed with a slow loop speed and
a low loop gain such that the average inductor
current smoothly follows the low-frequency line
input voltage for high power factor and low THD.
The on-time of MPFC therefore appears to be
fixed (with an additional modulation to be
discussed later) over several cycles of the line
voltage. With a fixed on-time, and an off-time
determined by the inductor current discharging
to zero, the result is a system where the
switching frequency is free-running and
constantly changing from a high frequency near
the zero crossing of the AC input line voltage,
to a lower frequency at the peaks (Figure 7).
V, I
t
Figure 7: Sinusoidal line input voltage (solid line), triangular
PFC Inductor current and smoothed sinusoidal line input
current (dashed line) over one half-cycle of the line input
voltage.
When the line input voltage is low (near the zero
crossing), the inductor current will charge up to
a small amount and the discharge time will be
fast resulting in a high switching frequency.
When the input line voltage is high (near the
peak), the inductor current will charge up to a
higher amount and the discharge time will be
longer giving a lower switching frequency. The
triangular PFC inductor current is then smoothed
by the EMI filter to produce a sinusoidal line
input current.
The PFC control circuit of the IR2166 (Figure 8)
only requires four control pins: VBUS, COMP,
ZX and PFC. The VBUS pin is for sensing the
DC bus voltage (via an external resistor voltage
divider), the COMP pin programs the on-time of
MPFC and the speed of the feedback loop, the
ZX pin detects when the inductor current
discharges to zero (via a secondary winding
from the PFC inductor), and the PFC pin is the
low-side gate driver output for MPFC.
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23
IR2166
LPFC
(+)
Fault Mode Signal
Run Mode Signal
GAIN
DFPC
1
6
VBUS
COMP
VCC
COMP4
COMP5
OTA1
4.0V
4.3V
8
PFC
RS3
S
Q
Q
RVBUS1
R
M1
RZX
COMP2
WATCH
DOG
TIMER
Discharge
VCC to
UVLO-
VBUS
ZX
C1
M2
3.0V
RS4
CBUS
PFC
Control
S
Q
Q
R1
R2
RPFC
PFC
COMP
MPFC
COMP3
7
ZX
2.0V
7.6V
COM
DCOMP CCOMP
RVBUS
Figure 9: IR2166 detailed PFC control circuit
(-)
The off-time of MPFC is determined by the time
it takes the LPFC current to discharge to zero.
This zero current level is detected by a
secondary winding on LPFC which is connected
to the ZX pin. A positive-going edge exceeding
the internal 2V threshold signals the beginning
of the off-time. A negative-going edge on the
ZX pin falling below 1.7V will occur when the
LPFC current discharges to zero which signals
the end of the off-time and MPFC is turned on
again (Figure 10). The cycle repeats itself
indefinitely until the PFC section is disabled due
to a fault detected by the ballast section (Fault
Mode), an over-voltage or under-voltage
condition on the DC bus, or, the negative
transition of ZX pin voltage does not occur.
Should the negative edge on the ZX pin not occur,
MPFC will remain off until the watch-dog timer
forces a turn-on of MPFC for an on-time duration
programmed by the voltage on the COMP pin.
The watch-dog pulses occur every 400µs
indefinitely until a correct positive- and negative-
going signal is detected on the ZX pin and normal
PFC operation is resumed.
Figure 8:IR2166 simplified PFC control circuit
The VBUS pin is regulated against a fixed
internal 4V reference voltage for regulating the
DC bus voltage (Figure 9). The feedback loop
is performed by an operational transconductance
amplifier (OTA) that sinks or sources a current
to the external capacitor at the COMP pin. The
resulting voltage on the COMP pin sets the
threshold for the charging of the internal timing
capacitor (C1) and therefore programs the on-
time of MPFC. During preheat and ignition
modes of the ballast section, the gain of the
OTA is set to a high level to raise the DC bus
level quickly. When the voltage on the VBUS pin
exceeds 3V, the gain is set to a low level to
reduce overshoot. When the voltage on the VBUS
pin exceeds 4V, the gain is set to a high level
again to minimize the transient on the DC bus
which can occur during ignition. During run
mode, the gain is then decreased to a lower
level necessary for achieving high power factor
and low THD.
24
www.irf.com
IR2166
modulation circuit has been added to the PFC
control. This circuit dynamically increases the
on-time of MPFC as the line input voltage nears
the zero-crossings (Figure 11). This causes the
peak LPFC current, and therefore the smoothed
line input current, to increase slightly higher near
the zero-crossings of the line input voltage. This
reduces the amount of cross-over distortion in
the line input current which reduces the THD
and higher harmonics to low levels.
ILPFC
0
0
0
PFC
pin
ILPFC
0
ZX
pin
PFC
pin
0
near peak region of
rectified AC line
near zero-crossing region
of rectified AC line
Figure 10: LPFC current, PFC pin and ZX pin timing
diagram.
Figure 11: On-time modulation near the zero-crossings.
Over-voltage Protection (OVP)
On-time Modulation
Should over-voltage occur on the DC bus
causing the VBUS pin to exceed the internal 4.3V
threshold, the PFC output is disabled (set to a
logic 'low'). When the DC bus decreases again
causing the VBUS pin to decrease below the
internal 4V threshold, a watch-dog pulse is forced
on the PFC pin and normal PFC operation is
resumed.
A fixed on-time of MPFC over an entire cycle of
the line input voltage produces a peak inductor
current which naturally follows the sinusoidal
shape of the line input voltage. The smoothed
averaged line input current is in phase with the
line input voltage for high power factor but the
total harmonic distortion (THD), as well as the
individual higher harmonics, of the current can
still be too high. This is mostly due to cross-
over distortion of the line current near the zero-
crossings of the line input voltage. To achieve
low harmonics which are acceptable to
international standard organizations and general
market requirements, an additional on-time
Under-voltage Reset (UVR)
When the line input voltage is decreased,
interrupted or a brown-out condition occurs, the
PFC feedback loop causes the on-time of MPFC
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25
IR2166
Ballast Design Equations
to increase in order to keep the DC bus constant.
Should the on-time increase too far, the resulting
peak currents in LPFC can exceed the saturation
current limit of LPFC. LPFC will then saturate
and very high peak currents and di/dt levels will
occur. To prevent this, the maximum on-time is
limited by limiting the maximum voltage on the
COMP pin with an external zener diode DCOMP
(Figure 8). As the line input voltage decreases,
the COMP pin voltage and therefore the on-time
will eventually limit. The PFC can no longer
supply enough current to keep the DC bus fixed
for the given load power and the DC bus will
begin to drop. Decreasing the line input voltage
further will cause the VBUS pin to eventually
decrease below the internal 3V threshold (Figure
9). When this occurs, VCC is discharged
internally to UVLO-, the IR2166 enters UVLO
mode and both the PFC and ballast sections
are disabled (see State Diagram). The start-up
supply resistor to VCC, together with the micro-
power start-up current of the IR2166, determine
the line input turn-on voltage. This should be
set such that the ballast turns on at a line voltage
level above the under-voltage turn-off level. It
is the correct selection of the value of the supply
resistor to VCC and the zener diode on the
COMP pin that correctly program the on and off
line input voltage thresholds for the ballast. With
these thresholds correctly set, the ballast will
turn off due to the 3V under-voltage threshold
on the VBUS pin, and on again at a higher line
input voltage (hysterisis) due to the supply
resistor to VCC. This hysterisis will result in a
proper reset of the ballast without flickering of
the lamp, bouncing of the DC bus or re-ignition
of the lamp when the DC bus is too low.
Note: The results from the following design
equations can differ slightly from experimental
measurements due to IC tolerances, component
tolerances, and oscillator over- and undershoot
due to internal comparator response time.
Step 1: Program Dead-time
The dead-time between the gate driver outputs
HO and LO is programmed with timing capacitor
CT and an internal dead-time resistor RDT. The
dead-time is the discharge time of capacitor CT
from 3/5VCC to 1/3VCC and is given as:
[Seconds]
(1)
tDT = CT 1475
or
tDT
CT =
[Farads]
(2)
1475
Step 2: Program Run Frequency
The final run frequency is programmed with
timing resistor RT and timing capacitor CT. The
charge time of capacitor CT from 1/3VCC to
3/5VCC determines the on-time of HO and LO
gate driver outputs. The run frequency is
therefore given as:
1
fRUN
=
[Hertz] (3)
2 CT (0.51 RT +1475)
or
1
RT =
− 2892
[Ohms] (4)
1.02 CT fRUN
26
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IR2166
Step 5: Program Maximum Ignition Current
Step 3: Program Preheat Frequency
The maximum ignition current is programmed
with the external resistor RCS and an internal
threshold of 1.3 volts. This threshold determines
the over-current limit of the ballast, which can
be exceeded when the frequency ramps down
towards resonance during ignition and the lamp
does not ignite. The maximum ignition current
is given as:
The preheat frequency is programmed with
timing resistors RT and RPH, and timing
capacitor CT. The timing resistors are
connected in parallel internally for the duration
of the preheat time. The preheat frequency is
therefore given as:
1
fPH
=
0.51 RT RPH
RT + RPH
[Hertz] (5)
2 CT
+1475
1.3
IIGN
=
[Amps Peak] (9)
[Ohms] (10)
RCS
or
or
1
− 2892 RT
1.3
1.02 CT fPH
RCS
=
RPH
=
IIGN
1
[Ohms] (6)
RT −
− 2892
1.02 CT fPH
Step 4: Program Preheat Time
The preheat time is defined by the time it takes
for the capacitor on pin CPH to charge up to
10 volts. An internal current source of 3uA flows
out of pin CPH. The preheat time is therefore
given as:
tPH = CPH 3.33e6
[Seconds] (7)
[Farads] (8)
or
CPH = tPH 0.3e − 6
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27
IR2166
P FC D esign E quations
ꢀ
S tep1: C alculate P FC inductor value:
ꢀ
2
MIN
(VBUS
−
2 VAC
) VAC
η
ꢀꢀ
MIN
ꢀꢀꢀꢀꢀꢀꢀ
ꢀ
[H enries] (1)
ꢀ
LPFC
=
2
f MIN POUT VBUS
ꢀ
w here,
ꢀ
VBUS
ꢀ
ꢁꢀꢀ
D C bus voltage
ꢀꢀꢀꢁꢀꢀ
M inim um rm s A C input voltage
P FC efficiency (typically 0.95)
VAC
ꢀ
MIN
ꢀ
ꢁꢀꢀ
ꢁꢀꢀ
ꢁꢀꢀ
η
ꢀ ꢀ
ꢀꢀ
M inim um P FC switching frequency at m inim um A C input voltage
B allast output power
f MIN
POUT
ꢀ
S tep 2: C alculate peak P FC inductor current:
2
2
POUT
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
[A m ps P eak] (2)
iPK
=
VAC
η
MIN
iPK
N ote: The PFC inductor m ust not saturate at
over the specified ballast operating tem perature range.
P roper core sizing and air-gapping should be considered in the inductor design.
S tep 3: C alculate m axim um on-tim e:
2
POUT L PFC
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ ꢀ
ꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
[Seconds] (3)
tON
=
2
MAX
VAC
η
MIN
S tep 4: C alculate m axim um C O M P voltage:
tON
MAX
ꢀꢀꢀꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
V COMP
=
[V olts] (4)
MAX
0.9 E − 6
S tep 5: S elect zener diode D C O M P value:
≈
ꢀ
ꢀ
ꢀ
zener voltage
V COMP
[V olts] (5)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
D COMP
MAX
S tep 6: C alculate resistor R S U P P LY value:
VAC
+ 10
MIN
PK
ꢀꢀꢀꢀꢀꢀ
[O hm s] (6)
R SUPPLY
=
IQCCUV
ꢀ
28
www.irf.com
IR2166
Case outline
01-6015
01-3065 00 (MS-001A)
16 Lead PDIP
01-6018
16 Lead SOIC (narrow body)
01-3064 00 (MS-012AC)
http://www.irf.com/ Data and specifications subject to change without notice.
3/19/2003
www.irf.com
29
相关型号：
IR2167S
PFC Ballast Control. Thermal Overload Protection. Brown Out Protection. Programmable Preheat and Frequency. Programmable Deadtime in a 20 Lead SOIC package
INFINEON
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