IR22141SSTRPBF [INFINEON]
Half Bridge Based Peripheral Driver, PDSO24, LEAD FREE, MO-150AH, SSOP-24;
| 型号： | IR22141SSTRPBF |
| 厂家： | 
Infineon |
| 描述： | Half Bridge Based Peripheral Driver, PDSO24, LEAD FREE, MO-150AH, SSOP-24 驱动 光电二极管 接口集成电路 |
| 文件： | 总33页 (文件大小：666K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IR2114SSPbF/IR21141SSPbF
IR2214SSPbF/IR22141SSPbF
HALF-BRIDGE GATE DRIVER IC
Features
Product Summary
•
•
•
•
•
•
•
•
•
Floating channel up to +600 V or +1200 V
Soft over-current shutdown
600 V or
1200 V max.
VOFFSET
Synchronization signal to synchronize shutdown with the other phases
Integrated desaturation detection circuit
Two stage turn on output for di/dt control
Separate pull-up/pull-down output drive pins
Matched delay outputs
IO+/- (min)
VOUT
Deadtime matching (max)
Deadtime (typ)
Desat blanking time (typ)
DSH, DSL input voltage
threshold (typ)
1.0 A / 1.5 A
10.4 V – 20 V
75 ns
330 ns
3 µs
Undervoltage lockout with hysteresis band
LEAD-FREE
8.0 V
Description
Soft shutdown time (typ)
9.25 µs
The IR211(4,41)/IR221(4,41) gate driver family is suited to drive a single half
bridge in power switching applications. These drivers provide high gate driving
capability (2 A source, 3 A sink) and require low quiescent current, which allows
the use of bootstrap power supply techniques in medium power systems. These
drivers feature full short circuit protection by means of power transistor
desaturation detection and manage all half-bridge faults by smoothly turning off
the desaturated transistor through the dedicated soft shutdown pin, therefore
preventing over-voltages and reducing EM emissions. In multi-phase systems,
the IR211(4,41)/ IR221(4,41) drivers communicate using a dedicated local
network (SY_FLT and FAULT/SD signals) to properly manage phase-to-phase
short circuits. The system controller may force shutdown or read device fault
state through the 3.3 V compatible CMOS I/O pin (FAULT/SD). To improve the
signal immunity from DC-bus noise, the control and power ground use dedicated
pins enabling low-side emitter current sensing as well. Undervoltage conditions
in floating and low voltage circuits are managed independently.
Package
24-Lead SSOP
Typical connection
DC+
VCC
VB
15 V
HOP
HON
SSDH
LIN
HIN
DSH
VS
DC BUS
uP,
Motor
FAULT/SD
FLT_CLR
SY_FLT
Control
(Up to 1200 V)
LOP
LON
SSDL
DSL
COM
VSS
DC-
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1
IR211(4,41)/IR221(4,41)SSPbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to VSS, all currents are defined positive into any lead The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
VS
High side offset voltage
VB - 25
VB + 0.3
(IR2114 or IR21141)
(IR2214 or IR22141)
High side floating output voltage (HOP, HON and SSDH)
Low side and logic fixed supply voltage
Power ground
Low side output voltage (LOP, LON and SSDL)
Logic input voltage (HIN, LIN and FLT_CLR)
FAULT input/output voltage (FAULT/SD and SY_FLT)
-0.3
625
VB
High side floating supply voltage
-0.3
1225
VHO
VCC
COM
VLO
VS - 0.3
-0.3
VCC - 25
VCOM -0.3 VCC + 0.3
VSS -0.3
VSS -0.3
VS -3
VCOM -3
—
VB + 0.3
25
VCC + 0.3
V
VIN
VCC + 0.3
VCC + 0.3
VB + 0.3
VCC + 0.3
50
VFLT
VDSH
VDSL
dVs/dt
PD
High side DS input voltage
Low side DS input voltage
Allowable offset voltage slew rate
Package power dissipation @ TA ≤ 25 °C
Thermal resistance, junction to ambient
Junction temperature
V/ns
W
°C/W
—
—
—
1.5
65
150
RthJA
TJ
TS
Storage temperature
-55
150
°C
TL
Lead temperature (soldering, 10 seconds)
—
300
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute
voltages referenced to VSS. The VS offset rating is tested with all supplies biased at a 15 V differential.
Symbol
Definition
Min.
Max. Units
VB
High side floating supply voltage (Note 1)
VS + 11.5
VS + 20
High side floating supply offset
(IR2114 or IR21141)
(IR2214 or IR22141)
Note 2
Note 2
VS
VCOM
11.5
-5
VSS
600
VS
voltage
1200
VHO
VLO
VCC
COM
VIN
VFLT
VDSH
VDSL
TA
High side output voltage (HOP, HON and SSDH)
Low side output voltage (LOP, LON and SSDL)
Low side and logic fixed supply voltage (Note 1)
Power ground
Logic input voltage (HIN, LIN and FLT_CLR)
Fault input/output voltage (FAULT/SD and SY_FLT)
High side DS pin input voltage
Low side DS pin input voltage
Ambient temperature
VS + 20
VCC
20
5
VCC
VCC
VB
VCC
125
V
VSS
VS - 2.0
VCOM - 2.0
-40
°C
Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables
the output drivers if the UV thresholds are not reached.
Note 2: Logic operational for VS from VSS-5 V to VSS +600 V or 1200 V. Logic state held for VS from VSS -5 V
to VSS-VBS. (Please refer to the Design Tip DT97-3 for more details).
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2
IR211(4,41)/IR221(4,41)SSPbF
Static Electrical Characteristics
VCC = 15 V, VSS = COM = 0 V, VS = 600 V or 1200 V and TA = 25 °C unless otherwise specified.
Pins: VCC, VSS, VB, VS
Symbol
Definition
Min Typ Max Units
Test Conditions
VCCUV+
VCCUV-
VCCUVH
VBSUV+
VBSUV-
VBSUVH
VCC supply undervoltage positive going threshold
VCC supply undervoltage negative going threshold
VCC supply undervoltage lockout hysteresis
(VB-VS) supply undervoltage positive going threshold
(VB-VS) supply undervoltage negative going threshold
(VB-VS) supply undervoltage lockout hysteresis
9.3 10.2 11.4
8.7 9.3 10.3
—
0.9
—
V
9.3 10.2 11.4
8.7 9.3 10.3
VS = 0 V, VS = 600 V
or 1200 V
—
0.9
—
VB = VS = 600 V or
1200 V
VIN = 0 V or 3.3 V
(No load)
ILK
Offset supply leakage current
—
—
50
µA
IQBS
IQCC
Quiescent VBS supply current
Quiescent VCC supply current
—
—
400 800
0.7
2.5
mA
Note 1: Refer to Fig. 1
Pins: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT
Symbol
Definition
Min
Typ
Max Units
Test Conditions
VIH
VIL
VIHSS
Logic "1" input voltage
Logic "0" input voltage
Logic input hysteresis
2.0
—
0.2
—
—
0.4
—
0.8
—
VCC = VCCUV-
to 20 V
V
Logic “1” input bias current (HIN, LIN, FLTCLR)
Logic “0” input bias current (FAULT/SD, SY_FLT)
Logic “0” input bias current
Logic “1” input bias current (FAULT/SD, SY_FLT)
FAULT/SD open drain resistance
SY_FLT open drain resistance
—
0
-1
-1
—
—
330
—
—
—
60
60
—
1
0
0
—
—
IIN+
VIN = 3.3 V
VIN = 0 V
µA
IIN-
RON,FLT
RON,SY
Ω
PW≤ 7 µs
Note 1: Refer to Figs. 2 & 3
Pins: DSL, DSH
The active bias is present only the IR21141and IR22141. VDESAT, IDS and IDSB parameters are referenced to COM and VS
respectively for DSL and DSH.
Symbol
VDESAT+
VDESAT-
VDSTH
Definition
Min Typ Max Units
7.2 8.0 8.8
Test Conditions
High desat input threshold voltage
Low desat input threshold voltage
Desat input voltage hysteresis
High DSH or DSL input bias current
Low DSH or DSL input bias current
V
See Figs. 4,16
6.3 7.0 7.7
—
—
—
1.0
21
-160
—
—
—
IDS+
VDESAT = VCC or VBS
VDESAT = 0 V
µA
IDS
-
DSH or DSL input bias current
IDSB
—
-20
—
mA
VDESAT = (VCC or VBS) – 2 V
(IR21141 and IR22141 only)
Note 1: Refer to Fig. 4
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3
IR211(4,41)/IR221(4,41)SSPbF
Pins: HOP, LOP
Symbol
Definition
Min Typ Max Units Test Conditions
VOH
High level output voltage, VB – VHOP or VCC –VLOP
—
40
300 mV
IO= 20 mA
V
HOP/LOP= 0 V, HIN
or LIN = 1, PW≤
200 ns, resistive
load, see Fig. 8
IO1+
Output high first stage short circuit pulsed current
1
2
—
A
V
HOP/LOP= 0 V, HIN
or LIN= 1,
Output high second stage short circuit pulsed current
IO2+
0.5
1
—
400 ns ≤PW≤ 10
µs, resistive load,
see Fig. 8
Note 1: Refer to Fig. 5
Pins: HON, LON, SSDH, SSDL
Symbol
Definition
Min Typ Max Units Test Conditions
VOL
RON,SSD
Low level output voltage, VHON or VLON
Soft Shutdown on resistance (Note 1)
—
—
45
90
300 mV
IO= 20 mA
PW≤ 7 µs
—
Ω
VHOP/LOP = 15 V,
IN or LIN = 0, PW≤
10 µs
IO-
Output low short circuit pulsed current
1.5
3
—
A
H
Note 1: SSD operation only
Note 2: Refer to Fig. 6
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4
IR211(4,41)/IR221(4,41)SSPbF
AC Electrical Characteristics
VCC = VBS = 15 V, VS = VSS and TA = 25 °C unless otherwise specified.
Symbol
Definition
Min. Typ. Max. Units
Test Conditions
ton
toff
tr
tf
ton1
Turn on propagation delay
Turn off propagation delay
Turn on rise time (CLOAD=1 nF)
Turn off fall time (CLOAD=1 nF)
Turn on first stage duration time
220
220
—
—
120
440
440
24
7
200
660
660
—
—
280
VIN = 0 & 1, VS = 0 V to 600 V
or 1200 V,
HOP shorted to HON, LOP
shorted to LON, Fig. 7
Fig. 8
DSH to HO soft shutdown propagation delay at HO
turn on
tDESAT1
tDESAT2
tDESAT3
tDESAT4
2000 3300 4600
1050
2000 3300 4600
VHIN= 1 V
DSH to HO soft shutdown propagation delay after
blanking
—
—
V
V
DESAT = 15 V, Fig. 10
LIN = 1 V
DSL to LO soft shutdown propagation delay at LO
turn on
V
DSL to LO soft shutdown propagation delay after
blanking
1050
1000
—
—
—
—
DESAT = 15 V, Fig. 10
tDS
tSS
Soft shutdown minimum pulse width of desat
Soft shutdown duration period
Fig. 9
5700 9250 13500
VDS=15 V, Fig. 9
ns
tSY_FLT,
—
1300
—
3600
—
—
—
—
—
—
V
HIN = 1 V
DS = 15 V, Fig. 10
LIN = 1 V
DESAT=15 V, Fig. 10
DSH to SY_FLT propagation delay at HO turn on
DSH to SY_FLT propagation delay after blanking
DSL to SY_FLT propagation delay at LO turn on
DESAT1
tSY_FLT,
DESAT2
V
tSY_FLT
,
3050
—
V
DESAT3
tSY_FLT
,
1050
—
V
DSL to SY_FLT propagation delay after blanking
DS blanking time at turn on
DESAT4
V
HIN = VLIN = 1 V, VDESAT=15 V,
tBL
3000
Fig. 10
Deadtime/Delay Matching Characteristics
DT
Deadtime
—
—
330
—
—
Fig. 11
MDT
PDM
Deadtime matching, MDT=DTH-DTL
75
External DT = 0 s, Fig. 11
Propagation delay matching,
Max (ton, toff) – Min (ton, toff)
—
—
75
External DT > 500 ns, Fig. 7
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5
IR211(4,41)/IR221(4,41)SSPbF
schmitt
trigger
comparator
VCC/V
B
internal
signal
HIN/LIN/
FLTCLR
internal
signal
UV
10k
VCCUV/VBSUV
VSS/V
S
VSS
Figure 1: Undervoltage Diagram
Figure 2: HIN, LIN and FLTCLR Diagram
VCC/VBS
active
bias
100k
700k
fault/hold
FAULT/SD
SY_FLT
internal signal
comparator
schmitt
trigger
DSL/DSH
internal
signal
SSD
R
ON
hard/soft shutdown
internal signal
V
DESAT
V
SS
COM/VS
Figure 3: FAULT/SD and SY_FLT Diagram
Figure 4: DSH and DSL Diagram
200ns
V
CC/VB
oneshot
LON/HON
V
OH
SSDL/SSDH
on/off
on/off
internal signal
internal signal
VOL
LOP/HOP
RON,SSD
desat
internal signal
COM/V
S
Figure 5: HOP and LOP Diagram
Figure 6: HON, LON, SSDH and SSDL Diagram
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6
IR211(4,41)/IR221(4,41)SSPbF
3.3V
50%
HIN
LIN
50%
tr
PWin
toff
ton
tf
PWout
HO (HOP=HON)
LO (LOP=LON)
90%
10%
90%
10%
Figure 7: Switching Time Waveforms
Ton1
Io1+
Io2+
Figure 8: Output Source Current
3.3V
HIN/LIN
t DS
DSH/DSL
8V
8V
SSD Driver Enable
tSS
tDESAT
HO/LO
Figure 9: Soft Shutdown Timing Waveform
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7
IR211(4,41)/IR221(4,41)SSPbF
50%
50%
HIN
LIN
50%
8V
8V
DSH
8V
8V
DSL
50%
50%
SY_FLT,DESAT3
50%
SY_FLT,DESAT1
50%
t
t
SY_FLT
t
SY_FLT,DESAT2
t
SY_FLT,DESAT4
FAULT/SD
FLTCLR
Turn_Off propagation Delay
t
DESAT2
t
DESAT1
90%
90%
90%
SoftShutdown
SoftShutdown
50%
50%
10%
HON
t
DESAT4
tBL
tBL
t
DESAT3
90%
90%
SoftShutdown
90%
SoftShutdown
50%
50%
Turn-On Propagation Delay
10%
LON
tBL
tBL
Turn-On Propagation Delay
Figure 10: Desat Timing
LIN
50%
50%
HIN
50%
DTH
50%
DTL
50%
50%
MDT=DTH-DTL
Figure 11: Internal Deadtime Timing
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8
IR211(4,41)/IR221(4,41)SSPbF
Lead Assignments
1
DSH
24
HIN
LIN
VB
N.C.
HOP
HON
VS
FLT_CLR
SY_FLT
FAULT/SD
VSS
24-Lead SSOP
SSOP24
SSDL
SSDH
N.C.
N.C.
N.C.
N.C.
COM
LON
LOP
VCC
DSL
12
N.C.
13
Lead Definitions
Symbol
Description
VCC
VSS
HIN
LIN
Low side gate driver supply
Logic ground
Logic input for high side gate driver outputs (HOP/HON)
Logic input for low side gate driver outputs (LOP/LON)
Dual function (in/out) active low pin. Refer to Figs. 15, 17, and 18. As an output, indicates fault condition.
FAULT/SD As an input, shuts down the outputs of the gate driver regardless HIN/LIN status.
Dual function (in/out) active low pin. Refer to Figs. 15, 17, and 18. As an output, indicates SSD sequence
SY_FLT
FLT_CLR
is occurring. As an input, an active low signal freezes both output status.
Fault clear active high input. Clears latched fault condition (see Fig. 17)
LOP
LON
DSL
SSDL
COM
VB
HOP
HON
DSH
SSDH
VS
Low side driver sourcing output
Low side driver sinking output
Low side IGBT desaturation protection input
Low side soft shutdown
Low side driver return
High side gate driver floating supply
High side driver sourcing output
High side driver sinking output
High side IGBT desaturation protection input
High side soft shutdown
High side floating supply return
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IR211(4,41)/IR221(4,41)SSPbF
VCC
VB
on/off
SCHMITT
TRIGGER
INPUT
LATCH
HOP
HON
on/off (HS)
on/off (LS)
on/off
desat
di/dt control
Driver
HIN
LIN
LOCAL DESAT
PROTECTION
INPUT
HOLD
LOGIC
OUTPUT
SHUTDOWN
LOGIC
soft
LEVEL
SHOOT
SHIFTERS
shutdown
THROUGH
PREVENTION
SOFT SHUTDOWN
UV_VBS DETECT
SSDH
DSH
(DT) Deadtime
VS
UV_VCC
DETECT
UV_VCC
on/off
LOP
LON
di/dt control
Driver
DesatHS
soft
SSD
HOLD
SD
LOCAL DESAT
PROTECTION
FAULT LOGIC
managemend
(See figure 14)
SY_FLT
FAULT/SD
FLT_CLR
shutdown
FAULT
SSDL
DSL
SOFTSHUTDOWN
DesatLS
COM
VSS
FUNCTIONAL BLOCK DIAGRAM
Start-Up
Sequence
ShutDown
HO=LO=0
UnderVoltage
VCC
UnderVoltage
VBS
FAULT
HO=LO=0
HO=0, LO=LIN
UV_VCC
DESAT
EVENT
HO/LO=1
UV_VBS
Soft
ShutDown
Freeze
STATE DIAGRAM
Stable State
Temporary State
System Variable
−
−
−
−
−
−
−
FAULT
−
−
SOFT SHUTDOWN
START UP SEQUENCE
−
−
−
−
−
−
−
FLT_CLR
HIN/LIN
UV_VCC
UV_VBS
DSH/L
SY_FLT
FAULT/SD
HO=LO=0 (Normal operation)
HO/LO=1 (Normal operation)
UNDERVOLTAGE VCC
SHUTDOWN (SD)
UNDERVOLTAGE VBS
FREEZE
NOTE 1: A change of logic value of the signal labeled on lines (system variable) generates a state transition.
NOTE 2: Exiting from UNDERVOLTAGE VBS state, the HO goes high only if a rising edge event happens in HIN.
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IR211(4,41)/IR221(4,41)SSPbF
HO/LO Status
HOP/LOP
HON/LON
SSDH/SSDL
0
1
HiZ
1
0
HiZ
HiZ
0
HiZ
HiZ
SSD
HiZ
LO/HO
LOn-1/HOn-1
Output follows inputs (in=1->out=1, in=0->out=0)
Output keeps previous status
IR2214 Logic Table: Output Drivers Status Description
Undervoltage
Yes: V< UV
threshold
INPUTS
INPUT/OUTPUT
No : V> UV
threshold
OUTPUTS
X: don’t care
______
_________
FAULT/SD
SY_FLT
SSD: desat (out)
HOLD: freezing
(in)
Operation
SD: shutdown (in)
FAULT: diagnostic
(out)
VCC
VBS
HO
LO
Hin
Lin
FLT_CLR
Shutdown
Fault Clear
X
HIN
1
X
LIN
0
X
X
0 (SD)
(FAULT)
X
X
0
HO
1
0
LO
0
NOTE1
No
No
No
No
No
No
No
No
0
0
0
1
1
1
1
1
1
Normal
0
1
0
1
Operation
0
0
0
0
Anti Shoot
Through
1
1
0
1
1
1
No
No
0
0
(SSD)
Soft
1
0
0
1
0
0
0
0
X
X
X
No
No
No
No
No
No
Yes
No
No
No
No
No
Yes
X
SSD
0
SSD
0
Shutdown
(SSD)
(SSD)
(SSD)
1
0
(entering)
(FAULT)
Soft
X
X
X
X
X
X
0
Shutdown
(finishing)
(FAULT)
X
0
HOn-1
0
0
Freeze
X
0 (HOLD)
1
LOn-1
LO
0
LIN
X
1
1
1
Undervoltage
0 (FAULT)
0
NOTE 1: SY_FLT automatically resets after the SSD event is over and FLT_CLR is not required. In order to avoid the
FLT_CLR conflicting with the SSD procedure, FLT_CLR should not be operated while SY_FLT is active.
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IR211(4,41)/IR221(4,41)SSPbF
1.4 Fault Management
The IR211(4,41)/ IR221(4,41) is able to manage supply
failure (undervoltage lockout) and transistor desaturation
(on both the low and high side switches).
1 Features Description
1.1 Start-Up Sequence
At power supply start-up, it is recommended to keep the
FLT_CLR pin active until the supply voltages are
properly established. This prevents spurious diagnostic
signals being generated. All protection functions are
operating independently from the FLT_CLR status and
the output driver status reflects the input commands.
1.4.1 Undervoltage (UV)
The undervoltage protection function disables the
driver’s output stage which prevents the power device
from being driven when the input voltage is less than the
undervoltage threshold. Both the low side (VCC supplied)
and the floating side (VBS supplied) are controlled by a
dedicate undervoltage function.
When the bootstrap supply topology is used for
supplying the floating high side stage, the following start-
up sequence is recommended (see also Fig. 12):
An undervoltage event on the VCC pin (when
VCC < UVVCC-) generates a diagnostic signal by forcing
the FAULT/SD pin low (see FAULT/SD section and Fig.
14). This event disables both the low side and floating
drivers and the diagnostic signal holds until the
undervoltage condition is over. The fault condition is not
latched and the FAULT/SD pin is released once VCC
1. Set VCC
,
2. Set FLT_CLR pin to HIGH level,
3. Set LIN pin to HIGH level and charge the
bootstrap capacitor,
4. Release LIN pin to LOW level,
5. Release FLT_CLR pin to LOW level.
becomes higher than UVVCC+
.
The VBS undervoltage protection works by disabling only
the floating driver. Undervoltage on VBS does not prevent
the low side driver from activating its output nor does it
generate diagnostic signals. The VBS undervoltage
condition (VBS < UVVBS-) latches the high side output
stage in the low state. VBS must exceed the UVVBS+
threshold to return the device to its normal operating
mode. To turn on the floating driver, HIN must be re-
asserted high (rising edge event on HIN is required).
VCC
FLT_CLR
LIN
LO
Figure 12 Start-Up Sequence
1.4.2 Power Devices Desaturation
A minimum 15 µs LIN and FLT-CLR pulse is required.
Different causes can generate a power inverter failure
(phase and/or rail supply short-circuit, overload
conditions induced by the load, etc.). In all of these fault
conditions, a large increase in current results in the
IGBT.
1.2 Normal Operation Mode
After the start-up sequence has completed, the device
becomes fully operative (see grey blocks in the State
Diagram).
The IR211(4,41)/ IR221(4,41) fault detection circuit
monitors the IGBT emitter to collector voltage (VCE) (an
external high voltage diode is connected between the
IGBT’s collector and the ICs DSH or DSL pins). A high
current in the IGBT may cause the transistor to
HIN and LIN produce driver outputs to switch
accordingly, while the input logic monitors the input
signals and deadtime (DT) prevent shoot-through events
from occurring.
desaturate; this condition results in an increase of VCE
.
1.3 Shutdown
The system controller can asynchronously command the
Hard Shutdown (HSD) through the 3.3 V compatible
CMOS I/O FAULT/SD pin. This event is not latched.
Once in desaturation, the current in the power transistor
can be as high as 10 times the nominal current.
Whenever the transistor is switched off, this high current
generates relevant voltage transients in the power stage
that need to be smoothed out in order to avoid
destruction (by over-voltage). The gate driver is able to
control the transient condition by smoothly turning off the
desaturated transistor with its integrated soft shutdown
(SSD) protection.
In a multi-phase system, FAULT/SD signals are or-ed so
the controller or one of the gate drivers can force the
simultaneous shutdown of the other gate drivers through
the same pin.
1.4.3 Desaturation Detection: DSH/L Function
Figure 13 shows the structure of the desaturation
sensing and soft shutdown block. This configuration is
the same for both the high and low side output stages.
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12
IR211(4,41)/IR221(4,41)SSPbF
sensing
diode
VB/Vcc
HOPH/L
HONH/L
SSDH/L
PreDriver
ONE
SHOT
(ton1)
on/off
tBL
Blanking
tss
One Shot
DesatHS/LS
tDS
DSH/L
filter
desat
comparator
VDESAT
VS/COM
Figure 13: High and Low Side Output Stage
internal
HOLD
internal FAULT
(hard shutdown)
SY_FLT
(external
hold)
FAULT/SD
(external hard
shutdown)
SET
CLR
Q
Q
S
R
DesatHS
DesatLS
UVCC
FLTCLR
Figure 14: Fault Management Diagram
The external sensing diode should have BV > 600 V or
1200 V and low stray capacitance (in order to minimize
noise coupling and switching delays). The diode is
biased by an internal pull-up resistor RDSH/L (equal to
Eligible desaturation signals initiate the SSD sequence.
While in SSD, the driver’s output goes to a high
impedance state and the SSD pull-down is activated to
turn off the IGBT through the SSDH/SSDL pin. The
SY_FLT output pin (active low, see Fig. 14) reports the
gate driver status during the SSD sequence (tSS). Once
the SSD has finished, SY_FLT releases, and the gate
driver generates a FAULT signal (see the FAULT/SD
section) by activating the FAULT/SD pin. This generates
a hard shutdown for both the high and low output stages
(HO=LO=low). Each driver is latched low until the fault is
cleared (see FLT_CLR).
V
CC/IDS- or VBS/IDS- for IR2114 or IR2214) or by a
dedicated circuit (see the active-bias section for IR21141
and IR22141). When VCE increases, the voltage at the
DSH or DSL pin increases too. Being internally biased to
the local supply, the DSH/DSL voltage is automatically
clamped. When DSH/DSL exceeds the VDESAT+
threshold, the comparator triggers (see Fig. 13). The
comparator’s output is filtered in order to avoid false
desaturation detection by externally induced noise;
pulses shorter than tDS are filtered out. To avoid
detecting a false desaturation event during IGBT turn on,
the desaturation circuit is disabled by a blanking signal
(TBL, see blanking block in Fig. 13). This time is the
estimated maximum IGBT turn on time and must be not
exceeded by proper gate resistance sizing. When the
IGBT is not completely saturated after TBL, desaturation
is detected and the driver will turn off.
Figure 14 shows the fault management circuit. In this
diagram DesatHS and DesatLS are two internal signals
that come from the output stages (see Fig. 13).
It must be noted that while in SSD, both the
undervoltage fault and external SD are masked until the
end of SSD. Desaturation protection is working
independently by the other control pin and it is disabled
only when the output status is off.
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13
IR211(4,41)/IR221(4,41)SSPbF
In the high side circuit, the desaturation biasing current
may become relevant for dimensioning the bootstrap
capacitor (see Fig. 19). In fact, a pull up resistor with a
FAULT
low resistance may result in
a high current the
VCC
VB
VCC
VB
VCC
VB
significantly discharges the bootstrap capacitor. For that
reason, the typical pull up resistor value is on the order
of 100 kꢀ. This is the value of the internal pull up.
LIN
HIN
FLT_CLR
HOP
HON
SSH
LIN
HIN
FLT_CLR
HOP
HON
SSH
LIN
HIN
FLT_CLR
HOP
HON
SSH
DSH
VS
DSH
VS
DSH
VS
SY_FLT
SY_FLT
SY_FLT
LOP
LON
SSL
LOP
LON
SSL
LOP
LON
SSL
FAULT/SD
FAULT/SD
FAULT/SD
While the impedance of the DSH/DSL pins is very low
when the transistor is on (low impedance path through
the external diode down to the power transistor), the
impedance is only controlled by the pull up resistor when
the transistor is off. In that case, relevant dV/dt applied
by the power transistor during the commutation at the
output results in a considerable current injected through
the stray capacitance of the diode into the desaturation
detection pin (DSH/DSL). This coupled noise may be
easily reduced be using an active bias structure for the
sensing diode.
DSL
DSL
DSL
VSS
COM
VSS
COM
VSS
COM
phase U
phase V
phase W
Figure 15: IR2214 Used in a 3 Phase Application
1.4.4 Fault Management in Multi-Phase Systems
In a system with two or more gate drivers the IR2214/1
devices must be connected as shown in Fig. 15.
SY_FLT: The bi-directional SY_FLT pins communicate
each other through a local network. The logic signal is
active low. The device that detects the IGBT
desaturation activates the SY_FLT, which is then read
by the other gate drivers. When SY_FLT is active all the
drivers hold their output state regardless of the input
signals (HIN, LIN) they receive from the controller (freeze
state). This feature is particularly important in phase-to-
phase short circuit where two IGBTs are involved; in
fact, while one is softly shutting-down, the other must be
prevented from hard shutdown to avoid exiting SSD. In
the freeze state, the frozen drivers are not completely
inactive because desaturation detection still takes the
highest priority. SY_FLT communication has been
designed for creating a local network between the
drivers. There is no need to wire SY_FLT to the
controller.
An active bias structure is available only for the IR21141
or IR22141 versions. The DSH/DSL pins present an
active pull-up respectively to VB/VCC, and a pull-down
respectively to VS/COM.
The dedicated biasing circuit reduces the impedance on
the DSH/DSL pin when the voltage exceeds the VDESAT
threshold (see Fig. 16). This low impedance helps in
rejecting the noise provided by the current injected by
the parasitic capacitance. When the power transistor is
fully on, the sensing diode is forward biased and the
voltage at the DSH/DSL pin decreases. At this point the
biasing circuit deactivates, in order to reduce the bias
current of the diode as shown in Fig. 16.
RDSH/L
100K ohm
FAULT/SD:
The bi-directional FAULT/SD pins
communicate with each other and with the system
controller. The logic signal is active low. When low, the
FAULT/SD signal commands the outputs to go off by
hard shutdown. There are three events that can force
FAULT/SD low:
100 ohm
VDSH/L
1. Desaturation detection event: the FAULT/SD
pin is latched low when SSD is over, and only a
FLT_CLR signal can reset it,
Figure 16: RDSH/L Active Biasing
2. Undervoltage on VCC: the FAULT/SD pin is
forced low and held until the undervoltage is
active (not latched),
1.6 Output Stage
The structure is shown in Fig. 13 and consists of two
turn on stages and one turn off stage. When the driver
turns on the IGBT (see Fig. 8), a first stage is activated
while an additional stage is maintained in the active state
for a limited time (ton1). This feature boosts the total
driving capability in order to accommodate both a fast
gate charge to the plateau voltage and dV/dt control in
switching.
3. FAULT/SD is externally driven low either from
the controller or from another IR2x14/1 device.
This event is not latched; therefore the
FLT_CLR cannot disable it. Only when
FAULT/SD becomes high the device returns to
its normal operating mode.
1.5 Active Bias
At turn off, a single n-channel sinks up to 3 A (IO-) and
offers a low impedance path to prevent the self-turn on
due to the parasitic Miller capacitance in the power
switch.
For the purpose of sensing the power transistor
desaturation, the collector voltage is monitored (an
external high voltage diode is connected between the
IGBT’s collector and the IC’s DSH or DSL pin). The
diode is normally biased by an internal pull up resistor
connected to the local supply line (VB or VCC). When the
transistor is “on” the diode is conducting and the amount
of current flowing in the circuit is determined by the
internal pull up resistor value.
1.7 Timing and Logic State Diagrams Description
The following figures show the input/output logic
diagram. Figure 17 shows the SY_FLT and FAULT/SD
signals as outputs, whereas Fig. 18 shows them as
inputs.
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14
IR211(4,41)/IR221(4,41)SSPbF
A
B
C
D
E
F
G
HIN
LIN
DSH
DSL
SY_FLT
FAULT/SD
FLT_CLR
HO(HOP/HON)
LO(LOP/LON)
Figure 17: I/O Timing Diagram with SY_FLT and FAULT/SD as Output
A
B
C
D
E
F
HIN
LIN
SY_FLT
FAULT/SD
FLT_CLR
HO (HOP/HON)
LO (LOP/LON)
Figure 18: I/O Logic Diagram with SY_FLT and FAULT/SD as Input
Referred to the timing diagram of Fig. 17:
Referred to the timing diagram Fig. 18:
A. The device is in the hold state, regardless of
input variations. The hold state results as
SY_FLT is forced low externally,
A. When the input signals are on together the
outputs go off (anti-shoot through),
B. The HO signal is on and the high side IGBT
desaturates, the HO turn off softly while the
SY_FLT stays low. When SY_FLT goes high
the FAULT/SD goes low. While in SSD, if LIN
goes up, LO does not change (freeze),
C. When FAULT/SD is latched low (see
FAULT/SD section) FLT_CLR can disable it
and the outputs go back to follow the inputs,
D. The DSH goes high but this is not read
because HO is off,
B. The device outputs go off by hard shutdown,
externally commanded. A through B is the
same sequence adopted by another IR2x14x
device in SSD procedure.
C. Externally driven low FAULT/SD (shutdown
state) cannot be disabled by forcing FLT_CLR
(see FAULT/SD section),
D. The FAULT/SD is released and the outputs go
back to follow the inputs,
E. The LO signal is on and the low side IGBT
desaturates, the low side behaviour is the
same as described in point B,
E. Externally driven low FAULT/SD: outputs go
off by hard shutdown (like point B),
F. As point A and B but for the low side output.
F. The DSL goes high but this is not read as LO
is off,
G. As point A (anti-shoot through).
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15
IR211(4,41)/IR221(4,41)SSPbF
−
− Charge required by the internal level shifters
(QLS); typical 20 nC,
2 Sizing Tips
2.1 Bootstrap Supply
− Bootstrap capacitor leakage current (ILK_CAP),
− High side on time (THON).
The VBS voltage provides the supply to the high side
driver circuitry of the gate driver. This supply sits on top
of the VS voltage and so it must be floating. The
bootstrap method is used to generate the VBS supply
and can be used with any of the IR211(4,41)/
IR221(4,41) drivers. The bootstrap supply is formed by
a diode and a capacitor as connected in Fig. 19.
ILK_CAP is only relevant when using an electrolytic
capacitor and can be ignored if other types of
capacitors are used. It is strongly recommend using at
least one low ESR ceramic capacitor (paralleling
electrolytic and low ESR ceramic may result in an
efficient solution).
bootstrap
resistor
bootstrap
diode
DC+
Then we have:
Rboot
VF
VCC
VB
QTOT = QG + QLS + (ILK _ GE + IQBS
+
VCC
HOP
HON
VS
+ ILK + ILK _ DIODE + ILK _ CAP + IDS − )⋅THON
The minimum size of bootstrap capacitor is:
QTOT
bootstrap
capacitor
VBS
VGE
ILOAD
motor
SSDH
VCEon
VFP
CBOOT min
=
∆VBS
COM
An example follows using IR2214SS or IR22141SS:
Figure 19: Bootstrap Supply Schematic
a) using a 25 A @ 125 °C 1200 V IGBT
(IRGP30B120KD):
This method has the advantage of being simple and low
cost but may force some limitations on duty-cycle and
on-time since they are limited by the requirement to
refresh the charge in the bootstrap capacitor. Proper
capacitor choice can reduce drastically these
limitations.
• IQBS = 800 µA
(datasheet IR2214);
• ILK = 50 µA (see Static Electrical Characteristics);
• QLS = 20 nC
• QG = 160 nC
• ILK_GE = 100 nA
• ILK_DIODE = 100 µA
• ILK_CAP = 0
• IDS- = 150 µA (see Static Electrical Characteristics);
• THON = 100 µs.
(datasheet IRGP30B120KD);
(datasheet IRGP30B120KD);
(reverse recovery <100 ns);
2.2 Bootstrap Capacitor Sizing
(neglected for ceramic capacitor);
To size the bootstrap capacitor, the first step is to
establish the minimum voltage drop (∆VBS) that we
have to guarantee when the high side IGBT is on.
And:
If VGEmin is the minimum gate emitter voltage we want
to maintain, the voltage drop must be:
•
VCC = 15 V
•
•
•
VF = 1 V
∆VBS ≤VCC −VF −VGE min −VCEon
under the condition,
VCEonmax = 3.1 V
VGEmin = 10.5 V
the maximum voltage drop ∆VBS becomes
VGE min >VBSUV −
where VCC is the IC voltage supply, VF is bootstrap
diode forward voltage, VCEon is emitter-collector voltage
of low side IGBT, and VBSUV- is the high-side supply
undervoltage negative going threshold.
∆VBS ≤VCC −VF −VGEmin −VCEon
=
=15V−1V−10.5V−3.1V= 0.4 V
And the bootstrap capacitor is:
Now we must consider the influencing factors
contributing VBS to decrease:
290 nC
0.4V
CBOOT
≥
= 725 nF
− IGBT turn on required gate charge (QG),
− IGBT gate-source leakage current (ILK_GE),
− Floating section quiescent current (IQBS),
− Floating section leakage current (ILK),
− Bootstrap diode leakage current (ILK_DIODE),
− Desat diode bias when on (IDS- ),
−
NOTICE: VCC has been chosen to be 15 V. Some
IGBTs may require a higher supply to work correctly
with the bootstrap technique. Also VCC variations
must be accounted in the above formulas.
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16
IR211(4,41)/IR221(4,41)SSPbF
minimize the amount of charge fed back from the
2.3 Some Important Considerations
bootstrap capacitor to VCC supply.
Voltage Ripple: There are three different cases to
consider (refer to Fig. 19).
2.4 Gate Resistances
The switching speed of the output transistor can be
controlled by properly sizing the resistors controlling the
turn-on and turn-off gate currents. The following section
provides some basic rules for sizing the resistors to
obtain the desired switching time and speed by
introducing the equivalent output resistance of the gate
driver (RDRp and RDRn).
ꢀ
ILOAD < 0 A; the load current flows in the low side
IGBT (resulting in VCEon).
VBS = VCC −VF −VCEon
In this case we have the lowest value for VBS. This
represents the worst case for the bootstrap capacitor
sizing. When the IGBT is turned off, the Vs node is
pushed up by the load current until the high side
freewheeling diode is forwarded biased.
The example shown uses IGBT power transistors and
Figure 20 shows the nomencla*ture used in the following
paragraphs. In addition, Vge indicates the plateau
voltage, Qgc and Qge indicate the gate to collector and
gate to emitter charge respectively.
ꢀ
ILOAD = 0 A; the IGBT is not loaded while being on
and VCE can be neglected
IC
CRES
VBS = VCC −VF
VGE
ꢀ
ILOAD > 0 A; the load current flows through the
freewheeling diode
t1,QGE
VCE
t2,QGC
dV/dt
VBS = VCC −VF +VFP
In this case we have the highest value for VBS. Turning
on the high side IGBT, ILOAD flows into it and VS is
pulled up. To minimize the risk of undervoltage, the
bootstrap capacitor should be sized according to the
ILOAD< 0 A case.
IC
90%
CRESon
CRES
VGE
Vge
*
CRESoff
10%
10%
Bootstrap Resistor: A resistor (Rboot) is placed in series
with the bootstrap diode (see Fig. 19) in order to limit
the current when the bootstrap capacitor is initially
charged. We suggest not exceeding 10 ꢀ to avoid
increasing the VBS time-constant. The minimum on time
for charging the bootstrap capacitor or for refreshing its
charge must be verified against this time-constant.
t,Q
tSW
tDon
tR
Figure 20: Nomenclature
2.5 Sizing The Turn-On Gate Resistor
Bootstrap Capacitor: For high THON designs where an
electrolytic capacitor is used, its ESR must be
considered. This parasitic resistance forms a voltage
divider with Rboot, which generats a voltage step on VBS
at the first charge of bootstrap capacitor. The voltage
step and the related speed (dVBS/dt) should be limited.
As a general rule, ESR should meet the following
constraint.
Switching-Time: For the matters of the calculation
included hereafter, the switching time tsw is defined
as the time spent to reach the end of the plateau
voltage (a total Qgc+Qge has been provided to the
IGBT gate). To obtain the desired switching time the
gate resistance can be sized starting from Qge and
ESR
*
Qgc, Vcc, Vge (see Fig. 21):
⋅VCC ≤ 3V
ESR+ RBOOT
Qgc + Qge
Iavg
=
A parallel combination of a small ceramic capacitor and
a large electrolytic capacitor is normally the best
compromise, the first capacitor posses a fast time
constant and limits the dVBS/dt by reducing the
equivalent resistance. The second capacitor provides a
large capacitance to maintain the VBS voltage drop
tsw
and
Vcc −Vg*e
within the desired ∆VBS
.
RTOT
=
Iavg
Bootstrap Diode: The diode must have a BV > 600 V or
1200 V and a fast recovery time (trr < 100 ns) to
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17
IR211(4,41)/IR221(4,41)SSPbF
IGBT, the device may self turn on, causing large
Iavg
CRES
Vcc/Vb
RDRp
oscillation and relevant cross conduction.
dV/dt
HS Turning ON
RGon
CRESoff
COM/Vs
RGoff
OFF
ON
Figure 21: RGon Sizing
RDRn
CIES
where RTOT = RDRp + RGon
Figure 22: RGoff Sizing: Current Path When Low Side is
RGon = gate on-resistor
Off and High Side Turns On
RDRp = driver equivalent on-resistance
The transfer function between the IGBT collector and
the IGBT gate then becomes:
When RGon > 7 ꢀ, RDRp is defined by
tSW
Vcc Vcc
Vge
s ⋅(RGoff + RDRn )⋅CRESoff
+
−1 when tSW > ton1
=
Io1+ Io2+ ton1
RDRp
=
Vde 1+ s ⋅(RGoff + RDRn ) ⋅(CRESoff + CIES )
Vcc
Io1+
when tSW ≤ ton1
Which yields to a high pass filter with a pole at:
1
1/τ =
(IO1+ ,IO2+ and ton1 from “Static Electrical
Characteristics”).
(RGoff + RDRn ) ⋅(CRESoff + CIES )
Table 1 reports the gate resistance size for two
commonly used IGBTs (calculation made using typical
datasheet values and assuming VCC= 15 V).
As a result, when τ is faster than the collector rise time
(to be verified after calculation) the transfer function can
be approximated by:
Output Voltage Slope: The turn-on gate resistor
RGon can be sized to control the output slope
(dVOUT/dt). While the output voltage has a non-
linear behaviour, the maximum output slope can be
approximated by:
Vge
Vde
= s ⋅(RGoff + RDRn )⋅CRESoff
dVde
in the
So that Vge = (RGoff + RDRn ) ⋅CRESoff
time domain.
⋅
Iavg
CRESoff
dt
dVout
dt
=
Then the condition:
inserting the expression yielding Iavg and rearranging:
dVout
dt
*
( )
Vth >Vge = RGoff + RDRn ⋅CRESoff
must be verified to avoid spurious turn on.
Vcc −Vge
RTOT
=
dVout
CRESoff
⋅
Rearranging the equation yields:
As an example, table 2 shows the sizing of gate
resistance to get dVout/dt= 5 V/ns when using two
popular IGBTs (typical datasheet values are used and
VCC= 15 V is assumed).
Vth
RGoff
<
− RDRn
dV
dt
CRESoff
⋅
In any case, the worst condition for unwanted turn on is
with very fast steps on the IGBT collector.
NOTICE: Turn on time must be lower than TBL to avoid
improper desaturation detection and SSD triggering.
In that case, the collector to gate transfer function can
be approximated with the capacitor divider:
2.6 Sizing the Turn-Off Gate Resistor
The worst case in sizing the turn-off resistor RGoff is
when the collector of the IGBT in the off state is forced
to commutate by an external event (e.g., the turn-on of
the companion IGBT). In this case the dV/dt of the
output node induces a parasitic current through CRESoff
flowing in RGoff and RDRn (see Fig. 22). If the voltage
drop at the gate exceeds the threshold voltage of the
CRESoff
Vge =Vde ⋅
(CRESoff + CIES )
which is driven only by IGBT characteristics.
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18
IR211(4,41)/IR221(4,41)SSPbF
As an example, table 3 reports RGoff (calculated with the
above mentioned disequation) for two popular IGBTs to
withstand dVout/dt = 5 V/ns.
NOTICE: The above-described equations are intended
to approximate a way to size the gate resistance. A
more accurate sizing may provide more precise device
and PCB (parasitic) modelling.
IGBT
Qge
Qgc
Vge*
tsw
Iavg
Rtot
Tsw
RGon → std commercial value
IRGP30B120K(D) 19 nC 82 nC
9 V
9 V
400 ns 0.25 A
200 ns 0.15 A
24 Ω RTOT - RDRp = 12.7 ꢀ → 10 ꢀ
40 Ω RTOT - RDRp = 32.5 ꢀ → 33 ꢀ
→420 ns
→202 ns
IRG4PH30K(D)
IGBT
10 nC 20 nC
Table 1: tsw Driven RGon Sizing
Qge
Qgc
Vge* CRESoff
Rtot
dVout/dt
RGon → std commercial value
IRGP30B120K(D)
IRG4PH30K(D)
19 nC
10 nc
82 nC
20 nC
9 V
9 V
85 pF
14 pF
14 Ω
85 Ω
RTOT - RDRp = 6.5 ꢀ → 8.2 ꢀ
RTOT - RDRp = 78 ꢀ → 82 ꢀ
→4.5 V/ns
→5 V/ns
Table 2: dVOUT/dt Driven RGon Sizing
IGBT
IRGP30B120K(D)
IRG4PH30K(D)
Vth(min)
4
CRESoff
85 pF
14 pF
RGoff
RGoff ≤ 4 ꢀ
3
RGoff ≤ 35 ꢀ
Table 3: RGoff Sizing
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19
IR211(4,41)/IR221(4,41)SSPbF
3 PCB Layout Tips
3.5 Routing and Placement Example
Figure 24 shows one of the possible layout solutions
using a 3 layer PCB. This example takes into account
all the previous considerations. Placement and routing
for supply capacitors and gate resistances in the high
and low voltage side minimize the supply path loop and
the gate drive loop. The bootstrap diode is placed under
the device to have the cathode as close as possible to
the bootstrap capacitor and the anode far from high
3.1 Distance from High to Low Voltage
The IR2x14/1 pin out maximizes the distance between
floating (from DC- to DC+) and low voltage pins. It’s
strongly recommended to place components tied to
floating voltage on the high voltage side of device (VB,
VS side) while the other components are placed on the
opposite side.
voltage and close to VCC
.
3.2 Ground Plane
To minimize noise coupling, the ground plane must not
be placed under or near the high voltage floating side.
R2
D2
D3
DC+
VGH
R3
3.3 Gate Drive Loops
R4
Current loops behave like antennas and are able to
receive and transmit EM noise. In order to reduce the
EM coupling and improve the power switch turn on/off
performances, gate drive loops must be reduced as
much as possible. Figure 23 shows the high and low
side gate loops.
IR2214
Phase
R5
VGL
R6
R7
C2
a) Top Layer
Moreover, current can be injected inside the gate drive
loop via the IGBT collector-to-gate parasitic
capacitance. The parasitic auto-inductance of the gate
loop contributes to developing a voltage across the
gate-emitter, increasing the possibility of self turn-on.
For this reason, it is strongly recommended to place the
three gate resistances close together and to minimize
the loop area (see Fig. 23).
C1
VEH
VCC
R1
VEL
IGC
VB/ VCC
gate
b) Bottom Layer
resistance
CGC
H/LOP
H/LON
SSDH/L
Gate Drive
VGE
Loop
VS/COM
Figure 23: gate drive loop
c) Ground Plane
Figure 24: layout example
3.4 Supply Capacitors
The IR2x14x output stages are able to quickly turn on
an IGBT, with up to 2 A of output current. The supply
capacitors must be placed as close as possible to the
device pins (VCC and VSS for the ground tied supply, VB
and VS for the floating supply) in order to minimize
parasitic inductance/resistance.
Information below refers to Fig. 24:
Bootstrap section: R1, C1, D1
High side gate: R2, R3, R4
High side Desat: D2
Low side supply: C2
Low side gate: R5, R6, R7
Low side Desat: D3
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20
IR211(4,41)/IR221(4,41)SSPbF
Figures 25-83 provide information on the experimental performance of the IR211(4,41)/ IR221(4,41)SSPbF HVIC. The
line plotted in each figure is generated from actual lab data. A large number of individual samples from multiple wafer lots
were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The
line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been
connected together to illustrate the understood trend. The individual data points on the curve were determined by
calculating the averaged experimental value of the parameter (for a given temperature).
10.30
10.25
10.20
10.15
10.10
10.05
10.00
9.95
9.60
9.55
9.50
9.45
9.40
9.35
9.30
9.25
9.20
9.15
Exp.
Exp.
-50
-25
0
25
Temperature (oC)
Figure 25. VCCUV+ Threshold vs. Temperature
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Figure 26. VCCUV- Threshold vs. Temperature
9.70
9.65
9.60
9.55
9.50
9.45
9.40
9.35
9.30
9.25
10.45
10.40
10.35
10.30
10.25
10.20
10.15
10.10
10.05
10.00
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 28. VBSUV- Threshold vs. Temperature
Figure 27. VBSUV+ Threshold vs. Temperature
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
600
500
400
300
200
100
0
Exp.
Exp.
-50
-25
0
25
Temperature (oC)
Figure 30. VCC Quiescent Current vs. Temperature
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Figure 29. VBS Quiescent Current vs. Temperature
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21
IR211(4,41)/IR221(4,41)SSPbF
2.70
2.30
1.90
1.50
1.10
2.10
1.80
1.50
1.20
0.90
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
Temperature (oC)
Figure 32. VIL Logic Input Voltage vs. Temperature
50
75
100
125
Temperature (oC)
Figure 31. VIH Logic Input Voltage vs. Temperature
2.20
0.60
Exp.
0.50
1.90
1.60
1.30
1.00
0.40
0.30
0.20
0.10
0.00
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 34. LIN Logic "1" Input Voltage vs. Temperature
Figure 33. VIHSS HIN Logic Input Hysteresis vs.
Temperature
1.90
0.90
0.70
1.60
1.30
1.00
0.70
Exp.
0.50
Exp.
0.30
0.10
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 35. LIN Logic "0" Input Voltage vs. Temperature
Figure 36. VIHSS LIN Logic Input Hysteresis vs.
Temperature
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22
IR211(4,41)/IR221(4,41)SSPbF
2.30
2.00
1.70
1.40
1.10
1.70
1.40
1.10
0.80
Exp.
Exp.
-50
-25
0
25
50
75
100
125
125
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 37. VIH FLTCLR Logic Input Voltage vs.
Temperature
Figure 38. VIL FLTCLR Logic Input Voltage vs.
Temperature
2.10
0.60
Exp.
1.70
1.30
0.90
0.50
0.50
0.40
0.30
0.20
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
Temperature (oC)
Temperature (oC)
Figure 40. VIH SD Logic Input Voltage vs. Temperature
Figure 39. VIHSS FLTCLR Logic Input Hysteresis vs.
Temperature
0.60
2.10
0.50
1.70
1.30
0.90
0.50
Exp.
0.40
0.30
0.20
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
Temperature (oC)
Temperature (oC)
Figure 42. VIHSS SD Logic Input Hysteresis vs. Temperature
Figure 41. VIL SD Logic Input Voltage vs. Temperature
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23
IR211(4,41)/IR221(4,41)SSPbF
2.40
2.00
1.60
1.20
0.80
2.40
2.00
1.60
1.20
0.80
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 43. VIH SYFLT Logic Input Voltage vs. Temperature
Figure 44. VIL SYFLT Logic Input Voltage vs. Temperature
60
50
40
0.60
0.50
Exp.
0.40
0.30
0.20
Exp.
30
20
-50
-25
0
25
50
75
100
125
-50
-25
0
25
Temperature (oC)
Figure 46. VOL LO vs. Temperature
50
75
100
125
Temperature (oC)
Figure 45. VIHSS SYFLT Logic Input Hysteresis vs.
Temperature
65
55
45
35
25
900
725
550
375
200
Exp.
Exp.
-50
-25
0
25
Temperature (oC)
Figure 48. VOL HO vs. Temperature
50
75
100
125
-50
-25
0
25
Temperature (oC)
Figure 47. VOH LO vs. Temperature
50
75
100
125
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24
IR211(4,41)/IR221(4,41)SSPbF
9
8
7
6
5
900
725
550
375
200
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
Temperature (oC)
Figure 49. VOH HO vs. Temperature
50
75
100
125
Temperature (oC)
Figure 50. VDSH+ DSH Input Voltage vs. Temperature
8.30
9
7.60
9
8
8
7
Exp.
6.90
6.20
5.50
Exp.
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 52. VDSH- DSH Input Voltage vs. Temperature
Figure 51. VDSL+ DSL Input Voltage vs. Temperature
90
75
60
8.00
7.50
Exp.
7.00
45
6.50
6.00
Exp.
30
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 54. FAULT/SD Open Drain Resistance vs.
Temperature
Figure 53. VDSL- DSL Input Voltage vs. Temperature
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25
IR211(4,41)/IR221(4,41)SSPbF
490
430
370
310
250
130
105
80
Exp.
55
Exp.
30
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 55. SY_FLT Open Drain Resistance vs. Temperature
Figure 56. DTL Off Deadtime vs. Temperature
780
660
540
420
300
490
430
Exp.
370
Exp.
310
250
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 58. TonH Propagation Delay vs. Temperature
Figure 57. DTH Off Deadtime vs. Temperature
780
660
540
420
300
32
28
24
20
Exp.
Exp.
16
12
-50
-25
0
25
Temperature (oC)
Figure 60. TrH Turn On Rise Time vs. Temperature
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Figure 59. ToffH Propagation Delay vs. Temperature
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26
IR211(4,41)/IR221(4,41)SSPbF
780
18
15
12
9
660
540
420
300
Exp.
Exp.
6
-50
-25
0
25
50
75
100
125
-50
-25
0
25
Temperature (oC)
Figure 61. TfH Turn Off Fall Time vs. Temperature
50
75
100
125
Temperature (oC)
Figure 62. TonL Propagation Delay vs. Temperature
780
40
33
660
540
420
300
26
Exp.
Exp.
19
12
-50
-25
0
25
Temperature (oC)
Figure 63. ToffL Propagation Delay vs. Temperature
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Figure 64. TrL Turn On Rise Time vs. Temperature
6
5
4
3
2
20
16
12
8
Exp.
Exp.
4
-50
-25
0
25
50
75
100
125
-50
-25
0
25
Temperature (oC)
Figure 66. tDSAT1 vs. Temperature
50
75
100
125
Temperature (oC)
Figure 65. TfL Turn Off Fall Time vs. Temperature
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27
IR211(4,41)/IR221(4,41)SSPbF
6
5
4
3
2
3
3
2
2
1
Exp.
Exp.
-50
-25
0
25
Temperature (oC)
Figure 67. tDSAT2 vs. Temperature
50
75
100
100
100
125
125
125
-50
-25
0
25
Temperature (oC)
Figure 68. tDSAT3 vs. Temperature
50
75
100
125
17
14
11
8
4.50
3.50
2.50
1.50
0.50
Exp.
Exp.
5
-50
-25
0
25
Temperature (oC)
Figure 69. tDSAT4 vs. Temperature
50
75
-50
-25
0
25
Temperature (oC)
Figure 70. tSSH vs. Temperature
50
75
100
125
1.80
1.45
1.10
0.75
0.40
17
14
11
8
Exp.
Exp.
5
-50
-25
0
25
Temperature (oC)
Figure 72. IO2+H SC Pulsed Current vs. Temperature
50
75
100
125
-50
-25
0
25
Temperature (oC)
Figure 71. tSSL vs. Temperature
50
75
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28
IR211(4,41)/IR221(4,41)SSPbF
1.80
1.45
1.10
0.75
0.40
3.25
2.80
2.35
1.90
1.45
Exp.
Exp.
-50
-25
0
25
Temperature (oC)
Figure 73. IO2+L SCPulsed Current vs. Temperature
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Figure 74. IO-H SC Pulsed Current vs. Temperature
3.50
900
3.05
2.60
2.15
1.70
1.25
700
Exp.
Exp.
500
300
100
-50
-25
0
25
50
75
100
125
-50
-25
0
25
Temperature (oC)
Figure 76. tON1H vs. Temperature
50
75
100
125
Temperature (oC)
Figure 75. IO-L SC Pulsed Current vs. Temperature
3.00
500
400
2.50
2.00
1.50
1.00
Exp.
300
Exp.
200
100
-50
-25
0
25
Temperature (oC)
Figure 78. IO1+H SC Pulsed Current vs. Temperature
50
75
100
125
-50
-25
0
25
Temperature (oC)
Figure 77. tON1L vs. Temperature
50
75
100
125
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29
IR211(4,41)/IR221(4,41)SSPbF
900
700
500
300
100
4
3
2
1
0
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 79. IO1+L SC Pulsed Current vs. Temperature
Figure 80. IHIN+ Logic "1" Input Bias Current vs.
Temperature
0.02
900
Exp.
-0.03
700
500
300
100
-0.08
-0.13
-0.18
-0.23
-0.28
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 81. IHIN- Logic "0" Input Bias Currentvs.
Temperature
Figure 82. ILIN+ Logic "1" Input Bias Current vs.
Temperature
0.02
-0.03
Exp.
-0.08
-0.13
-0.18
-0.23
-0.28
-50
-25
0
25
50
75
100
125
Temperature (oC)
Figure 83. ILIN- Logic "0" Input Bias Current vs.
Temperature
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30
IR211(4,41)/IR221(4,41)SSPbF
Case Outline
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31
IR211(4,41)/IR221(4,41)SSPbF
LOADED TAPE FEED DIRECTION
B
A
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 24SSOP:2000 units per reel
Metric
Imperial
Code
A
Min
11.90
3.90
15.70
7.40
8.30
8.50
1.50
1.50
Max
12.10
4.10
16.30
7.60
8.50
8.70
n/a
Min
Max
0.476
0.161
0.641
0.299
0.334
0.342
n/a
0.468
0.153
0.618
0.291
0.326
0.334
0.059
0.059
B
C
D
E
F
G
H
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 24SSOP
Metric
Imperial
Max
Code
A
Min
329.60
20.95
12.80
1.95
Max
330.25
21.45
13.20
2.45
102.00
22.40
21.10
18.40
Min
12.976
0.824
0.503
0.767
3.858
n/a
13.001
0.844
0.519
0.096
4.015
0.881
0.830
0.724
B
C
D
E
98.00
n/a
18.50
16.40
F
G
0.728
0.645
H
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32
IR211(4,41)/IR221(4,41)SSPbF
LEAD-FREE PART MARKING INFORMATION
Part number
IRSxxxxx
YWW?
Date code
IR logo
?XXXX
Pin 1
Identifier
Lot Code
(Prod mode – 4 digit SPN code)
?
P
MARKING CODE
Lead Free Released
Non-Lead Free
Relased
Assembly site code
Per SCOP 200-002
ORDER INFORMATION
24-Lead SSOP IR2114SSPbF
24-Lead SSOP IR21141SSPbF
24-Lead SSOP IR2214SSPbF
24-Lead SSOP IR22141SSPbF
24-Lead SSOP Tape & Reel IR2114SSPbF
24-Lead SSOP Tape & Reel IR21141SSPbF
24-Lead SSOP Tape & Reel IR2214SSPbF
24-Lead SSOP Tape & Reel IR22141SSPbF
WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 90245 Tel: (310) 252-7105
This part has been qualified per industrial level
http://www.irf.com Data and specifications subject to change without notice. 5/18/2006
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33
相关型号：
IR2233SPBF
Floating channel designed for bootstrap operation Fully operational to 600V or1200V Tolerant to negative transient voltage dV/dt immune
INFINEON
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