IR3084U_技术文档

IR3084U

Data Sheet No. PD94719

XPHASE^TMVR10, VR11 & OPTERON/ATHLON64 CONTROL IC

DESCRIPTION

The IR3084U Control IC combined with an IR XPhase^TMPhase IC provides a full featured and flexible

way to implement a complete VR10, VR11, Opteron, or Athlon64 power solution. The “Control” IC

provides overall system control and interfaces with any number of “Phase” ICs which each drive and

monitor a single phase of a multiphase converter. The XPhase^TMarchitecture results in a power supply

that is smaller, less expensive, and easier to design while providing higher efficiency than conventional

approaches.

The IR3084U is based on the IR3084 VR10 Control IC, but incorporates the following modifications;

•

Supports VR11 7-bit VID, VR10 7-bit extended VID, and Opteron/Athlon64 5-bit VID codes

Supports both VR11 and legacy Opteron/Athlon64 start-up sequences

VID Select pin sets the DAC to VR10, VR11, or Opteron/Athlon64

INTL_MD output pin indicates which DAC is selected – Intel or AMD

VOSENS− float detection protects the CPU in the event that the VOSENS− trace is broken

Enable Input Thresholds set by VID Select pin to either VR10, VR11 or Opteron/Athlon64

VID Input Thresholds set by VID Select pin to either 0.6V (VR10/VR11) or 1.24V (AMD)

No-Load Setpoint Current changes polarity based on VID Select to accommodate VR10, VR11

(negative offset from DAC) or Opteron/Athlon64 (positive offset from DAC).

FEATURES

•

1 to X phase operation with matching Phase IC

7-bit VR 10/11 compatible VID with 0.5% overall system set point accuracy

5-bit Opteron/Athlon64 compatible VID with 1% overall system set point accuracy

Programmable Dynamic VID Slew Rate

+/-300mV Differential Remote Sense

Programmable VID Offset Voltage at the Error Amplifier’s Non-Inverting Input allows Zero Offset

Programmable 150kHz to 1MHz oscillator

Programmable VID Offset and Load Line output impedance

Programmable Hiccup Over-Current Protection with Delay to prevent false triggering

Simplified VR Ready output provides indication of proper operation and avoids false triggering

Operates from 12V input with 9.9V Under-Voltage Lockout

6.8V/6mA Bias Regulator provides System Reference Voltage

Phase IC Gate Driver Bias Regulator / VRHOT Comparator

Reduced Over-Current Detect Delay eliminates and external resistor in typical applications

Small thermally enhanced 28L MLPQ package

Page 1 of 47

9/14/2005

IR3084U

TYPICAL APPLICATION CIRCUIT

CCP1

100pF

EA

+5.0V

RT2

R117

4.7K, B=4450 1.21K

RCP

2.49K

CCP

56nF

R1331

1

Q4

CJD200

VREG_12V_FILTERED

VGDRIVE

R137

2K

RFB1

162

CFB

12nF

C204

0.1uF

C135

1uF

18

EAOUT

U5

VCC_SENSE

VSS_SENSE

17

27

15

19

20

VR_RDY

ISHARE

RMP

FB

VRRDY

IIN

RFB

348

RMPOUT

VBIAS

C1009

1nF

RDRP1

750

VBIAS

RDRP

750

C134

0.1uF

C89

100pF

IR3084UMTR

Q5

24

23

25

REGDRV

16

VDRP

REGFB

REGSET

28

9

8

7

6

5

4

3

1

OUTEN

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID_SEL

ENABLE

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VIDSEL

2

RVGDRV

97.6K

CVGDRV

10nF

INTL_MD

Q6

RVSETPT1

124

14

13

12

11

VSETPT

OCSET

VDAC

VREG_12V_FILTERED

RVSETPT

124

21

26

VCC

R30

10

C130

0.1uF

ROCSET

12.7K

SS/DEL

VDAC

CSS/DEL

0.1uF

RVDAC

3.5

CVDAC

33nF

VOSNS-- LGND ROSC

10 22

ROSC

30.1K

Page 2 of 47

9/14/2005

IR3084U

ORDERING INFORAMATION

DEVICE

ORDER QUANTITY

3000 Tape and Reel

100 Piece Strip

IR3084UMTRPBF

IR3084UMPBF

ABSOLUTE MAXIMUM RATINGS

Operating Junction Temperature……………..0 to 150^oC

Storage Temperature Range………………….−65^oC to 150^oC

ESD Rating………………………………………HBM Class 1B JEDEC standard

Moisture Sensitivity Level………………………JEDEC Level 3 @ 260 ^oC

PIN #

1

PIN NAME

VIDSEL

INTL_MD

VID6−VID0

VOSNS-

ROSC

V_MAX

20V

0.5V

20V

10V

20V

n/a

V_MIN

-0.3V

-0.5V

-0.3V

n/a

I_SOURCE

1mA

10mA

1mA

5mA

1mA

20mA

5mA

50mA

1mA

50mA

1mA

10mA

1mA

I_SINK

1mA

10mA

1mA

5mA

1mA

20mA

5mA

10mA

50mA

1mA

50mA

1mA

20mA

1mA

2

3-9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

VDAC

OCSET

VSETPT

IIN

VDRP

FB

EAOUT

RMPOUT

VBIAS

VCC

LGND

REGFB

REGDRV

REGSET

SS/DEL

VRRDY

ENABLE

20V

-0.3V

Page 3 of 47

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IR3084U

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over: 9.5V ≤ V_CC≤ 16V, −0.3V ≤ VOSNS- ≤ 0.3V,

0 ^oC ≤ T_J≤ 100 ^oC, ROSC = 24kΩ, CSS/DEL = 0.1μF ±10%

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

VDAC REFERENCE

VR10/VR11 System Set-Point

Accuracy (Deviation from

Tables 1 & 2 per test circuit in

Figure 1 which emulates in-VR

operation)

VID ≥ 1V, 10kΩ≤ROSC≤100kΩ,

25 ^oC ≤ T_J≤ 100 ^oC

−0.5

0.5

%

0.8V ≤ VID < 1V, 10kΩ≤ROSC≤100kΩ,

25 ^oC ≤ T_J≤ 100 ^oC

−5

−1

+5

1

mV

%

Opteron/Athlon64 System Set-

Point Accuracy

25 ^oC ≤ T_J≤ 100 ^oC

Source Current

Sink Current

Includes OCSET and VSETPT currents

104

92

113

100

122

108

μA

VR10/VR11 VIDx Input

Threshold

500

600

700

mV

V

Opteron/Athlon64 VIDx Input

Threshold

1.04

1.24

1.44

VIDx Input Bias Current

VIDx 11111x Blanking Delay

VIDSEL Pull up Voltage

VIDSEL Pull up Resistor

0V < VIDx < VCC

−5

0

5

2.1

2.85

9

μA

μs

V

Measure Time till VRRDY drives low

VIDSEL Floating

0.5

1.3

2.4

4.5

1.95

2.25

KΩ

VIDSEL VR10/Opteron

Threshold

VIDSEL “LOW”

0.5

0.9

1.8

0.6

1.3

0.7

1.7

2.1

V

VIDSEL Opteron Voltage

6.49K from VIDSEL to GND

VIDSEL Opteron/VR11

Threshold

1.95

ERROR AMPLIFIER

Measure V(FB) – V(VSETPT) per test

circuit in Figure 1. Applies to all VID

codes. Note 2.

Input Offset Voltage

−5

0.0

5

mV

FB Bias Current

VSETPT Bias Current

DC Gain

−1

48.5

−54

90

−0.1

51

0.5

53.5

−39

110

μA

VR10/VR11 Mode

Opteron/Athlon64 Mode

Note 1

−47

100

10

dB

Gain Bandwidth Product

Corner Frequency

Slew Rate

Note 1

6

MHz

Hz

45 deg Phase Shift, Note 1

Note 1

200

3.2

400

5

1.4

−1.2

0.5

V/μs

mA

Source Current

Sink Current

−0.7

1.1

−0.35

1.7

VBIAS–VEAOUT (referenced to

VBIAS)

Max Voltage

Min Voltage

150

30

350

125

600

200

mV

Normal operation or Fault mode

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9/14/2005

IR3084U

PARAMETER

CURRENT SENSE INPUT

IIN BIAS CURRENT

TEST CONDITION

MIN

TYP

MAX

UNIT

−2.0

−0.2

1.0

V(SS/DEL) > 0.85V, V(EAOUT) > 0.5V

V(SS/DEL) < 0.35V

µA

IIN Preconditioning Pull-Down

Resistance

5.6

12.5

19.4

KΩ

IIN Preconditioning RESET

Threshold

V(EAOUT)

V(SS/DEL)

0.20

0.35

0.60

0.50

0.85

V

IIN Preconditioning SET

Threshold

VDRP BUFFER AMPLIFIER

Input Offset Voltage

Source Current

Sink Current

V(VDRP) – V(IIN), 0.5V < V(IIN) < 5V

0.5V < V(IIN) < 5V

Note 1

−10

−9.0

0.2

1

−2

−6.8

0.85

6

mV

mA

−4.0

4.1

mA

Bandwidth (-3dB)

Slew Rate

MHz

V/μs

Note 1

5

10

VBIAS REGULATOR

Output Voltage

Current Limit

−5mA < I(VBIAS) < 0mA

6.6

6.9

7.2

V

−35

−20

−6

mA

OVER-CURRENT COMPARATOR

Input Offset Voltage

OCSET Bias Current

1V < V(OCSET) < 5V

−10

0

10

mV

−53.5

−51

−48.5

μA

SOFT START AND DELAY

Start Delay (TD1)

RDRP = ∞

1.2

0.8

0.2

1.8

1.0

2.6

2.8

2.5

ms

Soft Start Time (TD2)

VID Sample Delay (TD3)

RDRP = ∞, Time to reach 1.1V

VR10/VR11 mode only

DVID Slew Time & VRRDY

Delay (TD4+TD5)

VR10/VR11 mode only

0.5

1.3

2.2

ms

Opteron/Athlon64 mode. Measured from

Vcore=1.1V to when VRRDY transitions HI.

PowerGood Delay

0.7

150

0.85

2.3

250

1.3

4.7

350

1.5

ms

us

V

OC Delay Time

SS/DEL to FB Input Offset

Voltage

With FB = 0V, adjust V(SS/DEL) until

EAOUT drives high

SS/DEL Charge Current

40

4

70

100

9

μA

SS/DEL Discharge Current

6.5

Charge/Discharge Current

Ratio

9.5

11.2

12.5

μA/μA

OC Discharge Current

Charge Voltage

Note 1

20

40

60

μA

V

3.6

3.85

4.1

OC/VRRDY Delay Comparator Relative to Charge Voltage, SS/DEL

Threshold rising

OC/VRRDY Delay Comparator Relative to Charge Voltage, SS/DEL

80

mV

100

20

mV

V

Threshold

falling

Delay Comparator Hysteresis

Note 1

VID Sample Delay

Comparator Threshold

VR10/VR11 mode only

3.10

SS/DEL Discharge

Comparator Threshold

215

mV

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IR3084U

PARAMETER

VRRDY OUTPUT

TEST CONDITION

MIN

TYP

MAX

UNIT

Output Voltage

I(VRRDY) = 4mA

150

0

300

10

mV

Leakage Current

V(VRRDY) = 5.5V

μA

ENABLE INPUT

VR10/11 Threshold Voltage

VR10/11 Threshold Hysteresis

ENABLE rising

ENABLE falling

800

700

70

850

750

100

900

800

130

mV

Opteron/Athlon64 Threshold

Voltage

ENABLE rising

ENABLE falling

1.11

1.06

1.23

1.17

1.35

1.29

V

Opteron/Athlon64 Threshold

Voltage

Opteron/Athlon64 Threshold

Hysteresis

35

50

75

60

85

mV

KΩ

ns

Input Resistance

100

250

200

400

Noise Pulse < 250ns will not register

an ENABLE state change. Note 1

Blanking Time

OSCILLATOR

Switching Frequency

ROSC = 24KΩ

450

70

500

71

550

74

kHz

%

Peak Voltage (4.8V typical,

measured as % of VBIAS)

Valley Voltage (0.9V typical,

measured as % of VBIAS)

10

13

15

%

INTL_MD OUTPUT

Source Current

Sink Current

Max Voltage

Min Voltage

V(INTL_MD)=2V, VR10 or VR11 mode

V(INTL_MD)=2V, Opteron mode

Pin Floating, V(VBIAS)−V(INTL_MD)

Pin Floating, LGND referenced

100

250

50

200

750

170

400

300

1500

350

µA

mV

900

VOSNS− FLOAT DETECT

V(VOSNS−) with respect to V(LGND),

Verify V(VRRDY) and V(EAOUT) are

low.

Detect Voltage

1.2

2

2.6

V

V(VOSNS-) 0V to 2.6V step, measure

time when V(VRRDY) falls. Note 1

Detect Delay

200

350

600

ns

DRIVER BIAS REGULATOR

REGSET Bias Current

1.5V < V(REGSET) < VCC – 1.5V

−112

−12

−99

−85

μA

1.5V < V(REGSET) < VCC – 1.5V,

100μA < I(REGDRV) < 10mA

Input Offset Voltage

0

12

mV

V(REGDRV) = 0V,

1.5V < V(REGSET) < VCC – 1.5V,

Note 1

Short Circuit Current

Dropout Voltage

10

20

50

mA

V

I(REGDRV) = 10mA, Note 1

0.4

0.87

1.33

Page 6 of 47

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IR3084U

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

VCC UNDER-VOLTAGE LOCKOUT

Start Threshold

Stop Threshold

9.3

8.5

550

9.9

9.1

10.3

9.5

V

Hysteresis

Start – Stop

800

1000

mV

GENERAL

VCC Supply Current

9

14

18

mA

−0.3V < VOSNS− < 0.3V,

All VID Codes

VOSNS− Current

−1.45

−1.1

−0.75

Note 1: Guaranteed by design, but not tested in production

Note 2: VDAC Output is trimmed to compensate for Error Amp input offsets errors

+

IR3084U

EAOUT

-

ERROR

AMP

200 OHM

FB

200 OHM

VDAC

BUFFER

AMP

-

+

VSETPT

OCSET

VDAC

ISOURCE

ISINK

SYSTEM

SET POINT

VOLTAGE

INTEL: +IOFFSET

AMD: --IOFFSET

IOCSET

IROSC

RVDAC

CVDAC

+

-

"FAST"

VDAC

ROSC

BUFFER

AMP

CURRENT

SOURCE

GENERATOR

+

-

ROSC

+

-

ROSC

1.2V

VOSNS-

Figure 1 – System Set Point Test Circuit

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IR3084U

PIN DESCRIPTIONS

PIN# PIN SYMBOL

DESCRIPTION

Selects the DAC table and the type of Soft Start. There are 3 possible modes of

operation: (1) GND selects VR10 DAC and VR11 type startup, (2) FLOAT (2.4V)

selects VR11 DAC and VR11 type startup, (3) 6.49K to GND (1.3V) selects

Opteron/Athlon64 DAC and legacy type startup. Additional details are provided in

the Theory of Operation section.

1

VIDSEL

Output that indicates if the controller is in Intel Mode or AMD Mode. This pin will be

Low when in AMD mode and High when in Intel mode.

2

INTL_MD

Inputs to the D to A Converter. Must be connected to an external pull up resistor.

Negative Remote Sense Input. Connect to ground at the Load.

3-9

10

VID6−VID0

VOSNS−

Connect a resistor from this pin to VOSNS− to program the oscillator’s frequency,

OCSET, VSETPT, REGSET, and VDAC bias currents.

11

ROSC

Regulated output voltage programmed by the VID inputs. Connect an external RC

network to from this pin to VOSNS− to program the Dynamic VID slew rate and

provide compensation for the internal Buffer Amplifier.

12

VDAC

Programs the hiccup over-current threshold through an external resistor tied to

VDAC and an internal current source. Over-current protection can be disabled by

connecting a resistor from this pin to VDAC to program the threshold higher than the

possible signal into the IIN pin from the Phase ICs but no greater than 5V (do not

float this pin as improper operation will occur).

13

14

OCSET

Error Amp non-inverting input. The converter’s output voltage can be decreased

(Intel) or increased (AMD) from the VDAC voltage with an external resistor

connected between VDAC and an internal current source. Current sensing and

PWM operation are referenced to this pin.

VSETPT

Current Sense input from the Phase IC(s). Prior to startup, when SS/DEL<0.6V, this

pin is pulled low by a 12.5K resistor to disable current balancing in the Phase ICs.

When SS/DEL>0.6V and EAOUT>0.35V, this pin is released and current balancing

is enabled. If AVP or over-current protection is not required, connect this pin to

VDAC. To ensure proper do not float this pin.

15

16

IIN

Buffered IIN signal. Connect an external resistor from this pin to the FB pin to set the

converter’s output impedance.

VDRP

Inverting input to the Error Amplifier.

17

18

19

FB

Output of the Error Amplifier. When Low, provides UVL function to the Phase ICs.

Oscillator Output voltage. Used by the Phase ICs to program Phase Delay.

EAOUT

RMPOUT

6.9V/6mA Regulated output used as a system reference voltage for internal circuitry

and for phase timing at the Phase ICs.

20

VBIAS

Power Input for the internal circuitry.

21

22

VCC

Local Ground for internal circuitry and IC substrate connection

LGND

Inverting input of the Bias Regulator Error Amp. Connect this pin to the collector of

the Phase IC Gate Driver Bias transistor.

23

24

REGFB

Output of the Bias Regulator Error Amp.

REGDRV

Non-inverting input of the Bias Regulator Error Amp. The output voltage of the

Phase IC Gate Driver Bias Regulator is set by an internal current source supplying

an external resistor connected from this pin to ground.

25

REGSET

Controls converter start-up and over-current timing. Connect an external capacitor

from this pin to LGND to program the soft start and delay times.

26

27

28

SS/DEL

VRRDY

ENABLE

Open Collector output that drives low during start-up and when any external fault

occurs. Connect external pull-up resistor.

Enable Input. A logic low applied to this pin puts the IC into Fault mode. This pin

has a 100K pull-down resistor to GND.

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IR3084U

SYSTEM THEORY OF OPERATION

XPhase^TMArchitecture

The XPhase^TMarchitecture is designed for multiphase interleaved buck converters which are used in

applications requiring small size, design flexibility, low voltage, high current and fast transient response. The

architecture can be used in any multiphase converter ranging from 1 to 16 or more phases where flexibility

facilitates the design trade-off of multiphase converters. The scalable architecture can be applied to other

applications which require high current or multiple output voltages.

As shown in Figure 2, the XPhase^TMarchitecture consists of a Control IC and a scalable array of phase

converters each using a single Phase IC. The Control IC communicates with the Phase ICs through a 5-wire

analog bus, i.e. bias voltage, phase timing, average current, error amplifier output, and VID voltage. The Control

IC incorporates all the system functions, i.e. VID, PWM ramp oscillator, error amplifier, bias voltage, and fault

protections etc. The Phase IC implements the functions required by the converter of each phase, i.e. the gate

drivers, PWM comparator and latch, over-voltage protection, and current sensing and sharing.

There is no unused or redundant silicon with the XPhase^TMarchitecture compared to others such as a 4 phase

controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus

eliminates the need for point-to-point wiring between the Control IC and each Phase. The critical gate drive and

current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the

parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal.

VR READY

PHASE FAULT

VR HOT

VR FAN

12V

ENABLE

VIDSEL

PHASE FAULT

VID6

VID5

VID4

VID3

VID2

VID1

VID0

CIN

IR3084

CONTROL

IC

>> BIAS VOLTAGE

>> PHASE TIMING

<< CURRENT SENSE

>> PWM CONTROL

>> VID VOLTAGE

VOUT SENSE+

VOUT+

CURRENT SHARE

IR3086

PHASE

IC

COUT

VOUT-

CCS RCS

VOUT SENSE-

PHASE FAULT

CURRENT SHARE

IR3086

PHASE

IC

CCS RCS

ADDITIONAL PHASES

CONTROL BUS

INPUT/OUTPUT

Figure 2 – System Block Diagram

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IR3084U

PWM Control Method

The PWM block diagram of the XPhase^TMarchitecture is shown in Figure 3. Feed-forward voltage mode control

with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is

used for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to

program the slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp

slope will change with the input voltage and automatically compensate for changes in the input voltage. The input

voltage can change due to variations in the silver box output voltage or due to drops in the PCB related to

changes in load current.

VIN

CONTROL IC

PHASE IC

SYSTEM

REFERENCE

VOLTAGE

BIASIN

50%

PWM

LATCH

RAMP GENERATOR

DUTY

CYCLE

VPEAK

RMPOUT

RAMPIN+

GATEH

GATEL

VOSNS+

VOUT

+

-

CLOCK

PULSE

S

PWM

COMPARATOR

GENERATOR

RESET

DOMINANT

RRAMP1

VVALLEY

RAMPIN-

EAIN

COUT

-

VBIAS

VOSNS-

VDAC

R

+

VDAC

GND

+

-

RRAMP2

VBIAS

REGULATOR

ENABLE

PWMRMP

+

RAMP

SLOPE

ADJUST

O% DUTY

CYCLE

COMPARATOR

-

RPWMRMP

VOSNS-

RAMP

DISCHARGE

CLAMP

VSETPT

EAOUT

RVSETPT

SCOMP

CPWMRMP

+

-

SHARE

CSCOMP

ADJUST

ERROR

AMP

X

0.91

ERROR

AMP

+

-

RVFB

RDRP

CURRENT

SENSE

AMP

ISHARE

DACIN

20mV

CSIN+

CSIN-

10K

+

FB

CCS RCS

-

X34

IOFFSET

IROSC

VDRP

AMP

+

VDRP

-

IIN

PHASE IC

SYSTEM

BIASIN

REFERENCE

VOLTAGE

PWM

LATCH

RAMPIN+

GATEH

GATEL

+

-

CLOCK

PULSE

GENERATOR

S

RRAMP1

PWM

COMPARATOR

RESET

DOMINANT

RAMPIN-

EAIN

-

R

+

RRAMP2

ENABLE

PWMRMP

+

RAMP

O% DUTY

CYCLE

COMPARATOR

SLOPE

ADJUST

-

RPWMRMP

RAMP

DISCHARGE

CLAMP

SCOMP

CPWMRMP

SHARE

CSCOMP

ADJUST

ERROR

AMP

X

0.91

+

-

CURRENT

SENSE

AMP

ISHARE

DACIN

20mV

CSIN+

CSIN-

10K

+

CCS RCS

-

X34

Figure 3 – IR3084U PWM Block Diagram

Frequency and Phase Timing Control

The oscillator is located in the Control IC and its frequency is programmable from 150kHz to 1MHZ by an external

resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of

approximately 5V and 1V. This signal is used to program both the switching frequency and phase timing of the

Phase ICs. The Phase IC is programmed by resistor divider RRAMP1 and RRAMP2 connected between the

VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the

oscillator waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the

PWM cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors.

Figure 4 shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be

used for synchronization by swapping the RAMP + and – pins.

Page 10 of 47

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IR3084U

50% RAMP

DUTY CYCLE

SLOPE

=

80mV

/

%

DC

ns

VPEAK (5.0V)

1.6mV

8.0mV

/

@

200kHz

1MHz

VPHASE4&5 (4.5V)

VPHASE3&6 (3.5V)

VPHASE2&7 (2.5V)

VPHASE1&8 (1.5V)

VVALLEY (1.00V)

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

CLK8

Figure 4 – 8 Phase Oscillator Waveforms

PWM Operation

The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set, the

PWMRMP voltage begins to increase, the low side driver is turned off, and the high side driver is then turned on.

When the PWMRMP voltage exceeds the Error Amp’s output voltage the PWM latch is reset. This turns off the

high side driver, turns on the low side driver, and activates the Ramp Discharge Clamp. The clamp quickly

discharges the PWMRMP capacitor to the VDAC voltage of the Control IC until the next clock pulse.

The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in

response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step

increase with turn-on gated by the clock pulses. An Error Amp output voltage greater than the common mode

input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This

arrangement guarantees the Error Amp is always in control and can demand 0 to 100% duty cycle as required. It

also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of

most systems. The inductor current will increase much more rapidly than decrease in response to load transients.

This control method is designed to provide “single cycle transient response” where the inductor current changes

in response to load transients within a single switching cycle maximizing the effectiveness of the power train and

minimizing the output capacitor requirements. An additional advantage is that differences in ground or input

voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC.

Page 11 of 47

9/14/2005

IR3084U

Body Braking^TM

In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in

response to a load step decrease is;

T_SLEW= [L x (I_MAX- I_MIN)] / Vout

The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in

response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the

synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout +

V_{BODY DIODE}. The minimum time required to reduce the current in the inductor in response to a load transient

decrease is now;

T_SLEW= [L x (I_MAX- I_MIN)] / (Vout + V_{BODY DIODE}

)

Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be

increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished

through the “0% Duty Cycle Comparator” located in the Phase IC. If the Error Amp’s output voltage drops below

91% of the VDAC voltage this comparator turns off the low side gate driver.

Figure 5 depicts PWM operating waveforms under various conditions

PHASE IC

CLOCK

PULSE

EAIN

PWMRMP

VDAC

BODY BRAKING

THRESHOLD

GATEH

GATEL

STEADY-STATE

OPERATION

DUTY CYCLE INCREASE

DUE TO LOAD

INCREASE

DUTY CYCLE DECREASE

DUE TO VIN INCREASE

(FEED-FORWARD)

DUTY CYCLE DECREASE DUE TO LOAD

DECREASE (BODY BRAKING) OR FAULT

(VCC UV, VCCVID UV, OCP, VID=11111X)

STEADY-STATE

OPERATION

Figure 5 – PWM Operating Waveforms

Lossless Average Inductor Current Sensing

Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the

inductor and measuring the voltage across the capacitor. The equation of the sensing network is,

R_L+ sL

1+ sR_SC_S

1

v_C(s) = v_L(s)

= i_L(s)

1+ sR_SC_S

Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time

constant of the inductor which is the inductance L over the inductor DCR. If the two time constants match, the

voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense

resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of

inductor DC current, but affects the AC component of the inductor current.

Page 12 of 47

9/14/2005

IR3084U

The advantage of sensing the inductor current versus high side or low side sensing is that actual output current

being delivered to the load is obtained rather than peak or sampled information about the switch currents. The

output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in

series with the inductor, this is the only sense method that can support a single cycle transient response. Other

methods provide no information during either load increase (low side sensing) or load decrease (high side

sensing).

An additional problem associated with peak or valley current mode control for voltage positioning is that they

suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of

frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10%

larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense

amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all

additional sources of peak-to-average errors.

Current Sense Amplifier

A high speed differential current sense amplifier is located in the Phase IC, as shown in Figure 6. Its gain

decreases with increasing temperature and is nominally 34 at 25ºC and 29 at 125ºC (-1470 ppm/ºC). This

reduction of gain tends to compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the

Phase IC junction is hotter than the inductor these two effects tend to cancel such that no additional temperature

compensation of the load line is required.

The current sense amplifier can accept positive differential input up to 100mV and negative up to -20mV before

clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC

and other Phases through an on-chip 10KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the

phases are tied together and the voltage on the share bus represents the average inductor current through all the

inductors and is used by the Control IC for voltage positioning and current limit protection.

vL

L

RL

iL

Vo

Rs

Cs

vc

Co

CSA

CO

Figure 6 – Inductor Current Sensing and Current Sense Amplifier

Average Current Share Loop

Current sharing between phases of the converter is achieved by the average current share loop in each Phase

IC. The output of the current sense amplifier is compared with the share bus less a 20mV offset. If current in a

phase is smaller than the average current, the share adjust amplifier of the phase will activate a current source

that reduces the slope of its PWM ramp thereby increasing its duty cycle and output current. The crossover

frequency of the current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop

does not interact with the output voltage loop.

Page 13 of 47

9/14/2005

IR3084U

IR3084U THEORY OF OPERATION

Block Diagram

VRRDY

IIN

VCC UVLO

COMPARATOR

VCC

-

UVLO

VOSNS OPEN

DISABLE

+

S

R

+

OVER CURRENT

VOSNS FLOAT

DETECT

2.0V

9.9V

9.1V

-

0.6V

DISCHARGE

0.215V

12.5K

-

NO CPU

NO CPU LATCHED

+

COMPARATOR

S

+

-

ENABLE

COMPARATOR

FAULT

LATCH

250ns

BLANKING

-

0.35V

ENABLE

INTEL AMD

-

DELAY

COMPARATOR

-

+

R

+

-

+

S

IIN

VID

+

PRECONDITIONING

+

-

FAULT

LATCH

850mV 1.23V

750mV 1.17V

100k

LATCH

80mV

VCHG

3.85V

OC

VDRP

AMP

R

-

+

100mV

DISCHARGE

CURRENT

40uA

ON

-

+

-

OC

COMPARATOR

OCSET

ON

LGND

S

R

SS/DEL

DISCHARGE

IHICCUP

DISCHARGE

6.5uA

VID SAMPLE

DELAY COMPARATOR

START

LATCH

OFF

ICHG

70uA

-

3.1V

SS/DEL

+

1.3us

BLANKING

IROSC

DISABLE

NO_CPU

1.3V

+

-

EAOUT

FB

DIGITAL TO

IROSC

VID INPUT

COMPARATORS

VID6

VID5

VID4

VID3

VID2

VID1

VID0

-

+

ANALOG

IROSC

ERROR

AMP

+

-

CONVERTER

(1 OF

9

IROSC

INTL_MD

SHOWN)

+

-

SOFTSTART

CLAMP

-

+

IROSC

VSETPT

VDAC

"FAST"

+

INTEL: IOFFSET

AMD: -IOFFSET

IOCSET

IROSC

VDAC

+

-

INTEL: 0.6V

AMD: 1.24V

+

-

+

IROSC

ISOURCE

ISINK

-

IROSC

0.6V

1.95V

2.4V

INTEL/AMD

-

1.1V

VDAC

BUFFER

AMP

4.5K

VID = 1.1V BOOT

1.2V

VIDSEL

VOSNS-

VBIAS

INTL_MD

-

+

VBIAS

REGULATOR

VBIAS

IROSC

6.9V

50%

DUTY

CYCLE

RAMP GENERATOR

BIAS

REGULATOR

ERROR AMP

4.8V

0.9V

+

-

REGDRV

REGFB

ROSC

BUFFER

AMP

RMPOUT

ROSC

CURRENT

SOURCE

GENERATOR

+

-

IROSC

IREGSET

VCC

REGSET

Figure 7 – IR3084U Block Diagram

VID Control

A 7-bit VID voltage compatible with VR10 (see Table 1) and VR11 (see Table 2) and Opteron/Athlon64 (see

Table 3) is available at the VDAC pin. The VIDSEL pin configures the DAC for VR10 if grounded, VR11 if

floating, and Opteron/Athlon64 if connected to GND via a 6.4K resistor. The VIDSEL pin is internally pulled-up to

2.4V through a 4.5Kohm resistor. The VID pins require an external bias voltage and should not be floated. The

VID input comparators, with 0.6V reference for VR10/VR11 and 1.24V for Opteron/Athlon64, monitor the VID

pins and control the 7-bit Digital-to-Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier.

The output of the buffer amp is the VDAC pin. The VDAC voltage is post-package trimmed to compensate for

the input offsets of the Error Amp to provide a 0.5% system accuracy. The actual VDAC voltage does not

represent the system set point and has a wider tolerance.

Page 14 of 47

9/14/2005

IR3084U

VID4

0

1

VID3

1

0

1

VID2

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID5

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID6

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Voltage

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

VID4

1

0

VID3

1

0

1

VID2

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID5

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID6

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Voltage

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

FAULT

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

Table 1 – VR10 7-bit VID Table with 6.25mV Extension

Page 15 of 47

9/14/2005

IR3084U

Hex (VID7:VID0)

00

Dec (VID7:VID0)

00000000

00000001

00000010

00000011

00000100

00000101

00000110

00000111

00001000

00001001

00001010

00001011

00001100

00001101

00001110

00001111

00010000

00010001

00010010

00010011

00010100

00010101

00010110

00010111

00011000

00011001

00011010

00011011

00011100

00011101

00011110

00011111

00100000

00100001

00100010

00100011

00100100

00100101

00100110

00100111

00101000

00101001

00101010

00101011

00101100

00101101

00101110

00101111

00110000

00110001

00110010

00110011

00110100

00110101

00110110

00110111

00111000

00111001

00111010

00111011

00111100

00111101

00111110

00111111

Voltage

Fault

Hex (VID7:VID0)

40

Dec (VID7:VID0)

01000000

01000001

01000010

01000011

01000100

01000101

01000110

01000111

01001000

01001001

01001010

01001011

01001100

01001101

01001110

01001111

01010000

01010001

01010010

01010011

01010100

01010101

01010110

01010111

01011000

01011001

01011010

01011011

01011100

01011101

01011110

01011111

01100000

01100001

01100010

01100011

01100100

01100101

01100110

01100111

01101000

01101001

01101010

01101011

01101100

01101101

01101110

01101111

01110000

01110001

01110010

01110011

01110100

01110101

01110110

01110111

01111000

01111001

01111010

01111011

01111100

01111101

01111110

01111111

Voltage

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

0.82500

0.81875

01

02

03

04

05

06

07

08

41

42

43

44

45

46

47

48

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

09

49

0A

0B

0C

0D

0E

0F

10

11

12

13

14

4A

4B

4C

4D

4E

4F

50

51

52

53

54

15

16

17

18

55

56

57

58

19

59

1A

1B

1C

1D

1E

1F

20

21

22

23

24

5A

5B

5C

5D

5E

5F

60

61

62

63

64

25

26

27

28

65

66

67

68

29

69

2A

2B

2C

2D

2E

2F

30

31

32

33

34

6A

6B

6C

6D

6E

6F

70

71

72

73

74

35

36

37

38

75

76

77

78

39

79

3A

3B

3C

3D

3E

3F

7A

7B

7C

7D

7E

7F

Table 2 – VR11 7-bit VID Table

Page 16 of 47

9/14/2005

IR3084U

VID4 VID3 VID2 VID1 VID0 Vout (V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.550

1.525

1.500

1.475

1.450

1.425

1.400

1.375

1.350

1.325

1.300

1.275

1.250

1.225

1.200

1.175

1.150

1.125

1.100

1.075

1.050

1.025

1.000

0.975

0.950

0.925

0.900

0.875

0.850

0.825

0.800

OFF⁴

Table 3 – Opteron 5-bit VID Table

Page 17 of 47

9/14/2005

IR3084U

Dynamic VID Operation

The IR3084U can accept changes in the VID code while operating and vary the DAC voltage accordingly. The

sink/source capability of the VDAC buffer amp is programmed by the external resistor that sets the oscillator

frequency (Rosc). The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between

VDAC pin and the VOSNS− pin. A resistor connected in series with this capacitor is required to compensate the

VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and

converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output

voltage.

Adaptive Voltage Positioning (AVP)

Adaptive Voltage Positioning (AVP) is needed to reduce the total output voltage deviations during load transients

and to reduce the power dissipation of the load when it is drawing high current. The circuitry related to the voltage

positioning is shown in Figure 8.

Resistor RSETPT is connected between the VDAC pin and the VSETPT pin to set the desired amount of fixed

offset voltage above or below the DAC voltage. The VSETPT pin is internally connected to both the non-inverting

input of the voltage error amplifier and an internal current source, I_OFFSET. The magnitude of I_OFFSETis

programmed by the external resistor that programs the oscillator frequency (Rosc) while the polarity of I_OFFSETis

set by the VIDSEL pin. When the VR10 and VR11 DAC tables are selected, the polarity of I_OFFSETis positive

(current flows into the pin). When the Opteron/Athlon64 DAC table is selected, the polarity of I_OFFSETis negative

(current flow out of the pin). The voltage across RSETPT sets the no load offset voltage above or below the

VDAC voltage.

The voltage at the VDRP pin is a buffered version of the current share bus (Iin) and represents the sum of the

VDAC voltage and the average inductor current of all the phases. The VDRP pin should be connected to the FB

pin through the resistor RDRP. Because the Error Amp will regulate the voltage at the FB pin equal to the

voltage at the VSETPT pin, a current will flow from the VDRP pin to the FB pin equal to (VDRP−VSETPT) / RDRP.

When the load current increases, the VDRP voltage will increase, additional current will flow through the

feedback resistor RFB and the converter’s output voltage will droop below the no load setpoint. The amount of

voltage droop can be programmed by the resistor RDRP so the converter’s output impedance meets the load-line

specification set by the CPU manufacturer. The offset and slope of the converter’s output impedance are

referenced to VDAC and are therefore independent of the exact VDAC (VID) setting.

Due to the difference between VDAC and FB, the voltage at the VDRP pin causes additional offset voltage

through RDRP and RFB. The total offset voltage is the sum of the voltage across RVSETPT and the voltage

drop across the RFB resistor at no load.

Control IC

VDAC

Phase IC

RSETPT

Current Sense

V SETPT

Amplifier

CSIN+

CSIN-

+

ISHARE

VDAC

+

-

EA OUT

FB

10k

IOFFSET

Vo

RFB

Error

Amplifier

RDRP

VDRP

Amplifier

Phase IC

VDRP

IIN

Current Sense

-

+

Amplifier

CSIN+

CSIN-

+

ISHARE

VDAC

-

10k

Figure 8 - Adaptive voltage positioning

Page 18 of 47

9/14/2005

IR3084U

Inductor DCR Temperature Correction

If the thermal compensation of the inductor DCR provided by the temperature dependent gain of the current

sense amplifier is not adequate, a negative temperature coefficient (NTC) thermistor can be used for additional

correction. The thermistor should be placed close to the inductor and connected in parallel with the feedback

resistor, as shown in Figure 9. The resistor in series with the thermistor is used to reduce the nonlinearity of the

thermistor.

Control IC

VDAC

RSETPT

V SETPT

+

EA OUT

-

Vo

RFB

Error

Amplifier

IOFFSET

RFB2

Rt

RDRP

AVP

Amplifier

VDRP

IIN

-

+

Figure 9 - Temperature compensation of inductor DCR

Remote Voltage Sensing

To compensate for impedance in the ground plane, the VOSNS− pin is used for remote ground sensing and

connects directly to the load. The VDAC voltage is referenced to VOSNS− to avoid additional error terms or

delays related to a separate differential amplifier. The capacitor connecting the VDAC and VOSNS− pins ensure

that high speed transients are fed directly into the error amp without delay.

Start-up Modes

The IR3084U has a programmable soft-start function to limit the surge current during converter start-up. A

capacitor connected between the SS/DEL and LGND pins controls soft start timing, over-current protection delay,

and hiccup mode timing. A charge current of 70µA controls the positive slope of the voltage at the SS/DEL pin.

There are two types of start-up possible: VR11 and Opteron/Athlon64. In VR11 mode, the soft start circuitry will

set the voltage at the VDAC pin to the 1.1V Boot voltage and the converter’s output will slowly rise using the slew

rate set by the capacitor at the SS/DEL pin until it’s equal to the VDAC voltage. After Vcore reaches the 1.1V

Boot voltage there will be a short delay, the VID pins will be sampled, and the voltage at the VDAC pin and the

converter’s output will increase or decrease to the desired VID setting using the dynamic VID slew rate. In

Opteron/Athlon64 mode, the soft start sequence will ramp the voltage at the VDAC pin directly to the external VID

setting using the slew rate set by the capacitor at the SS/DEL pin without pausing at the 1.1V Boot voltage.

Page 19 of 47

9/14/2005

IR3084U

Figure 10a depicts the start-up sequence without AVP in Boot mode − the VIDSEL pin is either grounded or

floated. First, the VDAC pin is charged to the 1.1V Boot voltage. Then, if there are no fault conditions, the

SS/DEL capacitor will begin to be charged. Initially, the error amplifier’s output will be clamped low until the

voltage at the SS/DEL reaches 1.3V. After the voltage at the SS/DEL pin rises to 1.3V, the error amplifier’s

output will begin to rise and the converter’s output voltage will be regulated 1.3V below the voltage at the SS/DEL

pin. The converter’s output voltage will slowly ramp to the 1.1V Boot voltage. The SS/DEL voltage will continue

to increase until it rises above the 3.10V threshold of the VID delay comparator. When the SS/DEL voltage

exceeds 3.10V, the VID inputs will be sampled and the VDAC pin will transition to the level determined by the VID

inputs at the dynamic VID slew rate. When the voltage on the SS/DEL pin rises above 3.77V the VRRDY Delay

Comparator will allow the VRRDY signal to be asserted. SS/DEL will continue to rise until finally settling at

3.85V, indicating the end of the start-up sequence.

Figure 10b depicts the start-up sequence in Opteron/Athlon64 mode − VIDSEL is connected to GND via a 6.49K

resistor. First, the external VID setting is sampled and the VDAC pin is set to the desired VID voltage. Then, if

there are no fault conditions, the SS/DEL capacitor will begin to charge. Initially, the error amplifier’s output will

be clamped low until the voltage at the SS/DEL rises to 1.3V. After the voltage at the SS/DEL pin reaches 1.3V,

the error amplifier’s output will begin to rise and the converter’s output voltage will be regulated 1.3V below the

voltage at the SS/DEL pin. As the voltage at the SS/DEL pin continues to rise, the converter’s output voltage will

slowly increase until it is equal to the voltage at the VDAC pin. When the voltage on the SS/DEL pin rises above

3.77V the VRRDY Delay Comparator will allow the VRRDY signal to be asserted. SS/DEL will continue to rise

until finally settling at 3.85V, indicating the end of the start-up sequence.

If AVP is used, the soft start timing will change slightly because of the resistor from the VDRP amplifier to the

Error Amplifier’s FB pin. During startup with AVP, the VDRP amplifier will produce a voltage at the FB pin equal

to VDAC times the resistor divider formed by the droop resistor and the feedback resistor from Vcore to the FB

pin. To offset the contribution from the VDRP amplifier, the voltage at the SS/DEL pin will have to rise to beyond

1.3V before the Error Amplifier’s output and Vcore begin to rise. For a DAC setting of 1.3V with typical VR11

AVP, the Error Amplifier’s output will begin to rise when the voltage at the SS/DEL pin reaches approximately

1.8V. The effect of this offset will be to slightly lengthen the Start Delay (TD1) and shorten the Soft Start Ramp

Time (TD2).

The following table summarizes the differences between the 3 modes associated with setting the VIDSEL pin. In

addition to changing the soft start sequence, the NO_CPU code may or may not be ignored during startup and

the NO_CPU code may or may not be latched.

1.1V Boot

Voltage During

Startup?

Ignore NO CPU

Codes During

Startup?

VIDSEL

Voltage

VID

Table

Latch NO CPU

Fault Code?

GND

(<0.6V)

FLOAT

VR10

VR11

YES

NO

YES

NO

YES

NO

(>1.8V)

6.49K to GND

(0.9V<VIDSEL<1.7V)

Opteron/Athlon64

Table 4: Controller Functionality versus VIDSEL Voltages

Page 20 of 47

9/14/2005

IR3084U

9.1V

UVLO

+12Vin

0.85V

ENABLE

(VTT)

1.100V

VDAC

3.85V

3.77V

3.10V

1.30V

SS/DEL

EAOOUT

1.100V

VDAC

IIN

1.100V

VOUT

VRRDY

VID

VR_RDY DELAY

1.3ms (TD4+TD5)

START

(ENABLE ENDS

FAULT MODE)

START DELAY

1.8ms (TD1)

NORMAL

OPERATION

POWER-DOWN

(VCC UVL

INITIATES

FAULT MODE)

SOFT START TIME

1.6ms (TD2)

SAMPLE

DELAY

1.0ms

(TD3)

DYNAMIC VID TIME

200us (TD4)

Figure 10a – Start-up Waveforms with Boot Mode (VID Setting > 1.1V)

9.1V

UVLO

+12Vin

0.85V

ENABLE

(VTT)

VID SETTING

VDAC

3.77V

1.30V

SS/DEL

EAOOUT

VID SETTING

IIN

VID SETTING

VOUT

VRRDY

POWER-DOWN

(VCC UVL

INITIATES

FAULT MODE)

START

(ENABLE ENDS

FAULT MODE)

START DELAY

1.8ms

SOFT START TIME

1.8ms

VR_RDY DELAY

2.3ms

NORMAL

OPERATION

Figure 10b – Opteron/Athlon64 Start-up Waveforms (VID Setting=1.1V)

Page 21 of 47

9/14/2005

IR3084U

Fault Modes

Under Voltage Lock Out, VID = FAULT, as well as a low signal on the ENABLE input immediately sets the fault

latch. This causes the EAOUT pin to drive low which turns off the Phase IC drivers. The VRRDY pin also drives

low. The SS/DEL capacitor will discharge down to 0.215V through a 6.5µA current source. If the fault has cleared

when SS/DEL falls to 0.215V then the fault latch will be reset by the discharge comparator allowing a normal

start-up sequence to occur. If a VID = FAULT condition is latched it can only be cleared by cycling power to the

IR3084U on and off.

SS/DEL

(3.85V

3.77V

3.75V

DURING

NORMAL

OPERATION)

1.3V

DISCHARGE VOLTAGE (0.215V)

VOUT

VRRDY

IOUT

OCP THRESHOLD

NORMAL

OPERATION

HICCUP OVER-CURRENT

PROTECTION

RESTART NORMAL

AFTER

OPERATION

OCP

DELAY

Figure 11 – Over-Current Protection Waveforms (VID = 1.1V for simplicity)

Over-Current Protection Delay and Hiccup Mode

Figure 11 depicts the operating waveforms of the Over Current Protection (OCP). A delay is included if an over-

current condition occurs after a successful soft start sequence. This delay is required because over-current

conditions can occur as part of normal operation due to load transients or VID transitions. If an over-current fault

occurs during normal operation it will activate the over-current discharge current of 40µA but will not set the fault

latch immediately. If the over-current condition persists long enough for the SS/DEL capacitor to discharge below

the 100mV offset of the delay comparator, the Fault latch will be Se, the error amp’s output will be pulled low,

switching in the phase ICs will be inhibited, and the VRRDY signal will be de-asserted.

The SS/DEL capacitor will continue to discharge until it reaches 0.215V and the fault latch is Reset allowing a

normal soft start to occur. If an over-current condition is again encountered during the soft start cycle the fault

latch will be set without any delay and hiccup mode will begin. During hiccup mode the 11.2 to 1 charge to

discharge current ratio results in a 9% hiccup mode duty cycle regardless of at what point the over-current

condition occurs.

If the SS/DEL pin is pulled below 0.85V, the converter can be disabled.

Page 22 of 47

9/14/2005

IR3084U

Under Voltage Lockout (UVLO)

The UVLO function monitors the IR3084U’s VCC supply pin and ensures that there is adequate voltage to safely

power the internal circuitry. The IR3084U’s UVLO is set higher than the minimum operating voltage of compatible

Phase ICs thus providing UVLO protection for them as well. UVLO at the Phase ICs is a function of the Error

Amplifier’s output voltage. When the IR3084U is in UVLO, the Error Amplifier is disabled and EAOUT is at a very

low voltage (<200mV) thus preventing the Phase ICs from becoming active.

During power-up the fault latch will be reset when VCC exceeds 9.9V and there are no other faults. If the VCC

voltage drops below 9.1V the fault latch will be set.

Over Current Protection (OCP)

The current limit threshold is set by a resistor connected between the OCSET and VDAC pins. If the IIN pin

voltage, which is proportional to the average phase current plus DAC voltage, exceeds the OCSET voltage, the

over-current protection is triggered.

VID = Fault Code (NO_CPU)

When VIDSEL is grounded or left floating, NO_CPU VID codes of 11111XX for VR10 and 0000000X, 1111111X

for VR11 will set both the VID Fault Latch and the Fault Latch to disable the error amplifier. The controller will be

latched OFF and a power-on reset (POR) must be performed to produce a new soft start sequence. In these 2

modes, the NO_CPU codes are ignored during startup. See Table 1 for further details.

When VIDSEL is connected to GND via a 6.49K resistor, NO_CPU VID codes of 11111 will set the Fault Latch to

disable the error amplifier but the VID Fault Latch will not be set. The controller will not be latched OFF and a

soft start sequence will be produced when the NO_CPU code is removed and the SS/DEL voltage falls below

0.215V. In Opteron/Athlon64 mode, the NO_CPU codes are not ignored during startup. See Table 1 for further

details.

A 1.3µs delay is provided to prevent a NO_CPU fault condition from occurring during Dynamic VID changes.

VR_RDY (Power Good) Output

The VRRDY pin is an open-collector output and should be pulled up to a voltage source through a resistor.

During soft start, the VRRDY remains low until the output voltage is in regulation and SS/DEL is above 3.77V.

The VRRDY pin becomes low if the fault latch is set. A high level at the VRRDY pin indicates that the converter is

in operation and has no fault, but does not ensure the output voltage is within the specification. Output voltage

regulation within the design limits can logically be assured however, assuming no component failure in the

system.

Load Current Indicator Output

The VDRP pin voltage represents the average phase current of the converter plus the DAC voltage. The load

current can be retrieved by subtracting the VDAC voltage from the VDRP voltage.

Page 23 of 47

9/14/2005

IR3084U

System Reference Voltage (VBIAS)

The IR3084U supplies a 6.8V/6mA precision reference voltage from the VBIAS pin. The oscillator ramp trip points

are based on the VBIAS voltage so it should be used to program the Phase ICs phase delay to minimize phase

errors.

Phase IC Gate Driver Bias Regulator / VRHOT Comparator

An internal amplifier can be configured as a gate driver bias regulator to provide programmable gate driver

voltage for phase ICs (Figure 12a), or a thermal monitor to provide VRHOT/VRFAN signal as required in VR11

(Figure 12b).

The internal current source IREGSET whose value is programmed by the switching frequency going through the

external RSET resistor sets the gate driver voltage or the VRHOT/VRFAN threshold voltage. An NTC thermistor

is used to monitor the temperature on the VRM/VRD.

+12V

VCC

RPU

1ohm / 1206

IREGSET

0Adc

REGSET

+

-

REGDRV

REGFB

Q1

CJD200

CVGDRV

10nF

RVGDRV

97.6K

VGDRIVE

C2

10uF

+

IR3084 CONTROL IC

Figure 12a – IR3084U Bias Regulator configured for Gate Driver Bias Regulator

RH2

36K

RH1

1.1MEG

+3.3V

VBIAS

VCC

RPU1

2K

VRHOT#

IREGSET

R1

10K

R4

2K

REGSET

REGFB

+

-

Q5

2N7002

REGDRV

R5

1K

C2

10nF

C1

1nF

R2

100K

IR3084 CONTROL IC

R3

3K

Figure 12b – IR3084U Bias Regulator configured for VRHOT/VRFAN function

Page 24 of 47

9/14/2005

IR3084U

PERFORMANCE CHARACTERISTICS

Figure 13: Oscillator Frequency versus ROSC

Figure 14: I(OCSET) versus ROSC

1000

120

110

100

90

900

800

700

600

500

400

300

200

100

80

70

60

50

40

30

20

10

20

30

40

50

60

70

80

90

10

20

30

40

50

60

70

80

90

ROSC (Kohms)

Figure 16: I(REGSET) CURRENT versus ROSC

Figure 15: I(VSETPT) versus ROSC

250

230

210

190

170

150

130

110

90

120

110

100

90

80

70

60

50

40

70

30

50

20

30

10

20

30

40

50

60

70

80

90

10

20

30

40

50

60

70

80

90

ROSC (Kohms)

Figure 17: VDAC SINK & SOURCE CURRENT vs. ROSC

Figure 18: IR3084 Error Amplifier Bode Plot

200

260

240

220

200

180

160

140

120

100

80

I(VDAC SOURCE) (uA)

I(VDAC SINK) (uA)

Gain

150

100

50

Phase

0

60

40

20

-50

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

10

20

30

40

50

60

70

80

90

Frequency (Hz)

ROSC (Kohms)

Page 25 of 47

9/14/2005

IR3084U

APPLICATIONS INFORMATION

VR READY

VRHOT

PHASE FAULT

VOUT SENSE-

VOUT SENSE+

+12V

RCS-

CIN

R1332

1

Q8

CJD200

CCS+

CCS-

RBIASIN

C205

0.1uF

C137

1uF

RCS+

0.1uF

CCP

100pF

1

15

RMPIN+

VCCH

DISTRIBUTION

RT

R118

2

3

4

5

14

13

12

11

IMPEDANCE

VOUT+

IR3086

PHASE

IC

+5.0V

RMPIN-

HOTSET

VRHOT

ISHARE

GATEH

PGND

GATEL

VCCL

4.7K, B=4450 1.21K

RCP

2.49K

CCP

56nF

R138

2K

COUT

RFB

162

CFB

12nF

18

EAOUT

U6

17

27

15

19

20

FB

VRRDY

IIN

RMPOUT

VBIAS

RFB

348

0.1uF

C1010

100pF

RDRP2

750

RDRP1

750

C136

0.1uF

C90

100pF

RPWMRMP

0.1uF

IR3084UMTR

24

23

25

CSCOMP

REGDRV

REGFB

16

VDRP

REGSET

OUTEN

28

9

8

7

6

5

4

3

1

2

RVGDRV

97.6K

CVGDRV

10nF

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

VID_SEL

ENABLE

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VIDSEL

INTL_MD

RCS-

CCS-

CCS+

RVSETPT1

RBIASIN

14

13

12

11

VSETPT

OCSET

VDAC

RCS+

0.1uF

+12V

RVSETPT2

124

21

VCC

R31

10

C131

0.1uF

ROCSET

12.7K

26

SS/DEL

CSS/DEL

0.1uF

1

15

RMPIN+

VCCH

GATEH

PGND

GATEL

VCCL

RVDAC

3.5

2

3

4

5

14

13

12

11

IR3086

PHASE

IC

VOSNS-- LGNDROSC

10 22

RMPIN-

HOTSET

VRHOT

ISHARE

CVDAC

33nF

ROSC

30.1K

0.1uF

RPWMRMP

0.1uF

CSCOMP

RCS-

CCS-

CCS+

RBIASIN

RCS+

0.1uF

1

15

RMPIN+

VCCH

GATEH

PGND

GATEL

VCCL

2

3

4

5

14

13

12

11

IR3086

PHASE

IC

RMPIN-

HOTSET

VRHOT

ISHARE

0.1uF

RPWMRMP

0.1uF

CSCOMP

RCS-

CCS-

CCS+

RBIASIN

RCS+

0.1uF

1

15

RMPIN+

VCCH

GATEH

PGND

GATEL

VCCL

2

3

4

5

14

13

12

11

IR3086

PHASE

IC

RMPIN-

HOTSET

VRHOT

ISHARE

0.1uF

RPWMRMP

0.1uF

CSCOMP

RCS-

CCS-

CCS+

RBIASIN

RCS+

0.1uF

1

15

RMPIN+

VCCH

GATEH

PGND

GATEL

VCCL

2

3

4

5

14

13

12

11

IR3086

PHASE

IC

RMPIN-

HOTSET

VRHOT

ISHARE

0.1uF

RPWMRMP

0.1uF

CSCOMP

Figure 19 – IR3084U/3086 5 Phase VRM/EVRD 11 Converter

Page 26 of 47

9/14/2005

IR3084U

DESIGN PROCEDURES – IR3084U and IR3086 Chipset

IR3084U EXTERNAL COMPONENTS

Oscillator Resistor Rosc

The oscillator of IR3084 generates a triangle waveform to synchronize the phase ICs, and the switching

frequency of the each phase converter equals the oscillator frequency, which is set by the external resistor ROSC

according to the curve in Figure 13 on page

VDAC Slew Rate Programming Capacitor C_VDACand Resistor R_VDAC

The sink and source currents of the VDAC pin are set by the value of R_OSC. The sink current capability of the

VDAC pin is slightly less than the source current. Therefore, the VDAC sink current (I_SINK) should be used to

calculate C_VDACto insure that the dynamic VID slew rate when Vcore decreases is not too slow.

The negative slew rate of VDAC (SR_DOWN) is programmed by the external capacitor C_VDACas shown in Equation

(1). The resistor R_VDACis used to compensate/stabilize the VDAC circuit and is determined by Equation (2). The

positive slew rate of the VDAC voltage (SR_UP) is proportional to the negative slew rate of VDAC and can be

calculated using Equation (3).

I_SINK

C_VDAC

=

(1)

SR_DOWN

Where: I_SINKis the sink current of the VDAC pin at the chosen value of R_OSCas shown in Figure 17 on

page 25.

3.2 ∗10⁻¹⁵

(2)

(3)

R_VDAC= 0.5Ω +

2

C_VDAC

I_SOURCE

SR_UP

=

C_VDAC

Where: I_SOURCEis the source current of the VDAC pin at the chosen value of R_OSCas shown in Figure 17

on page 25.

The VID voltage rise or fall time during startup with Boot Mode (TD4) can be calculated using either Equation

(4a) or (4b).

C_VDAC

TD4 =

∗

(

VDAC −1.1V

)

if VDAC > 1.1V

if VDAC < 1.1V

(4a)

(4b)

I_SOURCE

C_VDAC

∗

(

1.1V −VDAC

)

I_SINK

Where: VDAC is the DAC voltage set by the VID pins.

I_SOURCEand I_SINKare the source and sink currents of the VDAC pin.

If Boot Mode is not used then TD4 = 0.

Page 27 of 47

9/14/2005

IR3084U

No Load Output Voltage Setting Resistor RVSETPT, Feedback Resistor RFB, and AVP Resistor RDRP

An external resistor, R_VSETPT, connected between the VDAC pin and the VSETPT pin is used to set the no load

output voltage offset, V_{O_NLOFST}, which is the difference between the VDAC voltage and output voltage at no load.

However, the converter’s output voltage will be set by the combination of VSETPT plus some contribution from

the VDRP pin. At no load, both pins of the Error Amplifier are at VDAC – VSETPT while the VDRP pin is at

VDAC + V_{CS_OFST}•G_CSA(V_{CS_OFST}and G_CSAare the input offset and gain of the current sense amplifiers). Because

the VDRP pin is at a higher voltage than the FB pin of the Error Amplifier, VDRP will contribute to the no load

offset through the RDRP and RFB resistors. The design approach is to choose a value for the feedback resistor,

RFB, from 100 to 2K and then calculate RDRP and R_VSETPTto provide the required no load offset voltage.

A* D − C * B

(A + B − C − D)

VSETPT =

(5)

^CSA+VCS _ TOFST *GCSA

C = VCS _ TOFST *GCSA

D = VO_NLOFST

Io* R *G

L

A =

n

B = VO_NLOFST + Io* Ro

Where:

I_Ois the full load output current of the converter

R_Lis the DCR of the output inductor

G_CSAis the gain of the current sense amplifiers

n is the number of phases

V_{O_NLOFST}is the no load offset voltage below the DAC setting,

a positive number for VR10 and VR11, a negative number for AMD

Ro is the desired load line slope (ohms)

V_{CS_TOFST}is the total offset voltage of the current sense amplifiers, see below.

The total input offset voltage (VCS_TOFST) of the current sense amplifier in the phase IC is the sum of input offset

(VCS_OFST) of the amplifier itself plus that created by the amplifier input bias currents flowing through the current

sense resistors RCS+ and RCS− as shown in Equation (6).

V_{CS_TOFST}= V_{CS_OFST}

+

(

I_{CSIN +}∗ R_{CS +}

)

−

(

I_{CSIN −}∗ R_{CS −}

)

(6)

Finally, calculate the no-load setpoint resistor using Equation (7) and the droop resistor using Equation (8);

VSETPT

RVSETPT =

(7)

(8)

IVSETPT

Where:

I_VSETPTis the current into the VSETPT pin at the switching frequency,

which is a function of R_OSC. See Figure 15 on page 25.

VSETPT is calculated by Equation (5).

VSETPT + C

D −VSETPT

RDRP = RFB ⋅

Page 28 of 47

9/14/2005

IR3084U

Soft Start Capacitor CSS/DEL and Resistor RSS/DEL

Because the capacitor CSS/DEL programs three different time parameters, i.e. soft start time, over current latch

delay time, and the frequency of hiccup mode, they should be considered together while choosing CSS/DEL.

The soft-start ramp time (TD2) is the time required for the converter’s output voltage to rise from 0V to the DAC

voltage (VDAC). Given a desired soft-start ramp time (TD2) and the soft-start charge current (I_CHG) from the data

sheet, the value of the external capacitor (C_SS/DEL) can be calculated using Equation (9).

70*10⁻⁶*TD2

I

_CHG*TD2

(9)

C_{SS / DEL}

=

RFB

⎛

⎞

⎟

⎛

⎞

⎟

VDAC ∗ 1−

⎜

RFB + RDRP

⎝

⎠

⎝

⎠

Where: VDAC = 1.1V in Boot Mode or the DAC voltage set by the VID pins without Boot Mode.

RFB is the resistor from Vcore to the FB pin of the controller.

RDRP is the resistor from VDRP to FB.

If droop is not used, set the second term within the parenthesis to zero (RDRP = ∞).

Once C_SS/DELis determined, the soft start delay time TD1, the VID sample time TD3, the VRRDY delay time TD5,

and the over-current fault latch delay time T_OCDELare determined and can be calculated using Equations (10),

(11), (12), and (13) respectively.

C_{SS / DEL}

RFB

⎛

⎝

⎞

⎟

(10)

TD1 =

∗ 1.3V +VDAC ∗

⎜

I_CHG

RFB + RDRP

⎠

Where: VDAC = 1.1V in Boot Mode or the DAC voltage set by the VID pins without Boot Mode.

ICHG is the soft-start charge current, nominally 70µA.

RFB is the resistor from Vcore to the FB pin of the controller.

RDRP is the resistor from VDRP to FB.

If droop is not used, set the second term within the parenthesis to zero (RDRP = ∞).

C_{SS / DEL}

70*10⁻⁶

TD3 =

∗

(

3.1V −1.3V −1.1V

)

=

∗ 0.7V

(11)

(12)

(13)

I_CHG

If Boot Mode is not used, then TD3 is zero.

C_{SS / DEL}*(3.85V − 3.1V )

C_{SS / DEL}*0.75V

TD5 =

−TD4 =

−TD4

70*10⁻⁶

I_CHG

Where: TD4 is the VID voltage rise time calculated from Equation 4.

C_{SS / DEL}*100mV C_{SS / DEL}*100mV

T_OCDEL

=

40*10⁻⁶

I_{OC _ DISCHG}

Where: I_{OC_DISCHG}is the over-current discharge current of the SS/DEL pin from the data sheet.

Page 29 of 47

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IR3084U

Over Current Setting Resistor ROCSET

The inductor DC resistance is utilized to sense the inductor current. The copper wire of the inductor has a

constant temperature coefficient of 3850 PPM, and therefore the maximum inductor DCR can be calculated from

Equation (14), where RL_MAX and RL_ROOM are the inductor DCR at maximum temperature TL_MAX and room

temperature T_ROOM respectively.

R_{L_MAX}= R_{L_ROOM}∗ [1 + 3850*10⁻⁶∗(T_{L_MAX}−T_ROOM)]

(14)

The current sense amplifier gain of the IR3086A decreases with temperature at the rate of 1470 PPM, which

compensates part of the inductor DCR increase. The phase IC die temperature is only a couple of degrees

Celsius higher than the PCB temperature due to the low thermal impedance of MLPQ package. The minimum

current sense amplifier gain at the maximum phase IC temperature TIC_MAX is calculated from Equation (15).

G_{CS_MIN}= G_{CS_ROOM}∗ [1 − 1470*10⁻⁶∗(T_{IC_MAX}−T_ROOM)]

(15)

The over-current limit is set by the external resistor R_OCSETas defined in Equation (16), where ILIMIT is the

required over current limit. IOCSET, the bias current of the OCSET pin, changes with switching frequency setting

resistor ROSC and is determined by the curve in Figure 14 on page 25. KP is the ratio of inductor peak current to

average current in each phase and is calculated from Equation (17).

G_{CS _ MIN}

I_LIMIT

(16)

(17)

R_OCSET= [

∗ R_{L_MAX}∗(1+ K_P) +V_{CS_TOFST}] ∗

n

I_OCSET

(V_I−V_{O _ FL})∗V_{O _ FL}/(L ∗V_I∗ f_SW∗ 2)

K_P=

I_LIMIT/n

Where: V_Iis the input voltage to the converter (nominally 12V).

V_{O_FL}is the output voltage of the converter with droop at the over-current threshold.

L is the value of the output inductors.

f_SWis the switching frequency.

I_LIMITis the DC output current of the converter when the over-current fault occurs.

n is the number of phases.

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IR3084U

IR3086 EXTERNAL COMPONENTS

PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP

PWM ramp is generated by connecting the resistor RPWMRMP between a voltage source and PWMRMP pin as

well as the capacitor CPWMRMP between PWMRMP and LGND. Choose the desired PWM ramp magnitude

VRAMP and the capacitor CPWMRMP in the range of 100pF and 470pF, and then calculate the resistor RPWMRMP

from Equation (18). To achieve feed−forward voltage mode control, the resistor RRAMP should be connected to

the input of the converter.

V

O

(18)

R

=

PWMRMP

V

*f

*C

*[ln(V −V

IN

) − ln(V −V

IN

−V

)]

IN SW PWMRMP

DAC

PWMRMP

Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCS−

The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS+ and capacitor

CCS+ in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage

across the capacitor CCS+ represents the inductor current. If the two time constants are not the same, the AC

component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch

does not affect the average current sharing among the multiple phases, but affect the current signal ISHARE as

well as the output voltage during the load current transient if adaptive voltage positioning is adopted.

Measure the inductance L and the inductor DC resistance RL. Pre−select the capacitor CCS+ and calculate RCS+

as follows.

L R_L

(19)

R_{CS +}

=

C_{CS +}

The bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across

RCS+, which is equivalent to an input offset voltage of the current sense amplifier. The offset affects the accuracy

of converter current signal ISHARE as well as the accuracy of the converter output voltage if adaptive voltage

positioning is adopted. To reduce the offset voltage, a resistor RCS− should be added between the amplifier

inverting input and the converter output. The resistor RCS− is determined by the ratio of the bias current from the

non-inverting input and the bias current from the inverting input.

I_{CSIN +}

(20)

R_{CS −}

=

∗ R_CS+

I_{CSIN −}

If RCS− is not used, RCS+ should be chosen so that the offset voltage is small enough. Usually RCS+ should be

less than 2 kΩ and therefore a larger CCS+ value is needed.

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IR3084U

Over Temperature Setting Resistors RHOTSET1 and RHOTSET2

The threshold voltage of VRHOT comparator is proportional to the die temperature TJ (ºC) of phase IC.

Determine the relationship between the die temperature of phase IC and the temperature of the power converter

according to the power loss, PCB layout and airflow etc, and then calculate HOTSET threshold voltage

corresponding to the allowed maximum temperature from Equation (21).

V_HOTSET= 4.73*10⁻³*T_J+ 1.241

(21)

There are two ways to set the over temperature threshold, central setting and local setting. In the central setting,

only one resistor divider is used, and the setting voltage is connected to HOTSET pins of all the phase ICs. To

reduce the influence of noise on the accuracy of over temperature setting, a 0.1uF capacitor should be placed

next to HOTSET pin of each phase IC. In the local setting, a resistor divider per phase is needed, and the setting

voltage is connected to HOTSET pin of each phase. The 0.1uF decoupling capacitor is not necessary. Use

VBIAS as the reference voltage. If RHOTSET1 is pre−selected, RHOTSET2 can be calculated as follows.

R_HOTSET1∗V_HOTSET

V_BIAS−V_HOTSET

R_HOTSET2

=

(22)

Phase Delay Timing Resistors RPHASE1 and RPHASE2

The phase delay of the interleaved multiphase converter is programmed by the resistor divider connected at

RMPIN+ or RMPIN− depending on which slope of the oscillator ramp is used for the phase delay programming of

phase IC, as shown in Figure 4.

If the positive slope is used, RMPIN+ pin of the phase IC should be connected to RMPOUT pin of the control IC

and RMPIN− pin should be connected to the resistor divider. When RMPOUT voltage is above the trip voltage at

RMPIN− pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time.

If the negative slope is used, RMPIN− pin of the phase IC should be connected to RMPOUT pin of the control IC

and RMPIN+ pin should be connected to the resistor divider. When RMPOUT voltage is below the trip voltage at

RMPIN− pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time.

It is best to use the VBIAS voltage as the reference for the resistor dividers because the oscillator ramp

magnitude from the control IC will track the VBIAS voltage. It is best to avoid the peak and valley of the oscillator

ramp for better noise immunity. Determine the ratio of the programming resistors corresponding to the desired

switching frequencies and phase numbers. If the resistor RPHASEx1 is pre-selected, the resistor RPHASEx2 is

determined as:

RA_PHASEx∗ R_PHASEx1

(23)

R_PHASEx2

=

1 − RA_PHASEx

Page 32 of 47

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IR3084U

Combining the Over Temperature and Phase Delay Setting Resistors RPHASE1, RPHASE2 and RPHASE3

The over temperature setting resistor divider can be combined with the phase delay resistor divider to save one

resistor per phase.

Calculate the HOTSET threshold voltage VHOTSET corresponding to the allowed maximum temperature from

Equation (20). If the over temperature setting voltage is lower than the phase delay setting voltage,

VBIAS*RAPHASEx, connect RMPIN+ or RMPIN− pin between RPHASEx1 and RPHASEx2 and connect HOTSET pin

between RPHASEx2 and RPHASEx3 respectively. Pre-select RPHASEx1, then calculate RPHASEx2 and RPHASEx3,

(RA_PHASEx∗V_BIAS−V_HOTSET)*R_PHASEx1

(24)

(25)

R_PHASEx2

=

V_BIAS∗(1 − RA_PHASEx

)

V_HOTSET∗ R_PHASEx1

V_BIAS*(1− RA_PHASEx

R_PHASEx3

)

If the over temperature setting voltage is higher than the phase delay setting voltage, VBIAS*RAPHASEx, connect

HOTSET pin between RPHASEx1 and RPHASEx2 and connect RMPIN+ or RMPIN− between RPHASEx2 and

RPHASEx3 respectively. Pre-select RPHASEx1,

(V_HOTSET− RA_PHASEx∗V_BIAS)∗ R_PHASEx1

R_PHASEx2

=

(26)

(27)

V_BIAS−V_HOTSET

RA_PHASEx∗V_BIAS*R_PHASEx1

V_BIAS−V_HOTSET

R_PHASEx3

Bootstrap Capacitor CBST

Depending on the duty cycle and gate drive current of the phase IC, a 0.1uF to 1uF capacitor is needed for the

bootstrap circuit.

Decoupling Capacitors for Phase IC

0.1uF−1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs.

Page 33 of 47

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IR3084U

VOLTAGE LOOP COMPENSATION

The adaptive voltage positioning is used in the computer applications to meet the load line requirements. Like

current mode control, the adaptive voltage positioning loop introduces extra zero to the voltage loop and splits the

double poles of the power stage, which make the voltage loop compensation much easier.

Resistors RFB and RDRP are chosen according to Equations (15) and (16), and the selection of compensation

type depends on the capacitors used. For the applications using Electrolytic, Polymer or AL−Polymer capacitors,

Type II compensation shown in Figure 20 (a) is usually adequate. While for the applications with only ceramic

capacitors, Type III compensation shown in Figure 20 (b) is preferred.

CCP1

RFB

CFB

RCP

CCP

VO+

RCP

CCP

RFB1

FB

-

EAOUT

RFB

EAOUT

VO+

FB

VDAC

-

RDRP

+

VDRP

EAOUT

VDAC

RDRP

CDRP

+

VDRP

(a) Type II compensation

(b) Type III compensation

Figure 20: Voltage Loop Compensation Networks

Type II Compensation

Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between

1/10 and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across

the output inductors matches that of the inductor, RCP and CCP can be determined by Equations (28) and (29).

(2π * f_C)²* L_E*C_E* R_FB*V_PWMRMP

(28)

(29)

R_CP

=

V_O* 1 + (2π * f_C*C_E* R_CE)²

10 * L_E*C_E

C_CP

R_CP

Where LE and RCE are the equivalent output inductance and ESR of the output capacitors, respectively. CCP1 is

optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A

ceramic capacitor between 10pF and 220pF is usually enough.

Page 34 of 47

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IR3084U

Type III Compensation

Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between

1/10 and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across

the output inductors matches that of the inductor, RCP and CCP can be determined by Equations (30) and (31),

where CE is equivalent output capacitance.

(2π * f_C)²* L_E*C_E*V_PWMRMP

(30)

(31)

R_CP

=

V_o

10 * L_E*C_E

C_CP

R_CP

Choose resistor RFB1 according to Equation (33), and determine CFB and RDRP from Equations (32) and (33).

1

2

R_FB1= * R_FB

to

R_FB1= * R_FB

(32)

(33)

2

3

1

C_FB

=

4π * f_C1* R_FB1

CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise.

A ceramic capacitor between 10pF and 220pF is usually enough.

CURRENT SHARE LOOP COMPENSATION

The crossover frequency of the current share loop should be at least one decade lower than that of the voltage

loop in order to eliminate the interaction between the two loops. A capacitor from SCOMP to LGND is usually

enough for most of the applications. Choose the crossover frequency of current share loop (fCI) based on the

crossover frequency of voltage loop (fC), and determine the CSCOMP,

0.65 * R_PWMRMP*V_I* I_O*G_{CS_ROOM}* R_LE* [1 + 2π * f_CI*C_E*( V_OI_O)] * F_MI

C_SCOMP

=

(34)

V_O* 2π * f_CI*1.05*10⁶

Where FMI is the PWM gain in the current share loop,

R_PWMRMP*C_PWMRMP* f_SW*V_PWMRMP

FMI =

(35)

(V_O−V_PWMRMP−V_DAC)*(V_I−V_DAC

)

Page 35 of 47

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IR3084U

DESIGN EXAMPLE: VRM 11 7−PHASE CONVERTER

SPECIFICATIONS

Input Voltage: VI = 12V

DAC Voltage: VDAC = 1.3V

No Load Output Voltage Offset: VO_NLOFST = 15mV

Output Current: IO = 130 ADC

Maximum Output Current: IOMAX = 150 ADC

Load Line Slope: RO = 1.20 mΩ

VRM11 Startup Boot Voltage = 1.100V

Soft Start Time: TD2 = 1.1ms

VCC Ready to VCC Power Good Delay: TD5 = 1.0ms

Over Current Delay: TOCDEL = 250µs

Dynamic VID Negative Slew Rate: SRDOWN = 2.5mV/us

Over Temperature Threshold: TPCB = 115 ºC

POWER STAGE

Phase Number: n = 7

Switching Frequency: f_SW=400 kHz

Output Inductors: L = 220 nH, RL = 0.60 mΩ

Output Capacitors: C = 560uF, RC = 7mΩ, Number Cn = 10

IR3084 EXTERNAL COMPONENTS

Oscillator Resistor Rosc

The switching frequency sets the value of ROSC as shown by the curve in Figure 13 on page 25. In this design,

the switching frequency of 400kHz per phase requires ROSC to be 30.1kΩ.

VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC

From Figure 17 on page 25, the sink current of the VDAC pin at 400kHz (R_OSC=30.1kΩ) is 80uA. Calculate the

VDAC slew-rate programming capacitor from the specified negative slew rate using Equation (1).

80*10⁻⁶

2.5*10⁻³/10⁻⁶

I_SINK

C_VDAC

=

= 32.0nF ,

Choose C_VDAC= 33nF

SR_DOWN

Calculate the VDAC compensation resistor from Equation (2);

3.2*10⁻¹⁵

R_VDAC= 0.5 +

= 0.5 +

= 3.5Ω

2

(33*10⁻⁹

)

C_VDAC

From Figure 17 on page 25, the source current of the VDAC pin is 90uA at R_OSC= 30.1KΩ. The VDAC positive

slew rate is can be calculated using Equation (3);

90*10⁻⁶

I_SOURCE

SR_UP

=

= 2.7mV/uS

33*10⁻⁹

C_VDAC

Page 36 of 47

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IR3084U

Using the calculated value of C_VDAC, find the positive VID voltage rise time (TD4) to the specified nominal DAC

voltage of 1.300V during startup with Boot Mode using Equation 4a;

C_VDAC

33nF

90uA

TD4 =

∗

(

VDAC −1.1V

)

=

*

(

1.300V −1.1V = 73.3us

)

I_SOURCE

No Load Output Voltage Setting Resistor RVSETPT, RFB and Adaptive Voltage Positioning Resistor RDRP

First, use Equations (19) and (20) to calculate the current sense resistors R_CS+and R_CS−, respectively. For this

design, in the next section, R_CS+is determined to be 10KΩ and R_CS−is found to be 6.19KΩ.

Second, calculate the total input offset voltage (V_{CS_TOFST}) of the current sense amplifiers using Equation (6).

From the IR3086A data sheet, typical values for the I_CSIN+and I_CSIN−bias currents are determined to be 0.25µA

and 0.40µA, respectively.

V_{CS_TOFST}= V_{CS_OFST}

+

(

I

_CSIN+∗ R_CS+

)

−

(

I

_CSIN−∗ R_CS−

)

= 0.55mV +

(

0.25*10⁻⁶*10KΩ

)

−

(

0.40*10⁻⁶*6.19KΩ

)

= 0.574mV

Next, derive the intermediate calculations (A,B,C,D) as shown below before finally calculating R_VSETPTand RDRP

using Equations (7) and (8). From Figure 15 on page Error! Bookmark not defined., the I_VSETPTbias current is

determined to be 40µA at ROSC=30.1kΩ and a typical value for the offset voltage of the error amplifier is 0.0mV.

^CSA+VCS _ TOFST *GCSA +VOS _ EA

*G

=

+ 0.574*10⁻³*34 + 0.0mV

Io* R

L

130*0.60*10⁻³*34

7

A =

= 0.3984

n

B = VO _ NLOFST + Io* Ro −VOS _ EA = 15*10⁻³+130*1.20*10⁻³− 0.0mV = 0.1710

C = V^CS_TOFST*G^CSA+V^OS_EA= 0.574*10⁻³*34 + 0.0mV = 0.0.0195

D = VO _ NLOFST −VOS _ EA = 15*10⁻³− 0.0mV = 0.015

A* D − C * B

0.3984*0.015 − 0.0195*0.1710

VSETPT =

=

= 0.00494V

(A + B − C − D) 0.3984 + 0.1710 − 0.0195 − 0.015

VSETPT 0.00494

RVSETPT =

=

= 123.5ohms

40x10⁻⁶

IVSETPT

Choose the closest standard resistor value to this with 1% tolerance or RVESTPT = 124ohms.

Page 37 of 47

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IR3084U

Select RFB = 324 ohms and then calculate the droop resistor,

VSETPT + C

D −VSETPT

0.00494 + 0.0195

0.015 − 0.00494

RDRP = RFB ⋅

= 324⋅

= 787.1ohms

Choose the next standard value higher than this with 1% tolerance or RDRP = 787ohms.

Soft Start Capacitor C_SS/DELand Startup Times

Calculate the soft start capacitor from the required soft start time using Equation (9) with Boot Mode;

70*10⁻⁶*TD2

70*10⁻⁶*1.1*10⁻³

C_{SS / DEL}

=

= 0.0988uF or 0.1uF

RFB

324

⎛

⎞

⎟

⎛

⎞

⎟

VDAC ∗ 1−

1.1V * 1−

⎜

RFB + RDRP

324 + 787

⎝

⎠

⎝

⎠

The soft start delay time can be calculated using Equation (10) with Boot mode;

0.1*10⁻⁶

70*10⁻⁶

324

C_SS/DEL

RFB

⎛

⎝

⎞

⎟

⎛

⎝

⎞

⎟

TD1 =

∗ 1.3V +VDAC ∗

=

* 1.3V +1.1V *

⎜

I_CHG

RFB + RDRP

324 + 787

⎠

= 2.31ms

The VID sample time can be found using Equation (11);

0.1*10⁻⁶∗ 0.7

C_{SS / DEL}∗ 0.7V

TD3 =

=

= 1.00ms

70*10⁻⁶

I_CHG

The power good delay time can be found using Equation (12);

0.1*10⁻⁶*0.75V

C

_{SS / DEL}*0.75V

TD5 =

−TD4 =

− 73us = 0.998ms

70*10⁻⁶

I_CHG

Finally, use Equation (13) to calculate the over-current fault latch delay time;

0.1*10⁻⁶*100*10⁻³

C_{SS / DEL}*100mV

T_OCDEL

=

= 250us

40*10⁻⁶

Page 38 of 47

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IR3084U

Over Current Setting Resistor ROCSET

Assume that room temperature is 25ºC and the target PCB temperature is 100 ºC. The phase IC die temperature

is usually about 1 ºC higher than that of phase IC and the inductor temperature is close to PCB temperature.

Calculate the Inductor’s DC resistance at 100 ºC using Equation (14);

−6

R_{L_MAX}= R_{L_ROOM}∗[1+3850*10 ∗(T_{L_MAX}−T_ROOM)] =0.60*10⁻³∗[1+3850*10 ∗(100−25)] = 0.77mΩ

The current sense amplifier gain is 34 at 25ºC, and its gain at 101ºC is calculated using Equation (15),

G_{CS_MIN}= G_{CS_ROOM}∗ [1 − 1470*10 ⁻⁶∗(T_{IC_MAX}− T_ROOM)] = 34 ∗ [1 − 1470*10 ⁻⁶∗(101 − 25)] = 30.2

Here we will set the over current shutdown threshold to 155A at maximum operating temperature. From Figure

14 on page Error! Bookmark not defined., the bias current of the OCSET pin (IOCSET) is 42.5µA with

ROSC=30.1kΩ. The total current sense amplifier input offset voltage calculated previously is 0.574mV, which

includes the offset created by the current sense amplifier input resistor mismatch.

Calculate the constant KP, the ratio of inductor peak current over average current in each phase using Equation

(17);

(12 −1.18) ∗1.18/(220*10⁻⁹∗12 ∗ 400*10³∗ 2)

(V_I−V_O) ∗V_O/(L ∗V_I∗ f_SW∗ 2)

K_P=

=

= 0.273

I_LIMIT/ n

155/ 7

Finally, calculate the over-current setting resistor using Equation (16);

G_{CS _ MIN}

I_LIMIT

R_OCSET= [

∗ R_{L_MAX}∗(1+ K_P) +V_{CS_TOFST}] ∗

n

I_OCSET

155

30.2

42.5*10⁻³

= (

∗ 0.77 *10⁻³∗

(

1+ 0.273

)

+ 0.574 *10⁻³) ∗

= 15.8KΩ

7

Page 39 of 47

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IR3084U

IR3086 PHASE IC COMPONENTS

PWM Ramp Resistor RRAMP and Capacitor CRAMP

Set the PWM ramp magnitude VPWMRMP to 0.8V. Choose 220pF for the PWM ramp capacitor CPWMRMP and

calculate the resistor RPWMRMP using Equation (18);

V_O

R_PWMRMP

=

V_IN∗ f_SW∗C_PWMRMP∗ [ln(V_IN−V_DAC) − ln(V_IN−V_DAC−V_PWMRMP)]

1.30

=

= 15.8k Ω ,

3

−12

12 ∗ 400*10 ∗ 220*10

∗ [ln(12 − 1.30) − ln(12 − 1.30 − 0.8)]

Choose a standard resistor value, RPWMRMP=15.8kΩ.

Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCS−

Choose CCS+=47nF and calculate RCS+ using Equation (19);

220*10⁻⁹/(0.47 *10⁻³)

L R_L

R_CS+

=

= 10.0kΩ

47 *10⁻⁹

C_CS+

The bias currents of CSIN+ and CSIN− are 0.25uA and 0.4uA respectively. Calculate resistor RCS− using

Equation (20);

0.25

0.4

0.25

0.4

R_{CS −}

=

∗ R_{CS +}

=

∗10.0*10³= 6.2kΩ ,

choose RCS− = 6.19kΩ

Over Temperature Setting Resistors RHOTSET1 and RHOTSET2

Use central over temperature setting and set the temperature threshold at 115 ºC, which corresponds the IC die

temperature of 116 ºC. Calculate the HOTSET threshold voltage corresponding to the temperature thresholds

using Equations (21) and (22);

V_HOTSET= 4.73*10⁻³*T_J+1.241 = 4.73*10⁻³∗116 +1.241 =1.79V , choose RHOTSET1=20.0kΩ,

20*10³∗1.79

R_HOTSET1∗V_HOTSET

V_BIAS−V_HOTSET

R_{HOTSET 2}

=

= 7.14kΩ

6.8 −1.79

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IR3084U

Phase Delay Timing Resistors RPHASEx1 to RPHASEx2 (x=1,2,…,7)

The phase delay resistor ratios for phases 1 to 7 at 400kHz are (from the X−Phase Excel based design

spreadsheet); RAPHASE1=0.580, RAPHASE2=0.397, RAPHASE3=0.215, RAPHASE4=0.206,

RAPHASE5=0.353 RAPHASE6=0.5 and RAPHASE7=0.647.

Pre−select RPHASE11=RPHASE21=RPHASE31=RPHASE41=RPHASE51=RPHASE61=RPHASE71=20kΩ,

RA_PHASE1

0.58

R_PHASE12

=

∗ R_PHASE11

=

∗ 20*10³= 27.6kΩ

1− RA_PHASE1

1− 0.58

Calculating the other resistors from the same formula results in; RPHASE22=13.2kꢀ, RPHASE32=5.48kꢀ,

RPHASE42=5.2kꢀ, PPHASE52=10.9kꢀ, RPHASE62=20kꢀ, RPHASE72=36.6kꢀ.

Phase ICs 1−3 should have the RMPOUT voltage from the 3084 controller connected to their RMPIN− pin so

they will trigger on the negative slope of the RMPOUT waveform. Phase ICs 4−7 should have the RMPOUT

voltage from the 3084 controller connected to their RMPIN+ pin so they will trigger on the positive slope of the

RMPOUT waveform.

Bootstrap Capacitor CBST

Choose CBST=0.1uF.

Decoupling Capacitors for Phase IC and Power Stage

Choose CVCC=0.1uF, CVCCL=0.1uF

VOLTAGE LOOP COMPENSATION

AL−Polymer output capacitors are used in the design, for instructional purposes Type III compensation as shown

in Figure 18(b) will be demonstrated here. First, choose the desired crossover frequency as 1/10 of the switching

frequency, f_C=40 kHz, and determine Rcp and CCP using Equations (30) and (31):

(2π * f_C)²* L_E*C_E* R_FB*V_PWMRMP

(2π *40*10³)²*(220*10⁻⁹/ 7)*(560*10⁻⁶*10)*324*0.8

1.30 − 0.015−130*1*10⁻³

R_CP

=

V_o

= 2.49KΩ

10* (220*10⁻⁹/ 7)*(560*10⁻⁶*10)

2.49*10³

10* L_E*C_E

,

Choose CCP=56nF

C_CP

=

= 53nF

R_CP

1

R_FB1= * R_FB= *324 = 162Ω

Choose R_FB1=162ꢀ

2

1

Choose CFB=10nF

C_FB

=

= 12.3nF

4π *40*10³*162

4π * f_C* R_FB1

Choose CCP1=100pF to reduce high frequency noise.

Page 41 of 47

9/14/2005

IR3084U

CURRENT SHARE LOOP COMPENSATION

The crossover frequency of the current share loop (f_CI) should be at least one decade lower than that of the

voltage loop f_C. Choose the crossover frequency of current share loop f_CI=4kHz, and calculate FMI and CSCOMP

using Equations (34) and (35);

15.8*10³* 220*10⁻¹²* 400*10³*0.8

R

_PWMRMP*C_PWMRMP* f_SW*V _PWMRMP

F_MI

=

= 0.0105

(V_I−V_PWMRMP−V_DAC)*(V_I−V_DAC

)

(12 − 0.8 −1.30)*(12 −1.30)

0.65* R_PWMRMP*V_I* I_O*G_{CS _ ROOM}* R_LE*[1+ 2π * f_CI*C_E*(V_OI_O)]* F_MI

V_O* 2π * f_CI*1.05*10⁶

C_SCOMP

=

0.65*15.8*10³*12*130*34*(0.47*10⁻³7)*[1+ 2π *4*10³*5600*10⁻⁶*(1.30 −130*1.0*10⁻³) 130]*0.0105

(1.30 −130*1.0*10⁻³)*2π *4*10³*1.05*10⁶

=

36574*[2.266]*0.0105

30.859*10⁹

=

= 28.2nF

Choose CSCOMP=22nF with 5% tolerance for best current sharing between phases.

Page 42 of 47

9/14/2005

IR3084U

LAYOUT GUIDELINES

The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB

layout, therefore minimizing the noise coupled to the IC.

•

Dedicate at least one middle layer for a ground plane LGND.

Connect the ground tab under the control IC to LGND plane through a via.

Place the following critical components on the same layer as control IC and position them as close as

possible to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, CVCC, CSS/DEL and RCC/DEL. Avoid using any

via for the connection.

•

Place the compensation components on the same layer as control IC and position them as close as possible

to EAOUT, FB and VDRP pins. Avoid using any via for the connection.

Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing

over the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.

Control bus signals, VDAC, RMPOUT, IIN, VBIAS, and especially EAOUT, should not cross over the fast

transition nodes.

LGND PLANE

RSETPT

To VIN

CVCC

ROCSET

RVDAC

ROSC

LGND

REGFB

VSETPT

OCSET

VDAC

RVCC

REGDRV

GND

REGSET

SS/DEL

ROSC

RREGSET

CSS/DEL

VOSNS-

VRRDY

VID0

VID1

CVDAC

ENABLE

To Voltage

Remote Sense

To SYSTEM

Page 43 of 47

9/14/2005

IR3084U

METAL AND SOLDER RESIST

• The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The

solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all

Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD

pads.

• The minimum solder resist width is 0.13mm, therefore it is recommended that the solder resist is

completely removed from between the lead lands forming a single opening for each “group” of lead

lands.

• At the inside corner of the solder resist where the lead land groups meet, it is recommended to

provide a fillet so a solder resist width of ≥ 0.17mm remains.

• The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto

the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is

allowable to have the solder resist opening for the land pad to be smaller than the part pad.

• Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high

aspect ratio of the solder resist strip separating the lead lands from the pad land.

• The single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger

than the diameter of the via.

Page 44 of 47

9/14/2005

IR3084U

PCB METAL AND COMPONENT PLACEMENT

• Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing

should be ≥ 0.2mm to minimize shorting.

• Lead land length should be equal to maximum part lead length + 0.2 mm outboard extension +

0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and

the inboard extension will accommodate any part misalignment and ensure a fillet.

• Center pad land length and width should be equal to maximum part pad length and width. However,

the minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper

and ≥ 0.23mm for 3 oz. Copper)

• A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground

to minimize the noise effect on the IC.

Page 45 of 47

9/14/2005

IR3084U

STENCIL DESIGN

• The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.

Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for

0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made

narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release.

• The stencil lead land apertures should therefore be shortened in length by 80% and centered on the

lead land.

• The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit

approximately 50% area of solder on the center pad. If too much solder is deposited on the center

pad the part will float and the lead lands will be open.

• The maximum length and width of the land pad stencil aperture should be equal to the solder resist

opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to

the lead lands when the part is pushed into the solder paste.

Page 46 of 47

9/14/2005

IR3084U

PACKAGE INFORMATION

28L MLPQ (5 x 5 mm Body) – θ_JA= 30^oC/W, θ_JC= 3^oC/W

Data and specifications subject to change without notice.

This product has been designed and qualified for the Consumer market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.

www.irf.com

Page 47 of 47

9/14/2005


型号：	IR3084U
厂家：	Infineon
描述：	XPHASETM VR10, VR11 & OPTERON/ATHLON64 CONTROL IC XPHASETM VR10 ， VR11和OPTERON / ATHLON64控制IC
文件：	总47页 (文件大小：724K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IR3084U [INFINEON]

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