IR3519MTRPBF [INFINEON]
Buffer/Inverter Based MOSFET Driver, PDSO8, 3 X 3 MM, ROH COMPLIANT, MLPD-8;
| 型号： | IR3519MTRPBF |
| 厂家： | 
Infineon |
| 描述： | Buffer/Inverter Based MOSFET Driver, PDSO8, 3 X 3 MM, ROH COMPLIANT, MLPD-8 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总10页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IR3519
Synchronous MOSFET Gate Driver IC
FEATURES
DESCRIPTION
The IR3519 is extended voltage range high-speed gate
driver optimized for switching power supply
applications. Performance is achieved by 7V/2A gate
source and 5-A sink drive capability and is capable of
operating at frequencies of up to 2MHz.
7V/2A gate drivers (5A GATEL sink current)
15ns adaptive non-overlap control
Integrated boot-strap synchronous PFET
Supports 3.3V and 5V PWM input signals
Tri-State PWM input for power stage shutdown
The 0.4-Ω impedance of the lower gate driver holds the
Sub 50ns minimum pulse width supports 2MHz per-
gate of the Synchronous MOSFET below its threshold
to prevent shoot-through current during high dv/dt
phase node transitions.
phase operation
Dual function EN/UV pin provides Enable input and
power good output
The IR3519 includes a two-way enable/under voltage
power good signal. Systems without 3-state featured
controllers can use the EN/UV input/output to hold both
outputs low during converter shut down.
Small thermally enhanced 8L SON & 3 x 3mm MLPD
packages
RoHS compliant
APPLICATION CIRCUIT
ORDER INFORMATION
Device
Package
8 Lead MLPD (3 x 3 mm body)
Order Quantity
IR3519MTRPBF
* IR3519MPBF
IR3519STRPBF
* IR3519SPBF
3000 per reel
100 piece strips
2500 per reel
95 per tube
8 Lead MLPD (3 x 3 mm body)
8 Lead SON
8 Lead SON
* Samples only
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IR3519
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings (Referenced to GND)
BOOT Voltage: ................................................40 V
PH Voltage:..............-5V(100ns),-0.3V(DC) to 35 V
UGATE Voltage: ......-5V(100ns),-0.3V(DC) to 40 V
LGATE Voltage:.........-5V(100ns),-0.3V(DC) to 8 V
BOOT - PH Voltage: ............................ -0.3V to 8 V
UGATE - PH Voltage: .......................... -0.3V to 8 V
VDD: ..................................................................8 V
GND: .................................................. -0.3V to 0.3V
All other pins ........................................ -0.3V to 8 V
Operating Junction Temperature..-10°C to +150oC
MSL Rating ..................................................Level 2
Reflow Temperature …................................260oC
Storage Temperature Range.......... -65oC to 150oC
ESD Rating ......... HBM Class 1C JEDEC Standard
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
RECOMMENDED OPERATING CONDITIONS
6.5V≤ VDD ≤ 7.5V, 0 oC ≤ TJ ≤ 125 oC
ELECTRICAL SPECIFICATIONS
The electrical characteristics involve the spread of values guaranteed within the recommended operating
conditions. Typical values represent the median values, which are related to 25°C. CUGATE = 3.3nF, CLGATE = 6.8nF
(unless otherwise specified).
PARAMETER
Gate Drivers
UGATE Source Resistance BOOT – PH = 7V. Note 1
TEST CONDITION
MIN
TYP
MAX
UNIT
1.0
1.0
1.0
0.4
2.0
2.5
2.5
2.5
1.0
Ω
Ω
Ω
Ω
A
UGATE Sink Resistance
LGATE Source Resistance
LGATE Sink Resistance
UGATE Source Current
BOOT – PH = 7V. Note 1
VDD –GND = 7V. Note 1
VDD – GND = 7V. Note 1
BOOT=7V, UGATE=3.5V,
SW=0V. Note 1
UGATE Sink Current
LGATE Source Current
LGATE Sink Current
UGATE Rise Time
UGATE Fall Time
BOOT=7V, UGATE=3.5V,
SW=0V. Note 1
2.0
2.0
5.0
5
A
A
VDD=7V, LGATE=3.5V,
GND=0V. Note 1
VDD=7V, LGATE=3.5V,
GND=0V. Note 1
A
BOOT – PH = 7V, measure 1V
to 4V transition time.
ns
ns
ns
ns
BOOT - PH = 7V, measure 4V to
1V transition time.
5
LGATE Rise Time
LGATE Fall Time
VDD – GND = 7V, Measure 1V
to 4V transition time.
10
5
VDD – GND = 7V, Measure 4V
to 1V transition time.
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IR3519
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
LGATE low to UGATE high
delay
BOOT = VDD = 7V, PH =0V GND
= 0V, measure time from LGATE
falling to 1V to UGATE rising to
1V.
5
15
ns
UGATE low to LGATE high BOOT = VDD = 7V, PH =0V GND
5
15
ns
delay
= 0V, measure time from UGATE
falling to 1V to LGATE rising to
1V.
Minimum Pulse Width
Note 1
30
20
50
ns
Passive Gate Pull-Down
Resistance
kꢀ
PH Bias Current
Measure with PWM=Tri-state,
PH=1V
-2
-10
μA
VDD Under Voltage Lockout Comparator (VUVLO
)
Start Threshold
5.65
5.4
6.0
5.7
6.3
6.1
0.4
V
V
V
Stop Threshold
Hysteresis
Start – Stop
PWM Input
UGATE Threshold Voltage,
VUGATE TH
PWM rising
PWM falling
2.0
1.9
30
2.2
2.1
90
2.4
2.3
170
1.0
1.1
V
V
UGATE Threshold Voltage,
VUGATE TH
UGATE Threshold
Hysteresis
mV
V
LGATE Threshold Voltage,
VLGATE TH
PWM falling
PWM rising
0.6
0.74
0.8
0.9
LGATE Threshold Voltage,
VLGATE TH
V
LGATE Threshold Hysteresis
30
90
170
1.8
mV
V
Tri-State Bias voltage,
VPWM TRI
1.2
1.6
Input Bias Current
V(PWM) = 0V
V(PWM) = 3.3V
V(PWM) = 5V
-260
140
370
-210
200
460
190
-160
270
570
μA
μA
μA
ns
Tri-State Time Constant
CPWM = 20pF, Measure time from
V(PWM) = 0V release to LGATE
< 1V. Note 1
CPWM = 20pF, Measure time from
V(PWM) = 3.3V release to
HGATE < 1V. Note 1
270
380
ns
ns
CPWM = 20pF, Measure time from
V(PWM) = 5V release to HGATE
< 1V. Note 1
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IR3519
PARAMETER
EN/UV Input/Output
Threshold Voltage, VEN TH
TEST CONDITION
MIN
TYP
MAX
UNIT
EN/UV rising, UV FET off
EN/UV falling, UV FET off
1.1
0.6
1.75
1.1
2.0
1.4
V
V
Hysteresis
350
600
200
650
1000
350
800
1400
500
mV
ꢀ
Pull-down Resistance
Sink Current
VDD = 2.5V, V(EN/UV) = 0.6V
I(BOOT) = 30mA, VDD = 7V
μA
Bootstrap PFET
Forward Voltage
General
450
660
750
mV
VDD Supply Current
VDD Supply Current
EN = 0, PWM = Tri-State
50
100
uA
uA
EN = 3.3 V, PWM = Tri-State
700
1000
Note 1: Guaranteed by design, but not tested in production
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IR3519
IC PIN ORDER AND DESCRIPTION
NAME
UGATE
BOOT
PWM
NUMBER I/O LEVEL
DESCRIPTION
1
2
3
4
5
6
7
VIN + VDD
VIN +VDD
Up to 5V
Reference IC
VDD
High-side driver output and input to GATEL non-overlap comparator
Bootstrapped gate drive supply – connect a capacitor to PHASE
Logic input
GND
Power return – connect to source of synchronous MOSFET
Lower gate drive for synchronous MOSFET
IC bias supply
LGATE
VDD
Typical 7V
3.3V
EN/UV
Bias this pin to > 2V to enable and < 0.6V to disable the IC (both gate
outputs held low). If VDD is below the under voltage lockout
threshold this pin is internally pulled low and provides an input Power
Good indicator function. If the Power Good and Enable functions are
not required this pin can be connected to the VDD pin. Do not float
this pin as incorrect operation could occur.
PH
8
VIN
Return for high-side driver, reference for GATEL non-overlap
comparator, and input to the diode emulation comparator.
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IR3519
BLOCK DIAGRAM
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IR3519
V (0)⋅C = Q = V(t )⋅(C + C )
B
B
T
on
B
g
FUNCTIONAL DESCRIPTION
After rearranging this equation, it becomes the
equation below.
IR3519 switches the LGATE and UGATE signals
when VDD is greater than VUVLO and EN/UV voltage
is greater than VEN TH
.
V (0)
⎛
⎞
B
CB = Cg ⋅⎜
−1⎟
⎜
⎟
ΔV
⎝
⎠
The gate drive logic features adaptive dead time
which prevents simultaneous conduction of the upper
and lower MOSFETs. The lower gate voltage must
be below approximately 1V after PWM goes HIGH
and before the upper MOSFET can be gated on. Also
the upper gate voltage, the different voltage between
UGATE and PH, must be below approximately 1V
after PWM goes LOW and before the lower MOSFET
can be gated on.
Choose a boot capacitor value larger than the
calculated CB. The voltage rating of this part needs to
be larger than VB(0) plus the desired derating
voltage. Its ESR and ESL needs to be low in order to
allow it to deliver the large current and di/dt’s which
drive MOSFETs most efficiently. In support of these
requirements a ceramic capacitor should be chosen.
The LGATE logic evaluates its input signal and
generates a GND referenced to drive the LGATE pin,
which turns on/off the external low side MOSFET.
The LGATE logic uses VDD source to turn on the low
side MOSFET because the source of low side
MOSFET is reference to GND.
The internal logic will evaluate the PWM voltage
level. The PWM is considered HIGH when its level is
greater than VUGATE TH. PWM is considered LOW
when its level is below VLGATE TH. In the middle
voltage region of VUGATE TH and VLGATE TH, the PWM
will be in tri-state mode. In the absence of external
drive, the PWM pin is pulled to this middle region by
a VPWM TRI source through an internal resistor. After a
short time delay in this middle region, IR3519 is
forced into a low power state.
LAYOUT RECOMMENDATION
One 1uF high quality ceramic capacitor is required to
place near VDD pin as possible. Other end of
capacitor is recommended to tie to GND pin plan as
close to as IC possible. This GND island plan can be
via or directly connect to the main GND plan or layer.
If the connection of GND pin to the source of low side
MOSFET through an internal layer, it is
The UGATE logic evaluates its input logic signal and
generates a PH referenced to drive the UGATE pin,
which turns on/off the external high side MOSFET.
PH pin is to be connected to the source of the upper
MOSFET, the buck inductor, and to the drain of the
lower MOSFET. To turn on the upper N channel
MOSFET, a bootstrap circuit is required. This is
accomplished by charging a capacitor (connected
BOOT to PH) after the lower MOSFET conducts and
the PH pin is substantially at GND. VDD provides the
charging current through an internal BOOTSTRAP
diode. The minimum boot capacitor value is
calculated below.
recommended connecting through at least 2 vias by
build a small island of next to GND pin. The boot
capacitor needs to place close to BOOT and PH pins
to reduce the impedance during the turn-on process
of high side MOSFET. The main function of boot
capacitor is to supply the energy for turning on high
side MOSFET. It is recommended to add zero Ohm
resistor in series with boot capacitor as place holder.
When connecting the trace for UGATE and LGATE
signals, one needs to keep in mind that the signal
return path is as an important as signal path.
The return path contains both AC and DC current.
DC current takes the least resistance path. AC
current takes the least impedance path. The return
path is exits whether or not provide it. If the designer
is overlooked the return path, the AC current will
cause the more noise in the system. Therefore, it is
recommended to place LGATE signal path on top
next to the source of low side MOSFET path and
place UGATE signal path on top of PH signal path.
When connecting PHASE signal path to power stage
area, PHASE signal needs to chose quite area.
Figure 1 shows the location of connection from power
stage to IR3519 PHASE pin less noise sensitive than
Figure 2.
The boot capacitor starts the cycle fully charged to a
voltage of VB(0). An equivalent gate drive
capacitance is calculated by consulting the high side
MOSFET data sheet and taking the ratio of total gate
charge at the VDD voltage, QG(VDD), to the VDD
voltage. QG(VDD)/VDD is the equivalent gate drive
capacitance Cg which will be used in the following
calculations. The voltage of the capacitor pair CB and
Cg after Cg becomes charged at CB’s expense will be
VB(0)-ΔV. Choose a sufficiently small ΔV such that
VB(0)-ΔV exceeds the maximum gate threshold
voltage to turn on the high side MOSFET. Since total
charge QT is conserved, we can write the following
equation.
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IR3519
PH
PH
Figure 1: Phase Node Sense with Less Noise
PH
PH
Figure 2: Phase Node Sense with More Noise
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IR3519
PACKAGE INFORMATION
3 X 3MM MLPD
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IR3519
8L SON
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 05/07
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