IR3742_15 [INFINEON]
20A Integrated PowIRstage;
| 型号： | IR3742_15 |
| 厂家： | 
Infineon |
| 描述： | 20A Integrated PowIRstage |
| 文件： | 总26页 (文件大小：1165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
20A Integrated PowIRstage®
IR3742
FEATURES
DESCRIPTION
The IR3742 integrated PowIRstage® is a synchronous
buck gate driver IC with co-packed control and
synchronous MOSFETs and Schottky diode. It is
optimized internally for PCB layout, heat transfer and
driver/MOSFET timing. Custom designed gate driver
and MOSFET combination enables higher efficiency at
lower output voltages required by cutting edge ASIC,
FPGA and advanced controller.
Single input voltage range from 5V to 21V
Wide input voltage range from 1.0V to 21V with
external VCC bias voltage
Integrated MOSFET drivers, Control FET,
Synchronous FET with Schottky diode,
bootstrap diode and the internal LDO
Enable input with voltage monitoring capability
Logic Level Tri-state PWM input
Up to 1.5MHz switching frequency enables high
Thermally compensated Over Current Indicator
performance
transient
response,
allowing
miniaturization of output inductors, as well as input and
output capacitors while maintaining industry leading
efficiency. The IR3742’s superior efficiency enables
smallest size and lower solution cost.
Open-drain over temperature and over current
fault indication
Under-voltage Lockout of VCC/LDO_Out
Operating temp: -40°C < Tj < 125°C
Package size: 5mm x 6mm PQFN
The IR3742 includes an over current indicator and over
temperature indicator in the event of a fault condition.
RoHS6 Compliant, lead-free and halogen-free
APPLICATIONS
Computing Applications
Set Top Box Applications
Storage Applications
Data Center Applications
Distributed Point of Load Power Architectures
ORDERING INFORMATION
Standard Pack
Base Part Number
IR3742
Package Type
Orderable Part Number
Form
Quantity
4000
PQFN 5 mm x 6 mm
Tape and Reel
IR3742MTRPBF
IR3742
PBF
TR
M
Lead Free
Tape and Reel
Package Type
1
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IR3742
BASIC APPLICATION
Vin
92
90
88
86
84
82
80
78
Vin PVin
Enable
Boot
SW
Vo
IR3742
Vcc /
PWM
VCC
Fault
LDO_out
OC_En
Fault
0
5
10
Iout [A]
15
20
NC Gnd PGnd
Figure 1: IR3742 Basic Application Circuit
Figure 2: IR3742 Efficiency –
PVin=Vin=12V, Vout=1.2V, Fs=300kHz, L=470nH
[DCR=0.165mOhm]
PINOUT DIAGRAM
Figure 3: 5mm x 6mm PQFN (Top View)
2
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IR3742
BLOCK DIAGRAM
10
14
Vcc/LDO_Out
VCC
6.8V Internal
LDO
Vin
9
Boot
UVcc
3.3V
UVcc
5.1kΩ
13
PVin
6
PWM
5.1kΩ
HDrv
DRIVER
Gnd
Gnd
4
PWM LOGIC
and
DEAD-TIME
CONTROL
17
12 SW
VCC
UVcc
LDrv
POR
DRIVER
UVEN
15
7
Enable
Fault
11 PGnd
POR
TSD
OC
THERMAL FAULT
DETECTION
3.3V
R
S
FAULT
Q
100kΩ
CONTROL
FAULT
OVER CURRENT
DETECTION
5
OC_En
Figure 4: Simplified Block Diagram
3
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IR3742
PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
1, 2, 3, 8,
16
NC
Must be connected to signal ground on the PCB layout.
Signal ground for internal reference and control circuitry.
4, 17
5
Gnd
Over current detection enable pin. Floating this pin enables the over current detection.
Shorting this pin to GND disables the over current detection.
OC_En
Logic level tri-state PWM input. “High” turns the control MOSFET on, and “Low” turns the
synchronous MOSFET on. “Tri-state” turns both MOSFETs off.
6
7
PWM
Fault
Open-drain fault indication. Connect a pull-up resistor from this pin to Vcc. Fault pin stays
high when VCC/LDO_Out or Enable voltage is below their thresholds. In normal
operation, Fault pin stays high. When over temperature or over current occurs, Fault pin is
latched low. Recycle Vcc or Enable to reset.
Input for internal LDO. A 1.0µF capacitor should be connected between this pin and
PGnd. If an external supply is connected to Vcc/LDO_out pin, this pin should be shorted
to Vcc/LDO_out pin.
9
Vin
Output of the internal LDO and optional input of an external biased supply voltage. A
minimum 2.2µF ceramic capacitor is recommended between this pin and PGnd.
10
Vcc/LDO_Out
Power Ground. This pin serves as a separated ground for the MOSFET drivers and
should be connected to the system’s power ground plane.
11
12
PGnd
SW
Switch node. Connect this pin to the output inductor.
Input voltage for power stage.
13
PVin
Supply voltage for high side driver, a 100nF capacitor should be connected between this
pin and SW pin.
14
15
Boot
Enable pin to turn on and off the device. Input voltage monitoring (input UVLO) can also
be implemented by connecting this pin to PVin pin through a resistor divider.
Enable
4
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IR3742
ABSOLUTE MAXIMUM RATINGS
Stresses beyond these listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
PVin, Vin to PGnd (Note 4)
Vcc/LDO_Out to PGnd (Note 4)
Boot to PGnd (Note 4)
SW to PGnd (Note 4)
-0.3V to 25V
-0.3V to 8V (Note 1)
-0.3V to 33V
-0.3V to 25V (DC), -VCC for 20ns (AC)
-0.3V to VCC + 0.3V (Note 2)
-0.3V to VCC + 0.3V (Note 2)
-0.3V to 5V
Boot to SW
Fault to Gnd (Note 4)
PWM, to Gnd
Enable, OC_En to Gnd (Note 4)
PGnd to Gnd
-0.3V to +3.9V
-0.3V to +0.3V
THERMAL INFORMATION
Junction to Ambient Thermal Resistance ƟjA
30 °C/W (Note 3)
Junction to PCB Thermal Resistance Ɵj-PCB
2 °C/W
Storage Temperature Range
-55°C to 150°C
Junction Temperature Range
-40°C to 150°C
Note 1: Vcc must not exceed 7.5V for Junction Temperature between -10°C and -40°C.
Note 2: Must not exceed 8V.
Note 3: Based on a 4-layer PCB board (2.23”x2”) using 2 oz. copper on each layer.
Note 4: PGnd pin and Gnd pin are connected together.
5
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IR3742
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
SYMBOL
MIN
MAX
UNITS
Input Voltage Range with External Vcc Note 5, Note 7
Input Voltage Range with Internal LDO Note 6, Note 7
Supply Voltage Range (Note 6)
PVin
1.0
5.5
4.5
4.5
0
21
21
Vin, PVin
V
VCC
7.5
7.5
20
Supply Voltage Range (Note 6)
Boot to SW
Output Current Range
I0
A
Switching Frequency
FS
TJ
300
-40
1500
125
kHz
°C
Operating Junction Temperature
Note 5: Vin is connected to Vcc to bypass the internal LDO.
Note 6: Vin is connected to PVin. For single-rail applications with PVin=Vin <7.4V, the internal LDO may operate in dropout mode. Please
refer to the application information of the Internal LDO and the Over Current Protection.
Note 7: Maximum SW node voltage should not exceed 25V.
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, these specifications apply over, 7.4V < Vin = PVin < 21V, 0°C < TJ < 125°C. Typical values are
specified at Ta = 25°C.
PARAMETER
Power Stage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PVin = Vin = 12V, Vo = 1.2V,
Io = 20A, Fs = 600kHz, L =
0.3uH, Note 8
4.98
8
W
Power Losses
PLOSS
VBOOT –Vsw = 6.8V, Io = 20A,
Tj = 25°C
Top Switch RDS(ON)
RDS(on)-T
10.4
5.2
mΩ
Vcc = 6.8V, Io = 20A,
Tj = 25°C
Bottom Switch RDS(ON)
RDS(on)-B
VFWD
4
Bootstrap Diode Forward
Voltage
I(Boot) = 15mA
200
2.5
370
550
1
mV
VSW = 0V, Enable = 0V
Note 8
µA
ns
ISW
TD
SW Leakage Current
Dead Band Time
10
PWM Comparator
PWM Input High Threshold
VPWM-HIGH
PWM Tri-State to High
V
PWM Input Low Threshold
PWM Tri-State Float Voltage
VPWM-LOW
VPWM-TRI
PWM Tri-State to Low
PWM Floating
0.8
1.8
V
V
1.35
0.1
1.65
0.2
Active to Tri-state or Tri-state
to Active, Note 8
Hysteresis
VPWM-HYS
0.3
V
6
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IR3742
ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, these specifications apply over, 7.4V < Vin = PVin < 21V, 0°C < TJ < 125°C. Typical values are
specified at Ta = 25°C.
PARAMETER
SYMBOL
TPWM-DELAY
RPWM-SINK
CONDITIONS
MIN
TYP
MAX
UNITS
PWM Tri-state to low
transition of SW node, Note 8
19.8
36.4
ns
ns
Tri-State Propagation Delay
PWM Sink Impedance
PWM Tri-state to high
transition of SW node, Note 8
PWM = 3.3V
3.57
3.57
4.8
6.63
6.63
kΩ
PWM Source Impedance
Internal Pull Up Voltage
Minimum Pulse Width
RPWM-SOURCE
VPWM-PULLUP
TPWM-MIN
PWM = GND
Vcc > UVLO
Note 8
4.8
3.3
41
kΩ
V
58
ns
Supply Current
Vin Supply Current
(standby)
EN = Low, No Switching
Iin(Standby)
Iin(Dyn)
125
23
µA
Vin Supply Current
(dynamic)
EN = High, Fs = 600kHz,
Vin = PVin = 21V
20
mA
VCC/LDO_Out
Vin(min) = 7.4V, Io = 0-50mA,
Cload = 2.2uF; EN = High
Output Voltage
Vcc
6.5
6.8
7.0
V
Vin=6.5V,Io=50mA,
Cload=2.2uF
LDO Dropout Voltage
Short Circuit Current
Vcc_drop
Ishort
0.88
V
EN = High
70
mA
Under-Voltage Lockout
Vcc-Start Threshold
VCC UVLO
Start
Vcc rising trip Level
Vcc falling trip Level
ramping up
3.9
3.5
4.15
3.86
1.19
0.93
4.4
4.1
V
V
V
Vcc-Stop Threshold
VCC UVLO
Stop
Enable-Start-Threshold
Enable-Stop-Threshold
Enable Leakage Current
Enable UVLO
Start
1.13
0.85
1.27
Enable UVLO
Stop
ramping down
Enable = 3.3V
1.1
1
V
IEN_LK
µA
7
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IR3742
ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, these specifications apply over, 7.4V < Vin = PVin < 21V, 0°C < TJ < 125°C. Typical values are
specified at Ta = 25°C.
Fault
Over Current Limit
ILIMIT
TTSD
VFAULT
OCDISABLE
Tj = 25°C
Note 8
29
35
41
A
°C
V
Over Temperature
Threshold
145
Fault Voltage Low
IFAULT = -5mA
Note 8
0.5
0.8
OC_EN Fault Disable
Threshold
V
Note 8: Guaranteed by design, but not tested in production.
8
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IR3742
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
Test Conditions: PVin=Vin=12V, VCC=6.8V, Vout = 1.2V, L=470nH, Switching Frequency = 300kHz, TA=25°C
and natural convention cooling unless otherwise noted.
5.0
4.0
3.0
2.0
1.0
0.0
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
L = 215nH
L = 215nH
3.3V
1.8V
1.2V
1.0V
0
5
10
15
20
0
500
1000
1500
Iout [A]
Frequency [kHz]
Figure 5: Power Loss vs. Output Current
Figure 6: Power Loss vs. Switching Frequency
1.25
7.0
VCC = 5V, L = 470nH, Fs = 300kHz
L=215uH
1.20
6.5
6.0
5.5
5.0
1.15
1.10
1.05
1.00
0.95
0.90
5
10
15
20
25
4
5
6
7
8
Vin=PVin [V]
VCC [V]
Figure 7: Power Loss vs. Input Voltage
Figure 8: Power Loss vs. Driver Supply Voltage
6.850
50
45
40
35
30
25
20
15
10
5
Vin = VCC; Iout = 0A
T = 25°C; Iout = 0A
6.825
6.800
6.775
6.750
6.725
6.700
VCC = 7V
VCC = 5V
0.00 0.25 0.50 0.75 1.00 1.25 1.50
0.00 0.25 0.50 0.75 1.00 1.25 1.50
Frequency [MHz]
Frequency [MHz]
Figure 9: VCC vs. Frequency
Figure 10: Driver Supply Current vs. Switching
Frequency
9
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IR3742
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
Test Conditions: PVin=Vin=12V, VCC=6.8V, Vout = 1.2V, L=470nH, Switching Frequency = 300kHz, TA=25°C
and natural convention cooling unless otherwise noted.
12.5
12.0
11.5
11.0
10.5
10.0
9.5
1.05
1.00
0.95
0.90
L = 470nH, Fs = 300kHz
L = 470nH
Fs = 1MHz
Fs = 300kHz
9.0
0
5
10
15
20
4
5
6
7
8
Iout [A]
VCC [V]
Figure 11: Driver Supply Current vs. Driver Supply
Voltage
Figure 12: Normalized Driver Supply Current vs.
Output Current
4.2
2.50
VPWM_HI
2.25
4.1
VVCC_UVLO_START
VPWM_HI
2.00
VPWM_HZ
4.0
3.9
1.75
1.50
VPWM_LT
1.25
3.8
VPWM_LO
VVCC_UVLO_STOP
1.00
0.75
0.50
3.7
3.6
4
5
6
7
8
-40 -20 0 20 40 60 80 100 120 140
VCC [V]
Temperature [ºC]
Figure 13: UVLO Threshold vs. Temperature
Figure 14: PWM Threshold vs. Driver Supply Voltage
2.50
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
VPWM_HI
2.25
VPWM_HI
2.00
VEN_UVLO_START
VPWM_HZ
1.75
1.50
VPWM_LT
1.25
VPWM_LO
1.00
0.75
0.85
0.80
VEN_UVLO_STOP
0.50
-40 -20 0 20 40 60 80 100 120 140
4
5
6
7
8
Temperature [ºC]
VCC [V]
Figure 15: PWM Threshold vs. Temperature
Figure 16: EN Threshold vs. VCC Voltage
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IR3742
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
Test Conditions: PVin=Vin=12V, VCC=6.8V, Vout = 1.2V, L=470nH, Switching Frequency = 300kHz, TA=25°C
and natural convention cooling unless otherwise noted.
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VEN_UVLO_START
VEN_UVLO_STOP
-40 -20 0 20 40 60 80 100120140
-40 -20
0
20 40 60 80 100 120 140
Temperature [ºC]
Temperature [ºC]
Figure 17: EN Threshold vs. Temperature
Figure 18: Boot Diode Forward Voltage vs.
Temperature
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IR3742
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
Test Conditions: PVin=Vin=12V, VCC=6.8V, Vout = 1.2V, L=470nH, Switching Frequency = 300kHz, TA=25°C
and natural convention cooling unless otherwise noted.
Figure 19: Switching Waveform, Iout = 0A
Figure 20: Switching Waveform, Iout = 10A
Figure 21: Switching Waveform, Iout = 20A
Figure 22: PWM to SW Delay, Iout = 10A
Figure 23: PWM Tri-state Delay, Iout = 10A
Figure 24: PWM Tri-state Delay, Iout = 10A
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IR3742
THEORY OF OPERATION
the bus voltage UVLO. It prevents the IR3742 from
regulating at PVin lower than the desired voltage
level. Figure 26 shows the start-up waveform with
the input UVLO voltage set at 10V.
DESCRIPTION
The IR3742 PowIRStage® is a synchronous buck
driver with co-packed MOSFETs with integrated
Schottky diode, which provices system designers
with ease of use and flexibility required in medium
current low-profile applications.
PVin
The IR3742 is designed to work with a PWM
controller. The IR3742 PWM input is compatible
with 3.3V logic signal and 7V tolerant. It accepts 3-
level PWM input signals with tri-state.
R1
R2
IR3742
Enable
The IR3742 provides a fault indicator that monitors
over current events and over temperature events.
UNDER-VOLTAGE LOCKOUT AND POR
Figure 25: Implementation of Input Under-
Voltage Lockout (UVLO) using Enable Pin
The Power On Ready (POR) circuit monitors the
voltage of VCC/LDO_Output pin and the Enable pin.
It assures that the MOSFET driver outputs remain
off whenever either of these two signals is below the
set thresholds. The POR signal is generated when
all these signals reach the valid logic level (see
system block diagram). Normal operation resumes
once both VCC/LDO_Output and Enable voltages rise
above their thresholds.
12V
10V
PVin
Vcc
> 1.2V
1.2V
Enable Threshold
Enable
ENABLE/EXTERNAL PVIN MONITOR
The IR3742 has an Enable function providing
another level of flexibility for start-up. The Enable pin
has a precise threshold which is internally monitored
by Under-Voltage Lockout (UVLO) circuit. If the
voltage at Enable pin is below its UVLO threshold,
both high-side and low-side FETs are off. When
Enable pin is below its UVLO, and Fault stays low.
Intl_SS
Vout
Figure 26: Illustration of start-up with PVin UVLO
threshold voltage of 10V. The internal soft-start
is used in this case.
The Enable pin should not be left floating. A pull-
down resistor in the range of several kilo-ohms is
recommended to between the Enable Pin and
ground.
INTERNAL LDO
The IR3742 has an internal Low Dropout Regulator
(LDO), offering 6.8V. 6.8 VCC voltage results in
higher full load efficiency due to less conduction
loss.
In addition to being a logical input, the Enable pin
can help form a precise input voltage UVLO. As
shown in Figure 25, the input of the Enable pin is
derived from the PVin voltage by a resistive divider,
R1 and R2. By selecting different divider ratios,
users can program the UVLO threshold voltage for
The internal LDO is beneficial for single rail (supply)
applications, where no external bias supplies will be
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IR3742
Ext VCC
4.5V-7.5V
needed. For these applications, Vin pin should be
connected to PVin and VCC/LDO_Out pin is left
floating as shown in Figure 27. 1.0μF and 2.2μF
ceramic bypass capacitors should be placed close to
Vin pin and VCC/LDO_Out pin respectively.
Input =1.0V-21V
Vin PVin
IR3742
VCC/
LDO_OUT
Input =7.4V-21V
2.2uF
PGnd
1.0uF
Vin PVin
IR3742
VCC/
LDO_OUT
Figure 29: Use External Bias Voltage
PWM TRI-STATE INPUT
2.2uF
PGnd
The IR3742 PWM accepts 3-level input signals.
When PWM input is high, the synchronous MOSFET
is turned off and the control MOSFET is turned on.
When the PWM input is low, control MOSFET is
turned off and synchronous MOSFET is turned on.
Figure 19 - Figure 24 show the PWM input and the
corresponding SW output of the IR3742. If PWM pin
is floated, the built-in resistors pull the PWM pin into
a tri-state region centered about 1.65V.
Figure 27: Internally Biased Single-Rail
Configuration
VCC/LDO_Out pin can be directly connected to the
PVin pin to bypass the internal LDO and therefore to
avoid the voltage drop on the internal LDO. This
configuration is illustrated in Figure 28.
OVER CURRENT INDICATOR AND OC_EN
Figure 29 shows the configuration using an external
VCC voltage. With this configuration, the input voltage
range can be extended down to 1.0V.
The over current indication monitors the current
through the Synchronous MOSFET using RDS(on)
sensing. This method enhances the converter’s
efficiency and reduces cost by eliminating a current
sense resistor and any layout related noise issues.
The current limit is pre-set internally and is
compensated according to the IC temperature. So at
different ambient temperature, the over-current
threshold remains almost constant.
It should be noted as the VCC voltage decreases, the
efficiency and the over current limit will decrease
due to the increase of RDS(ON). Please refer to the
section of the over current protection for more
information.
Input =4.5V-7.5V
Over current is measured at the valley of the
inductor current. Over current events are flagged
after PWM goes high and the internal LDrv signal
goes low. The drivers follow the PWM signal even
when an over current event is detected and/or the
Fault indicator is set.
1.0uF
Vin PVin
IR3742
VCC/
LDO_OUT
2.2uF
PGnd
OC_en signal enables the over current fault indicator
functionality. IR3742 pulls Fault low when an over
current event is detected, if OC_en is set high. If a
fault is set, toggling OC_en does not reset the Fault
signal.
Figure 28: Single-Rail Configuration for 4.5V-7V
inputs
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IR3742
The switch node also has a minimum pulse width.
The minimum pulse is the shortest amount of time
which Ctrl FET may be reliably turned on.
40
35
30
25
20
15
10
5
VCC = 6.8V
VCC = 4.5V
Any design or application using IR3742 must ensure
operation with a pulse width that is longer than this
minimum on-time and preferably higher than 70ns.
This is necessary for the circuit to operate without
jitter and pulse-skipping, which can cause high
inductor current ripple and high output voltage ripple.
0
-40 -20 0 20 40 60 80 100 120 140
Vout
D
ton
Temperature [ºC]
Fs Vin Fs
Figure 30: OC Indicator Threshold over
temperature
In any application that uses IR3742, the following
condition must be satisfied:
ton(min) ton
THERMAL FAULT INDICATOR
Temperature sensing is provided inside IR3742. The
trip threshold is typically set to 145ºC. When trip
threshold is exceeded, the open drain fault pin pulls
low. The driver will continue switching if a PWM
signal is applied and the part is enabled. The fault
pin remains low until Enable is pulled low or
VCC_UVLO_STOP is triggered.
Vout
Vout
ton(min)
, therefore, Vin Fs
Vin Fs
ton(min)
The minimum output voltage is limited by the
reference voltage and hence Vout(min) = 0.6 V.
Therefore,
FAULT OUTPUT
Vout(min)
0.6V
70ns
Vin Fs
8.57V / s
The Fault signal is an open drain signal that requires
an external pull up resistor. High state indicates no
over current event occurred and no over
temperature events were detected. The Fault signal
is an indicator that does not prevent the driver from
following the PWM signal when set.
ton(min)
Therefore, at the maximum recommended input
voltage 21V and minimum output voltage, the
converter should be designed at a switching
frequency that does not exceed 408 kHz.
Conversely, at the maximum switching frequency
(1.5 MHz) and minimum output voltage (0.6V), the
input voltage (PVin) should not exceed 5.7V,
otherwise pulse skipping will happen.
Clearing or resetting the Fault signal requires the
toggling of the Enable signal or toggling the
VCC_UVLO. Fault remains low after setting until it
is reset with Enable or VCC.
MAXIMUM DUTY RATIO
MINIMUM SWITCH PULSE AND PWM PULSE
CONSIDERATIONS
The maximum duty ratio for the IR3742 is
determined by the Toff time. Each cycle requires the
gate to be turned off for a minimum of 250nS. This
provides an upper limit on the operating duty ratio.
IR3742 is designed to operate from 300 kHz to 1.5
MHz. implying maximum duty cycles of 92.5% and
62.5% respectively.
PWM pulses control the switching of the converter in
normal operation. However, the IR3742 blanks
PWM pulses that are too short. To avoid blanking
PWM pulses, ensure the minimum PWM pulse is
greater than 70nS.
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IR3742
DESIGN EXAMPLE
The following example is a typical application for
IR3742. The application circuit is shown in Figure 1.
diode. The voltage, Vc, across the bootstrap
capacitor C1 can be calculated as
PVin = Vin = 12V (±10%)
Vo = 1.2V
VC VCC VD
where VD is the forward voltage drop of the
bootstrap diode.
Io = 20A
Peak-to-Peak Ripple Voltage = ±1% of Vo
ΔVo = ± 4% of Vo (for 30% Load Transient)
Fs = 300 kHz
When the control FET turns on in the next cycle, the
SW node voltage rises to the bus voltage, PVin. The
voltage at the Boot pin becomes:
VBOOT PV VCC VD
in
EXTERNAL PVIN MONITOR (INPUT UVLO)
As explained in the section of Enable/External PVin
monitor, the input voltage, PVin, can be monitored by
connecting the Enable pin to PVin through a set of
resistor divider. When PVin exceeds the desired
voltage level such that the voltage at the Enable pin
exceeds the Enable threshold, 1.2V, the IR3742 is
turned on. The implementation of this function is
shown in Figure 25.
A good quality ceramic capacitor of 0.1μF with
voltage rating of at least 25V is recommended for
most applications.
VIN
Cvin
+ VD
-
Boot
For a typical Enable threshold of VEN = 1.2 V
V
cc
+
Vc
-
R2
C1
PVin(min)
VEN 1.2
R1 R2
SW
L
VEN
PVin(min) VEN
R2 R
1
PGnd
For the minimum input voltage PVin (min) = 9.2V,
select R1=49.9kΩ, and R2=7.5kΩ.
Figure 31: Bootstrap circuit to generate the
supply voltage for the high-side driver voltage
BOOTSTRAP CAPACITOR SELECTION
INPUT CAPACITOR SELECTION
To drive the Control FET, it is necessary to supply a
gate voltage at least 4V greater than the voltage at
the SW pin, which is connected to the source of the
Control FET. This is achieved by using a bootstrap
configuration, which comprises the internal bootstrap
diode and an external bootstrap capacitor, C1, as
shown in Figure 31. The operation of the circuit is as
follows: When the sync FET is turned on, the
capacitor node connected to SW is pulled low. VCC
starts to charge C1 through the internal bootstrap
Good quality input capacitors are necessary to
minimize the input ripple voltage and to supply the
switch current during the on-time. The input
capacitors should be selected based on the RMS
value of the input ripple current and requirement of
the input ripple voltage.
The RMS value of the input ripple current can be
calculated as follows:
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IR3742
INDUCTOR SELECTION
IRMS Io D(1 D)
The inductor is selected based on output power,
operating frequency and efficiency requirements. A
low inductor value causes large ripple current,
resulting in the smaller size, faster response to a
load transient but poor efficiency and high output
noise. Generally, the selection of the inductor value
can be reduced to the desired maximum ripple
current in the inductor (Δi). The optimum point is
usually found between 20% and 40% ripple of the
output current.
Where D is the duty cycle and Io is the output
current. For Io=20A and D=0.1, IRMS= 6A
The input voltage ripple is the result of the charging
of the input capacitors and the voltage induced by
ESR and ESL of the input capacitors.
Ceramic capacitors are recommended due to their
high ripple current capabilities. They also feature low
ESR and ESL at higher frequency which enables
better efficiency.
The saturation current of the inductor is desired to
be higher than the over current limit plus the inductor
ripple current. An inductor with soft-saturation
characteristic is recommended.
For this application, it is suggested to use three
22μF/25V ceramic capacitors, C3216X5R1E226M,
from TDK. In addition, although not mandatory, a
1x330uF, 25V SMD capacitor EEE-FK1E331P from
Panasonic may also be used as a bulk capacitor and
is recommended if the input power supply is not
located close to the converter.
For the buck converter, the inductor value for the
desired operating ripple current can be determined
using the following relation:
iLmax
t
D
Fs
PVinmax Vo L
;
t
HIGH OUTPUT VOLTAGE DESIGN
CONSIDERATION
When using IR3742 for higher voltage levels, the
design should consider maximum duty cycle, power
loss and current sensing. Power loss and thermals
need to be accounted for when running high loads.
Vo
Vin iLmax Fs
L (PVinmax Vo )
Where:
PVinmax = Maximum input voltage
V0 = Output Voltage
The maximum output voltage is limited by the
required off time. When selecting the switching
frequency and output voltage, each cycle should
never have less than 250nS off time. IR3742 can
reach higher output voltages at lower switching
frequencies since the required off time is a smaller
percentage at slower frequencies.
ΔiLmax = Maximum Inductor Peak-to-Peak
Ripple Current
Fs
Δt
D
= Switching Frequency
= On time
= Duty Cycle
IR3742 can provide high output voltages, but may
require an external cooling. When running high
output voltage or higher current rails, care should be
taken to ensure the part is adequate cooled.
Select ΔiLmax ≈ 35%×Io, then the output inductor is
calculated to be 0.51 μH. Select L=0.47 μH,
744309047, from Wurth Electronics which provides
an inductor suitable for this application.
Inductor current sensing range needs to be
addressed. Depending on the controller and current
sense methodology, the input range of the current
sense circuit maybe a limiting factor on the
maximum output voltage.
OUTPUT CAPACITOR SELECTION
Output capacitors are usually selected to meet two
specific requirements: (1) Output ripple voltage and
(2) load transient response. The load transient
response is also greatly affected by the control
bandwidth. So it is common practice to select the
output capacitors to meet the requirements of the
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IR3742
output ripple voltage first, and then design the
control bandwidth to meet the transient load
response. For some cases, even with the highest
allowable control bandwidth, the resulting load
transient response still cannot meet the requirement.
The number of output capacitors then need to be
increased.
Where ΔiLmax is maximum inductor peak-to-peak
ripple current.
Good quality ceramic capacitors are recommended
due to their low ESR, ESL and the small package
size. It should be noted that the capacitance of
ceramic capacitors are usually de-rated with the DC
and AC biased voltage. It is important to use the de-
rated capacitance value for the calculation of output
ripple voltage as well as the voltage loop
compensation design. The de-rated capacitance
value may be obtained from the manufacturer’s
datasheets.
The voltage ripple is attributed by the ripple current
charging the output capacitors, and the voltage drop
due to the Equivalent Series Resistance (ESR) and
the Equivalent Series Inductance (ESL). Following
lists the respective peak-to-peak ripple voltages:
In this case, three 22uF ceramic capacitors,
C2012X5R0J226M, from TDK are used to achieve
±12mV peak-to-peak ripple voltage requirement. The
de-rated capacitance value with 1.2VDC bias and
10mVAC voltage is around 18uF each.
iLmax
8Co Fs
Vo(C)
Vo(ESR) iLmax ESR
PVin V
Vo(ESL) (
o ) ESL
L
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IR3742
LAYOUT RECOMMENDATIONS
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to
perform with worse than expected results.
The critical bypass components such as capacitors
for Vin and VCC should be close to their respective
pins. In a multilayer PCB use one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are referenced.
The goal is to localize the high current path to a
separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout
at a single point. It is recommended to place all
the compensation parts over the analog ground
plane in top layer.
Make the connections for the power components in
the top layer with wide, copper filled areas or
polygons. In general, it is desirable to make proper
use of power planes and polygons for power
distribution and heat dissipation.
The inductor, output capacitors and the IR3742
should be as close to each other as possible. This
helps to reduce the EMI radiated by the power
traces due to the high switching currents through
them. Place the input capacitor directly at the PVin
pin of IR3742.
The Power QFN is a thermally enhanced package.
Based on thermal performance it is recommended to
use at least a 4-layers PCB. To effectively remove
heat from the device the exposed pad should be
connected to the ground plane using via holes.
Figure 32 - Figure 35 illustrates the implementation
of the layout guidelines outlined above, on the
IRDC3742 4-layer demo board.
The feedback part of the system should be kept
away from the inductor and other noise sources.
Vout
Enough copper &
minimum ground
path length between
Input and Output
PGnd
PVin
SW node copper is
kept only at the top
layer to minimize
the switching noise
AGnd
All bypass caps
should be placed
as close as possible
to their connecting pins
Figure 32: IRDC3742 Demo Board – Top Layer
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PVin
PGnd
Vout
Single point connection
between AGND & PGND,
should be close to the
PowIRStage kept away from
noise sources
Figure 33: IRDC3742 Demo Board – Bottom Layer
PGnd
AGnd
Figure 34: IRDC3742 Demo Board – Middle Layer 1
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IR3742
PGnd
Figure 35: IRDC3742 Demo Board – Middle Layer 2
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IR3742
PCB METAL AND COMPONENT PLACEMENT
Evaluations have shown that the best overall
performance is achieved using the substrate/PCB
layout as shown in following figures. PQFN devices
should be placed to an accuracy of 0.050mm on
both X and Y axes. Self-centering behavior is highly
dependent on solders and processes, and
experiments should be run to confirm the limits of
self-centering on specific processes.
For further information, please refer to “SupIRBuck™
Multi-Chip Module (MCM) Power Quad Flat No-Lead
(PQFN) Board Mounting Application Note.”
(AN1132)
Figure 36: PCB Metal Pad Spacing (all dimensions in mm)
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format
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IR3742
SOLDER RESIST
IR recommends that the larger Power or Land Area
pads are Solder Mask Defined (SMD.) This allows
the underlying Copper traces to be as large as
possible, which helps in terms of current carrying
capability and device cooling capability.
are Non Solder Mask Defined (NSMD) or Copper
Defined.
When using NSMD pads, the Solder Resist Window
should be larger than the Copper Pad by at least
0.025mm on each edge, (i.e. 0.05mm in X&Y,) in
order to accommodate any layer to layer
misalignment.
When using SMD pads, the underlying copper
traces should be at least 0.05mm larger (on each
edge) than the Solder Mask window, in order to
accommodate any layer to layer misalignment. (i.e.
0.1mm in X & Y.)
Ensure that the solder resist in-between the smaller
signal lead areas are at least 0.15mm wide, due to
the high x/y aspect ratio of the solder mask strip.
However, for the smaller Signal type leads around
the edge of the device, IR recommends that these
Figure 37: Solder Resist
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IR3742
STENCIL DESIGN
Stencils for PQFN can be used with thicknesses of
0.100-0.250mm (0.004-0.010"). Stencils thinner than
0.100mm are unsuitable because they deposit
insufficient solder paste to make good solder joints
with the ground pad; high reductions sometimes
create similar problems. Stencils in the range of
0.125mm-0.200mm (0.005-0.008"), with suitable
reductions, give the best results.
Evaluations have shown that the best overall
performance is achieved using the stencil design
shown in following figure. This design is for a stencil
thickness of 0.127mm (0.005"). The reduction
should be adjusted for stencils of other thicknesses.
Figure 38: Stencil Pad Spacing (all dimensions in mm)
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IR3742
MARKING INFORMATION
LOGO
PART NUMBER
SITE/DATE/MARKING CODE
LOT CODE
3742
?YWW?
xxxxx
PIN 1
PACKAGE INFORMATION
MILIMITERS
MIN MAX
INCHES
MIN MAX
MILIMITERS
INCHES
MIN MAX
DIM
DIM
MIN
MAX
A
A1
b
b1
c
D
E
e
e1
e2
0.800 1.000 0.0315 0.0394
0.000 0.050 0.0000 0.0020
0.375 0.475 0.1477 0.1871
0.250 0.350 0.0098 0.1379
L
M
N
O
P
Q
R
0.350
2.441
0.703
2.079
3.242
1.265
2.644
1.500
0.450 0.0138 0.0177
2.541 0.0961 0.1000
0.803 0.0277 0.0316
2.179 0.0819 0.0858
3.342 0.1276 0.1316
1.365 0.0498 0.0537
2.744 0.1041 0.1080
1.600 0.0591 0.0630
0.203 REF.
5.000 BASIC
6.000 BASIC
1.033 BASIC
0.650 BASIC
0.852 BASIC
0.008 REF.
1.969 BASIC
2.362 BASIC
0.0407 BASIC
0.0256 BASIC
0.0335 BASIC
S
t1, t2, t3
t4
0.401 BASIC
1.153 BASIC
0.727 BASIC
0.016 BACIS
0.045 BASIC
0.0286 BASIC
t5
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IR3742
ENVIRONMENTAL QUALIFICATIONS
Industrial
JEDEC Level 2 @ 260°C
Class B
Qualification Level
Moisture Sensitivity Level
Machine Model
5mm x 6mm PQFN
(JESD22-A115A)
200V to <400V
Class 2
Human Body Model
(JESD22-A114F)
ESD
2000V to <4000V
Class II
Charged Device Model
(JESD22-C101D)
200V to <500V
RoHS6 Compliant
Yes
† Qualification standards can be found at International Rectifier web site: http://www.irf.com
Data and specifications subject to change without notice.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com
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