IR38164M [INFINEON]
OptiMOS™ IPOL DC-DC转换器,单输入电压,30A降压稳压器,配备SVIDO;型号: | IR38164M |
厂家: | Infineon |
描述: | OptiMOS™ IPOL DC-DC转换器,单输入电压,30A降压稳压器,配备SVIDO DC-DC转换器 稳压器 |
文件: | 总64页 (文件大小:1869K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IR38164
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Features
Internal LDO allows single 16 V operation
Output Voltage Range: 0.5 V to 0.875*PVin
0.5% accurate Reference Voltage
Intel VR12.5 (Rev 1.5), SVID (Rev 1.7) and VR13 (Rev 1.1) compliant
Enhanced line/load regulation with Feedforward
Frequency programmable by PMBus™ up to 1.5 MHz
Enable input with Voltage Monitoring Capability
Remote Sense Amplifier with True Differential Voltage Sensing
Fast mode I2C and 400 kHz PMBus™ interface for programming, sequencing and margining output voltage,
and for monitoring input voltage, output voltage, output current and temperature.
PMBus™ configurable fault thresholds for input UVLO, output OVP, OCP and thermal shutdown.
Thermally compensated pulse-by-pulse current limit and Hiccup Mode Over Current Protection
Dedicated output voltage sensing for power good indication and over-voltage protection which remains
active even when Enable is low.
Enhanced Pre-Bias Start up
Integrated MOSFET drivers and Bootstrap diode
Operating junction temp: -40 C<Tj<125 C
Thermal Shut Down
PMBus™ Programmable Power Good Output
Small Size 5 mmx 7 mm PQFN
⁰
⁰
Pb-Free (RoHS Compliant)
External resistor allows setting up to 16 PMBus™ addresses
Applications
Designed for Intel® single phase power rails requiring SVID communication such as VCCIO and VCMP on
platforms such as VR13HC, VR13 and VR12.5.
Servers and High End Desktop CPU VRs for non-core applications
Telecom & Datacom Applications
Distributed Point of Load Power Architectures
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22
Final Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1 of 64
V2.2
Feb 6 2019
Description
The IR38164 OptiMOS™ IPOL is an easy to use, fully integrated and highly efficient dc-dc regulator with Intel
SVID and I2C/PMBus™ interfaces. The on-chip PWM controller and co-packaged low duty cycle optimized
MOSFETs make the device a space-efficient solution, providing accurate power delivery for low output voltage
and high current applications that require an Intel SVID interface.
The IR38164 offers programmability of switching frequency, output voltage, and fault/warning thresholds and
fault responses while operating over a wide input range. Providing flexibility as well as system level security in
the event of fault conditions.
The switching frequency is programmable from 500 kHz to 1.5 MHz for an optimum solution.
The on-chip sensors and ADC along with the SVID, I2C and PMBus™ make it easy to monitor and report input
voltage, output voltage, output current and temperature.
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Table of contents
Table of contents
Features ........................................................................................................................................ 1
Applications................................................................................................................................... 1
Product validation.......................................................................................................................... 1
Description .................................................................................................................................... 2
Table of contents............................................................................................................................ 3
1
2
3
4
5
6
7
Ordering information ............................................................................................................. 5
Functional block diagram........................................................................................................ 6
Typical application diagram .................................................................................................... 7
Pin descriptions ..................................................................................................................... 8
Absolute maximum ratings ....................................................................................................10
Electrical specifications .........................................................................................................11
Electrical characteristics........................................................................................................12
8
Typical efficiency and power loss curves..................................................................................18
PVin = Vin = 12 V, VCC=5 V, Fs = 600 kHz...................................................................................................18
PVin = Vin = 12 V, VCC (Internal LDO), Fs = 600 kHz..................................................................................19
PVin = Vin = Vcc = 5 V, Fs = 600 kHz...........................................................................................................20
8.1
8.2
8.3
9
Iout reporting curves (SVID) ...................................................................................................21
Thermal Derating curves........................................................................................................22
Typical application configurations ..........................................................................................23
RDS(ON) of MOSFETs Over Temperature.......................................................................................25
Typical operating characteristics (-40 °C to +125 °C)..................................................................26
10
11
12
13
14
14.1
14.2
14.3
14.4
14.5
14.6
14.7
Theory of operation...............................................................................................................28
Description ............................................................................................................................................28
Device Power-up and Initialization.......................................................................................................28
IꢀC and PMBUS™ Communication........................................................................................................29
Modes for Setting Output Voltages.......................................................................................................30
Bus Voltage UVLO ..................................................................................................................................33
Pre-Bias startup.....................................................................................................................................34
Soft-Start (Reference DAC ramp)..........................................................................................................34
Operating frequency ............................................................................................................................35
Shutdown ..............................................................................................................................................35
Current Sensing, Telemetry and Over-Current Protection..................................................................36
Current reporting limitation at high operating temperature ..............................................................39
Die temperature sensing, telemetry and thermal shutdown ..............................................................40
Remote voltage sensing........................................................................................................................40
Feed-forward.........................................................................................................................................41
Output voltage sensing, telemetry and faults......................................................................................41
Power Good Output ..............................................................................................................................41
Over-Voltage Protection (OVP) .............................................................................................................43
Minimum On-Time Considerations.......................................................................................................44
Maximum Duty Ratio.............................................................................................................................45
Bootstrap Capacitor..............................................................................................................................45
Intel SVID interface................................................................................................................................46
All Call support ......................................................................................................................................46
VR12.5 operation ...................................................................................................................................46
14.8
14.9
14.10
14.11
14.12
14.13
14.14
14.15
14.16
14.17
14.18
14.19
14.20
14.21
14.22
14.23
Final Datasheet
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30A Single-voltage Synchronous Buck Regulator with SVID
Table of contents
14.24
14.25
14.26
14.27
14.28
VR13 operation ......................................................................................................................................46
Set Work Point.......................................................................................................................................46
Dynamic VID slew rate...........................................................................................................................47
Loop compensation ..............................................................................................................................47
Dynamic VID compensation..................................................................................................................47
15
IꢄC and PMBus™ communication protocols ..............................................................................48
I2C Protocols .........................................................................................................................................48
SMBus/PMBus™ protocols ....................................................................................................................48
Supported PMBus™ commands............................................................................................................51
15.1
15.2
15.3
16
PCB footprint and layout recommendations.............................................................................55
Layout recommendations.....................................................................................................................55
PCB Metal and Component Placement ................................................................................................56
PCB copper and solder resist................................................................................................................56
PCB solder paste stencil........................................................................................................................57
16.1
16.2
16.3
16.4
17
Marking and package information...........................................................................................59
Final production marking .....................................................................................................................59
Early production marking .....................................................................................................................59
Package dimensions .............................................................................................................................60
17.1
17.2
17.3
18
19
Environmental Qualifications .................................................................................................62
References ...........................................................................................................................63
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Ordering information
1
Ordering information
Table 1
Ordering Information
Base Part Number
IR38164
Package Type
Standard Pack Form and Qty
Orderable Part Number
QFN 5 mm x 7 mm
Tape and Reel
4000
IR38164MTRPbF
IR38164
PBF
Lead Free
Tape and Reel
Package Type
TR
M
Figure 1
Package Top View
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Functional block diagram
2
Functional block diagram
VCC
Vin
P1V8
LDO
VLDOref
LDO
LGND
-
OT_Fault
+
UVcc
OC_Fault
BOOT
PVIN
VCC
UVcc
FAULT
CONTROL
UVEN
Fault
COMP
Fault
VDAC2
HDrv
+
-
E/A
HDin
GATE
DRIVE
LOGIC
OV_Fault
FCCM
SW
FB
VCC
LDrv
LDin
Enable
PGND
CONTROL AND FAULT LOGIC
Rso
RS-
PGood
RS+
ISense
TMON
Current Sense
SDA
SCL
SVID Interface, SMBus
Interface,
Logic, Command and Status registers
Temperature
Sense
Salert
Vcc
ADDR
Vsns
SV_ALERT
SV_CLK SV_DIO
Figure 2
Block diagram
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Typical application diagram
3
Typical application diagram
For applications in which Pvin>14V, a 1 ohm resistor is required in series with the boot capacitor.
5.5V <Vin<16V
Optional placeholder for boot resistor.
Default should be 0 ohm
Boot
P1V8
PVin
Enable
Vin
Vo
Vcc/
LDO_out
SW
Vsns
RS+
PGood
PGood
RS-
SV_CLK
SV_DIO
RSo
Fb
CPU
serial
bus
SV_ALERT
ADDR
Comp
LGnd
PGnd
Placeholder
for capacitor
Figure 3
IR38164 basic application circuit
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Pin descriptions
4
Pin descriptions
Table 2
Pin descriptions
Pin#
Pin name
Pin description
1
PVIN
Input voltage for power stage. Bypass capacitors between PVin and PGND should
be connected very close to this pin and PGND. Typical applications use four 22 µF
input capacitors and a low ESR, low ESL 0.1 µF decoupling capacitor in a
0603/0402 case size. A 3.3 nF capacitor may also be used in parallel with these
input capacitors to reduce ringing on the SW node.
2
Boot
Supply voltage for high side driver. A 0.1 µF capacitor should be connected from
this pin to the SW pin. It is recommended to provide a placement for a 0 ohm
resistor in series with the capacitor. For applications in which PVin>14 V, a 1 ohm
resistor is required in series with the boot capacitor.
3
4
ENABLE
ADDR
Enable pin to turn the IC on and off.
A resistor should be connected from this pin to LGnd to set the PMBus™ address
offset for the device. It is recommended to provide a placement for a 10 nF
capacitor in parallel with the offset resistor.
5
6
Vsns
FB
Sense pin for OVP and PGood. Typically connected to a local Vout capacitor at the
output of the inductor.
Inverting input to the error amplifier. This pin is connected directly to the output
of the regulator or to the output of the remote sense amplifier, via resistor divider
to set the output voltage and provide feedback to the error amplifier.
Output of error amplifier. An external resistor and capacitor network is typically
connected from this pin to FB to provide loop compensation.
Remote Sense Amplifier Output. When the remote sense amplifier is used, this is
connected to the feedback compensation network
7
8
COMP
RSo
9
10
11
RS-
RS+
PGood
Remote Sense Amplifier input. Connect to ground at the load.
Remote Sense Amplifier input. Connect to output at the load.
Power Good status pin. Output is open drain. Connect a pull up resistor from this
pin to VCC. If the power good voltage needs to be limited to < 500 mV prior power
supply ramps above the VCC UVLO, use a 49.9 kΩ pullup. After VCC UVLO a 4.99 kΩ
pullup will suffice.
12,25 PGND
Power ground. This pin should be connected to the system’s power ground plane.
Bypass capacitors between PVin and PGND should be connected very close to
PVIN pin (pin 1) and this pin.
13
14
15
LGND
Signal ground for internal reference and control circuitry. This should be
connected to the PGnd plane at a quiet location using a single point connection.
SVID CLK line. This is pulled up to VDDIO/VCCIO voltage. It is recommended to
provide a placement for a 0603 resistor between the pin and the pullup resistor.
SVID Data line. This is pulled up to VDDIO/VCCIO voltage. It is recommended to
provide a placement for a 0603 resistor between the pin and the pullup resistor.
SVID Alert line. This is pulled up to VDDIO/VCCIO voltage through a resistor.
SMBus Alert line; open drain SMBALERT# pin. This should be pulled up to 3.3 V-5 V
with a 1 kΩ - 5 kΩ resistor.
SV_CLK
SV_DIO
16
17
SV_ALERT
SAlert#
18
19
SDA
SCL
SMBus data serial input/output line. This should be pulled up to 3.3 V-5 V with a 1
kΩ - 5 kΩ resistor.
SMBus clock line. This should be pulled up to 3.3 V-5 V with a 1 kΩ - 5 kΩ resistor.
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Pin descriptions
Pin#
Pin name
Pin description
20
P1V8
This is the supply for the digital circuits; bypass with a 10 µF capacitor to PGnd.
21
22
Vin
Input Voltage for LDO. A 1 µF capacitor is placed from this pin to PGnd. If the
internal bias LDO is used, tie this pin to PVin. If an external bias voltage (typically 5
V) is available for Vcc, tie the Vin pin to Vcc.
Bias Voltage for IC and driver section, output of LDO. Add 10 µF bypass cap from
this pin to PGnd.
VCC
23,26 NC
24 SW
Do not connect to this pin.
Switch node. This pin is connected to the output inductor.
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Absolute maximum ratings
5
Absolute maximum ratings
Table 3
Absolute maximum ratings
-0.3 V to 25 V
PVin, Vin
-0.3 V to 6 V
Vcc/LDO_Out
P1V8
-0.3 V to 2 V
-0.3 V to 25 V (dc), -4 V to 25 V (ac, 100 ns)
-0.3 V to 31 V
SW
Boot
-0.3 V to 6 V (dc) (Note 1), -0.3 V to 6.5 V (ac, 100 ns)
-0.3 V to 6 V (Note 1)
Boot to SW
PGood, other Input/Output Pins
PGnd to Gnd
-0.3 V to + 0.3 V
Thermal information
Junction to ambient thermal resistance θJA
Junction to board thermal resistance θJB
Junction to case top thermal resistance θJC(top)
Junction to case top thermal parameter ΨJT (top)
Storage Temperature Range
11.1 C/W (Note 2)
4.16 C/W (Note 3)
18.9 C/W (Note 4)
0.32 C/W (Note 2)
-55 °C to 150 °C
-40 °C to 150 °C
Junction Temperature Range
(Voltage referenced to GND unless otherwise specified)
Attention:
Stresses beyond these listed under ꢀAbsolute Maximum Ratingsꢁ may cause permanent
damage to the device. These are stress ratings only and not functional operation ratings of
the device.
Note: 1 Must not exceed 6 V
2 Value obtained via thermal simulation under natural convection on an IR38164 demo board. 10 layer, 7” x
5.5”x0.072” PCB with 1.5 oz copper at the top and bottom layer. Inner layers 2, 3, 8 and 9 have 1 oz copper
and layers 4,5,6,7 have 2 oz copper. Ta = 25 ⁰C was used for the simulation.
3 PCB from note 2 and package is considered in thermal simulation with Ta=25 ⁰C. Pin 12 is considered.
4 Only package is considered. Simulation is used with a cold plate that fixes top of package at Ta=25 ⁰C.
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Electrical specifications
6
Electrical specifications
Table 4
Recommended operating conditions for reliable operation with margin
Input Voltage Range, PVin (Note 4)
Input Voltage Range, Vin
1.5 V to 16 V
5.3 V to 16 V
Supply Voltage Range, Vcc
Supply Voltage Range, Boot to SW
Output Voltage Range
4.5 V to 5.5 V
4.5 V to 5.5 V
0.5 V to 0.875 x Vin
0 to 30 A
Output Current Range
Switching Frequency
500 kHz to 1500 kHz
-40 °C to 125 °C
Operating Junction Temperature
(Voltages referenced to GND unless otherwise specified)
Note:
4 Maximum absolute SW node voltage should not exceed 25 V. A common practice is to have 20%
margin on the maximum SW node voltage in the design. For applications requiring PVin equal to
or above 14 V, a small resistor in series with the Boot pin should be used to ensure the maximum
SW node spike voltage does not exceed 25 V.
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Electrical characteristics
7
Electrical characteristics
Parameter
Symbol
Conditions
Min
Typ
Max Unit
Power Stage
VBoot – Vsw= 5 V, IO = 30 A,
Tj =25 °C
Top Switch
RDS(ON)_Top
RDS(ON)_Bot
2.2
mΩ
Vcc = 5 V, IO = 30 A, Tj
=25°C
Bottom Switch
0.78
300
Bootstrap Diode
Forward Voltage
I(Boot) = 40 mA
150
450 mV
ISW
SW = 0 V, Enable = 0 V
SW=0; Enable= 2 V
1
SW Leakage Current
µA
ISW_EN
18
Supply Voltage
PVin range
(using external Vcc=5 V)
Vin range
1.5-16
5.3-16
V
V
Fsw=600 kHz
Fsw=1.5 MHz
(using internal LDO)
5.5-16
5.0
4.5
5.5
4
V
Vin range (when Vin=Vcc)
Supply Current
Vin Supply Current
(standby) (internal Vcc)
Iin(Standby)
Enable low, No Switching,
Vin=16 V, low power mode
enabled
2.7
mA
Vin Supply Current
Iin(Dyn)
Enable high, Fs = 600 kHz,
Vin=16 V
Enable low, No Switching,
Vcc=5.5 V, low power mode
enabled
mA
mA
39
50
5
(dynamic) (internal Vcc)
VCC Supply Current
(Standby)(external Vcc)
Icc(Standby)
2.7
VCC Supply Current
(Dyn)(external Vcc)
Icc(Dyn)
Enable high, Fs = 600 kHz,
Vcc=5.5 V
39
50 mA
Internal Regulator
VCC\LDO)
Vin(min) = 5.5 V, Io=0 mA,
Cload = 10 µF
4.8
4.5
5.15
4.99
5.4
V
5.2
Output Voltage
VCC
Vin(min) = 5.5 V, Io=70 mA,
Cload = 10 µF
Io=0-70 mA, Cload =10µF,
Vin=5.1 V
VCC Dropout
VCCdrop
Ishort
0.7
V
Short Circuit Current
110
mA
Internal Regulator
(P1V8)
Output Voltage
P1V8
Vin(min) = 4.5 V, Io = 0‐1mA 1.795 1.83 1.905
, Cload = 10 µF
V
V
1.8V UVLO Start
P1V8_UVLO_Start
1.8 V Rising Trip Level
1.66
1.72
1.78
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Electrical characteristics
Parameter
1.8V UVLO Stop
Oscillator
Symbol
P1V8_UVLO_Stop
Conditions
1.8 V Falling Trip Level
Min
1.59
Typ
1.63
Max Unit
1.68
V
0.71
1.84
2.46
0.22
35
PVin=5 V, D=Dmax, Note 2
PVin=12 V, D=Dmax,Note 2
Vramp
Ramp Amplitude
Vp-p
V
PVin=16 V, D=Dmax,Note 2
Note 2
Ramp Offset
Ramp(os)
Tmin(ctrl)
Toff
Note 2
50
150
89
Min Pulse Width
Fixed Off Time
Max Duty Cycle
Error Amplifier
Input Bias Current
Sink Current
ns
ns
%
Note 2 Fs=1.5 MHz
Fs=400 kHz
100
87.5
86
Dmax
-0.5
0.6
8
+0.5
1.8
25
IFb(E/A)
Isink(E/A)
Isource(E/A)
SR
µA
1.1
13
mA
mA
V/µs
MHz
dB
Source Current
Slew Rate
7
12
20
Note 2
Note 2
Note 2
20
100
2.8
30
40
Gain-Bandwidth Product GBWP
DC Gain Gain
110
3.9
120
4.3
100
Maximum output Voltage Vmax(E/A)
Minimum output Voltage Vmin(E/A)
Reference Voltage
V
mV
1.25 V<VFB<2.555 V
VOUT_SCALE_LOOP=1;
-1
+1
0.75 V<VFB<1.25 V
VOUT_SCALE_LOOP=1;
-0.75
+0.75
Accuracy
%
%
00C<Tj<850C
-0.5
-1.6
+0.5
+1.6
0.45 V<VFB<0.75 V
VOUT_SCALE_LOOP=1;
1.25 V<VFB<2.555 V
VOUT_SCALE_LOOP=1;
0.75 V<VFB<1.25 V
VOUT_SCALE_LOOP=1;
-1.0
-2.0
+1.0
+2.0
Accuracy
-400C<Tj<1250C
0.45 V<VFB<0.75 V
VOUT_SCALE_LOOP=1;
Remote Sense Differential Amplifier
Note 2
Note 2
3
6.4
110
0
MHz
dB
Unity Gain Bandwidth
DC Gain
BW_RS
Gain_RS
Offset_RS
0.5 V<RS+<2.555 V, 4 kΩ
-1.6
1.6
3
Offset Voltage
load
⁰
⁰
27 C<Tj<85 C
0.5 V<RS+<2.555 V, 4kΩ
load
mV
-3
⁰
⁰
-40 C<Tj<125 C
V_RSO=1.5 V, V_RSP=4 V
11
16
2
mA
mA
V2.2
Source Current
Sink Current
Final Datasheet
Isource_RS
Isink_RS
0.4
1
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Electrical characteristics
Parameter
Symbol
Conditions
Note 2, Cload = 100 pF
Min
2
Typ
Max Unit
Slew Rate
Slew_RS
4
8
V/µs
V_RSO=1.5 V, V_RSP=4 V
11
36
36
0.5
16
74
74
1.5
20
mA
Kohm
Kohm
V
Source Current
Isource_RS
Rin_RS+
RS+ input impedance
55
Note 2
55
1
RS- input impedance
Maximum Voltage
Minimum Voltage
Power Good
Rin_RS-
V(VCC) – V(RS+)
Vmax_RS
Min_RS
4
mV
Power Good High
threshold
Power_Good_High
Power_Good_Low
Vsns rising,
VOUT_SCALE_LOOP=1,
Vout=0.5 V, PMBus™ mode
0.45
0.43
V
Power Good Low
Threshold
Vsns falling,
VOUT_SCALE_LOOP=1,
V
Vout=0.5 V, PMBus™ mode
Power Good High
Threshold Rising Delay
TPDLY
Vsns rising, Vsns >
Power_Good_High
0
ms
Power Good Low
Threshold Falling delay
VPG_low_Dly
PG(voltage)
Vsns falling, Vsns <
Power_Good_Low
150
175
200
0.5
µs
V
Pgood Voltage Low
Ipgood = -5 mA
Under-Voltage Lockout
Vcc-Start Threshold
4.0
3.7
4.2
3.9
0.6
0.4
4.4
4.1
0.65
0.45
1
VCC_UVLO_Start
VCC_UVLO_Stop
Vcc Rising Trip Level
Vcc Falling Trip Level
V
Vcc-Stop Threshold
0.55
0.35
Enable-Start-Threshold
Enable-Stop-Threshold
Enable Leakage Current
Over-Voltage Protection
OVP Trip Threshold
Enable_UVLO_Start EN supply ramping up
Enable_UVLO_Stop EN supply ramping down
V
Ien
Enable = 5.5 V
µA
OVP (trip)
Vsns rising,
VOUT_SCALE_LOOP=1,
Vout=0.5V
0.57 0.605 0.63
V
Vsns falling,
VOUT_SCALE_LOOP=1,
Vout=0.5 V
Vsns rising, Vsns-
OVP(trip)>200 mV
OVP Comparator Delay
OVP Fault Prop Delay
20
30
40
mV
ns
OVP (hyst)
OVP (delay)
200
Over-Curent Protection
OC limit=40, VCC = 5.05 V,
Tj=25 C
34.5
40
44
OC Trip Current
ITRIP
A
⁰
⁰
⁰
OCset Current
Temperature coefficient
-40 C to 125 C, VCC=5.05
V, Note 2
5900
20
ppm/°C
ms
OCSET(temp)
Tblk_Hiccup
Hiccup blanking time
Note 2
Over-Temperature
Protection
Thermal Shutdown
Note 2
145
°C
Final Datasheet
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V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Electrical characteristics
Parameter
Symbol
Conditions
Min
Typ
Max Unit
Hysteresis
Note 2
25
Input Over-Voltage
Protection
PVin over-voltage
threshold
PVinOV
22
23.7
25
V
V
PVin over-voltage
Hysteresis
PVin ov hyst
2.4
Output Voltage
Reporting
Resolution
Vout update rate
NVout
Note 2
1/256
31.25
V
kHz
Lowest reported Vout
Vomon_low
Vsns=0V
0
V
VOUT_SCALE_LOOP=1,
Vsns=3.3 V
3.3
V
V
V
V
VOUT_SCALE_LOOP=0.5,
Vsns=3.3 V
6.6
Highest reported Vout
Vomon_high
VOUT_SCALE_LOOP=0.25,
Vsns=3.3 V
13.2
26.4
VOUT_SCALE_LOOP=0.125,
Vsns=3.3 V
⁰
⁰
0 C to 85 C,
4.5 V<Vcc<5.5 V,
1 V<Vsns≤ 1.5 V
+/-0.6
VOUT_SCALE_LOOP=1
⁰
⁰
0 C to 85 C,
+/-1
4.5 V<Vcc<5.5 V, Vsns> 1.5 V
VOUT_SCALE_LOOP=1
%
Vout reporting accuracy
⁰
⁰
0 C to 125 C,
+/-1.5
4.5 V<Vcc<5.5 V, Vsns>0.9 V
VOUT_SCALE_LOOP=1
00C to 1250C,
4.5V<Vcc<5.5V,
0.5V<Vsns<0.9V
VOUT_SCALE_LOOP=1
+/-3
Iout Reporting
Resolution
NIout
Note 2
1/16
A
Iout update rate
Iout (digital) monitoring
Range
31.25
kHz
0
40
A
⁰
⁰
0 C to 125 C,
4.5 V<Vcc<5.5 V,
5 A < Iout <30 A
Iout_dig Accuracy
+/-5
%
I2C/PMBus™ mode
Final Datasheet
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Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Electrical characteristics
Parameter
Symbol
Conditions
Min
Typ
Max Unit
Note 3
Temperature Reporting
Resolution
NTmon
Note 2
1
°C
Temperature update rate
31.25
kHz
Temperature Monitoring Tmon_dig
Range
Thermal shutdown
hysteresis
Input Voltage Reporting
-40
150
21
°C
Note 2
Note 2
25
°C
V
Resolution
NPVin
1/32
Monitoring Range
PVin update rate
PMBVinmon
0
V
kHz
31.25
⁰
⁰
0 C to 85 C
-1.5
-1.5
1.5
1.5
4.5 V<Vcc<5.5V, PVin>10 V
-400C to 1250C
4.5 V<Vcc<5.5 V, PVin>14 V
%
Monitoring accuracy
⁰
⁰
-40 C to 125 C,
4.5 V<Vcc<5.5 V,
7V<PVin<14 V
-4
4
PMBus™ Interface
Timing Specifications
SMBus Operating
frequency
Bus Free time between
Start and Stop condition
Hold time after
FSMB
400
kHz
µs
TBUF
1.3
0.6
THD:STA
(Repeated) Start
Condition. After this
period, the first clock is
generated.
µs
Repeated start condition TSU:STA
setup time
0.6
0.6
µs
µs
Stop condition setup
time
TSU:STO
Data Rising Threshold
Data Falling Threshold
1.339
1.048
1.766
1.495
V
V
Data Rising Threshold
LVT
0.45
0.7
0.65
0.9
V
V
V
Clock Rising Threshold
LVT
Clock Falling Threshold
LVT
0.45
300
0.65
900
Data Hold Time
THD:DAT
ns
Final Datasheet
16 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Electrical characteristics
Parameter
Symbol
Conditions
Min
100
Typ
Max Unit
ns
Data Setup Time
Data pulldown resistance
TSU:DAT
8
11
12
16
17
35
Ω
SALERT# pulldown
resistance
9
Ω
Clock low time out
Clock low period
Clock High Period
TTIMEOUT
TLOW
25
1.3
0.6
ms
µs
µs
THIGH
50
Note:
Note:
2 Guaranteed by design and not tested in production.
3 Guaranteed by statistical correlation, but not tested in production.
Final Datasheet
17 of 64
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Typical efficiency and power loss curves
8
Typical efficiency and power loss curves
8.1
PVin = Vin = ꢁꢄ V, VCC=ꢅ V, Fs = ꢂꢆꢆ kHz
PVin = Vin = 12 V, VCC=5 V (external), Io=0-30 A, Fs= 600 kHz, Room Temperature, No Air Flow. Note that the
efficiency and power loss curves include the losses of IR38164, the inductor losses, the losses of the input and
output capacitors, and PCB trace losses. The table below shows the inductors used for each of the output
voltages in the efficiency measurement.
Table 5
Vout (V)
Inductors for PVin=Vin=12 V, VCC, Fs = 600 kHz
Lout (µH)
0.15
P/N
Size (mm)
12.4 x 8.3 x 8
12.4 x 8.3 x 8
12.4 x 8.3 x 8
12.4 x 8.3 x 8
12.4 x 8.3 x 8
12.7 x 13.4 x 8
12.7 x 13.4 x 8
DCR (m)
0.15
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
FP1308R3-R32-R (Cooper)
FP1308R3-R32-R (Cooper)
0.8
1.0
1.2
1.5
1.8
3.3
5
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.32
0.32
0.32
0.32
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Typical efficiency and power loss curves
8.2
PVin = Vin = ꢁꢄ V, VCC ꢇInternal LDOꢈ, Fs = ꢂꢆꢆ kHz
PVin = Vin = 12 V, Internal LDO, Io=0-30 A, Fs= 600 kHz, Room Temperature, No Air Flow. Note that the efficiency
and power loss curves include the losses of IR38164, the inductor losses, the losses of the input and output
capacitors, and PCB trace losses. The table below shows the inductors used for each of the output voltages in
the efficiency measurement.
Table 6
Vout (V)
Inductors for PVin=Vin=12 V, Internal LDO, Fs = 600 kHz
Lout (µH)
0.15
P/N
Size (mm)
12.4 x 8.3 x 8
12.4 x 8.3 x 8
12.4 x 8.3 x 8
12.4 x 8.3 x 8
12.4 x 8.3 x 8
12.7 x 13.4 x 8
12.7 x 13.4 x 8
DCR (m)
0.15
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
FP1308R3-R32-R (Cooper)
FP1308R3-R32-R (Cooper)
0.8
1.0
1.2
1.5
1.8
3.3
5
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.32
0.32
0.32
0.32
Final Datasheet
19 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Typical efficiency and power loss curves
8.3
PVin = Vin = Vcc = ꢅ V, Fs = ꢂꢆꢆ kHz
PVin = Vin = VCC = 5 V, Io=0-30 A, Fs= 600 kHz, Room Temperature, No Air Flow. Note that the efficiency and
power loss curves include the losses of IR38164, the inductor losses, the losses of the input and output
capacitors and PCB trace losses. The table below shows the inductors used for each of the output voltages in
the efficiency measurement.
Table 7
Vout (V)
Inductors for PVin=Vin=Vcc=5 V, Fs = 600 kHz
Lout (µH)
0.1
P/N
Size (mm)
12.4 x 8.3 x 8
12.4 x 8.3 x 8
12.4 x 8.3 x 8
12.4 x 8.3 x 8
12.4 x 8.3 x 8
DCR (m)
0.15
HCB138380D-101 (Delta)
HCB138380D-101 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
0.8
1.0
1.2
1.5
1.8
0.1
0.15
0.15
0.15
0.15
0.15
0.15
0.15
Final Datasheet
20 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Iout reporting curves (SVID)
9
Iout reporting curves ꢇSVIDꢈ
An Intel VRTT tool was used on a 38164 demo board running at 978 kHz to collect SVID Iout reporting data. This
is shown on Figure 4 and Figure 5.
25
20
15
10
NTC 0.03 Max Limit (6%)
NTC 0.03 Min Limit (6%)
5
0
0
5
10
15
20
25
Iout (A)
Figure 4
SVID readings from 37 units. Intel DCR 7%, NTC 3% spec.
25
20
15
10
5
Max Sweep
Min Sweep
Max Limit NTC 0.03 (6%)
Min Limit NTC 0.03 (6%)
0
0
5
10
15
20
25
-5
Iout (A)
Figure 5
Final Datasheet
SVID readings for the min and max gain. Intel DCR 7%, NTC 3% spec.
21 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Thermal Derating curves
10
Thermal Derating curves
The measurements were done on an IR38164 demo board. The PCB is ꢁ.ꢂꢃ x ꢄ.ꢄꢃ x ꢂ.ꢂꢁꢀꢃ with 10-layers, FR4
material and 2 oz. copper.
IR38164 Thermal Derating Curves)
PVin=12V, Vout=1V, Fsw=978kHz
31
29
27
25
23
0 LFM
200 LFM
400 LFM
21
19
17
15
25
30
35
40
45
50
55
60
65
70
75
80
85
TAmb (˚C)
Figure 6
PVin = 12 V, Vout=1 V, Vcc = Internal LDO, Fs = 978 kHz
Final Datasheet
22 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Typical application configurations
11
Typical application configurations
For applications in which Pvin>14V, a 1 ohm resistor is required in series with the boot capacitor.
5.5V <Vin<16V
Optional placeholder for boot resistor.
Default should be 0 ohm
Boot
P1V8
PVin
Enable
Vin
Vo
Vcc/
LDO_out
SW
Vsns
RS+
PGood
PGood
RS-
SV_CLK
SV_DIO
RSo
Fb
CPU
serial
bus
SV_ALERT
ADDR
Comp
LGnd
PGnd
Placeholder
for capacitor
Figure 7
Using the internal LDO, Vo < 2.555 V
For applications in which Pvin>14V, a 1 ohm resistor is required in series with the boot capacitor.
5.5V <Vin<16V
Optional placeholder for boot resistor.
Default should be 0 ohm
Boot
P1V8
PVin
Enable
Vin
Vo
Vcc/
LDO_out
SW
Vsns
RS+
PGood
R2
PGood
RS-
SV_CLK
SV_DIO
CPU
serial
bus
RSo
Fb
Recommend R2=499 ohm
SV_ALERT
Comp
LGnd
ADDR
PGnd
Placeholder
for capacitor
Figure 8
Using the internal LDO, Vo > 2.555 V
Final Datasheet
23 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Typical application configurations
For applications in which Pvin>14V, a 1 ohm resistor is required in series with the boot capacitor.
1.5V <PVin<16V
Optional placeholder for boot resistor.
Default should be 0 ohm
Boot
P1V8
PVin
Enable
Vin
Vcc=5V
PGood
Vo
Vcc/
LDO_out
SW
Vsns
RS+
PGood
RS-
SV_CLK
SV_DIO
CPU
serial
bus
RSo
Fb
SV_ALERT
Comp
LGnd
ADDR
PGnd
Placeholder
for capacitor
Figure 9
Using external Vcc, Vo<2.555 V
PVin=Vin=Vcc= 5V
Optional placeholder for boot resistor.
Default should be 0 ohm
Boot
P1V8
PVin
Enable
Vin
Vo
Vcc/
LDO_out
SW
Vsns
RS+
PGood
PGood
RS-
SV_CLK
SV_DIO
RSo
Fb
CPU
serial
bus
SV_ALERT
ADDR
Comp
LGnd
PGnd
Placeholder
for capacitor
Figure 10
Single 5 V application, Vo<2.555 V
Final Datasheet
24 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
RDS(ON) of MOSFETs Over Temperature
12
RDSꢇONꢈ of MOSFETs Over Temperature
Figure 11
RDS(on) of MOSFETs over Temperature
Final Datasheet
25 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Typical operating characteristics (-40 C to +125 C)
13
Typical operating characteristics ꢇ-ꢃꢆ °C to +ꢁꢄꢅ °Cꢈ
Figure 12
Typical operating characteristics (set 1 of 2)
Final Datasheet
26 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Typical operating characteristics (-40 C to +125 C)
Figure 13
Typical operating characteristics (set 2of 2)
Final Datasheet
27 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
14
Theory of operation
14.1
Description
The IR38164 is a 30 A rated synchronous buck converter that supports PMBus™ and I2C digital interfaces
respectively. This device is Intel SVID compliant and can support VR12.5 as well as VR13. It uses an externally
compensated fast, analog, PWM voltage mode control scheme to provide good noise immunity as well as fast
dynamic response in a wide variety of applications. At the same time, the digital communication interfaces
allow complete configurability of output setting and fault functions, as well as telemetry.
The switching frequency is programmable from 500 kHz to 1.5 MHz and provides the capability of optimizing
the design in terms of size and performance.
The IR38164 provides precisely regulated output voltages from 0.5 V to 0.875*PVin programmed via two
external resistors or through the communication interfaces. They operate with an internal bias supply (LDO),
typically 5.2 V. This allows operation with a single supply. The output of this LDO is brought out at the Vcc pin
and must be bypassed to the system power ground with a 10 µF decoupling capacitor. The Vcc pin may also be
connected to the Vin pin, and an external Vcc supply between 4.5 V and 5.5 V may be used, allowing an
extended operating bus voltage (PVin) range from 1.5 V to 16 V.
The device utilizes the on-resistance of the low side MOSFET (synchronous MOSFET) as the current sense
element. This method enhances the converter’s efficiency and reduces cost by eliminating the need for external
current sense components.
The IR38164 includes two low RDS(ONꢅ MOSFETs using Infineon’s OptiMOSTM technology. These are specifically
designed for low duty cycle, high efficiency applications.
14.2
Device Power-up and Initialization
During the power-up sequence, when Vin is brought up, the internal LDO converts it to a regulated 5.2 V at Vcc.
There is another LDO which further converts this down to 1.8 V to supply the internal digital circuitry. An under-
voltage lockout circuit monitors the voltage of VCC pin and the P1V8 pin, and holds the Power-on-reset (POR)
low until these voltages exceed their thresholds and the internal 48 MHz oscillator is stable. When the device
comes out of reset, it initializes a multiple times programmable (MTP) memory load cycle, where the contents
of the MTP are loaded into the working registers. Once the registers are loaded from MTP, the designer can use
PMBus™ commands to re-configure the various parameters to suit the specific VR design requirements if
desired, irrespective of the status of Enable.
The typical default configuration utilizes the internal LDO to supply the VCC rail when PVin is brought up. For
this configuration power conversion is enabled only when the Enable pin voltage exceeds its under-voltage
threshold, the PVin bus voltage exceeds its under-voltage threshold, the contents of the MTP have been fully
loaded into the working registers and the device address has been read. The initialization sequence is shown in
Figure 14. Another common default configuration uses an external power supply for the VCC rail. While in this
configuration it is recommended to ensure the VCC rail reaches its target voltage prior the enable signal goes
high.
Additional options are available to enable the device power conversion through software and these options
may be configured to override the default by using the I2C interface or PMBus™. For further details, see the
UN0075 IR3816x PMBus™ commandset user note.
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
PVIN=VIN
VCC
P1V8
UVOK
clkrdy
POR
Initialization
done
Enable
Vout
Figure 14 Initialization sequence showing PVin, Vin, Vcc, 1.8V, Enable and Vout signals as well as the
internal logic signals
14.3
IꢄC and PMBUS™ Communication
All the devices in this family have two 7-bit registers that are used to set the base I2C address and base PMBus™
address of the device, as shown below in Table 8 .
Table 8
Register
Registers used to set device base address
Description
I2c_address[6:0]
The chip I2C address. An address
of 0 will disable I2C
communication. Note that
disabling I2C does not disable
PMBus™.
PMBus™_address[6:0]
The chip PMBus™ address. An
address of 0 will disable PMBus™
communication. Note that
disabling PMBus™ does not
disable I2C.
In addition, a resistor may be connected between the ADDR and LGND pins to set an offset from the default
preconfigured I2C address (0x10) /PMBus™ address (0x40) in the MTP. Up to 16 different offsets can be set,
allowing 16 devices with unique addresses in a single system. This offset, and hence, the device address, is read
by the internal 10-bit ADC during the initialization sequence.
Table 9 below provides the resistor values needed to set the 16 offsets from the base address.
*Do not use these values for applications with ambient temperatures <0°C.
Table 9
Address offset vs External Resistor(RADDR)
ADDR Resistor (Ohm)
Address Offset
499
+0
+1
+2
+3
+4
+5
+6
1050
1540
2050
2610
3240
3830
Final Datasheet
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V2.2
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
ADDR Resistor (Ohm)
Address Offset
4530
5230
+7
+8
6040
+9
6980
7870
8870
9760
10700
>11800
+10
+11
+12
+13
+14
+15
The device will then respond to I2C/PMBus™ commands sent to this address. There is also a register bit
i2c_disable_addr_offset that may be set in order to instruct the device to ignore the resistor offset for both I2C
and PMBus™. If this bit is set, the device will always respond to commands sent to the base address. For
applications with junction temperatures below 0°C, offsets +0, +1, and +2 are not available.
14.4
Modes for Setting Output Voltages
These devices provide a configuration bit that allows the user to choose between PMBus™ and SVID modes.
When this bit is set, SVID mode, the output voltage will ramp to the configured boot voltage and subsequently,
respond to voltage set commands issued by the CPU on the Serial VID (SVID) interface. The VID tables for 5 mV
and 10 mV VID steps are shown in the tables below. A VID code of 0 corresponds to 0 V as well as the regulator
shutdown code in SVID mode. Vboot which is utilized in the SVID mode should not be set to 0 V as this will
shutdown the regulator. When this bit is zero, the regulation is determined by the output voltage set by the
PMBus™ commands. It should be noted that irrespective of the mode used to set the output voltage, telemetry
information always remains available on both the communications busses.
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
Table 10
Intel 5 mV VID table
VID
Voltage
VID
Voltage
VID
Voltage
(V)
VID
Voltage
(V)
VID
Voltage
(V)
(Hex)
(V)
(Hex)
(V)
(Hex)
(Hex)
(Hex)
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
EF
EE
ED
EC
EB
EA
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CF
CE
CD
CC
CB
CA
C9
C8
C7
C6
1.52
C5
C4
C3
C2
C1
C0
BF
BE
BD
BC
BB
BA
B9
B8
B7
B6
BB
BA
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
AF
AE
AD
AC
AB
AA
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
9F
9E
9D
9C
9B
9A
99
98
97
96
95
94
93
92
1.23
91
90
8F
8E
8D
8C
8B
8A
89
88
87
86
85
84
83
82
81
80
7F
7E
7D
7C
7B
7A
79
78
77
76
75
74
73
72
71
70
6F
6E
6D
6C
6B
6A
69
68
67
66
65
64
63
62
61
60
5F
5E
5D
5C
5B
5A
59
58
0.97
0.965
0.96
57
56
55
54
53
52
51
50
4F
4E
4D
4C
4B
4A
49
48
47
58
57
56
55
54
53
52
51
50
4F
4E
4D
4C
4B
4A
49
48
47
46
45
44
43
42
41
40
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
33
32
31
30
0.68
0.675
0.67
2F
2E
2D
2C
2B
2A
29
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
17
16
15
14
13
12
11
10
0F
0E
0D
0C
0B
0A
09
08
07
06
05
04
03
02
01
00
0.48
0.475
0.47
0.465
0.46
0.455
0.45
0.445
0.44
0.435
0.43
0.425
0.42
0.415
0.41
0.405
0.4
1.515
1.51
1.505
1.5
1.495
1.49
1.485
1.48
1.475
1.47
1.465
1.46
1.455
1.45
1.445
1.44
1.435
1.43
1.425
1.42
1.415
1.41
1.405
1.4
1.395
1.39
1.385
1.38
1.375
1.37
1.365
1.36
1.355
1.35
1.345
1.34
1.335
1.33
1.325
1.32
1.315
1.31
1.305
1.3
1.295
1.29
1.285
1.28
1.275
1.27
1.265
1.26
1.255
1.25
1.245
1.24
1.235
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
1.18
1.175
1.17
1.165
1.16
1.155
1.18
1.175
1.17
1.165
1.16
1.155
1.15
1.145
1.14
1.135
1.13
1.125
1.12
1.115
1.11
1.105
1.1
1.095
1.09
1.085
1.08
1.075
1.07
1.065
1.06
1.055
1.05
1.045
1.04
1.035
1.03
1.025
1.02
1.015
1.01
1.005
1
0.995
0.99
0.985
0.98
0.975
0.955
0.95
0.945
0.94
0.935
0.93
0.925
0.92
0.915
0.91
0.905
0.9
0.895
0.89
0.885
0.88
0.875
0.87
0.865
0.86
0.855
0.85
0.845
0.84
0.835
0.83
0.825
0.82
0.815
0.81
0.805
0.8
0.795
0.79
0.785
0.78
0.775
0.77
0.765
0.76
0.755
0.75
0.745
0.74
0.735
0.73
0.725
0.72
0.715
0.71
0.705
0.7
0.695
0.69
0.685
0.665
0.66
0.655
0.65
0.645
0.64
0.635
0.63
0.625
0.62
0.615
0.61
0.605
0.6
0.685
0.68
0.675
0.67
0.665
0.66
0.655
0.65
0.645
0.64
0.635
0.63
0.625
0.62
0.615
0.61
0.605
0.6
0.595
0.59
0.585
0.58
0.575
0.57
0.565
0.56
0.555
0.55
0.545
0.54
0.535
0.53
0.525
0.52
0.515
0.51
0.505
0.5
0.495
0.49
0.485
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Final Datasheet
31 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
Table 11
Intel 10 mV VID table
VID
Voltage
VID
Voltage
VID
Voltage
(V)
VID
Voltage
(V)
VID
Voltage
(V)
(Hex)
(V)
(Hex)
(V)
(Hex)
(Hex)
(Hex)
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
EF
EE
ED
EC
EB
EA
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CF
CE
CD
CC
CB
CA
C9
C8
C7
C6
3.04
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
2.95
2.94
2.93
2.92
2.91
2.90
2.89
2.88
2.87
2.86
2.85
2.84
2.83
2.82
2.81
2.80
2.79
2.78
2.77
2.76
2.75
2.74
2.73
2.72
2.71
2.70
2.69
2.68
2.67
2.66
2.65
2.64
2.63
2.62
2.61
2.60
2.59
2.58
2.57
2.56
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
C5
C4
C3
C2
C1
C0
BF
BE
BD
BC
BB
BA
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
AF
AE
AD
AC
AB
AA
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
9F
9E
9D
9C
9B
9A
99
98
97
96
95
94
93
92
91
90
8F
8E
8D
8C
2.46
2.45
2.44
2.43
2.42
2.41
2.40
2.39
2.38
2.37
2.36
2.35
2.34
2.33
2.32
2.31
2.30
2.29
2.28
2.27
2.26
2.25
2.24
2.23
2.22
2.21
2.20
2.19
2.18
2.17
2.16
2.15
2.14
2.13
2.12
2.11
2.10
2.09
2.08
2.07
2.06
2.05
2.04
2.03
2.02
2.01
2.00
1.99
1.98
1.97
1.96
1.95
1.94
1.93
1.92
1.91
1.90
1.89
8B
8A
89
88
87
86
85
84
83
82
81
80
7F
7E
7D
7C
7B
7A
79
78
77
76
75
74
73
72
71
70
6F
6E
6D
6C
6B
6A
69
68
67
66
65
64
63
62
61
60
5F
5E
5D
5C
5B
5A
59
58
57
56
55
54
53
52
1.88
1.87
1.86
1.85
1.84
1.83
1.82
1.81
1.80
1.79
1.78
1.77
1.76
1.75
1.74
1.73
1.72
1.71
1.70
1.69
1.68
1.67
1.66
1.65
1.64
1.63
1.62
1.61
1.60
1.59
1.58
1.57
1.56
1.55
1.54
1.53
1.52
1.51
1.50
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.40
1.39
1.38
1.37
1.36
1.35
1.34
1.33
1.32
1.31
51
50
4F
4E
4D
4C
4B
4A
49
48
47
46
45
44
43
42
41
40
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
33
32
31
30
2F
2E
2D
2C
2B
2A
29
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
1.30
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
1.19
1.18
1.17
1.16
1.15
1.14
1.13
1.12
1.11
1.10
1.09
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
0.94
0.93
0.92
0.91
0.90
0.89
0.88
0.87
0.86
0.85
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
0.74
0.73
17
16
15
14
13
12
11
10
0F
0E
0D
0C
0B
0A
09
08
07
06
05
04
03
02
01
0.72
0.71
0.70
0.69
0.68
0.67
0.66
0.65
0.64
0.63
0.62
0.61
0.60
0.59
0.58
0.57
0.56
0.55
0.54
0.53
0.52
0.51
0.50
Final Datasheet
32 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
14.5
Bus Voltage UVLO
If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can
be ensured that the device does not turn on until the bus voltage reaches the desired level as shown in Figure
15. Only after the bus voltage reaches or exceeds this level and voltage at the Enable pin exceeds its threshold
(typically 0.6 V) will the device be enabled. Therefore, in addition to being logic input pin to enable the
converter, the Enable feature, with its precise threshold, also allows the user to override the default 8 V under-
voltage lockout for the bus voltage (PVin). This is desirable particularly for high output voltage applications,
where we might want the device to be disabled at least until PVin exceeds the desired output voltage level.
Alternatively, the default 8 V PVin UVLO threshold may be reconfigured/overridden using the VIN_ON and
VIN_OFF PMBus™ commands or the corresponding registers. It should be noted that the input voltage is also
fed to an ADC through a 21:1 internal resistive divider. However, the digitized input voltage is used only for the
purposes of reporting the input voltage through the READ_VIN PMBus™ command. It has no impact on the bus
voltage UVLO, input over-voltage faults and input under-voltage warnings, all of which are implemented by
using analog comparators to compare the input voltage to the corresponding thresholds programmed by the
PMBus™ commands VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT and VIN_UV_WARN_LIMIT respectively. The bus
voltage reading as reported by READ_VIN has no effect on the input feedforward function either.
12V
10.2V
1 V
PVin
Vcc
> 0.6V
0.6V
EN_UVLO_START
EN
DAC2 (Reference DAC)
Figure 15 Normal Start up, device turns on when the bus voltage reaches 10.2 V. A resistor divider is
used at EN pin from PVin to turn on the device at 10.2 V.
PVin=Vin
Vcc
> 0.6V
EN
DAC2 (Reference DAC)
Figure 16 Recommended startup for Normal operation
Figure 16 shows the recommended startup sequence for the normal operation of the device, when Enable is
used as logic input.
Final Datasheet
33 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
14.6
Pre-Bias startup
The IR38164 is able to start up into pre-charged output, without oscillations or other disturbance of the output
voltage.
The output starts in asynchronous fashion and keeps the synchronous MOSFET (sync FET) off until the first gate
signal for the control MOSFET (ctrl FET) is generated. Figure 17 shows a typical pre-bias condition at start up.
[V]
Vo
Pre-Bias
Voltage
[Time]
Figure 17
Pre-Bias startup
The sync FET always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its
duty cycle with a step of 12.5% until it reaches the steady state value. There are 16 pulses in each step. This
value is internally programmed. Figure 18 shows the series of 16x8 startup pulses.
...
HDRv
...
...
...
...
87.5%
12.5%
16
25%
...
LDRv
...
...
...
End of
PB
...
16
Figure 18
Pre-bias startup pulses
14.7
Soft-Start ꢇReference DAC rampꢈ
This device has an internal soft starting DAC to control the output voltage rise and to limit the current surge at
the start-up. To ensure correct start-up, the DAC sequence initiates only after power conversion is enabled
when the Enable pin voltage exceeds its under-voltage threshold, the PVin bus voltage exceeds its under-
voltage threshold and the contents of the MTP have been fully loaded into the working registers. Figure 19
shows the waveforms during soft start. It should be noted that the part may also be configured to require
software Enable (set through the PMBus™ or the corresponding MTP register) instead of or in addition to a
ꢆhardwareꢃ signal at the Enable pin. In PMBus™ mode, the reference DAC soft-start may be delayed from the
time power conversion is enabled. The range for this programmable delay is 0 ms to 127 ms, and the resolution
is 1 ms. Further, in this mode, the soft start time may be configured from 1 ms to 127 ms with 1 ms resolution.
In SVID mode, the rise time is determined by the slow slew rate specified by Intel, and may be programmed to
one of four values: 0.625 mV/µs, 1.25 mV/µs, 2.5 mV/µs and 5 mV/µs. In this mode, the device uses 2.5 mV/µs by
default. It should be noted, however, that if Vboot is 0, the output voltage does not ramp until the CPU issues a
voltage setting command at either the fast slew rate or slow slew rate specified by the CPU.
Final Datasheet
34 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
For more details on the PMBus™ commands TON_DELAY and TON_RISE used to program the startup sequence,
please see the UN0075 IR3816x PMBus™ commandset user note.
Internal Enable
Reference
DAC
Vout
Ton_delay
t1
Ton_rise
t3
t
2
Figure 19 DAC2 (VREF) Soft start
During the startup sequence the over-current protection (OCP) and over-voltage protection (OVP) are active to
protect the device against any short circuit or over voltage conditions.
14.8
Operating frequency
Using the FREQUENCY_SWITCH PMBus™ command, or the corresponding registers, the switching frequency
may be programmed between 500 kHz and 1.5 MHz. For best telemetry accuracy, it is recommended that the
following switching frequencies be avoided: 500 kHz, 600 kHz, 750 kHz, 800 kHz, 1 MHz, 1.2 MHz and 1.5 MHz.
Instead the following values are recommended, 505 kHz, 607 kHz, 762 kHz, 813 kHz, 978 kHz, 1171 kHz and 1454
kHz respectively.
14.9
Shutdown
In the default configuration, the device can be shutdown by pulling the Enable pin below its 0.4 V threshold.
During shutdown the high side and the low side drivers are turned off. By default, the device exhibits an
immediate shutdown with no delay and no soft stop.
Alternatively, the part may be configured to allow shutdown using the OPERATION PMBus™ command or the
corresponding register. It may also be configured to allow a soft or controlled turned off. In PMBus™ mode, if
the soft-off option is used, the turn off may be delayed from the time the power conversion is disabled. The
range for this programmable delay is 0 ms to 127 ms, and the resolution is 1 ms. Further, in this mode, the soft
stop time may be configured from 1ms to 127 ms with 1 ms resolution. The programmable turn off delay only
applies in PMBus™ mode.
If VCC voltage supply is used to shutdown the system, a continuous ramp from 5V to 0V should be utilized.
Shutdown via the Enable pin is the recommended shutdown method.
Final Datasheet
35 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
14.10
Current Sensing, Telemetry and Over-Current Protection
Current sensing for both telemetry as well as over-current protection is done by sensing the voltage across the
sync FET RDS(ON). This method enhances the converter’s efficiency, reduces cost by eliminating a current sense
resistor and any minimizes sensitivity to layout related noise issues. A novel, patented scheme allows
reconstruction of the average inductor current from the voltage sensed across the Sync FET RDS(ON). It should
be noted here that it is this reconstructed average inductor current that is digitized by the ADC and used for
output current reporting as well as for over-current warning, the threshold for which may be set using the
IOUT_OC_WARN_LIMIT command. The current is reported in 1/16 A resolution using the READ_IOUT PMBus™
command. The current information may also be read back using I2C, through the 8-bit register
output_current_byte, which reports the current in 1/4 A resolution.
The Over current (OC) fault protection circuit also uses the voltage sensed across the RDS(ON) of the
Synchronous MOSFET; however, the protection mechanism relies on a fast comparator to compare the sensed
signal to the over-current threshold and does not depend on the ADC or reported current. The current limit
scheme uses an internal temperature compensated current source that has the same temperature coefficient
as the RDS(ON) of the Synchronous MOSFET. As a result, the over-current trip threshold remains almost constant
over temperature.
Over Current Protection circuitry senses the inductor current flowing through the Synchronous FET closer to
the valley point. The OCP circuit samples this current for 75 ns typically after the rising edge of the PWM set
pulse which is an internal signal that has a width of 12.5% of the switching period. The PWM pulse that turns on
the high side FET starts at the falling edge of the PWM set pulse. This makes valley current sense more robust as
current is sensed close to the bottom of the inductor downward slope where transient and switching noise is
low. This helps to prevent false tripping due to noise and transients.
The actual DC output current limit point will be greater than the valley point by an amount equal to
approximately half of the peak to peak inductor ripple current. The current limit point will be a function of the
inductor value, input voltage, output voltage and the frequency of operation. On equation 1, ILimit is the value
set when configuring the 38164 OCP value. The user should account for the inductor ripple to obtain the actual
DC output current limit.
i
IOCP ILIMIT
(1)
2
IOCP
ILIMIT
Δi
= DC current limit hiccup point
= Current Limit Valley Point
= Inductor ripple current
Final Datasheet
36 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
Over Current Limit
Hiccup Blanking Time
IL
0
HDrv
0
...
...
LDrv
0
PGood
0
Figure 20
Timing diagram for current limit hiccup
In the default configuration, if the over-current detection trips the OCP comparator for a total of 8 cycles, the
device goes into a hiccup mode. The hiccup is performed by de-asserting the internal Enable signal to the
analog and power conversion circuitry and holding it low for 20 ms.
Following this, the OCP signal resets and the converter recovers. After every hiccup cycle, the converter stays in
this mode until the overload or short circuit is removed. This behavior is shown in Figure 20.
Note that the user can override the default over-current threshold using the PMBus™ command
IOUT_OC_FAULT_LIMIT. This command can be used to program the over-current threshold from a minimum
recommended 16 A setting to a maximum of 56 A, in 4 A steps. While the IR38164 will still offer over-current
protection below 16 A and at magnitudes that are not multiples of 4, these thresholds will not be as accurate.
Therefore it’s recommended to keep the current limit setting from 16A to 56A with 4A increments. Systems with
a high inductor current ripple will affect the accuracy, refer to (1).
Also, using the PMBus™ command IOUT_OC_FAULT_RESPONSE or the corresponding registers, the part may be
configured to respond to an over-current fault in one of two ways:
1)
Pulse by pulse current limiting for a programmed number of eight switching cycles followed by a
latched shutdown.
2)
Pulse by pulse current limiting for a programmed number of eight switching cycles followed by hiccup.
The pulse-by-pulse or constant current limiting mechanism is briefly explained below.
Final Datasheet
37 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
IOUT_OC_FAULT_LIMIT
IL
20 ms
0
HDrv
0
LDrv
0
CLK
Fs
0
OCP High
1
2
3
4
5
6
7
8
Internal
Enable
Figure 21
Pulse by pulse current limiting for 8 cycles, followed by hiccup
In Figure 21 above, with the over-current response set to pulse-by-pulse current limiting for 8 cycles followed
by hiccup, the converter is operating at D<0.125 when the overcurrent condition occurs. In such a case, no duty
cycle limiting is applied.
IOUT_OC_ FAULT_ LIMIT
IL
0
HDrv
0
LDrv
0
CLK
Fs
0
1
2
3
4
5
6
7
8
9
10
11
...
Internal
Enable
Figure 22 Constant current limiting
Figure 22 depicts a case where the over-current condition happens when the converter is operating at D>0.5
and the over-current response has been set to constant current operation through pulse by pulse current
limiting. In such a case, after 3 consecutive over-current cycles are recognized, the pulse width is dropped such
that D=0.5 and then after 3 more consecutive OCP cycles, to 0.25 and then finally to 0.125 at which it keeps
running until the total OCP count reaches the programmed maximum following which the part enters hiccup
mode. Conversely, when the over-current condition disappears, the pulse width is restored to its nominal value
gradually, by a similar mechanism in reverse; every sequence of 4 consecutive cycles in which the current is
below the over-current threshold doubles the duty cycle, so that D goes from 0.125 to 0.25, then to 0.5 and
finally to its nominal value.
Final Datasheet
38 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
14.11
Current reporting limitation at high operating temperature
The IR38164 is designed to give the industry’s highest accuracy output current reporting across a range of ꢂ to
30 Amps. To achieve the goal of highest possible accuracy particularly at Iout up to 30Amps, a high gain was
used in the Rds_on current sensing circuit. As the operating temperature increases the Rds_on of the low side
MOSFET increases and at the rated current of 30A with junction temperatures around 90 °C, the ADC saturates
and no longer reads higher values of the MOSFET RDS_on. The result is that at a high operating junction
temperature condition the maximum PMBus™ and SVID current reporting is clamped as shown in Figure 23
below.
Maximum Iout reported verses IR38164 internal temperature
35
30
25
Typical (based on measured data)
20
Calculated worst case
15
10
5
0
0
20
40
60
80
IC die Temp , PMBUS reported ,C
100
120
Figure 23 Maximum Iout reported versus IR38164 reported die temperature
Note that Infineon does not recommend operating the part with a reading of the ADC being clamped, because
other readings of the ADC can be compromised. If higher Iout readings are needed, the IR38163 with a lower
gain in the Rds_on detection circuit is recommended to be used. Lastly, please note that the current limit
ability of the IR38164 is not affected by the ADC clamping. The IR38164 current limit function is performed by
an analog circuit and does not use the ADC. The OCP warn function (PMBUS setting) is however based on the
ADC output and will not function properly at a high temperature if the threshold is set higher than the
maximum current reported shown above.
Final Datasheet
39 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
14.12
Die temperature sensing, telemetry and thermal shutdown
On die temperature sensing is used for accurate temperature reporting and over-temperature detection. The
READ_TEMEPRATURE PMBus™ command reports this temperature in 10 ⁰C resolution. The temperature may
also be read back using I2C through the 8-bit register temp_byte, which reports the die temperature in 1 °C
resolution, offset by 40 °C. Thus, the temperature is given by temp_byte +40 °C.
The trip threshold is set by default to 125 °C. The default over temperature response of the device is to inhibit
power conversion while the fault is present, followed by automatic restart after the fault condition is cleared.
Hence, in the default configuration, when the trip threshold is exceeded, the internal Enable signal to the
power conversion circuitry is de-asserted, turning off both MOSFETs.
Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 25 °C
hysteresis in the thermal shutdown threshold.
The default over-temperature threshold as well as over-temperature response may be re-configured or
overridden using the OT_FAULT_LIMIT and OT_FAULT_RESPONSE PMBus™ commands respectively or the
corresponding registers may be used. The devices support three types of responses to an over-temperature
fault:
1)
2)
Ignore
Inhibit when the over-temperature condition exists and auto-restart when the over-temperature
condition disappears
3) Latched shutdown.
14.13
Remote voltage sensing
True differential remote sensing in the feedback loop is critical to high current applications where the output
voltage across the load may differ from the output voltage measured locally across an output capacitor at the
output inductor, and to applications that require die voltage sensing.
The RS+ and RS- pins form the inputs to a remote sense differential amplifier with high speed, low input offset
and low input bias current, which ensure accurate voltage sensing and fast transient response in such
applications.
The input range for the differential amplifier is limited to 1.5 V below the VCC rail. Therefore, for applications in
which the output voltage is more than 2.55 V, it is recommended to use local sensing, or if remote sensing is a
must, then the voltage between the RS+ and RS-pins must be divided down to less than 2.55 V using a resistive
voltage divider. It’s recommended that the divider be placed at the input of the remote sense amplifier and that
a low impedance such as 499 Ω be used between the RS+ and RS- nodes. A typical schematic for this setup is
shown on Figure 8 Please note, however, that this modifies the open loop transfer function and requires a
change in the compensation network to optimally stabilize the loop.
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
14.14
Feed-forward
Feed-Forward (F.F.) is an important feature, because it can keep the converter stable and preserve its load
transient performance when PVin varies over a wide range. The PWM ramp amplitude (Vramp) is
proportionally changed with PVin to maintain PVin/Vramp almost constant throughout PVin variation range (as
shown in Figure 24). Thus, the control loop bandwidth and phase margin can be maintained constant. The
feed-forward function can also minimize impact on output voltage from fast PVin changes. The feedforward is
disabled for PVin<4.7 V. Hence, for PVin<4.7 V, a re-calculation of control loop parameters is needed for re-
compensation.
21V
12V
12V
5V
PVin
0
PWM Ramp
Ramp Offset
0
Figure 24
Timing diagram for feed-forward (F.F.) function
14.15
Output voltage sensing, telemetry and faults
For this family of devices, the voltage sense and regulation circuits are decoupled, enabling ease of testing as
well as redundancy. In order to do this, the device uses the sense voltage at the dedicated Vsns pin for output
voltage reporting (in 1/256 V resolution, using the READ_VOUT PMBus™ command) as well as for power good
detection and output over-voltage protection.
Power good detection and output over-voltage detection rely on fast analog comparator circuits, whereas over-
voltage warnings as well as under-voltage faults and warnings rely on comparing the digitized Vsns to the
corresponding thresholds programmed using PMBus™ commands VOUT_OV_WARN_LIMIT,
VOUT_UV_FAULT_LIMIT and VOUT_UV_WARN_LIMIT respectively or the corresponding.
14.16
Power Good Output
The Vsns voltage is an input to the window comparator with programmable thresholds. The PGood signal is
high whenever Vsns voltage is within the PGood comparator window thresholds. The PGood pin is open drain
and it needs to be externally pulled high. High state indicates that output is in regulation. The Power Good
thresholds may be changed through the POWER_GOOD_ON and POWER_GOOD_OFF commands, which set the
rising and falling PGood thresholds respectively. The thresholds may also be programmed using the
corresponding MTP registers. However, when no resistive divider is used, such as for output voltages lower
than 2.555 V, the Power Good thresholds must be programmed to within 630 mV of the output voltage,
otherwise, the effective power good threshold changes from an absolute threshold to one that tracks the
output voltage with a 630 mV offset. By default, the PGood signal will assert as soon as the Vsns signal enters
the regulation window. In digital mode, this delay is programmable from 0 to 10 ms with a 1 ms resolution,
using the MFR_TPGDLY command.
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
The threshold is set differently in SVID mode. In this mode, the thresholds set by the POWER_GOOD_ON and
POWER_GOOD_OFF commands (or the corresponding registers) are ignored. Power Good is asserted when the
output voltage is within the tolerance band of the boot voltage. Following this, the Power Good signal remains
asserted irrespective of any output voltage transitions and is de-asserted only in the event of a fault that shuts
down power conversion, or, if so programmed, in the event of a command by the CPU to change the output
voltage to 0 V.
Fault DAC
0
Reference DAC
0
Power Good upper threshold
Vsns
0
Power Good lower threshold
PGD
0
160us
Figure 25
Power good in PMBus™ mode
Fault DAC
0
Reference DAC
0
Vboot+/-TOB
Vsns
0
PGD
0
Figure 26
Power Good in SVID mode, Vboot>0 V
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
14.17
Over-Voltage Protection ꢇOVPꢈ
Over-voltage protection is achieved by comparing sense pin voltage Vsns to a configurable over-voltage
threshold.
The OVP threshold may be reprogrammed to within 655 mV of the output voltage (for output voltages lower
than 2.555 V, without any resistive divider on the Fb pin), using the VOUT_OV_FAULT_LIMIT PMBus™ command
or the corresponding registers. For an OVP threshold programmed to be more than 655 mV greater than the
output voltage, the effective OV threshold ceases to be an absolute value and instead tracks the output voltage
with a 655 mV offset.
When Vsns exceeds the over-voltage threshold, an over-voltage trip signal asserts after 200 ns (typ.) delay. The
default response is that the high side drive signal HDrv is latched off immediately and PGood flags are set low.
The low side drive signal is kept on until the Vsns voltage drops below the threshold. HDrv remains latched off
until a reset is performed by cycling either Vcc or Enable or the OPERATION command. The device allows the
user to reconfigure this response by the use of the VOUT_OV_FAULT_RESPONSE PMBus™ command. In addition
to the default response described above, this command can be used to configure the device such that Vout
over-voltage faults are ignored and the converter remains enabled. (However, they will still be flagged in the
STATUS_REGISTERS and by SAlert). For further details on the corresponding PMBus™ commands related to
OVP, please refer to the UN0075 IR3816x PMBus™ commandset user note.
Vsns voltage is set by an external resistive voltage divider connected to the output. This divider ratio must
match the divider used on the feedback pin or on the RS+ pin.
It should be noted that the over-voltage threshold applies in PMBus™ mode as well as SVID mode.
DAC1+OV_OFFSET_DAC
Vout
DAC1
hysteresis
0
HDrv
0
LDrv
0
Comp
0
PGood
0
200 ns
200 ns
Figure 27
Timing diagram for OVP in non-tracking mode
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
14.18
Minimum On-Time Considerations
The minimum ON time is the shortest amount of time for the Control FET to be reliably turned on. This is a very
critical parameter for low duty cycle, high frequency applications. In the conventional approach, when the error
amplifier output is near the bottom of the ramp waveform with which it is compared to generate the PWM
output, propagation delays can be high enough to cause pulse skipping, and hence limit the minimum pulse
width that can be realized. Moreover, in the conventional approach, the bottom of the ramp often presents a
high gain region to the error amplifier output, making the modulator more susceptible to noise and requiring
the use of lower control loop bandwidth to prevent noise, jitter and pulse skipping.
Infineon has developed a proprietary scheme to improve and enhance the minimum pulse width which
minimizes these delays and hence, allows stable operation with small pulse-widths. At the same time, this
scheme also has greater noise immunity, thus allowing stable, jitter free operation down to very low pulse
widths even with a high control loop bandwidth, thus reducing the required output capacitance.
Any design or application using this IC must ensure operation with a pulse width that is higher than the
minimum on-time and at least 70 ns of on-time is recommended in the application. This is necessary for the
circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high
output voltage ripple.
Vout
Fs PV Fs
D
ton
(2)
in
In any application that uses this IC, the following condition must be satisfied:
ton(min) ton
(3)
Vout
ton(min)
(4)
(5)
PV Fs
in
Vout
PV Fs
in
ton(min)
The minimum output voltage is limited by the reference voltage and hence Vout(min) = 0.5 V. Therefore, for
Vout(min) = 0.5 V,
Vout
(6)
PV Fs
in
ton(min)
Therefore, at the maximum recommended input voltage of 16V with the minmum recommended frequency of
500 kHz the minimum output voltage should be => 0.56 V. Conversely for operation at a high frequency of 1 MHz
and minimum output voltage (0.5 V), the input voltage (PVin) should not exceed 7.1 V, otherwise pulse skipping
may happen. Pulse skipping is not an issue except that the ripple maybe slighty higher in this operating mode.
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
14.19
Maximum Duty Ratio
An upper limit on the operating duty ratio is imposed by the larger of a) fixed off time (dominant at high
switching frequencies) b) blanking provided by the PWMSet or clock pulse, which has a pulse width that is 1/8
of the switching period. The latter mechanism is dominant at lower switching frequencies (typically below 1.25
MHz). This upper limit ensures that the Sync FET turns on for a long enough duration to allow recharging the
bootstrap capacitor and also allows current sensing. Figure 28 shows a plot of the maximum duty ratio vs. the
switching frequency with built in input voltage feed-forward mechanism.
Figure 28
Maximum duty cycle vs. switching frequency with Vin feedforward
14.20
Bootstrap Capacitor
To drive the Control FET, it is necessary to supply a gate voltage at least 4 V greater than the voltage at the SW
pin, which is connected to the source of the Control FET. This is achieved by using a bootstrap configuration,
which comprises the internal bootstrap diode and an external bootstrap capacitor (C1) as shown in Figure 29.
Typically a 0.1 µF capacitor is used. A layout placement for a 0 ohm resistor in series with the capacitor is also
recommended. For applications where PVin>14 V, a 1 ohm resistor is required. The operation of the circuit is as
follows: When the sync FET is turned on, the capacitor node connected to SW is pulled down to ground. The
capacitor charges towards Vcc through the internal bootstrap diode which has a forward voltage drop VD. The
voltage Vc across the bootstrap capacitor C1 is approximately given as:
(7)
Vc Vcc VD
When the Control FET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage
PVin. However, if the value of C1 is appropriately chosen, the voltage Vc across C1 remains approximately
unchanged and the voltage at the Boot pin becomes:
(8)
VBoot PV V VD
in
cc
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
Cvin
PVIN
+ VD
-
Boot
V
cc
+
Vc
-
C1
SW
L
IR38164
PGnd
Figure 29
Bootstrap circuit to generate high side drive voltage
14.21
Intel SVID interface
The IR38164 implements a fully compliant Intel® VR 13, and VR 12.5 Serial VID (SVID) interface. This is a three-
wire interface between an Intel processor and a VR that consists of clock, data and alert# signals.
The IR38164 implements all the required SVID registers and commands per Intel specifications. For the selected
Intel mode, the IC also implements most of the optional commands and registers with very few exceptions.
The default SVID addresses of the devices is 02h. This address can be re-programmed in MTP or via GUI.
14.22
All Call support
All Call for the IR38164 can be configured in the following ways:
0E and 0F.
0E only.
0F only.
No All Call
The devices can be configured to be used as VR for CPU which is All Call 0F or Memory which is All Call 0E.
14.23
VRꢁꢄ.ꢅ operation
VR 12.5 mode is selectable via MTP bit. The boot voltage in VR 12.5 is also selectable and can be taken from the
boot registers. The resolution is programmable via MTP bit to 10 mV to be compatible to VR12.5 mode.
14.24
VRꢁꢀ operation
VR 13 mode is selectable via MTP bit. The boot voltage in VR13 mode is configured in the boot register. The
resolution is programmable via MTP bit to 5 mV or 10 mV, to be compatible to VR13 mode.
14.25
Set Work Point
This family of devices supports SVID Set WP command to Set VID voltage for all rails through all call address.
When the processor asserts a Set WP command, all the rails of the VR settle to the corresponding new set
voltage encoded in WP registers. Slew rate and power state of all the rails are identical during a set work point
operation.
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Theory of operation
14.26
Dynamic VID slew rate
The device provides the VR designer 16 fast slew rates that govern the rate of VID transitions. The slow slew rate
is also programmable as a function of the fast slew rate, and 4 different options are available for each setting
of the fast slew rate as shown below in Table 12.
Table 12
Slew Rates
Fast Rate
x 1/2
x 1/4
x 1/8 Factor
x 1/16 Factor
mV/us
Factor
Factor
10
5.0
7.5
10
2.50
3.75
5.00
6.25
7.5
1.25
1.875
2.50
3.125
3.75
4.375
5.0
0.0625
0.94
1.25
1.56
1.88
2.19
2.5
15
20
25
12.5
15
30
35
17.5
20
8.75
10
40
45
22.5
25
11.25
12.5
13.75
15
5.625
6.25
6.875
7.5
2.81
3.125
3.4375
3.75
4.0625
4.375
5
50
55
27.5
30
60
65
32.5
35
16.25
17.5
20
8.125
8.75
10
70
80
40
14.27
Loop compensation
Feedback loop compensation is achieved using standard Type III techniques and the compensation values can
be easily calculated using Infineon’s design tool. The design tool can also be used to predict the control
bandwidth and phase margin for the loop for any set of user defined compensation component values. For a
theoretical understanding of the calculations used, please refer to Infineon’s Application Note AN-1162
ꢆCompensator Design Procedure for Buck Converter with Voltage-Mode Error-Amplifierꢃ.
14.28
Dynamic VID compensation
This family of devices uses an analog control scheme with voltage mode control. In this scheme, the
compensator acts on the Vout signal and not just on the error signal. For load and line transients, with a steady
and unchanging reference voltage, this has the same dynamic characteristics as for a compensator that acts on
only the error signal. However, for reference voltage changes, as in the case of Dynamic VID, the dynamics are
altered. A proprietary dynamic VID compensation scheme allows the dynamic VID response to be tuned
optimally to the feedback compensator values. Once properly optimized, the output voltage will follow the DAC
more closely during a positive dynamic VID, and provide better dynamic VID alert timing, as required by Intel®
processors. Infineon’s SupIRBuck design tool will allow the user to quickly and conveniently calculate the
dynamic VID compensation parameters for optimal dynamic VID response.
Final Datasheet
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
IꢄC and PMBus™ communication protocols
15
IꢄC and PMBus™ communication protocols
15.1
IꢄC Protocols
All registers may be accessed using either I2C or PMBus™ protocols. I2C allows the use of a simple format
whereas PMBus™ provides error checking capability. Figure 30 shows the I2C format employed by IC.
S: Start Condition
1
S
7
Slave
Address
1
1
8
1
8
1
1
P
A: Acknowledge (0')
N: Not Acknowledge (1')
Sr: Repeated Start Condition
P: Stop Condition
Register
Address
WRITE
READ
A
A
A
W
Data Byte
R: Read (1')
1
7
1
1
P
1
S
7
Slave
Address
1
8
1
S
1
R
8
W: Write (0')
Register
Address
Slave
Address
A
Data Byte
A
A
N
W
PEC: Packet Error Checking
*: Present if PEC is enabled
: Master to Slave
: Slave to Master
Figure 30
I2C format
15.2
SMBus/PMBus™ protocols
To access IR’s configuration and monitoring registers, ꢇ different protocols are required:
the SMBus Read/Write Byte/Word protocol with/without PEC (for status and monitoring)
the SMBus Send Byte protocol with/without PEC (for CLEAR_FAULTS only)
the SMBus Block Read protocol for accessing Model and Revision information
the SMBus Process call (for accessing Configuration Registers)
In addition, IC supports:
Alert Response Address (ARA)
Bus timeout
Group Command for writing to many VRs within one command
These various commands are illustrated in Figure 31 through Figure 37 below.
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
IꢄC and PMBus™ communication protocols
S: Start Condition
8
1
S
7
Slave
Address
1
1
8
1
8
1
1
1
P
A: Acknowledge (0')
N: Not Acknowledge (1')
Sr: Repeated Start Condition
P: Stop Condition
Command
Code
A*
BYTE
A
A
Data Byte
A
PEC*
W
1
S
1
R: Read (1')
7
Slave
Address
1
8
8
1
Command
Code
Data Byte
Low
W: Write (0')
WORD
A
A
A
W
…
PEC: Packet Error Checking
*: Present if PEC is enabled
: Master to Slave
1
8
1
1
P
8
Data Byte
High
A*
PEC*
A
: Slave to Master
Figure 31
SMBus write byte/word
1
1
P
1
1
1
8
1
1
7
Slave
Address
1
R
1
8
1
7
Slave
Address
8
Command
Code
Data Byte
A*
A
A
A
PEC*
N
BYTE
S
W
Sr
1
S
7
Slave
Address
1
1
8
1
1
7
Slave
Address
1
R
1
8
1
Command
Code
Data Byte
Low
A
A
Sr
A
A
WORD
W
…
1
1
8
1
8
Data Byte
High
A*
PEC*
N
P
Figure 32
Figure 33
SMbus read byte/word
1
S
7
Slave
Address
1
1
8
1
8
1
1
P
Command
Code
PEC*
A
A*
A
W
SMBus send byte
1
S
7
Slave
Address
1
1
8
1
Command
Code
W
A
A
…
1
7
Slave
Address
1
R
1
8
8
8
1
1
1
1
Byte Count =1
Data Byte
A*
A
A
PEC*
N
P
Sr
Figure 34
Figure 35
SMBus block read with byte count = 1
PMBus
Address
Command
D1h
Register
Address
Data Byte
PEC*
S
W
A
A
A
A
A
P
MFR specific command to write an internal register
Final Datasheet
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V2.2
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IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
IꢄC and PMBus™ communication protocols
PMBus
Address
Command
D0h
Register
Address
S
W
A
A
A
...
PMBus
Address
Address+1
Data Byte
Data Byte
PEC*
Sr
R
A
A
A*
N
P
Figure 36
SMBus custom protocol call to read an internal register
1
S
7
Slave
Address 1
1
1
8
1
8
Low
Data Byte
1
8
High
Data Byte
1
8
1
Command
Code 1
A*
A
A
A
W
A
PEC1*
…
…
…
1 or more bytes
7
Slave
Address 2
1
1
1
8
1
8
Low
Data Byte
1
8
High
Data Byte
1
8
1
Command
Code 2
A
A*
A
A
A
Sr
W
PEC2*
…
1 or more bytes
1
7
1
1
1
8
1
8
1
8
1
8
1
Low
Data Byte
Slave
Address n
Command
Code n
High
Data Byte
A
A
A
P
Sr
W
A
A
PECn*
…
1 or more bytes
Figure 37
Group command
Final Datasheet
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V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
IꢄC and PMBus™ communication protocols
15.3
Supported PMBus™ commands
Table 13
Command
Code
SMBus
transaction bytes
No. of
Resolutio
n
Default
Value
Command Name
Range
Description
01h
02h
OPERATION
ON_OFF_CONFIG
R/W Byte
R/W Byte
1
1
Enables or disables the device and controls margining
Configures the combination of Enable pin input and
serial bus commands needed to turn the unit on and off.
Clear contents of Fault registers
03h
10h
CLEAR_FAULTS
Send Byte
R/W Byte
0
1
WRITE_PROTECT
Used to control writing to the PMBus™ device. The
intent of this command is to provide protection against
accidental changes.
15h
16h
STORE_USER_ALL
Send Byte
Send Byte
0
0
Burns the User section registers into OTP memory
RESTORE_USER_A
LL
Copies the OTP registers into User memory
19h
1Bh
CAPABILITY
Read Byte
1
2
Returns 1011xxxx to indicate Packet Error Checking is
supported, maximum bus speed is 400 kHz and
SMBAlert# is supported.
May be used to prevent a warning or fault condition
from asserting the SMBALERT# signal.
SMBALERT_MASK
VOUT_COMMAND16
Write
word/Block
read
Process call
R/W Word
21h
2
0-
2.555V/
VS
-128-
+128V
5mV/VS
1V
Causes the device to set its output voltage to the
commanded value.
VS= VOUT_SCALE_LOOP
22h
24h
VOUT_TRIM16
VOUT_MAX16
R/W Word
R/W Word
2
2
0V
2V
Available to the device user to trim the output voltage
Sets an upper limit on the output voltage the unit can
command regardless of any other commands or
combinations.
25h
26h
27h
29h
VOUT_MARGIN_HI
GH16
R/W Word
R/W Word
2
2
2
2
0-
2.555V/
VS
0-
2.555V/
VS
5mV/VS
5mV/VS
Sets the MARGIN high voltage when commanded by
OPERATION
VS= VOUT_SCALE_LOOP
Sets the MARGIN low voltage when commanded by
OPERATION
VL= VOUT_SCALE_LOOP
VOUT_MARGIN_LO
W16
VOUT_TRANSITION R/W Word
_RATE11
0-
0.0625mV/ 0.0625mV/us Sets the rate in mV/μs at which the output should
63.9mV/ us
us
0.125-1
change voltage. Exponent 0 to -4 allowed.
VOUT_SCALE_LOO
P11
R/W Word
1
Compensates for external resistor divider in feedback
path and in the sense path. Values 1, 0.5, 0.25, 0.125
allowed. Exponent -3 allowed.
33h
35h
FREQUENCY_SWIT
CH11
R/W Word
R/W Word
2
2
504-
1500kHz
0-16.5V
978kHz
8.0V
Sets the switching frequency, in kHz. Exponent 0 to 1
allowed.
Sets the value of the input voltage, in volts, at which the
unit should start power conversion. Exponent -1
allowed.
Sets the value of the input voltage, in volts, at which the
unit, once operation has started, should stop power
conversion. Exponent -1 allowed.
VIN_ON11
0.5V
0.5V
36h
VIN_OFF11
R/W Word
2
0-16V
7.0V
39h
40h
IOUT_CAL_OFFSET
R/W Word
R/W Word
2
2
-128A-
+127.5A
(25-
655mV)/
VS
0.25A
0A
Used to null out any offsets in the output current
sensing circuit. Exponent -2 allowed.
Sets the value of the output voltage measured at the
sense pin that causes an output over-voltage fault.
VS= VOUT_SCALE_LOOP
11
VOUT_OV_FAULT_
LIMIT16
10mV/VS
2.102V
41h
VOUT_OV_FAULT_
RESPONSE
R/W Byte
1
Ignore/S
hutdow
n
Shutdown Instructs the device on what action to take in response
to an output over-voltage fault. Ignore =0x00h,
Shutdown = 0x80h.
42h
43h
VOUT_OV_WARN_L R/W Word
2
2
3.9mV
3.9mV
1.902V
Sets the value of the output voltage at the
sense pin that causes an output voltage high warning.
Sets the value of the output voltage at the
sense pin that causes an output voltage low warning.
IMIT16
VOUT_UV_WARN_L R/W Word
0.902V
IMIT16
Final Datasheet
51 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
IꢄC and PMBus™ communication protocols
Command
Code
SMBus
transaction bytes
No. of
Resolutio
n
Default
Value
Command Name
Range
Description
44h
VOUT_UV_FAULT_
LIMIT16
VOUT_UV_FAULT_
RESPONSE
R/W Word
R/W Byte
2
1
3.9mV
0.898V
Sets the value of the output voltage at the
sense pin that causes an output under-voltage fault.
Instructs the device on what action to
45h
46h
Ignore/S
hutdow
n
Ignore
40A
take in response to an output under-voltage fault.
IOUT_OC_FAULT_L R/W Word
IMIT11
2
1
3-40A
0.5A
Sets the value of ILimit (valley), allowing user to set the
output current in amperes, that causes the over-
current detector to indicate an over-current fault.
Exponent -1 allowed.
47h
IOUT_OC_FAULT_
RESPONSE
R/W Byte
Pulse by
Instructs the device on what action to
pulse for 8 take in response to an output over-current fault.
cycles
followed by
hiccup, retry
after 20 ms
4Ah
4Fh
50h
IOUT_OC_WARN_L
IMIT11
R/W Word
R/W Word
R/W Byte
2
2
1
0-63.5A
0.5A
35A
Sets the value of the output current, in
amperes, that causes the over-current detector to
indicate an over-current warning. Exponent -1 allowed.
Set the temperature, in degrees Celsius, of the unit at
which it should indicate an over-temperature fault.
Exponent 0 allowed.
OT_FAULT_LIMIT11
0-150°C
1°C
125°C
OT_FAULT_RESPO
NSE
Ignore/S
hutdow
n/ Auto-
start
Auto-start Instructs the device on what action to take in response
to an over-temperature fault.
51h
OT_WARN_LIMIT11
R/W Word
2
0-150°C
1°C
100°C
Set the temperature, in degrees Celsius, of the unit at
which it should indicate an over-temperature warning
alarm. Exponent 0 allowed.
55h
56h
VIN_OV_FAULT_LI
MIT11
VIN_OV_FAULT_RE
SPONSE
R/W Word
R/W Byte
2
1
6.25V-
24V
Ignore/S
hutdow
n
0.25V
15V
Sets the value of the input voltage that causes an input
over-voltage fault. Exponent -2 allowed.
Instructs the device on what action to take
in response to an input over-voltage fault.
Ignore
58h
5Eh
5Fh
60h
VIN_UV_WARN_LIM R/W Word
IT11
2
2
2
2
0-16V
0.5V
10mV/VS
10mV/VS
1ms
7.5V
0.5V
Sets the value of the input voltage PVin, in volts,
that causes an input over-voltage fault. Exponent -1
allowed.
Sets the output voltage at which an optional
POWER_GOOD signal should be asserted.
VS=VOUT_SCALE_LOOP
Sets the output voltage at which an optional
POWER_GOOD signal should be negated.
VS=VOUT_SCALE_LOOP
Sets the time, in milliseconds, from when a start
condition is received (as programmed by the
ON_OFF_CONFIG command) until the output voltage
starts to rise. Exponent 0 allowed.
POWER_GOOD_ON
R/W Word
R/W Word
R/W Word
(0-
0.63V)/V
16
S
POWER_GOOD_OF
F16
(0-
0.63V)/V
S
0.25V
0ms
TON_DELAY11
0-127ms
61h
62h
TON_RISE11
R/W Word
R/W Word
2
2
0-127ms
0-127ms
1ms
1ms
1ms
Sets the time, in milliseconds, from when the output
starts to rise until the voltage has entered the
regulation band. Exponent 0 allowed.
TON_MAX_FAULT_
LIMIT11
0 (Disabled) Sets an upper limit, in milliseconds, on how long the
unit can attempt to power up the output without
reaching the output under-voltage fault limit. Exponent
0 allowed.
63h
64h
TON_MAX_FAULT_
RESPONSE
R/W Byte
R/W Word
1
2
Ignore/S
hutdow
n
Ignore
Instructs the device on what action to
take in response to a TON_MAX fault.
TOFF_DELAY
0-127ms
1ms
1ms
0ms
Sets the time, in milliseconds, from a stop condition is
received (as programmed by the ON_OFF_CONFIG
command) until the unit stops transferring energy to
the output. Exponent 0 allowed.
Sets the time, in milliseconds, in which the reference
voltage ramps down to zero (If a soft off is allowed by
the configuration of the ON_OFF_CONFIG command).
Exponent 0 allowed.
65h
78h
TOFF_FALL
R/W Word
Read Byte
2
1
0-127ms
1ms
STATUS BYTE
Returns 1 byte where the bit meanings are:
Bit <7> device busy fault
Final Datasheet
52 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
IꢄC and PMBus™ communication protocols
Command
Code
SMBus
transaction bytes
No. of
Resolutio
n
Default
Value
Command Name
Range
Description
Bit <6> output off (due to fault or enable)
Bit <5> Output over-voltage fault
Bit <4> Output over-current fault
Bit <3> Input under-voltage fault
Bit <2> Temperature fault
Bit <1> Communication/Memory/Logic fault
Bit <0>: None of the above
79h
STATUS WORD
Read Word
2
Returns 2 bytes where the Low byte is the same as the
STATUS_BYTE data. The High byte has bit meanings are:
Bit <7> Output high or low fault
Bit <6> Output over-current fault
Bit <5> Input under-voltage fault
Bit <4> Reserved; hardcoded to 0
Bit <3> Output power not good
Bit <2:0> Hardcoded to 0
7Ah
7Bh
7Ch
7Dh
STATUS_VOUT
STATUS_IOUT
STATUS_INPUT
Read Byte
Read Byte
Read Byte
Read Byte
1
1
1
1
Reports types of VOUT related faults.
Reports types of IOUT related faults.
Reports types of INPUT related faults.
STATUS_TEMPERA
TURE
Returns over- temperature warning and over-
temperature fault (OTP level). Does not report under-
temperature warning/fault. The bit meanings are:
Bit <7> Over-Temperature Fault
Bit <6> Over-Temperature Warning
Bit <5> Under-Temperature Warning
Bit <4> Under-Temperature Fault
Bit <3:0> Reserved
7Eh
STATUS_CML
Read Byte
1
Returns 1 byte where the bit meanings are:
Bit <7> Command not Supported
Bit <6> Invalid data
Bit <5> PEC fault
Bit <4> OTP fault
Bit <3:2> Reserved
Bit<1> Other communication fault
Bit<0> Other memory or logic fault; hardcoded to 0
Returns the input voltage in volts
88h
8Bh
8Ch
8Dh
READ_VIN11
READ_VOUT16
READ_IOUT11
Read Word
Read Word
Read Word
2
2
2
2
Returns the output voltage in volts
Returns the output current in amperes
Returns the device temperature in degrees Celsius
READ_TEMPERATU Read Word
RE11
96h
98h
READ_POUT11
Read Word
2
1
Returns the output power in watts
PMBUS™_REVISIO
Read Byte
Reports PMBus™ Part I rev 1.2 & PMBus™
Part II rev 1.2
N
99h
9Ah
MFR_ID
Block
Read/Write
Block
2
3
IR
Returns ꢀ bytes used to read the manufacturer’s ID.
User can overwrite with any value.
MFR_MODEL
Set 000000 If set to 000000h, returns a 1 byte code corresponding to
IC_DEVICE_ID. Alternatively, user can set to any non-zero
value
Read/Write
9Bh
ADh
MFR_REVISION
Block
Read/Write
3
Set 000000 If set to 000000h, returns a 1 byte code corresponding to
IC_DEVICE_REV.
Alternatively, user can set to any non-zero value
Used to read the type or part number of an IC.
IR38164: 6Dh
IC_DEVICE_ID
Block Read
Block Read
2
1
AEh
IC_DEVICE_REV
Used to read the revision of the IC
Final Datasheet
53 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
IꢄC and PMBus™ communication protocols
Command
Code
SMBus
transaction bytes
No. of
Resolutio
n
Default
Value
Command Name
Range
Description
D0h
MFR_READ_REG
Custom
Write Word
R/W Word
2
2
2
Manufacturer Specific: Read from configuration
registers
D1h
D8h
MFR_WRITE_REG
MFR_TPGDLY
Manufacturer Specific: Write to configuration & status
registers
0-10ms
0-1
1ms
0ms
CCM
10h
Sets the delay in milliseconds, between the output
voltage entering the regulation window and the
assertion of the PGood signal. Exponent 0 allowed.
Allows the user to choose between forced continuous
conduction mode and adaptive on-time operation at
light load.
D9h
MFR_FCCM
R/W Byte
R/W Word
1
D6h
DBh
MFR_I2C_address
MFR_VOUT_PEAK16 Read Word
1
2
0-7Fh
Sets and returns the device I2C base address
Continuously records and reports the highest value of
Read Vout.
Continuously records and reports the highest value of
Read Iout.
Continuously records and reports the highest value of
Read_Temperature
DCh
DDh
MFR_IOUT_PEAK11 Read Word
2
2
MFR_TEMPERATUR Read Word
E_PEAK11
Notes
11 Uses LINEAR11 format
16 Uses LINEAR16 format with exponent set to-8
Final Datasheet
54 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
PCB footprint and layout recommendations
16
PCB footprint and layout recommendations
16.1
Layout recommendations
PCB layout is very important when designing high frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with less than expected results.
Make the connections for the power components on the top layer with wide, copper filled areas or shapes. In
general, it is desirable to make proper use of power planes and polygons for power distribution and heat
dissipation.
The input capacitors, inductor, output capacitors and the IR38164 should be as close to each other as possible.
This helps to reduce the EMI radiated by the power traces due to the high switching currents through them.
Place the input capacitor directly at the PVin pin of IR38164. The feedback part of the system should be kept
away from the inductor and other noise sources. The critical bypass components such as capacitors for Vin,
Vcc, and 1.8 V should be close to their respective pins. It is important to place the feedback components
including feedback resistors and compensation components close to Fb and Comp pins.
In a multilayer PCB, use one layer as a power ground plane and have a control circuit ground (analog ground) to
which all signals are referenced. The goal is to localize the high current path to a separate loop that does not
interfere with the more sensitive analog control functions. These two grounds must be connected together on
the PC board layout at a single point. It is recommended to place all the compensation parts over the analog
ground plane in top layer.
IR38164 has three pins, SCL, SDA and SALERT# that are used for I2C/PMBus™ communication. It is
recommended that the traces used for these communication lines be at least 10 mils wide with spacing
between the SCL and SDA traces that is at least 2-3 times the trace width. Follow the Intel® recommended PCB
routing techniques for the SVID interface.
The Power QFN is a thermally enhanced package. To effectively remove heat from the device, the exposed pad
should be connected to the ground planes using multiple vias.
As shown in the PCB layout:
Allow enough copper for PVin, GND and Vout
All bypass capacitors are placed as close as possible to their connecting pins
Components for loop compensation are placed as close as possible to the COMP pin
AGND is connected to the inner PGND plane through via holes
Resistor Rt is placed as close as possible to the Rt pin
SW node copper should only be routed on the top layer to minimize switching noises
Fb and Vsns trace routing are kept away from SW node
Thermal via holes are placed on PVIN and PGND pads to aid thermal dissipation
Final Datasheet
55 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
PCB footprint and layout recommendations
16.2
PCB Metal and Component Placement
Evaluation has shown that the best overall performance is achieved using the substrate/PCB layout as shown in
the following figures. PQFN devices should be placed to an accuracy of 0.050 mm on both X and Y axes. Self-
centering behavior is highly dependent on solders and processes, and experiments should be run to confirm
the limits of self-centering on specific processes.
For further information, please refer to ꢆSupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead
(PQFN) Board Mounting Application Note.ꢃ ꢈANꢉꢉꢊꢀꢅ.
All dimensions in the following figures are in mm.
The PCB pads and component footprint are shown in Figure 38.
Figure 38
PCB pads and component
16.3
PCB copper and solder resist
Infineon recommends that larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the
underlying copper traces to be as large as possible, which helps in terms of current carrying capability and
device cooling capability.
When using SMD pads, the underlying copper traces should be at least 0.05 mm larger (on each edge) than the
Solder Mask window, in order to accommodate any layer to layer misalignment (i.e. 0.1 mm in X & Y).
For smaller signal type leads around the edge of the device, Infineon recommends that these are Non Solder
Mask Defined (NSMD) or Copper Defined.
When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025 mm
on each edge, (i.e. 0.05 mm in X&Y,) in order to accommodate any layer to layer misalignment.
Ensure that the solder resist in-between the smaller signal lead areas is at least 0.15 mm wide, due to the high
x/y aspect ratio of the solder mask strip.
Recommendations are shown in Figure 39 and Figure 40.
Final Datasheet
56 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
PCB footprint and layout recommendations
Figure 39
PCB copper and solder resist (pad sizes)
Figure 40
PCB copper and solder resist (pad spacing)
16.4
PCB solder paste stencil
Stencils for PQFN packages can be used with thicknesses of 0.100-0.250 mm (0.004-ꢂ.ꢂꢉꢂꢃꢅ. Stencils thinner
than 0.100 mm are unsuitable because they deposit insufficient solder paste to make good solder joints with
the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125 mm-0.200
mm (0.005-ꢂ.ꢂꢂꢋꢃꢅ, with suitable reductions, give the best results.
A recommended stencil design is shown in Figure 41 and Figure 42. This design is for a stencil thickness of 0.127
mm ꢈꢂ.ꢂꢂꢄꢃꢅ. The reduction should be adjusted for stencils of other thicknesses.
Final Datasheet
57 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
PCB footprint and layout recommendations
Figure 41
Solder paste stencil (pad sizes)
Figure 42
Solder paste stencil (pad spacing)
Final Datasheet
58 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Marking and package information
17
Marking and package information
17.1
Final production marking
Figure 43
Package marking
17.2
Early production marking
Figure 44
Package marking
Final Datasheet
59 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Marking and package information
17.3
Package dimensions
Package dimensions are shown in Figure 45 through Figure 47.
Figure 45
Package dimensions
Final Datasheet
60 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Marking and package information
Figure 46
Package dimensions
Figure 47
Package dimensions
Final Datasheet
61 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Environmental Qualifications
18
Environmental Qualifications
Table 14
Qualification Level
Industrial
Moisture Sensitivity
5mm x 7mm PQFN
MSL 2 260C
Human Body Model
(JESD22-A114-F)
JEDEC Class 1C
ESD
Charged Device Model
(JESD22-C101-F)
JEDEC Class 3
RoHS Compliant
Yes (with Exemption 7a)
Final Datasheet
62 of 64
V2.2
Feb 6 2019
IRꢀ8ꢁꢂꢃ OptiMOS™ iPOL
30A Single-voltage Synchronous Buck Regulator with SVID
Table of contents
19
References
[1] UN7005 IR3816x_ PMBus™ Command Set
[2] Application Note AN-1162. Compensator Design Procedure for Buck Converter with Voltage-Mode Error-
Amplifier.
[3] Application Note AN-ꢉꢉꢊꢀ. SupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN)
Board Mounting Application Note.
Final Datasheet
63 of 64
V2.2
Feb 6 2019
OptiMOSꢀiPOL
IR38164
RevisionꢀHistory
IR38164
Revision:ꢀ2019-03-25,ꢀRev.ꢀ2.2
Previous Revision
Revision Date
Subjects (major changes since last revision)
1.0
1.1
2.0
2.1
2.2
Release of preliminary version
Updated OCP limit.
2018-01-23
2018-02-13
2018-05-23
2018-09-26
2019-03-25
Release of final version
Updated package drawings.
Current reporting limation and corrected PMBUS spec revision.
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64
Rev.ꢀ2.2,ꢀꢀ2019-03-25
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