IR38265M [INFINEON]
OptiMOS™ IPOL DC-DC转换器，单输入电压，30A降压稳压器，配备PVID;
| 型号： | IR38265M |
| 厂家： | 
Infineon |
| 描述： | OptiMOS™ IPOL DC-DC转换器，单输入电压，30A降压稳压器，配备PVID DC-DC转换器 稳压器 |
| 文件： | 总55页 (文件大小：2976K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DCDC Converter
OptiMOS™ IPOL
IR38265
Single-input Voltage, 30A Buck
Regulators with PVID
FEATURES
DESCRIPTION
Internal LDO allows single 16V operation
Output Voltage Range: 0.5V to 0.875*PVin
0.5% accurate Reference Voltage
Enhanced line/load regulation with Feedforward
Frequency programmable by I2C up to 1.5 MHz
Enable input with Voltage Monitoring Capability
This family of OPTIMOS IPOL devices offers easy-to-use,
fully integrated and highly efficient DC/DC regulators with
PVID and I2C interface. The on-chip PWM controller and co-
packaged low duty cycle optimized MOSFETs make these
devices a space-efficient solution, providing accurate power
delivery for low output voltage and high current
Remote Sense Amplifier with True Differential
Voltage Sensing
applications that require a parallel VID interface.
3 pins (PVID) to program output voltage
These versatile devices offer programmability of switching
frequency, output voltage, and fault/warning thresholds
and fault responses while operating over a wide input
range. Thus, they offer flexibility as well as system level
security in event of fault conditions.
Fast mode I2C interface for programming,
sequencing and margining output voltage, and for
monitoring input voltage, output voltage, output
current and temperature.
I2C configurable fault thresholds for input UVLO,
output OVP, OCP and thermal shutdown.
Thermally compensated pulse-by-pulse current
limit and Hiccup Mode Over Current Protection
Dedicated output voltage sensing for power good
indication and overvoltage protection which
remains active even when Enable is low.
The switching frequency is programmable from 150 kHz to
1.5 MHz for an optimum solution.
The on-chip sensors and ADC along with the PVID and I2C
interfaces make it easy to monitor and report input voltage,
output voltage, output current and temperature.
Enhanced Pre-Bias Start up
Integrated MOSFET drivers and Bootstrap diode
Operating junction temp: -40oC<Tj<125oC
Thermal Shut Down
Post Package trimmed rising edge dead-time
I2C Programmable Power Good Output
Small Size 5mmx7mm PQFN
Pb-Free (RoHS Compliant)
External resistor allows setting up to 16 PMBus
addresses
APPLICATIONS
Intel® VR13 and VR12.5 based systems
Servers and High End Desktop CPU VRs for non-
core applications
Telecom and storage applications
BASIC APPLICATION
For applications in which Pvin>14V, a 1 ohm resistor is required in series with the boot capacitor.
5.5V <Vin<16V
Optional placeholder for boot resistor.
Default should be 0 ohm
For PVin >14V, a 1 ohm resistor is
required
P1V8
PVin
Enable Vin
Boot
Vo
Vcc/
LDO_out
SW
Vsns
RS+
PGood
PGood
RS-
VIDSEL0
VIDSEL1
RSo
Fb
3 bit
PVID
VIDSEL2
ADDR
Comp
LGnd
PGnd
Placeholder
for capacitor
Figure 1: Typical application circuit
1
Rev 3.5
Jun 7, 2019
IR38265
PIN DIAGRAM
Figure 2: IR38265 Package Top View
5mm X 7mm PQFN
ORDERING INFORMATION
Tape and Reel
Description
Package
Qty
Part Number
PQFN
4000
IR38265MTRPbF
30A Buck Regulator with PVID and I2C for PVNN
2
Rev 3.5
Jun 7, 2019
IR38265
FUNCTIONAL BLOCK DIAGRAM
VCC
Vin
P1V8
LDO
VLDOref
LDO
LGND
COMP
-
OT_Fault
+
UVcc
OC_Fault
BOOT
PVIN
VCC
UVcc
FAULT
CONTROL
UVEN
Fault
Fault
VDAC2
HDrv
+
-
E/A
HDin
GATE
DRIVE
LOGIC
OV_Fault
FCCM
SW
FB
VCC
LDrv
LDin
Enable
PGND
Rso
CONTROL AND FAULT LOGIC
RS-
PGood
RS+
ISense
TMON
Current Sense
SDA
SCL
SVID Interface, SMBus
Interface,
Logic, Command and Status registers
Temperature
Sense
Vcc
ADDR
Vsns
VIDSEL2
VIDSEL0
VIDSEL1
Figure 3: Simplified Block Diagram for IR38265
3
Rev 3.5
Jun 7, 2019
IR38265
PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
1
PVIN
Input voltage for power stage. Bypass capacitors between PVin and PGND should be
connected very close to this pin and PGND. Typical applications use four 22 uF input
capacitors and a low ESR, low ESL 0.1uF decoupling capacitor in a 0603/0402 case size. A
3.3nF capacitor may also be used in parallel with these input capacitors to reduce ringing on
the Sw node.
2
Boot
Supply voltage for high side driver. A 0.1uF capacitor should be connected from this pin to
the Sw pin. It is recommended to provide a placement for a 0 ohm resistor in series with the
capacitor. For applications in which PVin>14V, a 1 ohm resistor is required in series with
boot capacitor.
3
4
ENABLE
ADDR
Enable pin to turn on and off the IC.
A resistor should be connected from this pin to LGnd to set the I2C address offset for the
device. It is recommended to provide a placement for a 10 nF capacitor in parallel with the
offset resistor.
5
6
Vsns
FB
Sense pin for OVP and PGood. Typically connected to a local Vout capacitor at the output of
the inductor.
Inverting input to the error amplifier. This pin is connected directly to the output of the
regulator or to the output of the remote sense amplifier, via resistor divider to set the output
voltage and provide feedback to the error amplifier.
7
8
COMP
RSo
Output of error amplifier. An external resistor and capacitor network is typically connected
from this pin to FB to provide loop compensation.
Remote Sense Amplifier Output. When the remote sense amplifier is used, this is connected
to the feedback compensation network.
9
RS-
RS+
Remote Sense Amplifier input. Connect to ground at the load.
Remote Sense Amplifier input. Connect to output at the load.
10
11
PGood
Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to VCC.
If the power good voltage before VCC UVLO needs to be limited to < 500 mV, use a 49.9K
pullup, otherwise a 4.99K pullup will suffice.
12,25
PGND
Power ground. This pin should be connected to the system’s power ground plane. Bypass
capacitors between PVin and PGND should be connected very close to PVIN pin (pin 1) and
this pin.
13
14
LGND
Signal ground for internal reference and control circuitry. This should be connected to the
PGnd plane at a quiet location using a single point connection.
VIDSEL0
Used to select VID voltage registers. This is the LSB of the 3 bit PVID code that is internally
decoded to select the register containing the target voltage. Only connect to Vcc via a
4.99KΩ resistor and do not use a direct connection. Do not exceed 6V.
15
16
VIDSEL1
VIDSEL2
Used to select VID voltage registers. Only connect to Vcc via a 4.99KΩ resistor and do not
use a direct connection. Do not exceed 6V.
Used to select VID voltage registers. This is the MSB of the 3 bit PVID code that is internally
decoded to select the register containing the target voltage. Only connect to Vcc via a
4.99KΩ resistor and do not use a direct connection. Do not exceed 6V.
17
18
NC
NC
SDA
I2C data serial input/output line. This should be pulled up to 3.3V-5V with a 1K-5K resistor
4
Rev 3.5
Jun 7, 2019
IR38265
PIN #
PIN NAME
PIN DESCRIPTION
19
20
SCL
I2C clock line. This should be pulled up to 3.3V-5V with a 1K-5K resistor
P1V8
This is the supply for the digital circuits; bypass with a 10uF capacitor to PGnd. A 2.2uF
capacitor is valid however a 10uF capacitor is recommended.
21
22
Vin
Input Voltage for LDO. A 1 uF capacitor is placed from this pin to PGnd. If the internal bias
LDO is used, tie this pin to PVin. If an external bias voltage (typically 5V) is available for Vcc,
tie the Vin pin to Vcc.
VCC
Bias Voltage for IC and driver section, output of LDO. Add 10 uF bypass cap from this pin to
PGnd.
23,26
24
NC
NC
SW
Switch node. This pin is connected to the output inductor.
5
Rev 3.5
Jun 7, 2019
IR38265
ABSOLUTE MAXIMUM RATINGS
Stresses beyond these listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
PVin, Vin
-0.3V to 25V
VCC
-0.3V to 6V
P1V8
-0.3V to 2 V
SW
-0.3V to 25V (DC), -4V to 25V (AC, 100ns)
-0.3V to 31V
BOOT
BOOT to SW
-0.3V to 6V (DC) (Note 1), -0.3V to 6.5V (AC, 100ns)
-0.3V to 6V (Note 1)
PGD, other Input/output pins
PGND to GND, RS- to GND
-0.3V to + 0.3V
THERMAL INFORMATION
Junction to ambient thermal resistance θJA
Junction to board thermal resistance θJB
Junction to case top thermal resistance θJC(top)
11.1 C/W (Note 2)
4.16 C/W (Note 3)
18.9 C/W (Note 4)
Junction to case top thermal parameter ΨJT (top)
0.32 C/W (Note 2)
-55°C to 150°C
Storage Temperature Range
Junction Temperature Range
-40°C to 150°C
(Voltages referenced to GND unless otherwise specified)
Note 1: Must not exceed 6V.
Note 2: Value obtained via thermal simulation under natural convention on a PVNN, IR38263 demo board.
10 layer, 7” x 5.5”x0.072” PCB with 1.5 oz copper at the top and bottom layer. Inner layers 2, 3, 8 and 9 have
1 oz copper and layers 4,5,6,7 have 2 oz copper. Ta = 25C was used for the simulation.
Note 3: PCB from note 2 and package is considered in thermal simulation with Ta=25 ⁰C. Pin 12 is considered.
Note 4: Only package is considered. Simulation is used with a cold plate that fixes top of package at Ta=25 ⁰C.
6
Rev 3.5
Jun 7, 2019
IR38265
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
SYMBOL
DEFINITION
MIN
MAX
UNITS
PVin
Input Bus Voltage
1.5
5.3
4.5
4.5
0.5
0
16*
16
V
Vin
LDO supply voltage
LDO output/Bias supply voltage
High Side driver gate voltage
Output Voltage
VCC
5.5
Boot to SW
5.5
VO
IO
0.875*PVin
30
Output Current
A
Fs
TJ
Switching Frequency
Junction Temperature
150
-40
1500
125
kHz
°C
* SW Node must not exceed 25V
PARAMETER
MOSFET Rds(on)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Rds(on)_Top
Rds(on)_Bot
Top Switch
VBoot – VSW = 5V, ID = 30A, Tj
= 25°C
2.2
mΩ
Bottom Switch
Vcc =5V, ID = 30A, Tj = 25°C
0.78
Reference Voltage
1.25V<VFB<2.555V
VOUT_SCALE_LOOP=1;
-1
+1
%
Accuracy
00C<Tj<850C
0.75V<VFB<1.25V
VOUT_SCALE_LOOP=1;
-0.75
-0.5
+0.75
+0.5
0.45V<VFB<0.75V
%
%
VOUT_SCALE_LOOP=1;
1.25V<VFB<2.555V
VOUT_SCALE_LOOP=1;
-1.6
-1.0
-2.0
+1.6
+1.0
+2.0
Accuracy
-400C<Tj<1250C
0.75V<VFB<1.25V
VOUT_SCALE_LOOP=1;
%
%
0.45V<VFB<0.75V
VOUT_SCALE_LOOP=1;
Supply Current
PVin range (using
external Vcc=5V)
1.5-
16
V
V
Vin range (using internal
LDO)
Fsw=600kHz
5.3-
16
7
Rev 3.5
Jun 7, 2019
IR38265
PARAMETER
SYMBOL
CONDITIONS
Fsw=1.5MHz
MIN
TYP
MAX
UNIT
5.5-
16
Vin range (when
Vin=Vcc)
4.5
5.0
2.7
39
5.5
4
V
Iin(Standby)
Vin Supply Current
(Standby) (internal Vcc)
Enable low, No Switching,
Vin=16V, low power mode
enabled
mA
mA
mA
mA
Iin(Dyn)
Vin Supply Current
(Dyn)(internal Vcc)
Enable high, Fs = 600kHz,
Vin=16V
50
5
Icc(Standby)
VCC Supply Current
(Standby)(external Vcc)
Enable low, No Switching,
Vcc=5.5V, low power mode
enabled
2.7
39
Icc(Dyn)
VCC Supply Current
(Dyn)(external Vcc)
Enable high, Fs = 600kHz,
Vcc=5.5V
50
Under Voltage Lockout
VCC – Start – Threshold
VCC – Stop – Threshold
VCC_UVLO_Start
VCC_UVLO_Stop
Enable_UVLO_Start
VCC Rising Trip Level
VCC Falling Trip Level
Supply ramping up
4.0
3.7
4.2
3.9
4.4
4.1
V
Enable – Start –
Threshold
0.55
0.35
0.6
0.4
0.65
V
Enable_UVLO_Stop
Ien
Enable – Stop –
Threshold
Supply ramping down
Enable=5.5V
0.45
1
Enable leakage current
Oscillator
µA
Vramp
Ramp Amplitude
PVin=5V, D=Dmax, Note 2
PVin=12V, D=Dmax, Note 2
PVin=16V,D=Dmax, Note 2
Note 2
0.71
1.84
2.46
0.22
35
Vp-p
Ramp (os)
Dmin (ctrl)
Ramp Offset
Min Pulse Width
Fixed Off Time
Max Duty Cycle
Error Amplifier
Input Bias Current
Sink Current
V
Note 2
50
150
89
ns
ns
%
Note 2 Fs=1.5MHz
Fs=400kHz
100
87.5
Dmax
86
IFb(E/A)
Isink(E/A)
Isource(E/A)
SR
-0.5
0.6
8
+0.5
1.8
25
µA
mA
mA
V/µs
MHz
dB
1.1
13
Source Current
Slew Rate
Note 2
Note 2
Note 2
7
12
20
GBWP
Gain-Bandwidth Product
DC Gain
20
100
2.8
30
40
Gain
110
3.9
120
4.3
100
Vmax(E/A)
Vmin(E/A)
Maximum Voltage
Minimum Voltage
V
mV
8
Rev 3.5
Jun 7, 2019
IR38265
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Remote Sense Differential Amplifier
BW_RS
Unity Gain Bandwidth
Note 2
Note 2
3
6.4
MHz
dB
Gain_RS
DC Gain
110
0.5V<RS+<2.555V, 4kOhm
load
270C<Tj<850C
-1.6
-3
0
1.6
3
Offset_RS
Offset Voltage
mV
0.5V<RS+<2.555V, 4kOhm
load
-400C<Tj<1250C
Isource_RS
Isink_RS
Slew_RS
Rin_RS+
Rin_RS-
Source Current
Sink Current
V_RSO=1.5V, V_RSP=4V
11
0.4
2
16
2
mA
mA
1
4
Slew Rate
Note 2, Cload = 100pF
8
V/µs
Kohm
Kohm
V
RS+ input impedance
RS- input impedance
Maximum Voltage
Minimum Voltage
Bootstrap Diode
Forward Voltage
Switch Node
36
36
0.5
55
55
1
74
74
1.5
20
Note 2
Vmax_RS
Min_RS
V(VCC) – V(RS+)
4
mV
I(Boot) = 40mA
150
300
18
450
1
mV
µA
lsw
SW Leakage Current
SW = 0V, Enable = 0V
SW=0; Enable= 2V
Isw_En
Internal Regulator (VCC/LDO)
VCC
Output Voltage
Vin(min) = 5.5V, Io=0mA,
Cload = 10uF
4.8
4.5
5.15
4.99
5.4
5.2
0.7
V
Vin(min) = 5.5V, Io=70mA,
Cload = 10uF
VCC_drop
Ishort
VCC dropout
Io=0-70mA, Cload = 10uF,
Vin=5.1V
V
Short Circuit Current
110
mA
Internal Regulator (P1V8)
P1V8
Output Voltage
Vin(min) = 4.5V, Io = 0‐
1mA, Cload = 2.2uF
1.8V Rising Trip Level
1.795
1.83
1.905
V
P1V8_UVLO_Start
P1V8_UVLO_Stop
1.8V UVLO Start
1.8V UVLO Stop
1.66
1.59
1.72
1.63
1.78
1.68
V
V
1.8V Falling Trip Level
Adaptive On time Mode
ZC_Vth
Zero-crossing
comparator threshold
-4
-1
2
mV
s
ZC_Tdly
Zero-crossing
comparator delay
8/Fs
9
Rev 3.5
Jun 7, 2019
IR38265
PARAMETER
SYMBOL
CONDITIONS
FAULTS
MIN
TYP
MAX
UNIT
Power Good
TPDLY
Power Good High
Threshold Rising Delay
Vsns rising, Vsns >
Power_Good_High
0
ms
VPG_low_Dly
PG (voltage)
Power Good Low
Threshold Falling delay
Vsns falling, Vsns <
Power_Good_Low
150
175
200
0.5
µs
V
PGood Voltage Low
IPGood = -5mA
Over Voltage Protection (OVP)
OVP (trip)
OVP Trip Threshold
Vsns rising,
VOUT_SCALE_LOOP=1,
Vout=0.5V
0.60
5
0.57
20
0.63
40
V
OVP (hyst)
OVP comparator
Hysteresis
Vsns falling,
VOUT_SCALE_LOOP=1,
Vout=0.5V
30
mV
ns
OVP (delay)
OVP Fault Prop Delay
Vsns rising, Vsns-
OVP(trip)>200 mV
200
Over-Current Protection
ITRIP
OC limit=40, VCC = 5.05V,
Tj=250C
36
40
16
44
A
A
OC Trip Current
OC limit=16A, VCC = 5.05V,
Tj=250C
12.5
19.5
OCSET(temp)
Tblk_Hiccup
OCset Current
Temperature coefficient
-400C to 1250C, VCC=5.05V,
Note 2
5900
20
ppm/°C
ms
Hiccup blanking time
Thermal Shutdown
Thermal Shutdown
Hysteresis
Note 2
Note 2
Note 2
145
25
°C
°C
Input Over-Voltage Protection
PVinOV
PVin overvoltage
threshold
22
23.7
2.4
25
V
V
PVin ov hyst
PVin overvoltage
Hysteresis
MONITORING AND REPORTING
Bus Speed1
100
78
400
kHz
Hz
Iout & Vout filter
31.2
5
Iout & Vout Update rate
Vin & Temperature filter
kHz
Hz
78
Vin
update rate
&
Temperature
31.2
5
kHz
10
Rev 3.5
Jun 7, 2019
IR38265
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Output Voltage Reporting
Resolution
NVout
1/256
0
Note 2
V
V
Vomon_low
Vomon_high
Lowest reported Vout
Highest reported Vout
Vsns=0V
VOUT_SCALE_LOOP=1,
Vsns=3.3V
3.3
6.6
V
V
V
V
VOUT_SCALE_LOOP=0.5,
Vsns=3.3V
VOUT_SCALE_LOOP=0.25,
Vsns=3.3V
13.2
26.4
VOUT_SCALE_LOOP=0.125
, Vsns=3.3V
Vout reporting accuracy
00C to 850C, 4.5V<Vcc<5.5V,
1V<Vsns≤ 1.5V
VOUT_SCALE_LOOP=1
+/-
0.6
00C to 850C, 4.5V<Vcc<5.5V,
Vsns> 1.5V
+/-1
VOUT_SCALE_LOOP=1
%
00C to 1250C,
4.5V<Vcc<5.5V, Vsns>0.9V
VOUT_SCALE_LOOP=1
+/-
1.5
00C to 1250C,
4.5V<Vcc<5.5V,
0.5V<Vsns<0.9V
VOUT_SCALE_LOOP=1
+/-3
Iout Reporting
NIout
Resolution
Note 2
0.06
25
A
A
Iout_dig
I
Iout (digital) monitoring
Range
0
40
00C to 1250C,
4.5V<Vcc<5.5V, 5A < Iout
<30A
Iout_dig Accuracy
+/-5
1
%
Temperature Reporting
NTmon
Resolution
Note 2
Note 2
°C
°C
Tmon_dig
Temperature Monitoring
Range
-40
150
Thermal shutdown
hysteresis
25
°C
Input Voltage Reporting
Resolution
NPVin
Note 2
1/32
V
V
PMBVinmon
Monitoring Range
Monitoring accuracy
0
21
00C to 850C, 4.5V<Vcc<5.5V,
-1.5
1.5
11
Rev 3.5
Jun 7, 2019
IR38265
PARAMETER
SYMBOL
CONDITIONS
PVin>10V
MIN
TYP
MAX
UNIT
%
-400C to 1250C,
4.5V<Vcc<5.5V, PVin>14V
-1.5
-4
1.5
4
-400C to 1250C,
4.5V<Vcc<5.5V,
7V<PVin<14V
I2C Interface Timing Specifications
FSMB
I2C Operating frequency
400
kHz
µs
TBUF
Bus Free time between
Start and Stop condition
1.3
0.6
THD:STA
Hold time after
(Repeated) Start
Condition. After this
period, the first clock is
generated.
µs
TSU:STA
Repeated start condition
setup time
0.6
0.6
µs
µs
TSU:STO
Stop condition setup
time
Data Rising Threshold
Data Falling Threshold
Clock Rising Threshold
Clock Falling Threshold
1.339
1.048
1.339
1.048
1.766
1.495
1.766
1.499
V
V
V
V
Data Rising Threshold
LVT
0.7
0.45
0.7
0.9
0.65
0.9
V
V
V
V
Data Falling Threshold
LVT
Clock Rising Threshold
LVT
Clock Falling Threshold
LVT
0.45
0.65
900
THD:DAT
Data Hold Time
300
100
ns
ns
TSU:DAT
Data Setup Time
Data pulldown
resistance
8
11
16
35
Ω
TTIMEOUT
Clock low time out
25
1.3
0.6
ms
µs
µs
TLOW
Clock low period
THIGH
Clock High Period
50
Digital Inputs – Low Vth Type 2 (VIDSELx)
-
-
Input High Voltage
0.65
V
12
Rev 3.5
Jun 7, 2019
IR38265
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Input Low Voltage
Hysteresis
-
-
-
-
95
-
0.45
-
V
mV
µA
Input Leakage Current
Vpad = 0 to 2V
±1
Notes
2. Guaranteed by design but not tested in production
3. Guaranteed by statistical correlation, but not tested in production
13
Rev 3.5
Jun 7, 2019
IR38265
TYPICAL APPLICATION DIAGRAMS
5.5V <Vin<16V
Optional placeholder for boot resistor.
Default should be 0 ohm
For PVin >14V, a 1 ohm resistor is
required
P1V8
PVin
Enable
Vin
Boot
SW
Vo
Vcc/
LDO_out
Vsns
RS+
PGood
PGood
RS-
VIDSEL0
VIDSEL1
RSo
Fb
3 bit
PVID
VIDSEL2
ADDR
Comp
LGnd
PGnd
Placeholder
for capacitor
Figure 4: Using the internal LDO, Vo < 2.555V
For applications in which Pvin>14V, a 1 ohm resistor is required in series with the boot capacitor.
5.5V <Vin<16V
Optional placeholder for boot resistor.
Default should be 0 ohm
Boot
P1V8
PVin
Enable
Vin
Vo
Vcc/
LDO_out
SW
Vsns
RS+
PGood
R2
PGood
RS-
VIDSEL0
CPU
serial
bus
RSo
Fb
Recommend R2=499 ohm
VIDSEL1
VIDSEL2
Comp
LGnd
ADDR
PGnd
Placeholder
for capacitor
Figure 5: Using the internal LDO, Vo > 2.555V
14
Rev 3.5
Jun 7, 2019
IR38265
TYPICAL APPLICATION DIAGRAMS
1.5V <PVin<16V
Optional placeholder for boot resistor.
Default should be 0 ohm
For PVin >14V, a 1 ohm resistor is
required
P1V8
PVin
Enable
Vin
Boot
Vcc=5V
PGood
Vo
Vcc/
LDO_out
SW
Vsns
RS+
PGood
RS-
VIDSEL0
VIDSEL1
VIDSEL2
3 bit
PVID
RSo
Fb
Comp
LGnd
ADDR
PGnd
Placeholder
for capacitor
Figure 6: Using external Vcc, Vo<2.555V
PVin=Vin=Vcc= 5V
Optional placeholder for boot resistor.
Default should be 0 ohm
Boot
P1V8
PVin
Enable
Vin
Vo
Vcc/
LDO_out
SW
Vsns
RS+
PGood
PGood
RS-
VIDSEL0
VIDSEL1
VIDSEL2
RSo
Fb
3 bit
PVID
Comp
LGnd
ADDR
PGnd
Placeholder
for capacitor
Figure 7: Single 5V application, Vo<2.555V
15
Rev 3.5
Jun 7, 2019
IR38265
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
16
Rev 3.5
Jun 7, 2019
IR38265
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
17
Rev 3.5
Jun 7, 2019
IR38265
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
18
Rev 3.5
Jun 7, 2019
IR38265
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
19
Rev 3.5
Jun 7, 2019
IR38265
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = 12V, VCC = 5V, Io=0-30A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the
inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table below
shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
LOUT (uH)
0.15
P/N
DCR (mΩ)
0.15
0.8
1
HCB178380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-101 (Delta)
FP1308R3-R32-R (Cooper)
FP1308R3-R32-R (Cooper)
0.15
0.15
0.15
0.15
0.32
0.32
0.15
0.15
0.15
0.15
0.32
0.32
1.2
1.5
1.8
3.3
5
20
Rev 3.5
Jun 7, 2019
IR38265
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = 12V, Internal LDO, Io=0-30A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the
inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table below
shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
LOUT (uH)
0.15
P/N
DCR (mΩ)
0.15
0.8
1
HCB178380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-101 (Delta)
FP1308R3-R32-R (Cooper)
FP1308R3-R32-R (Cooper)
0.15
0.15
0.15
0.15
0.32
0.32
0.15
0.15
0.15
0.15
0.32
0.32
1.2
1.5
1.8
3.3
5
21
Rev 3.5
Jun 7, 2019
IR38265
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = VCC = 5V, Io=0-30A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the inductor,
input and output capacitors are also considered in the efficiency and power loss curves. The table below shows the
indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
LOUT (uH)
0.1
P/N
DCR (mΩ)
0.15
0.8
1
1.2
1.5
1.8
HCB138380D-101 (Delta)
HCB138380D-101 (Delta)
HCB138380D-101 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
0.1
0.15
0.15
0.15
0.15
0.15
0.15
0.15
22
Rev 3.5
Jun 7, 2019
IR38265
THERMAL DERATING CURVES
The measurements were done on an evaluation kit demo board. The PCB is 7.0” x 5.5” x 0.072” with 10-layers,
FR4 material and 2 oz. copper. The conditions used were, PVin = Vin = 12V, Internal LDO, Io=30A, Fs= 978kHz.
IR38265 Thermal Derating Curves
PVin=12V, Vout=1V, Fsw=978kHz
31
29
27
25
23
0 LFM
21
200 LFM
400 LFM
19
17
15
25
30
35
40
45
50
55
60
65
70
75
80
85
TAmb (˚C)
23
Rev 3.5
Jun 7, 2019
IR38265
THEORY OF OPERATION
DESCRIPTION
The IR38265 is a 30A rated synchronous buck converter that supports II2C communication. This device also has
3 pins that function as a parallel VID interface that can be used to set the output voltage to one of eight pre-
programmed settings. They use an externally compensated fast, analog, PWM voltage mode control scheme to
provide good noise immunity as well as fast dynamic response in a wide variety of applications. At the same time,
the digital communication interfaces allow complete configurability of output setting and fault functions, as well as
telemetry.
The switching frequency is programmable from 150 kHz to 1500 kHz and provides the capability of optimizing the
design in terms of size and performance. Recommend 500 kHz or higher frequencies.
This device provides precisely regulated output voltages from 0.5V to 0.875*PVin programmed via two external
resistors or through the communication interfaces. They operate with an internal bias supply (LDO), typically 5.2V.
This allows operation with a single supply. The output of this LDO is brought out at the Vcc pin and must be
bypassed to the system power ground with a 10 uF decoupling capacitor. The Vcc pin may also be connected to
the Vin pin, and an external Vcc supply between 4.5V and 5.5V may be used, allowing an extended operating bus
voltage (PVin) range from 1.5V to 16V.
The device utilizes the on-resistance of the low side MOSFET (synchronous MOSFET) as current sense element.
This method enhances the converter’s efficiency and reduces cost by eliminating the need for external current
sense resistor.
The IR38265 includes two low Rds(on) MOSFETs using Infineon’s OptiMOS technology. These are specifically
designed for low duty cycle, high efficiency applications.
DEVICE POWER-UP AND INITIALIZATION
During the power-up sequence, when Vin is brought up, the internal LDO converts it to a regulated 5.2V at Vcc.
There is another LDO which further converts this down to 1.8V to supply the internal digital circuitry. An under-
voltage lockout circuit monitors the voltage of VCC pin and the P1V8 pin, and holds the Power-on-reset (POR)
low until these voltages exceed their thresholds and the internal 48 MHz oscillator is stable. When the device
comes out of reset, it initializes a multiple times programmable (MTP) memory load cycle, where the contents of
the MTP are loaded into the working registers. Once the registers are loaded from MTP, the designer can use the
I2C interface to re-configure the various parameters to suit the specific VR design requirements if desired,
irrespective of the status of Enable.
The typical default configuration utilizes the internal LDO to supply the VCC rail when PVin is brought up. For this
configuration power conversion is enabled only when the Enable pin voltage exceeds its under-voltage threshold,
the PVin bus voltage exceeds its under-voltage threshold, the contents of the MTP have been fully loaded into the
working registers and the device address has been read. The initialization sequence is shown in Figure 8.
Another common default configuration uses an external power supply for the VCC rail. While in this configuration
it is recommended to ensure the VCC rail reaches its target voltage prior the enable signal goes high.
Additional options are available to enable the device power conversion through software and these options may
be configured to override the default by using the I2C interface.
24
Rev 3.5
Jun 7, 2019
IR38265
PVIN=VIN
VCC
P1V8
UVOK
clkrdy
POR
Initialization
done
Enable
Vout
Figure 8: Initialization sequence showing PVin, Vin, Vcc, 1.8V, Enable and Vout signals as well as the internal logic
signals
I2C COMMUNICATION
The IR38265 has two 7-bit registers that are used to set the base I2C address, as shown below in Table 1.
Table 1: Registers used to set device base address
Register
Description
I2C_address[6:0]
The chip I2C address. An
address of 0 will disable
I2C communication.
In addition, a resistor may be connected between the ADDR and LGND pins to set an offset from the default
preconfigured I2C address (0x10) in the MTP. Up to 16 different offsets can be set, allowing 16 devices with
unique addresses in a single system. This offset, and hence, the device address, is read by the internal 10 bit
ADC during the initialization sequence.
Table 2 below provides the resistor values needed to set the 16 offsets from the base address.
Table 2 : Address offset vs. External Resistor(RADDR
)
ADDR Resistor
Address Offset
(Ohm)
+0
+1
+2
+3
+4
+5
+6
+7
+8
499
1050
1540
2050
2610
3240
3830
4530
5230
25
Rev 3.5
Jun 7, 2019
IR38265
+9
6040
6980
+10
+11
+12
+13
+14
+15
7870
8870
9760
10700
>11800
The device will then respond to I2C commands sent to this address. There is also a register bit
I2C_disable_addr_offset that may be set in order to instruct the device to ignore the resistor offset. If this bit is set,
the device will always respond to commands sent to the base address.
MODES FOR SETTING OUTPUT VOLTAGES
The IR38265 uses the VIDSEL0, VIDSEL1 and VIDSEL2 lines to set the output voltage. The VIDSELx lines select
an MTP register which holds a VID value that sets the output voltage. The MTP registers are programmable via
I2C. Note that the same VID value can result in different voltages depending on which VID table, 5mV or 10mV
has been selected. Table 3 shows how the VIDSELx lines are used to select the register containing the target
value. It is worth noting that the VIDSEL lines may be driven with logic gates or with Open drain devices. When
driven by open drain devices, a pullup resistor of 4.99K must be used. When driven by logic gates, a resistor of
4.99K is required in series with the pin. The VID tables for 5mV and 10mV VID steps are shown in the tables 4
and 5 below.
Table 3: Mapping the VIDSEL lines to MTP registers
VIDSEL2
VIDSEL1
VIDSEL0
Selects MTP register address
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
26
Rev 3.5
Jun 7, 2019
IR38265
Table 4: Intel 5mV VID table
VID
Voltage
(V)
1.52
1.515
1.51
1.505
1.5
1.495
1.49
1.485
1.48
1.475
1.47
1.465
1.46
1.455
1.45
1.445
1.44
1.435
1.43
1.425
1.42
1.415
1.41
1.405
1.4
1.395
1.39
1.385
1.38
1.375
1.37
1.365
1.36
1.355
1.35
1.345
1.34
1.335
1.33
1.325
1.32
1.315
1.31
1.305
1.3
1.295
1.29
1.285
1.28
1.275
1.27
1.265
1.26
1.255
1.25
VID
Voltage
(V)
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
1.18
1.175
1.17
1.165
1.16
1.155
1.18
1.175
1.17
1.165
1.16
1.155
1.15
1.145
1.14
1.135
1.13
1.125
1.12
1.115
1.11
1.105
1.1
1.095
1.09
1.085
1.08
1.075
1.07
1.065
1.06
1.055
1.05
1.045
1.04
1.035
1.03
1.025
1.02
1.015
1.01
1.005
1
0.995
0.99
VID
Voltage
(V)
0.97
0.965
0.96
0.955
0.95
0.945
0.94
0.935
0.93
0.925
0.92
0.915
0.91
0.905
0.9
0.895
0.89
0.885
0.88
0.875
0.87
0.865
0.86
0.855
0.85
0.845
0.84
0.835
0.83
0.825
0.82
0.815
0.81
0.805
0.8
0.795
0.79
0.785
0.78
0.775
0.77
0.765
0.76
0.755
0.75
0.745
0.74
0.735
0.73
0.725
0.72
0.715
0.71
0.705
0.7
VID
Voltage
(V)
0.68
0.675
0.67
0.665
0.66
0.655
0.65
0.645
0.64
0.635
0.63
0.625
0.62
0.615
0.61
0.605
0.6
0.685
0.68
0.675
0.67
0.665
0.66
0.655
0.65
0.645
0.64
0.635
0.63
0.625
0.62
0.615
0.61
0.605
0.6
0.595
0.59
0.585
0.58
0.575
0.57
0.565
0.56
0.555
0.55
0.545
0.54
0.535
0.53
0.525
0.52
0.515
0.51
0.505
0.5
VID
Voltage
(V)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
2F
2E
2D
2C
2B
2A
29
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
17
16
15
14
13
12
11
10
F
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
EF
EE
ED
EC
EB
EA
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CF
CE
CD
CC
CB
CA
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
BF
BE
BD
BC
BB
BA
B9
B8
B7
B6
BB
BA
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
AF
AE
AD
AC
AB
AA
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
9F
9E
9D
9C
9B
9A
99
91
90
8F
8E
8D
8C
8B
8A
89
88
87
86
85
84
83
82
81
80
7F
7E
7D
7C
7B
7A
79
78
77
76
75
74
73
72
71
70
6F
6E
6D
6C
6B
6A
69
68
67
66
65
64
63
62
61
60
5F
5E
5D
5C
5B
5A
59
58
57
56
55
54
53
52
51
50
4F
4E
4D
4C
4B
4A
49
48
47
58
57
56
55
54
53
52
51
50
4F
4E
4D
4C
4B
4A
49
48
47
46
45
44
43
42
41
40
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
33
32
31
30
0.48
0.475
0.47
0.465
0.46
0.455
0.45
0.445
0.44
0.435
0.43
0.425
0.42
0.415
0.41
0.405
0.4
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
98
97
96
95
94
93
92
1.245
1.24
1.235
0.985
0.98
0.975
0.695
0.69
0.685
0.495
0.49
0.485
27
Rev 3.5
Jun 7, 2019
IR38265
Table 4: Intel 10mV VID table
VID
VOLTAGE
(V)
VID
VOLTAGE
(V)
VID
VOLTAGE
(V)
VID
VOLTAGE
(V)
VID
VOLTAGE
(V)
(HEX)
(HEX)
(HEX)
(HEX)
(HEX)
17
16
15
14
13
12
11
10
F
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
EF
EE
ED
EC
EB
EA
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CF
CE
CD
CC
CB
CA
C9
C8
C7
C6
3.04
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
2.95
2.94
2.93
2.92
2.91
2.90
2.89
2.88
2.87
2.86
2.85
2.84
2.83
2.82
2.81
2.80
2.79
2.78
2.77
2.76
2.75
2.74
2.73
2.72
2.71
2.70
2.69
2.68
2.67
2.66
2.65
2.64
2.63
2.62
2.61
2.60
2.59
2.58
2.57
2.56
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
C5
C4
C3
C2
C1
C0
BF
BE
BD
BC
BB
BA
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
AF
AE
AD
AC
AB
AA
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
9F
9E
9D
9C
9B
9A
99
2.46
2.45
2.44
2.43
2.42
2.41
2.40
2.39
2.38
2.37
2.36
2.35
2.34
2.33
2.32
2.31
2.30
2.29
2.28
2.27
2.26
2.25
2.24
2.23
2.22
2.21
2.20
2.19
2.18
2.17
2.16
2.15
2.14
2.13
2.12
2.11
2.10
2.09
2.08
2.07
2.06
2.05
2.04
2.03
2.02
2.01
2.00
1.99
1.98
1.97
1.96
1.95
1.94
1.93
1.92
1.91
1.90
1.89
8B
8A
89
88
87
86
85
84
83
82
81
80
7F
7E
7D
7C
7B
7A
79
78
77
76
75
74
73
72
71
70
6F
6E
6D
6C
6B
6A
69
68
67
66
65
64
63
62
61
60
5F
5E
5D
5C
5B
5A
59
58
57
56
55
54
53
52
1.88
1.87
1.86
1.85
1.84
1.83
1.82
1.81
1.80
1.79
1.78
1.77
1.76
1.75
1.74
1.73
1.72
1.71
1.70
1.69
1.68
1.67
1.66
1.65
1.64
1.63
1.62
1.61
1.60
1.59
1.58
1.57
1.56
1.55
1.54
1.53
1.52
1.51
1.50
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.40
1.39
1.38
1.37
1.36
1.35
1.34
1.33
1.32
1.31
51
50
4F
4E
4D
4C
4B
4A
49
48
47
46
45
44
43
42
41
40
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
33
32
31
30
2F
2E
2D
2C
2B
2A
29
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
1.30
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
1.19
1.18
1.17
1.16
1.15
1.14
1.13
1.12
1.11
1.10
1.09
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
0.94
0.93
0.92
0.91
0.90
0.89
0.88
0.87
0.86
0.85
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
0.74
0.73
0.72
0.71
0.70
0.69
0.68
0.67
0.66
0.65
0.64
0.63
0.62
0.61
0.60
0.59
0.58
0.57
0.56
0.55
0.54
0.53
0.52
0.51
0.50
E
D
C
B
A
9
8
7
6
5
4
3
2
1
98
97
96
95
94
93
92
91
90
8F
8E
8D
8C
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IR38265
BUS VOLTAGE UVLO
If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be
ensured that the device does not turn on until the bus voltage reaches the desired level as shown in Figure 9.
Only after the bus voltage reaches or exceeds this level and voltage at the Enable pin exceeds its threshold
(typically 0.6V) will the device be enabled. Therefore, in addition to being logic input pin to enable the converter,
the Enable feature, with its precise threshold, also allows the user to override the default under-Voltage Lockout
for the bus voltage (PVin). This is desirable particularly for high output voltage applications, where we might want
the device to be disabled at least until PVin exceeds the desired output voltage level. Alternatively, the default 8 V
PVin UVLO threshold may be reconfigured/overridden using the corresponding registers. It should be noted that
the input voltage is also fed to an ADC through a 21:1 internal resistive divider. However, the digitized input
voltage is used only for the purposes of reporting the input voltage through a 8-bit register v12_supply [7:0]. It has
no impact on the bus voltage UVLO, input overvoltage faults and input undervoltage warnings, all of which are
implemented by using analog comparators to compare the input voltage to the corresponding thresholds
programmed into the I2C registers. The bus voltage reading as reported by v12_supply has no effect on the input
feedforward function either.
12V
10.2V
1 V
PVin
Vcc
> 0.6V
0.6V
EN_UVLO_START
EN
DAC2 (Reference DAC)
Figure 9: Normal Start up, device turns on when the bus voltage reaches 10.2V. A resistor divider is used at EN pin
from PVin to turn on the device at 10.2V.
PVin=Vin
Vcc
> 0.6V
EN
DAC2 (Reference DAC)
Figure 10: Recommended startup for Normal operation
Figure 10 shows the recommended startup sequence for the normal operation of the device, when Enable is used
as logic input.
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IR38265
PRE-BIAS STARTUP
The IR38265 can start up into a pre-charged output, which prevents oscillation and disturbances of the output
voltage.
The output starts in asynchronous fashion and keeps the synchronous MOSFET (Sync FET) off until the first gate
signal for control MOSFET (Ctrl FET) is generated. Figure 11 shows a typical Pre-Bias condition at start up. The
sync FET always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty
cycle with a step of 12.5%, with 16 cycles at each step, until it reaches the steady state value. Figure 12 shows
the series of 16x8 startup pulses.
[V]
Vo
Pre-Bias
Voltage
[Time]
Figure 11: Pre-Bias startup
...
HDRv
...
...
...
...
87.5%
12.5%
16
25%
...
LDRv
...
...
...
End of
PB
...
16
Figure 12: Pre-Bias startup pulses
SOFT-START (REFERENCE DAC RAMP)
An internal soft starting DAC controls the output voltage rise and limit the current surge at the start-up. To ensure
correct start-up, the DAC sequence initiates only after power conversion is enabled when the Enable pin voltage
exceeds its undervoltage threshold, the PVin bus voltage exceeds its undervoltage threshold and the contents of
the MTP have been fully loaded into the working registers. Figure 13 shows the waveforms during soft start. The
output voltage rises with a slew rate of 0.625 mv/us.
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IR38265
Internal Enable
Reference
DAC
Vout
Ton_rise
t1
t 2
Figure 13: DAC2 (VREF) Soft start
During the startup sequence the over-current protection (OCP) and over-voltage protection (OVP) are active to
protect the device against any short circuit or over voltage condition.
OPERATING FREQUENCY
Using the corresponding I2C registers, the switching frequency may be programmed between 150 kHz and 1.5
MHz. For best telemetry accuracy, it is recommended that the following switching frequencies be avoided: 250
kHz, 300 kHz, 400 kHz, 500 kHz, 600 kHz, 750 kHz, 800 kHz, 1 MHz, 1.2 MHz and 1.5 MHz. Instead, Infineon
suggests using the following values 251 kHz, 302 kHz, 403 kHz, 505 kHz, 607 kHz, 762 kHz, 813 kHz, 978 kHz,
1171 kHz and 1454 kHz respectively.
SHUTDOWN
In the default configuration, the device can be shutdown by pulling the Enable pin below its 0.4V threshold.
During shutdown the high side and the low side drivers are turned off. By default, the device exhibits an
immediate shutdown with no delay and no soft stop.
Part may also be configured to allow a soft or controlled turned off. If the soft-stop option is used, the output
voltage slews down at 0.625 mV/us.
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CURRENT SENSING, TELEMETRY AND OVER CURRENT PROTECTION
Current sensing for both, telemetry as well as overcurrent protection is done by sensing the voltage across the
sync FET RDson. This method enhances the converter’s efficiency, reduces cost by eliminating a current sense
resistor and any minimizes sensitivity to layout related noise issues. A novel, patented scheme allows
reconstruction of the average inductor current from the voltage sensed across the Sync FET Rdson. It should be
noted here that it is this reconstructed average inductor current that is digitized by the ADC and used for output
current reporting as well as for overcurrent warning, the threshold for which may be set using the I2C commands.
The current information can be read back through the 8-bit register output_current_byte, which reports the current
in 1/4 A resolution.
The Over current (OC) fault protection circuit also uses the voltage sensed across the RDS(on) of the Synchronous
MOSFET; however, the protection mechanism relies on a fast comparator to compare the sensed signal to the
overcurrent threshold and does not depend on the ADC or reported current. The current limit scheme uses an
internal temperature compensated current source that has the same temperature coefficient as the RDS(on) of the
Synchronous MOSFET. As a result, the over-current trip threshold remains almost constant over temperature.
Over Current Protection circuitry senses the inductor current flowing through the Synchronous FET closer to the
valley point. The OCP circuit samples this current for 75 ns typically after the rising edge of the PWM set pulse
which is an internal signal that has a width of 12.5% of the switching period. The PWM pulse that turns on the
high side FET starts at the falling edge of the PWM set pulse. This makes valley current sense more robust as
current is sensed close to the bottom of the inductor downward slope where transient and switching noise is low.
This helps to prevent false tripping due to noise and transients.
The actual DC output current limit point will be greater than the valley point by an amount equal to approximately
half of the peak to peak inductor ripple current. The current limit point will be a function of the inductor value, input
voltage, output voltage and the frequency of operation. On equation 1, ILimit is the value set when configuring the
38265 OCP value. The user should account for the inductor ripple to obtain the actual DC output current limit.
i
2
IOCP ILIMIT
(1)
IOCP
ILIMIT
Δi
= DC current limit hiccup point
= Current Limit Valley Point
= Inductor ripple current
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IR38265
Current Limit
Hiccup
Tblk_Hiccup
20 ms
IL
0
HDrv
...
...
0
LDrv
0
PGood
0
Figure 14: Timing Diagram for Current Limit Hiccup
In the default configuration, if the overcurrent detection trips the OCP comparator for a total of 8 cycles, the device
goes into a hiccup mode. The hiccup is performed by de-asserting the internal Enable signal to the analog and
power conversion circuitry and holding it low for 20 ms.
Following this, the OCP signal resets and the converter recovers. After every hiccup cycle, the converter stays in
this mode until the overload or short circuit is removed. This behavior is shown in Figure 14.
It should be noted that on some units, a false OCP maybe experienced during device start-up due to noise. The
part will ride through this false OCP due to the pulse by pulse current limiting feature and successfully ramp to the
correct output voltage.
Note that the user can reprogram the default overcurrent threshold using I2C. It is recommended that the
overcurrent threshold be programmed to at least 16A for good accuracy. While these devices will still offer
overcurrent protection for thresholds programmed lower than these recommended values, the thresholds will not
be as accurate.
Also, there is a register than can be reprogrammed using I2C to configure the part to respond to an overcurrent
fault in one of two ways
1) Pulse by pulse current limiting for a programmed number of 8 switching cycles followed by a latched
shutdown.
2) Pulse by pulse current limiting for a programmed number 8 switching cycles followed by hiccup. This is
the default explained above.
The pulse-by-pulse or constant current limiting mechanism is briefly explained below.
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IOUT_OC_FAULT_LIMIT
IL
20 ms
0
HDrv
0
LDrv
0
CLK
Fs
0
OCP High
1
2
3
4
5
6
7
8
Internal
Enable
Figure 15: Pulse by pulse current limiting for 8 cycles, followed by hiccup.
In Figure 15 above, with the overcurrent response set to pulse-by-pulse current limiting for 8 cycles followed by
hiccup, the converter is operating at D<0.125 when the overcurrent condition occurs. In such a case, no duty
cycle limiting is applied.
IO UT_OC_FAULT_LIMIT
IL
0
HDrv
0
LDrv
0
CLK
Fs
0
OCP High
1
2
3
4
5
6
7
8
9
10
11
...
Internal
Enable
Figure 16: Constant current limiting.
Figure 16 depicts a case where the overcurrent condition happens when the converter is operating at D>0.5 and
the overcurrent response has been set to Constant current operation through pulse by pulse current limiting. In
such a case, after 3 consecutive overcurrent cycles are recognized, the pulse width is dropped such that D=0.5
and then after 3 more consecutive OCP cycles, to 0.25 and then finally to 0.125 at which it keeps running until the
total OCP count reaches the programmed maximum following which the part enters hiccup mode. Conversely,
when the overcurrent condition disappears, the pulse width is restored to its nominal value gradually, by a similar
mechanism in reverse; every sequence of 4 consecutive cycles in which the current is below the overcurrent
threshold doubles the duty cycle, so that D goes from 0.125 to 0.25, then to 0.5 and finally to its nominal value.
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DIE TEMPERATURE SENSING, TELEMETRY AND THERMAL SHUTDOWN
On die temperature sensing is used for accurate temperature reporting and over temperature detection. The
temperature may be read back through the 8-bit register temp_byte, which reports the die temperature in 10C
resolution, offset by 400C. Thus, the temperature is given by temp_byte +400C.
The trip threshold is set by default to 125oC. The default over temperature response of the device is to inhibit
power conversion while the fault is present, followed by automatic restart after the fault condition is cleared.
Hence, in the default configuration, when trip threshold is exceeded, the internal Enable signal to the power
conversion circuitry is de-asserted, turning off both MOSFETs.
Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 25oC
hysteresis in the thermal shutdown threshold.
The default overtemperature threshold as well as overtemperature response may be re-configured or overridden
using the corresponding MTP registers. The devices support three types of responses to an over-temperature
fault:
1) Ignore
2) Inhibit when over temperature condition exists and auto-restart when over temperature condition
disappears
3) Latched shutdown.
REMOTE VOLTAGE SENSING
True differential remote sensing in the feedback loop is critical to high current applications where the output
voltage across the load may differ from the output voltage measured locally across an output capacitor at the
output inductor, and to applications that require die voltage sensing.
The RS+ and RS- pins form the inputs to a remote sense differential amplifier with high speed, low input offset
and low input bias current, which ensure accurate voltage sensing and fast transient response in such
applications.
The input range for the differential amplifier is limited to 1.5V below the VCC rail. Therefore, for applications in
which the output voltage is more than 3V, it is recommended to use local sensing, or if remote sensing is a must,
then the voltage between the RS+ and RS-pins must be divided down to less than 3V using a resistive voltage
divider. It’s recommended that the divider be placed at the input of the remote sense amplifier and that a low
impedance such as 499 Ω be used between the RS+ and RS- nodes. A typical schematic for this setup is shown
on Figure 5. Please note, however, that this modifies the open loop transfer function and requires a change in the
compensation network to optimally stabilize the loop.
FEED-FORWARD
Feed-Forward (F.F.) is an important feature, because it can keep the converter stable and preserve its load
transient performance when PVin varies over a wide range. The PWM ramp amplitude (Vramp) is proportionally
changed with PVin to maintain PVin/Vramp almost constant throughout PVin variation range (as shown in Figure
17). Thus, the control loop bandwidth and phase margin can be maintained constant. Feed-forward function can
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IR38265
also minimize impact on output voltage from fast PVin change. The feedforward is disabled for PVin<4.7V. Hence,
for PVin<4.7V, a re-calculation of control loop parameters is needed for re-compensation.
21V
12V
12V
5V
PVin
0
PWM Ramp
Ramp Offset
0
Figure 17: Timing Diagram for Feed-Forward (F.F.) Function
LIGHT LOAD EFFICIENCY ENHANCEMENT (AOT)
These devices implement a diode emulation scheme with Adaptive On Time control or AOT to improve light load
efficiency. It is based on a COT (Constant On Time) control scheme with some novel advancements that make
the on-time during diode emulation adaptive and dependent upon the pulse width in constant frequency operation.
This allows the scheme to be combined with a PWM scheme, while providing relatively smooth transition between
the two modes of operation. In other words, the switching regulator can operate in AOT mode at light loads and
automatically switch to PWM at medium and heavy loads and vice versa. Therefore, the regulator will benefit from
the high efficiency of the AOT mode at light loads, and from the constant frequency and fast transient response of
the PWM at medium to heavy loads.
A register bit mfr_fccm bit can be used to enable AOT operation at light load.
Shortly after the reference voltage has finished ramping up, an internal circuit which is called the “calibration
circuit” starts operation. It samples the Comp voltage (output of the error amplifier), digitizes it and stores it in a
register. There is a DAC which converts the value of this register to an analog voltage which is equal to the
sampled Comp voltage. At this time, the regulator is ready to enter AOT mode if the load condition is appropriate.
If the load is so low that the inductor current becomes negative before the next SW pulse, the operation can be
switched to AOT mode. The condition to enter AOT is the occurrence of 8 consecutive inductor current zero
crossings in eight consecutive switching cycles. If this happens, operation is switched to AOT mode as shown in
Figure 18Figure 18. The inductor current is sensed using the RDS_ON of the Sync-FET and no direct inductor
current measuring is required. In AOT mode, just like COT operation, pulses with constant width are generated
and diode emulation is utilized. This means that a pulse is generated and LDrv is held on until the inductor current
becomes zero. Then both HDrv and LDrv remain off until the voltage of the sense pin comes down and reaches
the reference voltage. At this moment the next pulse is generated. The sense pin is connected to the output
voltage by a resistor divider which has the same ratio as the voltage divider which is connected to the feedback
pin (Fb).
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IR38265
...
Vout
0
8/Fs delay
Diode
Emulation
IL
...
0
Ton
...
...
SW
...
...
0
HDrv
0
LDrv
...
...
0
Reduced Switching
Frequency
1/Fs
Figure 18: Timing Diagram for Reduced Switching Frequency and Diode Emulation in Light Load Condition (AOT
mode)
When the load increases beyond a certain value, the control is switched back to PWM through either of the
following two mechanisms:
1) If due to the increase in load, the output voltage drops to 95% of the reference voltage.
2) If Vsense remains below the reference voltage for 3 consecutive inductor current zero-cross events
It is worth mentioning that in AOT mode, when Vsense comes down to reference voltage level, a new pulse in
generated only if the inductor current is already zero. If at this time the inductor current (sensed on the Sync-FET)
is still positive, the new pulse generation is postponed till the current decays to zero. The second condition
mentioned above usually happens when the load is gradually increased.
It should be noted that in tracking mode, AOT operation is disabled and the device can only operate in continuous
conduction mode even at light loads.
AOT is disabled during output voltage transitions. It is enabled only after reference voltage finishes its ramp (up or
down) and the calibration circuit has sampled and held the new Comp voltage.
In general, AOT operation is more jittery and noisier than FCCM operation, where the switching frequency may
vary from cycle to cycle, giving increased Vout ripple and noisier, inconsistent telemetry. Therefore, it is
recommended to use FCCM mode of operation as far as possible.
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IR38265
OUTPUT VOLTAGE SENSING, TELEMETRY AND FAULTS
In the IR38265, the voltage sense and regulation circuits are decoupled, enabling ease of testing as well as
redundancy. In order to do this, the device uses the sense voltage at the dedicated Vsns pin for output voltage
reporting (in 1/64 V resolution, using 2 registers: output_voltage_msb [2:0] and output_voltage_lsb [7:0]) as well
as for power good detection and output overvoltage protection.
Power good detection and output overvoltage detection rely on fast analog comparator circuits, whereas
overvoltage warnings as well as undervoltage faults and warnings rely on comparing the digitized Vsns to the
corresponding thresholds programmed in the MTP. The thresholds are reprogrammable using I2C.
Power Good Output
Power Good is asserted when the output voltage is within the tolerance band of the target voltage set in the
register selected by the VIDSELx pins. Following this, the Power Good signal remains asserted irrespective of
any output voltage transitions and is de-asserted only in the event of a fault that shuts down power conversion.
Fault DAC
0
Reference DAC
0
Vset+/-TOB
Vsns
0
PGD
0
Figure 19: Power Good in PVID mode, Vboot >0 V
Over-Voltage Protection (OVP)
Over-voltage protection is achieved by comparing sense pin voltage Vsns to a configurable overvoltage threshold.
The OVP threshold may be reprogrammed to within 655 mV of the output voltage (for output voltages lower than
2.555V, without any resistive divider on the Fb pin), using I2C. For an OVP threshold programmed to be more
than 655 mV greater than the output voltage, the effective OV threshold ceases to be an absolute value and
instead tracks the output voltage with a 655 mV offset.
When Vsns exceeds the over voltage threshold, an over voltage trip signal asserts after 200ns (typ.) delay. The
default response is that the high side drive signal HDrv is latched off immediately and PGood flags are set low.
The low side drive signal is kept on until the Vsns voltage drops below the threshold. HDrv remains latched off
until a reset is performed by cycling either Vcc or Enable or the OPERATION command. In addition to the default
38
Rev 3.5
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IR38265
response described above, I2C can be used to configure the device such that Vout overvoltage faults are ignored
and the converter remains enabled..
Vsns voltage is set by an external resistive voltage divider connected to the output. This divider ratio must match
the divider used on the feedback pin or on the RS+ pin.
DAC1+OV_OFFSET_DAC
Vout
DAC1
hysteresis
0
HDrv
0
LDrv
0
Comp
0
PGood
0
200 ns
200 ns
Figure 20: Timing Diagram for OVP in non-tracking mode
MINIMUM ON TIME CONSIDERATIONS
The minimum ON time is the shortest amount of time for Ctrl FET to be reliably turned on. This is a very critical
parameter for low duty cycle, high frequency applications. In the conventional approach, when the error amplifier
output is near the bottom of the ramp waveform with which it is compared to generate the PWM output,
propagation delays can be high enough to cause pulse skipping, and hence limit the minimum pulse width that
can be realized. Moreover, in the conventional approach, the bottom of the ramp often presents a high gain region
to the error amplifier output, making the modulator more susceptible to noise and requiring the use of lower
control loop bandwidth to prevent noise, jitter and pulse skipping.
Infineon has developed a proprietary scheme to improve and enhance the minimum pulse width which minimizes
these delays and hence, allows stable operation with pulse-widths as small as 35ns. At the same time, this
scheme also has greater noise immunity, thus allowing stable, jitter free operation down to very low pulse widths
even with a high control loop bandwidth, thus reducing the required output capacitance.
Any design or application using these devices must ensure operation with a pulse width that is higher than the
minimum on-time and at least 50 ns of on-time is recommended in the application. This is necessary for the circuit
to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage
ripple.
Vout
Fs PV Fs
D
ton
(2)
in
In any application that uses these devices, the following condition must be satisfied:
39
Rev 3.5
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IR38265
(3)
(4)
ton(min) ton
Vout
ton(min)
PV Fs
in
Vout
(5)
PV Fs
in
ton(min)
The minimum output voltage is limited by the reference voltage and hence Vout(min) = 0.5V. Therefore, for Vout(min)
0.5V,
=
Vout
(6)
PV Fs
in
ton(min)
0.5V
PVin Fs
10 V/μs
50ns
Therefore, at the maximum recommended input voltage 16V and minimum output voltage, the converter should
be designed at a switching frequency that does not exceed 625 kHz. Conversely, for operation at the maximum
recommended operating frequency (1.5 MHz) and minimum output voltage (0.5V), the input voltage (PVin) should
not exceed 6.67 V, otherwise pulse skipping may happen.
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IR38265
MAXIMUM DUTY RATIO
An upper limit on the operating duty ratio is imposed by the larger of a) A fixed off time (dominant at high
switching frequencies) b) blanking provided by the PWMSet or clock pulse, which has a pulse width that is 1/8 of
the switching period. The latter mechanism is dominant at lower switching frequencies (typically below 1.25 MHz).
This upper limit ensures that the Sync FET turns on for a long enough duration to allow recharging the bootstrap
capacitor and also allows current sensing. Figure 21 shows a plot of the maximum duty ratio vs. the switching
frequency with built in input voltage feed forward mechanism.
Figure 21: Maximum duty cycle vs. switching frequency
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IR38265
BOOTSTRAP CAPACITOR
To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW
pin, which is connected to the source of the Control FET. This is achieved by using a bootstrap configuration,
which comprises the internal bootstrap diode and an external bootstrap capacitor (C1). Typically a 0.1uF
capacitor is used. A layout placement for a 0 ohm resistor in series with the capacitor is also recommended. For
PVin> 14V, a 1 ohm series resistor is required. The operation of the circuit is as follows: When the sync FET is
turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards Vcc
through the internal bootstrap diode (Figure 22), which has a forward voltage drop VD. The voltage Vc across the
bootstrap capacitor C1 is approximately given as:
(7)
Vc Vcc VD
When the control FET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage
PVin. However, if the value of C1 is appropriately chosen, the voltage Vc across C1 remains approximately
unchanged and the voltage at the Boot pin becomes:
(8)
VBoot PV V VD
in
cc
Cvin
PVIN
+ VD
-
Boot
V
cc
+
Vc
-
C1
SW
L
IR38265
PGnd
Figure 22: Bootstrap circuit to generate high side drive voltage
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IR38265
LOOP COMPENSATION
Feedback loop compensation is achieved using standard Type III techniques and the compensation values can
be easily calculated using Infineon’s design tool. The design tool can also be used to predict the control
bandwidth and phase margin for the loop for any set of user defined compensation component values. For a
theoretical understanding of the calculations used, please refer to Infineon’s Application Note AN-1162
“Compensator Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier”.
DYNAMIC VID COMPENSATION
This family of devices uses an analog control scheme with voltage mode control. In this scheme, the compensator
acts on the Vout signal and not just on the error signal. For load and line transients, with a steady and unchanging
reference voltage, this has the same dynamic characteristics as for a compensator that acts on only the error
signal. However, for reference voltage changes, as in the case of Dynamic VID, the dynamics are altered. A
proprietary dynamic VID compensation scheme allows the dynamic VID response to be tuned optimally to the
feedback compensator values. Once properly optimized, the output voltage will follow the DAC more closely
during a positive dynamic VID, irrespective of whether the new voltage is commanded by using I2C or by using
the 3 VIDSELx pins to select a different register and target voltage. Infineon’s design tool will allow the user to
quickly and conveniently calculate the dynamic VID compensation parameters for optimal dynamic VID response.
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LAYOUT RECOMMENDATIONS
The layout is very important when designing high frequency switching converters. Layout will affect noise pickup
and can cause a good design to perform with less than expected results.
Make the connections for the power components in the top layer with wide, copper filled areas or polygons. In
general, it is desirable to make proper use of power planes and polygons for power distribution and heat
dissipation.
The input capacitors, inductor, output capacitors and the device should be as close to each other as possible.
This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place
the input capacitor directly at the PVin pin of IR38x6x.
Power vias should be at least 20/10 mil and a good rule of thumb is to design at 2A/via.
The feedback part of the system should be kept away from the inductor and other noise sources.
The critical bypass components such as capacitors for Vin, VCC and 1.8V should be close to their respective
pins. It is important to place the feedback components including feedback resistors and compensation
components close to Fb and Comp pins.
In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to
which all signals are referenced. The goal is to localize the high current path to a separate loop that does not
interfere with the more sensitive analog control functions. These two grounds must be connected together on the
PC board layout at a single point. It is recommended to place all the compensation parts over the analog ground
plane in top layer.
The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at
least a 6-layers PCB. To effectively remove heat from the device the exposed pad should be connected to the
ground plane using vias.
IR38265 has 3 pins, SCL, SDA and SALERT# that are used for I2C communication. It is recommended that the
traces used for these communication lines be at least 10 mils wide with spacing between the SCL and SDA traces
that is at least 2-3 times the trace width.
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I2C PROTOCOLS
All registers may be accessed using I2C protocols. I2C allows the use of a simple format whereas PMBus provides error
checking capability. Figure 23 shows the I2C format employed by IC.
S: Start Condition
1
S
7
1
1
A
8
1
A
8
1
A
1
P
A: Acknowledge (0')
N: Not Acknowledge (1')
Sr: Repeated Start Condition
P: Stop Condition
Slave
Register
Address
WRITE
READ
W
Data Byte
Address
R: Read (1')
1
7
1
1
P
1
S
7
1
8
1
S
1
R
8
W: Write (0')
Slave
Register
Address
Slave
A
Data Byte
A
A
N
W
Address
Address
PEC: Packet Error Checking
*: Present if PEC is enabled
: Master to Slave
: Slave to Master
Figure 23: I2C Format
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PCB PADS AND COMPONENT
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PCB COPPER AND SOLDER RESIST (PAD SIZES)
PCB COPPER AND SOLDER RESIST (PAD SPACING)
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SOLDER PASTE STENCIL (PAD SIZES)
SOLDER PASTE STENCIL (PAD SPACING)
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MARKING INFORMATION FOR FINAL PRODUCTION
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MARKING INFORMATION FOR EARLY PRODUCTION
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PACKAGE INFORMATION
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ENVIRONMENTAL QUALIFICATIONS
Industrial
Qualification Level
Moisture Sensitivity Level
Machine Model
5mm x 7mm PQFN
MSL 2 260C
JEDEC Class A
JEDEC Class 1C
JEDEC Class 3
(JESD22-A115A)
Human Body Model
(JESD22-A114F)
ESD
Charged Device Model
(JESD22-C101F)
RoHS Compliant
Yes (with Exemption 7a)
† Qualification standards can be found at International Rectifier web site: http://www.irf.com
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REVISION HISTORY
3.0
3.1
3.2
3.3
3.4
3.5
3/9/2017
3/20/2017
5/8/2017
12/12/2017
9/6/2018
6/7/2019
Initial Release.
Changed 1.8V LDO regulation current to 1 mA, updated stencil drawings.
Added requirement of 1 ohm series resistor for PVin>14V.
Added recommendation to use 10uF bypass capacitor at P1V8 pin. Added note about using a 4.99K
resistor for the VIDSEL pins section. Updated OCP and other functionality descriptions.
Updated package marking information on IC. Added thermal derating curves.
Removed comments in the revision history that came before the initial release. Post Rev 3.0
comments.
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Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
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(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information
regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any
kind, including without limitation warranties of non-infringement of intellectual property rights of any third party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
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product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s
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product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
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WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question please
contact your nearest Infineon Technologies office.
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or any consequences of the use thereof can reasonably be expected to result in personal injury.
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