IR3847M_15 [INFINEON]
Single-Input Voltage, Synchronous Buck Regulator;型号: | IR3847M_15 |
厂家: | Infineon |
描述: | Single-Input Voltage, Synchronous Buck Regulator |
文件: | 总55页 (文件大小:1961K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
25A Highly Integrated SupIRBuck®
Single-Input Voltage, Synchronous Buck Regulator
IR3847
DESCRIPTION
FEATURES
The IR3847 SupIRBuck® is an easy-to-use, fully
integrated and highly efficient DC/DC regulator. The
onboard PWM controller and MOSFETs make IR3847
a space-efficient solution, providing accurate power
delivery for low output voltage and high current
applications.
• Single 5V to 21V application
• Wide Input Voltage Range from 1.5V to 21V with
external Vcc
• Output Voltage Range: 0.6V to 0.86*PVin
• 0.5% accurate Reference Voltage
• Enhanced line/load regulation with Feed-Forward
• Programmable Switching Frequency up to
IR3847 is
a
versatile regulator which offers
1.5MHz
programmability of switching frequency and current
limit while operating in wide input and output voltage
range.
• Internal Digital Soft-Start
• Enable input with Voltage Monitoring Capability
• Remote Sense Amplifier with True Differential
The switching frequency is programmable from 300
kHz to 1.5MHz for an optimum solution.
Voltage Sensing
• Thermally compensated current limit and Hiccup
Mode Over Current Protection
It also features important protection functions, such as
Over Voltage Protection (OVP), Pre-Bias startup,
hiccup current limit and thermal shutdown to give
required system level security in the event of fault
conditions.
• Smart LDO to enhance efficiency
• Vp for tracking applications and sequencing
• Vref is available externally to enable margining
• External synchronization with Smooth Clocking
• Dedicated output voltage sensing for power good
indication and overvoltage protection which
remains active even when Enable is low.
APPLICATIONS
• Enhanced Pre-Bias Start up
• Netcom Applications
• Body Braking to improve transient
• Integrated MOSFET drivers and Bootstrap diode
• Thermal Shut Down
• Embedded Telecom Systems
• Server Application
• Post Package trimmed rising edge dead-time
• Programmable Power Good Output with tracking
• Small Size 5mm x 6mm PQFN
• Distributed Point of Load Power Architectures
• Storage Applications
• Operating Junction Temp: -40oC<Tj<125oC
• Lead-free, Halogen-free and RoHS Compliant
ORDERING INFORMATION
Base Part
Standard Pack
Orderable Part
Number
Package Type
Number
Form
Quantity
4000
IR3847
PQFN 5mm x 6mm
Tape and Reel
IR3847MTRPBF
IR3847
PBF
TR
M
Lead Free
Tape and Reel
Package Type
1
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BASIC APPLICATION
5.0V<Vin<21V
PVin
Vin
Vp
Boot
Vo
Vcc/
LDO_out
SW
OCSet
Vsns
RS+
PGood
PGood
RS-
Rt/SYNC
RSo
Fb
Enable
Comp
PGnd
Vref
Gnd
Figure 1: IR3847 Basic Application Circuit
Figure 2: Efficiency [Vin=12V, Fsw=600kHz]
PIN DIAGRAM
5mm X 6mm POWER QFN
Top View
PGnd
26
SW
25
24 SW
23 SW
32
SW
22 SW
PVin 1
21 SW
20 SW
27
PGnd
33
NC
31
NC
19 NC
NC
28
NC
30
Boot 2
Enable 3
Rt/Sync 4
OCset 5
18 VCC/LDO_out
17 Vin
29
PGnd
16 PGD
15 Vp
6
7
8
9
10 11 12 13 14
2
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FUNCTIONAL BLOCK DIAGRAM
Vin
Smart
LDO
VCC
VCC/
LDO_out
THERMAL
SHUTDOWN
TSD
DCM
LGnd
UVcc
FAULT
CONTROL
UVcc
OC
POR
OV
Comp
Vp
Vref
+
+
+
-
Boot
PVin
SW
VREF
E/A
0.6V
FB
FAULT
FB
HDrv
LDrv
Vref
Vp
DRIVER
OVER
VOLTAGE
UVcc
+
POR
Vsns
BODY
BRAKING
CONTROL
HDin
LDin
CLK
Intl_SS
PVin
DIGITAL
SOFT
START
POR
FAULT
PGnd
SSOK
ZERO CROSSING
COMPARATOR
ZC
OC
UVEN
Enable
UVEN
UVcc
CONTROL
LOGIC
POR
POR
OVER CURRENT
OCset
Vp
VREF
FB
-
RS-
DCM
+
RS+
Rt/Sync
RSo
PGD
Figure 3: IR3847 Simplified Block Diagram
3
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PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
Input voltage for power stage. Bypass capacitors between PVin and
PGND should be connected very close to this pin and PGND; also forms
input to feedforward block
1
PVin
2
3
Boot
Supply voltage for high side driver
Enable
Enable pin to turning on and off the IC.
Use an external resistor from this pin to LGND to set the switching
frequency, very close to the pin. This pin can also be used for external
synchronization.
4
Rt/Sync
Current limit setpoint. This pin allows the trip point to be set to one of
three possible settings by either floating this pin, tying it to VCC or tying it
to PGnd.
5
6
OCset
Vsns
Sense pin for OVP and PGood
Inverting input to the error amplifier. This pin is connected directly to the
output of the regulator or to the output of the remote sense amplifier, via
resistor divider to set the output voltage and provide feedback to the
error amplifier.
7
FB
Output of error amplifier. An external resistor and capacitor network is
typically connected from this pin to FB to provide loop compensation.
8
9
COMP
RSo
Remote Sense Amplifier Output
Power ground. This pin should be connected to the system’s power
ground plane. Bypass capacitors between PVin and PGND should be
connected very close to PVIN pin (pin 1) and this pin.
10, 26, 27,
29
PGND
11
12
13
LGND
RS-
Signal ground for internal reference and control circuitry.
Remote Sense Amplifier input. Connect to ground at the load.
Remote Sense Amplifier input. Connect to output at the load.
RS+
External reference voltage can be used for margining operation. A
capacitor between 100pF and 180pF should be connected between this
pin and LGnd. Tie to LGnd for tracking function.
14
15
Vref
Vp
Used for voltage sequencing and tracking. Leave open if sequencing or
tracking is not needed, ensuring that there is no capacitor on the pin.
Power Good status pin. Output is open drain. Connect a pull up resistor
from this pin to VCC.
16
17
18
PGD
Vin
Input Voltage for LDO.
Bias Voltage for IC and driver section, output of LDO. Add a minimum of
4.7uF bypass cap from this pin to PGnd.
VCC/LDO_out
19, 28, 30,
31, 33
NC
No Connect
20, 21, 22,
23, 24, 25,
32
SW
Switch node. This pin is connected to the output inductor.
4
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IR3847
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
PVin
-0.3V to 25V
Vin
-0.3V to 25V
VCC
SW
BOOT
-0.3V to 8V (Note 1)
-0.3V to 25V (DC), -4V to 25V (AC, 100ns)
-0.3V to 33V
BOOT to SW
Input/Output pins
-0.3V to VCC + 0.3V (Note 2)
-0.3V to 3.9V
RS+, RS-, RSo, PGD, Enable, OCset
PGND to LGND, RS- to LGND
Junction Temperature Range
Storage Temperature Range
-0.3V to 8V (Note 1)
-0.3V to + 0.3V
-40°C to 150°C
-55°C to 150°C
Class A
Machine Model
ESD
Human Body Model
Class 1C
Charged Device Model
Class III
Moisture Sensitivity level
RoHS Compliant
JEDEC Level 3 @ 260°C
Yes
Note:
1. VCC must not exceed 7.5V for Junction Temperature between -10°C and -40°C.
2. Must not exceed 8V.
THERMAL INFORMATION
Thermal Resistance, Junction to Case (θJC_TOP
Thermal Resistance, Junction to PCB (θJB)
)
31.5°C/W
2.41°C/W
Thermal Resistance, Junction to Ambient (θJA) (Note 3) 14.7°C/W
Note:
3. Thermal resistance (θJA) is measured with components mounted on a high effective thermal conductivity
test board in free air.
5
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ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
SYMBOL
UNIT
DEFINITION
Input Bus Voltage *
Supply Voltage
Supply Voltage **
Supply Voltage
Output Voltage
MIN
1.5
5.0
4.5
4.5
0.6
0
MAX
21
21
7.5
7.5
PVin
Vin
VCC
V
Boot to SW
VO
IO
0.86 PVin
±25
Output Current
A
Fs
TJ
Switching Frequency
Junction Temperature
300
-40
1500
125
kHz
°C
*
**
SW node must not exceed 25V
When VCC is connected to an externally regulated supply, also connect Vin.
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, these specification apply over, 1.5V < PVin < 21V, 4.5V< VCC < 7.5V, 0oC < TJ <
125oC.
Typical values are specified at TA = 25oC.
PARAMETER
Power Loss
SYMBOL
CONDITIONS
MIN
TYP
MAX UNIT
Vin = PVin = 12V, VO =
1.2V, IO = 25A, Fs =
600kHz, L=0.215uH, TA =
25°C, Note 4
Power Loss
PLOSS
3.62
W
MOSFET Rds(on)
V
Boot – VSW = 6.8V, ID =
Top Switch
Rds(on)_Top
Rds(on)_Bot
4
5.2
mΩ
2.3
25A, Tj = 25°C
VCC =6.8V, ID = 25A, Tj
= 25°C
Bottom Switch
1.8
Reference Voltage
Feedback Voltage
VFB
0.6
V
Vref=0.6V,
-0.5
-1.0
+0.5
%
0°C < Tj < 105°C
Accuracy
Vref=0.6V,
+1.0
-40°C < Tj < 125°C
Sink Current
Isink_Vref
Isrc_Vref
Vref=0.7V
Vref=0.5V
12.7
12.7
16.0
16.0
19.3
µA
Source Current
19.3
Vref Pin connected
externally
Vref_disable
Vref_enable
0.15
V
V
Vref Comparator Threshold
0.4
Supply Current
Vin Supply Current
(Standby)
Vin=21V, Enable low, No
Switching
Iin(Standby)
300
425
µA
6
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PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNIT
Vin Supply Current (Dyn)
Vin=21V, Enable high,
Fs = 600kHz
Iin(Dyn)
40
425
40
mA
µA
VCC Supply Current
(Standby)
Enable low, VCC=7V, No
Switching
Icc(Standby)
Icc(Dyn)
300
VCC Supply Current (Dyn)
Enable high, VCC=7V,
Fs = 600kHz
mA
Under Voltage Lockout
VCC–Start–Threshold
VCC–Stop–Threshold
Enable–Start–Threshold
Enable–Stop–Threshold
Enable leakage current
Oscillator
VCC_UVLO_Start
VCC_UVLO_Stop
VCC Rising Trip Level
VCC Falling Trip Level
4.0
3.8
4.2
3.9
1.2
1.0
4.4
4.2
1.36
1.06
1
V
Enable_UVLO_Start Supply ramping up
Enable_UVLO_Stop Supply ramping down
1.14
0.9
V
Ien
Enable=3.3V
µA
Rt Voltage
1
V
Rt=80.6k
Rt=39.2k
Rt=15k
270
540
300
600
330
660
Frequency Range
Ramp Amplitude
FS
kHz
1350 1500 1650
1.02
PVin=6.8V, PVin(max)
slew rate=1V/us, Note 4
PVin=12V, PVin(max)
slew rate=1V/us, Note 4
Vramp
1.8
2.4
Vp-p
PVin=16V, PVin(max)
slew rate=1V/us, Note 4
Ramp Offset
Ramp (os)
Tmin (ctrl)
Note 4
Note 4
Note 4
0.16
50
V
Min Pulse Width
Fixed Off Time
Max Duty Cycle
ns
ns
200
200
230
Dmax
Fs=300kHz,
PVin=Vin=12V
86
%
Sync Frequency Range
Sync Pulse Duration
Note 4
270
100
3
1650
kHz
ns
High
Low
Sync Level Threshold
V
0.6
Error Amplifier
%
Vos_Vref
VFb – Vref, Vref = 0.6V
VFb – Vp, Vp = 0.6V
-1.5
+1.5
Vref
Input Offset Voltage
Vos_Vp
IFb(E/A)
IVp(E/A)
Isink(E/A)
-1.5
-0.5
0
+1.5
+0.5
4
%Vp
µA
Input Bias Current
Input Bias Current
Sink Current
µA
0.4
0.85
1.2
mA
7
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PARAMETER
Source Current
Slew Rate
SYMBOL
Isource(E/A)
SR
CONDITIONS
MIN
4
TYP
7.5
12
MAX UNIT
11
20
mA
V/µs
MHz
dB
Note 4
7
Gain-Bandwidth Product
DC Gain
GBWP
Note 4
Note 4
20
100
30
40
Gain
110
120
Maximum Output
Voltage
Vmax(E/A)
1.7
2
2.3
V
Minimum Output Voltage
Common Mode Voltage
Margining Range
Vmin(E/A)
Vcm_Vp
100
1.2
1.2
mV
V
Note 4
Note 4
0
Vmarg_Vref
0.4
V
Remote Sense Differential Amplifier
Unity Gain Bandwidth
DC Gain
BW_RS
Note 4
Note 4
3
6.4
9
MHz
dB
Gain_RS
110
Vref=0.6V,
-1.5
-2
0
1.5
2
mV
mV
0°C < Tj < 85°C
Offset Voltage
Offset_RS
Vref=0.6V,
-40°C < Tj < 125°C
Source Current
Sink Current
Isource_RS
Isink_RS
Slew_RS
Rin_RS+
Rin_RS-
3
0.4
2
13
1
20
2
mA
mA
Slew Rate
Note 4, Cload = 100pF
4
8
V/µs
kohm
kohm
V
RS+ input impedance
RS- input impedance
Maximum Voltage
Minimum Voltage
Internal Digital Soft Start
Soft Start Clock
45
63
63
1
85
Note 4
Vmax_RS
Min_RS
V(VCC) – V(RSo)
0.5
1.5
50
mV
Clk_SS
Note 4
Note 4
180
0.3
200
0.4
220
0.5
kHz
mV /
µs
Soft Start Ramp Rate
Ramp(SS_Start)
Bootstrap Diode
Forward Voltage
Switch Node
I(Boot) = 30mA
360
520
960
1
mV
µA
SW = 0V, Enable = 0V
SW Leakage Current
lsw
SW = 0V, Enable =
HIGH, Vp=0 V
Internal Regulator (VCC/LDO)
Vin(min) = 7.2V, Io=0-
30mA, Cload = 2.2uF,
DCM=0
6.3
4
6.8
4.4
7.1
4.8
Output Voltage
VCC
V
Vin(min) = 7.2V, Io=0-
30mA, Cload = 2.2uF,
DCM=1
8
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PARAMETER
VCC dropout
SYMBOL
VCC_drop
Ishort
CONDITIONS
MIN
TYP
MAX UNIT
Vin = 7V, Io=70 mA,
Cload = 2.2uF
0.7
V
Short Circuit Current
Note 4
70
mA
s
Zero-crossing
Comparator Delay
256 /
Fs
Tdly_zc
Zero-crossing
Comparator Offset
0
0
mV
Vos_zc
Note 4
Body Braking
Fb > Vref, Sw duty cycle,
Note 3
BB Threshold
BB_threshold
%
FAULTS
Power Good
Vsns Rising,
%
Vref
115
115
1.5
120
120
2.5
125
125
3.5
Power Good Low Upper
Threshold
0.4V < Vref < 1.2V
VPG_low(upper)
Vsns Rising, Vref < 0.1V
% Vp
µs
Power Good Low Upper
Threshold Falling delay
VPG_low(upper)_Dly Vsns > VPG_low(upper)
Vsns Rising,
%
Vref
95
95
Power Good High Lower
Threshold
0.4V < Vref < 1.2V
VPG_high(lower)
Vsns Rising, Vref < 0.1V
% Vp
ms
Power Good High Lower
Threshold Rising Delay
VPG_high(lower)_Dly Vsns rising
Vsns falling,
1.28
%
Vref
90
90
Power Good Low Lower
Threshold
0.4V < Vref < 1.2V
VPG_low(lower)
Vsns falling, 0.1V < Vref
%Vp
µs
V
Power Good Low Lower
Threshold Falling delay
VPG_low(lower)_Dly Vsns < VPG_low(lower)
PG (voltage) IPGood = -5mA
VPG(tracker_upper) Vp Rising, Vref < 0.1V
101
150
199
0.5
PGood Voltage Low
Tracker Comparator
Upper Threshold
0.4
0.3
V
Tracker Comparator
Lower Threshold
V
VPG(tracker_lower)
Tdelay(tracker)
Vp Falling, Vref < 0.1V
Vp Rising, Vref < 0.1V
Tracker Comparator
Delay
1.28
ms
Over Voltage Protection (OVP)
Vsns Rising,
%
Vref
115
120
125
0.45V < Vref < 1.2V
OVP Trip Threshold
OVP (trip)
Vsns Rising,
Vref < 0.1V
115
1.5
120
2.5
125
3.5
% Vp
µs
OVP Fault Prop Delay
OVP (delay)
Vsns rising
9
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PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNIT
Over-Current Protection
OCSet=VCC, VCC =
6.8V, TJ = 25°C
29.25 32.5 35.75
23.4 26 28.6
A
A
OCSet=floating, VCC =
6.8V, TJ = 25°C
OC Trip Current
ITRIP
OCSet=PGnd, VCC
=6.8V, TJ = 25°C
17.55 19.5 21.85
20.48
A
Hiccup blanking time
Thermal Shutdown
Thermal Shutdown
Hysteresis
Tblk_Hiccup
Note 4
ms
Note 4
Note 4
145
20
°C
°C
Notes:
4. Guaranteed by design but not tested in production.
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TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = 12V, VCC = Internal LDO, Io=0-25A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the
losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves.
The table below shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
LOUT (uH)
0.215
P/N
DCR (mΩ)
0.29
PCDC1008-R215EMO (Cyntec)
PCDC1008-R215EMO (Cyntec)
FP1109-R33-R (Coiltronics)
7443320068 (Wurth Elektronik)
1.2
1.8
3.3
0.215
0.311
0.68
0.29
0.42
0.72
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TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, Vin = VCC = 5V, Io=0-25A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of
the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table
below shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
LOUT (uH)
0.215
P/N
DCR (mΩ)
0.29
PCDC1008-R215EMO (Cyntec)
PCDC1008-R215EMO (Cyntec)
FP1109-R33-R (Coiltronics)
7443320068 (Wurth Elektronik)
1.2
1.8
3.3
0.215
0.311
0.68
0.29
0.42
0.72
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TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = VCC = 5V, Io=0-25A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the
inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table
below shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
LOUT (uH)
0.215
P/N
DCR (mΩ)
0.29
PCDC1008-R215EMO (Cyntec)
PCDC1008-R215EMO (Cyntec)
FP1109-R33-R (Coiltronics)
1.2
1.8
0.215
0.311
0.29
0.42
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THERMAL DERATING CURVES
Measurements are done on IR3847 Evaluation board. PCB is a 6 layer board with 2 oz copper and FR4 material.
Vin=PVin=12V, Vout =1.2V, VCC=internal LDO (6.8V), Fs = 600kHz
Vin=PVin=12V, Vout =5.0V, VCC=internal LDO (6.8V), Fs = 600kHz
Note: International Rectifier Corporation specifies current rating of SupIRBuck devices conservatively. The
continuous current load capability might be higher than the rating of the device if input voltage is 12V typical and
switching frequency is below 600kHz. However, the maximum current is limited by the internal current limit and
designers need to consider enough guard bands between load current and minimum current limit to guarantee
that the device does not trip at steady state condition.
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MOSFET RDSON VARIATION OVER TEMPERATURE
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TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C)
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TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C)
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TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C)
OCset=VCC
OCset=VCC
OCset=Float
OCset=GND
OCset=Float
OCset=GND
OCset=VCC
OCset=Float
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THEORY OF OPERATION
set thresholds. Normal operation resumes once VCC
and Enable rise above their thresholds.
DESCRIPTION
The IR3847 uses a PWM voltage mode control
scheme with external compensation to provide good
noise immunity and maximum flexibility in selecting
inductor values and capacitor types.
The POR (Power On Ready) signal is generated when
all these signals reach the valid logic level (see
system block diagram). When the POR is asserted the
soft start sequence starts (see soft start section).
The switching frequency is programmable from
300kHz to 1.5MHz and provides the capability of
optimizing the design in terms of size and
performance.
ENABLE
The Enable features another level of flexibility for
startup. The Enable has precise threshold which is
internally monitored by Under-Voltage Lockout
(UVLO) circuit. Therefore, the IR3847 will turn on only
when the voltage at the Enable pin exceeds this
threshold, typically, 1.2V.
IR3847 provides precisely regulated output voltage
programmed via two external resistors from 0.6V to
0.86*PVin.
The IR3847 operates with an internal bias supply
(LDO) which is connected to the VCC pin. This allows
operation with single supply. The bias voltage is
variable according to load condition. If the output load
current is less than half of the peak-to-peak inductor
current, a lower bias voltage, 4.4V, is used as the
internal gate drive voltage; otherwise, a higher
voltage, 6.8V, is used.
If the input to the Enable pin is derived from the bus
voltage by a suitably programmed resistive divider, it
can be ensured that the IR3847 does not turn on until
the bus voltage reaches the desired level as shown in
Figure 4. Only after the bus voltage reaches or
exceeds this level and voltage at the Enable pin
exceeds its threshold, IR3847 will be enabled.
Therefore, in addition to being a logic input pin to
enable the IR3847, the Enable feature, with its precise
threshold, also allows the user to implement an
Under-Voltage Lockout for the bus voltage (PVin). It
can help prevent the IR3847 from regulating at low
PVin voltages that can cause excessive input current.
This feature helps the converter to reduce power
losses. The device can also be operated with an
external bias from 4.5V to 7.5V, allowing an extended
operating input voltage (PVin) range from 1.5V to 21V.
For using the internal LDO supply, the Vin pin should
be connected to PVin pin. If an external bias is used, it
should be connected to VCC pin and the Vin pin
should be shorted to VCC pin.
12V
10.2V
The device utilizes the on-resistance of the low side
MOSFET (synchronous Mosfet) as current sense
element. This method enhances the converter’s
efficiency and reduces cost by eliminating the need for
external current sense resistor.
PVin
Vcc
> 1.2V
1.2V
EN_UVLO_START
EN
IR3847 includes two low Rds(on) MOSFETs using IR’s
HEXFET technology. These are specifically designed
for high efficiency applications.
Intl_SS
UNDER-VOLTAGE LOCKOUT AND POR
Figure 4: Normal Start up, device turns on when the
bus voltage reaches 10.2V
The under-voltage lockout circuit monitors the voltage
of VCC pin and the Enable input. It assures that the
MOSFET driver outputs remain in the off state
whenever either of these two signals drops below the
A resistor divider is used at EN pin from PVin to turn
on the device at 10.2V.
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input. In this operating mode Vref is left floating.
Figure 6 shows the recommended startup sequence
for sequenced operation of IR3847 with Enable used
as logic input. Figure 7 shows the recommended
startup sequence for tracking operation of IR3847 with
Enable used as logic input. For this mode of
operation, Vref should be connected to LGND.
PVin=Vin
Vcc
Vp
> 1.0V
> 1.2V
EN
PRE-BIAS STARTUP
Intl_SS
Vo
IR3847 is able to start up into pre-charged output,
which prevents oscillation and disturbances of the
output voltage.
Figure 5: Recommended startup for Normal operation
The output starts in asynchronous fashion and keeps
the synchronous MOSFET (Sync FET) off until the
first gate signal for control MOSFET (Ctrl FET) is
generated. Figure 8 shows a typical Pre-Bias condition
at start up. The sync FET always starts with a narrow
pulse width (12.5% of a switching period) and
gradually increases its duty cycle with a step of 12.5%
until it reaches the steady state value. The number of
these startup pulses for each step is 16 and it’s
internally programmed. Figure 9 shows the series of
16x8 startup pulses.
PVin=Vin
Vcc
Vp
> 1.2V
EN
Intl_SS
Vo
[V]
Vo
Figure 6: Recommended startup for sequencing
operation (ratiometric or simultaneous)
Pre-Bias
Voltage
PVin=Vin
Vcc
[Time]
Figure 8: Pre-Bias startup
VDDQ
...
VDDQ/2
> 1.2V
0V
Vp
EN
HDRv
...
...
...
...
87.5%
12.5%
16
25%
...
LDRv
...
...
...
Vref
Vo
End of
PB
...
16
VTT Tracking
Figure 9: Pre-Bias startup pulses
SOFT-START
Figure 7: Recommended startup for memory tracking
operation (Vtt-DDR)
IR3847 has an internal digital soft-start to control the
output voltage rise and to limit the current surge at the
start-up. To ensure correct start-up, the soft-start
sequence initiates when the Enable and VCC rise
Figure 5 shows the recommended startup sequence
for the normal (non-tracking, non-sequencing)
operation of IR3847, when Enable is used as a logic
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Table 1: Switching Frequency(Fs) vs. External
above their UVLO thresholds and generate the Power
On Ready (POR) signal. The internal soft-start
(Intl_SS) signal linearly rises with the rate of 0.4mV/µs
from 0V to 1.5V. Figure 10 shows the waveforms
during soft start. The normal Vout startup time is fixed,
and is equal to:
Resistor(Rt)
Freq
Rt (KΩ)
(KHz)
80.6
60.4
48.7
39.2
34
300
400
500
600
700
(
0.75V − 0.15V
0.4mV / µS
)
=1.5mS
Tstart =
(1)
29.4
26.1
23.2
21
19.1
17.4
16.2
15
800
900
During the soft start the over-current protection (OCP)
and over-voltage protection (OVP) is enabled to
protect the device for any short circuit or over voltage
condition.
1000
1100
1200
1300
1400
1500
POR
3.0V
1.5V
0.75V
SHUTDOWN
0.15V
IR3847 can be shutdown by pulling the Enable pin
below its 1.0V threshold. During shutdown the high
side and the low side drivers are turned off.
Intl_SS
Vout
OVER CURRENT PROTECTION
t
t
2
t
3
1
The Over Current (OC) protection is performed by
sensing the inductor current through the RDS(on) of the
Synchronous MOSFET. This method enhances the
converter’s efficiency, reduces cost by eliminating a
current sense resistor and any layout related noise
issues. The Over Current (OC) limit can be set to one
of three possible settings by floating the OCset pin, by
pulling up the OCset pin to VCC, or pulling down the
OCset pin to PGnd. The current limit scheme in the
IR3847 uses an internal temperature compensated
current source to achieve an almost constant OC limit
over temperature.
Figure 10: Theoretical operation waveforms during
soft-start (non tracking / non sequencing)
OPERATING FREQUENCY
The switching frequency can be programmed between
300kHz – 1500kHz by connecting an external resistor
from Rt pin to LGnd. Table 1 tabulates the oscillator
frequency versus Rt.
Over Current Protection circuit senses the inductor
current flowing through the Synchronous MOSFET.
To help minimize false tripping due to noise and
transients, inductor current is sampled for about 30 nS
on the downward inductor current slope approximately
12.5% of the switching period before the inductor
current valley. However, if the Synchronous MOSFET
is on for less than 12.5% of the switching period, the
current is sampled approximately 40nS after the start
of the downward slope of the inductor current. When
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the sampled current is higher than the OC Limit, an
OC event is detected.
Automatic restart is initiated when the sensed
temperature drops within the operating range. There
is a 20oC hysteresis in the thermal shutdown
threshold.
When an Over Current event is detected, the
converter enters hiccup mode. Hiccup mode is
performed by latching the OC signal and pulling the
Intl_SS signal to ground for 20.48 mS (typ.). OC
signal clears after the completion of hiccup mode and
the converter attempts to return to the nominal output
voltage using a soft start sequence. The converter will
repeat hiccup mode and attempt to recover until the
overload or short circuit condition is removed.
REMOTE VOLTAGE SENSING
True differential remote sensing in the feedback loop
is critical to high current applications where the output
voltage across the load may differ from the output
voltage measured locally across an output capacitor
at the output inductor, and to applications that require
die voltage sensing.
Because the IR3847 uses valley current sensing, the
actual DC output current limit will be greater than OC
limit. The DC output current is approximately half of
peak to peak inductor ripple current above selected
OC limit. OC Limit, inductor value, input voltage,
output voltage and switching frequency are used to
calculate the DC output current limit for the converter.
Equation (2) to determine the approximate DC output
current limit.
The RS+ and RS- pins of the IR3847 form the inputs
to a remote sense differential amplifier (RSA) with
high speed, low input offset and low input bias current
which ensure accurate voltage sensing and fast
transient response in such applications.
The input range for the differential amplifier is limited
to 1.5V below the VCC rail. Note that IR3847
incorporates a smart LDO which switches the VCC rail
voltage depending on the loading. When determining
the input range assume the part is in light load and
using the lower VCC rail voltage.
∆i
IOCP = ILIMIT
+
(2)
2
IOCP
ILIMIT
Δi
= DC current limit hiccup point
= Current Limit Valley Point
= Inductor ripple current
There are two remote sense configurations that are
usually implemented. Figure 12 shows a general
remote sense (RS) configuration. This configuration
allows the RSA to monitor output voltages above
VCC. A resistor divider is placed in between the
output and the RSA to provide a lower input voltage to
the RSA inputs. Typically, the resistor divider is
calculated to provide VREF (0.6V) across the RSA
inputs which is then outputted to RSo. The input
impedance of the RSA is 63 KOhms typically and
should be accounted for when determining values for
the resistor divider. To account for the input
impedance, assume a 63 KOhm resistor in parallel to
Current Limit
Hiccup
Tblk_Hiccup
20.48 mS*
IL
0
HDrv
...
...
0
LDrv
0
the lower resistor in the divider network.
compensation is then designed for 0.6V to match the
RSo value.
The
*typical filter delay
PGD
0
Figure 11: Timing Diagram for Current Limit Hiccup
Low voltage applications can use the second remote
sense configuration. When the output voltage range
is within the RSA input specifications, no resistor
divider is needed in between the converter output and
RSA. The second configuration is shown in Figure
13. The RSA is used as a unity gain buffer and
compensation is determined normally.
THERMAL SHUTDOWN
Temperature sensing is provided inside IR3847. The
trip threshold is typically 145oC. When trip threshold is
exceeded, thermal shutdown turns off both MOSFETs
and resets the internal soft start.
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transitions to output voltage, a diode is recommended
to add between the external clock and Rt/Sync pin.
Figure 14 shows the timing diagram of these
transitions.
Resistor Divider
RS+ RSo
+
+
FB
-
Vout
(< VCC-1.5V)
RSA
RS-
An internal circuit is used to change the PWM ramp
slope according to the clock frequency applied on
Rt/Sync pin. Even though the frequency of the
external synchronization clock can vary in a wide
range, the PLL circuit keeps the ramp amplitude
constant, requiring no adjustment of the loop
compensation. PVin variation also affects the ramp
amplitude, which will be discussed separately in Feed-
Forward section.
-
Figure 12: General Remote Sense Configuration
Vo
RS+ RSo
+
+
FB
-
Vout
(< VCC-1.5V)
RSA
RS-
Synchronize to the
external clock
Free Running
Frequency
Return to free-
running freq
-
...
SW
Figure 13: Remote Sense Configuration for Vout less
than VCC-1.5V
Gradually change
Gradually change
Fs1
SYNC
Fs1
...
EXTERNAL SYNCHRONIZATION
Fs2
IR3847 incorporates an internal phase lock loop (PLL)
circuit which enables synchronization of the internal
oscillator to an external clock. This function is
important to avoid sub-harmonic oscillations due to
beat frequency for embedded systems when multiple
point-of-load (POL) regulators are used. A multi-
function pin, Rt/Sync, is used to connect the external
clock. If the external clock is present before the
converter turns on, Rt/Sync pin can be connected to
the external clock signal solely and no other resistor is
needed. If the external clock is applied after the
converter turns on, or the converter switching
frequency needs to toggle between the external clock
frequency and the internal free-running frequency, an
external resistor from Rt/Sync pin to LGnd is required
to set the free-running frequency.
Figure 14: Timing Diagram for Synchronization
to the external clock (Fs1>Fs2 or Fs1<Fs2)
FEED-FORWARD
Feed-Forward (F.F.) is an important feature, because
it can keep the converter stable and preserve its load
transient performance when PVin varies. The PWM
ramp amplitude (Vramp) is proportionally changed
with PVin to maintain PVin/Vramp almost constant
throughout PVin variation range (as shown in Figure
15). The PWM ramp amplitude is adjusted to 0.15 of
PVin. Thus, the control loop bandwidth and phase
margin can be maintained constant. Feed-forward
function can also minimize impact on output voltage
from fast PVin change. F.F. is disabled when
PVin<6.2V and the PWM ramp is typically 0.9V. For
PVin<6.2V, PVin voltage should be accounted for
when calculating control loop parameters.
When an external clock is applied to Rt/Sync pin after
the converter runs in steady state with its free-running
frequency,
a
transition from the free-running
frequency to the external clock frequency will happen.
This transition is to gradually make the actual
switching frequency equal to the external clock
frequency, no matter which one is higher. When the
external clock signal is removed from Rt/Sync pin, the
switching frequency is also changed to free-running
gradually. In order to minimize the impact from these
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21V
12V
12V
Users can configure the IR3847 to use a single supply
or dual supplies. Depending on the configuration used
the PVin, Vin and VCC pins are connected differently.
6.8V
PVin
0
PWM Ramp
Amplitude =
0.15xPVin
PWM Ramp
Amplitude = 3.15V
PWM Ramp
PWM Ramp
Amplitude = 1.8V
Below several configurations are shown.
In an
PWM Ramp
Amplitude = 1.02V
internally biased configuration, the LDO draws from
the Vin pin and provides a gate drive voltage, as
shown in Figure 17. By connecting Vin and PVin
together as shown in the Figure 18, IR3847 is an
internally biased single supply configuration that runs
off a single supply.
Ramp Offset
0
Figure 15: Timing Diagram for Feed-Forward (F.F.)
Function
IR3847 can also use an external bias to provide gate
drive voltage for the drivers instead of the internal
LDO. To use an external bias, connected Vin and
VCC to the external bias. PVin can use a separate rail
as shown in Figure 19 or run off the same rail as Vin
and VCC.
SMART LOW DROPOUT REGULATOR (LDO)
IR3847 has an integrated low dropout (LDO) regulator
which can provide gate drive voltage for both drivers.
In order to improve overall efficiency over the whole
load range, LDO voltage is set to 6.8V (typ.) at mid- or
heavy load condition to reduce Rds(on) and thus
MOSFET conduction loss; and it is reduced to 4.4V
(typ.) at light load condition to reduce gate drive loss.
Vin
PVin
Vin PVin
IR3847
The smart LDO selects its output voltage according to
the load condition by sensing the inductor current (IL).
At light load condition, the inductor current can fall
below zero as shown in Figure 16. A zero crossing
comparator is used to detect when the inductor
current falls below zero at the LDrv Falling Edge. If the
comparator detects zero crossing events for 256
consecutive switching cycles, the smart LDO reduces
its output to 4.4V. The LDO voltage will remain low
until a zero crossing is not detected. Once a zero
crossing is not detected, the counter is reset and LDO
voltage returns to 6.8V. Figure 16 shows the timing
diagram. Whenever the device turns on, LDO always
starts with 6.8V, then goes to 4.4V / 6.8V depending
upon the load condition. However, if only Vin is
applied with Enable low, the LDO output is 4.4V.
VCC
PGND
Figure 17: Internally Biased Configuration
Vin
Vin PVin
IR3847
VCC
PGND
Figure 18: Internally Biased Single Supply
Configuration
...
IL
...
...
...
0
256/Fs
6.8V
Vcc/
LDO
6.8V
4.4V
0
Figure 16: Time Diagram for Smart LDO
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For normal operation, Vp and Vref is left floating (Vref
should have a bypass capacitor).
Ext VCC
PVin
Vin PVin
IR3847
Therefore, in normal operating condition, after Enable
goes high, the internal soft-start (Intl_SS) ramps up
the output voltage until Vfb (voltage of feedback/Fb
pin) reaches about 0.6V. Then Vref takes over and the
output voltage is regulated.
VCC
PGND
Tracking-mode operation is achieved by connecting
Vref to LGND. Then, while Vp = 0V, Enable is taken
above its threshold so that the soft-start circuit
generates Intl_SS signal. After the Intl_SS signal
reaches the final value (refer to Figure 7), ramping up
the Vp input will ramp up the output voltage. In
tracking mode, Vfb always follows Vp which means
Vout is always proportional to Vp voltage (typical for
DDR/Vtt rail applications). The effective Vp range is
0V~1.2V.
Figure 19: Externally Biased Configuration
When the Vin voltage is below 6.8V, the internal LDO
enters the dropout mode at medium and heavy load.
The dropout voltage increases with the switching
frequency. Figure 20 shows the LDO voltage for
600kHz
and
1000kHz
switching
frequency
respectively.
In sequencing mode of operation (simultaneous or
ratiometric), Vref is left floating and Vp is kept to
ground level until Intl_SS signal reaches the final
value. Then Vp is ramped up and Vfb follows Vp.
When Vp>0.6V the error-amplifier switches to Vref
and the output voltage is regulated with Vref. The
final Vp voltage after sequencing startup should
between 0.8V ~ 3.0V.
Enable (Master)
1.2V
VCC
Vref=0.6V
Enable (slave)
Figure 20: LDO_Out Voltage in dropout mode
Soft Start (slave)
Vo1 (master)
OUTPUT VOLTAGE TRACKING AND
SEQUENCING
(a)
(b)
Vo2 (slave)
IR3847 can accommodate user programmable
tracking and/or sequencing options using Vp, Vref,
Enable, and Power Good pins. In the block diagram
presented on page 3, the error-amplifier (E/A) has
been depicted with three positive inputs. Ideally, the
input with the lowest voltage is used for regulating the
output voltage and the other two inputs are ignored. In
practice the voltage of the other two inputs should be
at least 200mV greater than the low-voltage input so
that their effects can completely be ignored. Vp is
pulled up to an internal rail via a high impedance path.
Vo1 (master)
Vo2 (slave)
Figure 21: Typical waveforms for sequencing mode of
operation: (a) simultaneous, (b) ratiometric
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Tracking and sequencing operations can be
implemented to be simultaneous or ratiometric (refer
to Figure 21 and Figure 22). Figure 23 shows typical
circuit configuration for sequencing operation. With
this power-up configuration, the voltage at the Vp pin
of the slave reaches 0.6V before the Fb pin of the
master. If RE/RF =RC/RD, simultaneous startup is
achieved. That is, the output voltage of the slave
follows that of the master until the voltage at the Vp
pin of the slave reaches 0.6 V. After the voltage at the
Vp pin of the slave exceeds 0.6V, the internal 0.6V
reference of the slave dictates its output voltage. In
reality the regulation gradually shifts from Vp to
internal Vref. The circuit shown in Figure 23 can also
be used for simultaneous or ratiometric tracking
operation if Vref of the slave is connected to LGND.
Table 2 summarizes the required conditions to
Vp (Master)
VCC
Vref=0V
Enable (Master and Slave)
Soft Start (Master and Slave)
Vo1 (master)
(a)
(b)
Vo2 (slave)
Vo1 (master)
Vo2 (slave)
achieve
simultaneous/ratiometric
tracking
or
sequencing operations.
Figure 22: Typical waveforms in tracking mode of
operation: (a) simultaneous, (b) ratiometric
5V <Vin<21V
Table 2: Required Conditions for Simultaneous /
Ratiometric Tracking and Sequencing (Figure 23)
Vp
Vo1
(master)
Enable
PVin
Vin
Vp
Boot
Vcc/
Operating
Mode
Vref
(Slave)
Required
Condition
SW
OCSet
LDO_out
Vp
Vsns
RS+
PGood
Normal
PGood
RS-
(Non-
0.6
(Floating)
RA
Rt/SYNC
Floating
―
RSo
Fb
sequencing,
Non-tracking)
Simultaneous
Sequencing
Comp
PGnd
Vref
Gnd
Ramp
up from
0V
RA/RB >
RE/RF =
RC/RD
RA/RB >
RE/RF >
RC/RD
RB
0.6V
0.6V
0V
Ratiometric
Sequencing
Ramp
up from
0V
5V<Vin<21V
Vo1(master)
Simultaneous
Tracking
Ramp
up from
0V
RE/RF =
RC/RD
RE
Vo2
(slave)
Enable
PVin
Vin
Vp
Vcc/
Boot
RF
SW
OCSet
LDO_out
Vsns
RS+
Ratiometric
Tracking
Ramp
up from
0V
RE/RF >
RC/RD
PGood
PGood
RS-
0V
RC
Rt/SYNC
RSo
Fb
Comp
PGnd
Vref
Gnd
VREF
RD
This pin reflects the internal reference voltage which is
used by the error amplifier to set the output voltage. In
most operating conditions this pin is only connected to
an external bypass capacitor and it is left floating. A
minimum 100pF ceramic capacitor is required from
stability point of view. In tracking mode this pin should
Figure 23: Application Circuit for Simultaneous and
Ratiometric Sequencing
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be pulled to LGND. For margining applications, an
external voltage source is connected to Vref pin and
overrides the internal reference voltage. The external
voltage source should have a low internal resistance
(<100Ω) and be able to source and sink more than
25µA.
0.4V
Vp
0.3V
0
1.2*Vp
Vsns
0.95*Vp
0
POWER GOOD OUTPUT (TRACKING,
SEQUENCING, VREF MARGINING)
PGD
0
IR3847 continually monitors the output voltage via the
sense pin (Vsns) voltage. The Vsns voltage is an input
to the window comparator with upper and lower
threshold of 1.2*VREF and 0.95*VREF respectively.
PGood signal is high whenever Vsns voltage is within
the PGood comparator window thresholds. Hysteresis
has been applied to the lower threshold, PGood signal
goes low when Vsns drops below 0.9*VREF instead
of 0.95*VREF. The PGood pin is open drain and it
needs to be externally pulled high. High state
indicates that output is in regulation.
1.28 mS
Figure 25: Vp Tracking (Vref = 0V)
Intl_SS
0
Vref
0.6V
0
(1V<Vp<3.3V)
0.6V
The threshold is set differently in different operating
modes and the results of the comparison sets the
PGood signal. Figure 24, Figure 25 and Figure 26
show the timing diagram of the PGood signal at
different operating modes. Vsns signal is also used by
OVP comparator for detecting output over voltage
condition. PGood signal is low when Enable is low.
Vp
0
1.2*Vref
Vsns
0.95*Vref
0
PGD
Vref
0.6V
0
0
1.28 mS
1.2*VREF
Figure 26: Vp Sequence and Vref Margin
0.90*VREF
OVER-VOLTAGE PROTECTION (OVP)
Vsns
0.95*VREF
0
Over-voltage protection in IR3847 is achieved by
comparing sense pin voltage Vsns to a pre-set
threshold. In non-tracking mode, OVP threshold can
be set at 1.2*Vref; in tracking mode, it can be at
1.2*Vp. When Vsns exceeds the over voltage
threshold, an over voltage trip signal asserts after 2.5
uS (typ.) delay. The high side drive signal HDrv is
latched off immediately and PGood flags are set low.
The low side drive signal is kept on until the Vsns
voltage drops below the threshold. HDrv remains
latched off until a reset is performed by cycling VCC.
OVP is active when enable is high or low.
OVP
Latch
PGD
0
1.28 mS 150 uS 1.28 mS
2.5 uS
Figure 24: Non-sequence, Non-tracking Startup
and Vref Margin (Vp pin floating)
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IL
VD
= Inductor current
= Forward voltage drop of the body diode of
the Sync FET.
= output voltage
= Inductor value
Vsns voltage is set by the voltage divider connected to
the output and it can be programmed externally.
Figure 27 shows the timing diagram for OVP in non-
tracking mode.
Vo
L
1.2*VREF
VREF
The Body Braking mechanism is kept OFF during pre-
bias operation. Also, in the event of an extremely
severe load step-down transient causing OVP, the
Body Brake is overridden by the OVP latch, which
turns on the Sync FET.
Vsns
0
HDrv
0
MINIMUM ON TIME CONSIDERATIONS
LDrv
0
The minimum ON time is the shortest amount of time
for Ctrl FET to be reliably turned on. This is very
critical parameter for low duty cycle, high frequency
applications. Conventional approach limits the pulse
width to prevent noise, jitter and pulse skipping. This
results to lower closed loop bandwidth.
Comp
0
2.5 uS
PGD
IR has developed a proprietary scheme to improve
and enhance minimum pulse width which utilizes the
benefits of voltage mode control scheme with higher
switching frequency, wider conversion ratio and higher
closed loop bandwidth, the latter results in reduction
of output capacitors. Any design or application using
IR3847 must ensure operation with a pulse width that
is higher than the minimum on-time. This is necessary
for the circuit to operate without jitter and pulse-
skipping, which can cause high inductor current ripple
and high output voltage ripple.
0
Figure 27: Timing Diagram for OVP in non-tracking
mode
BODY BRAKINGTM
The Body Braking feature of the IR3847 allows
improved transient response for step-down load
transients. A severe step-down load transient would
cause an overshoot in the output voltage and drive the
Comp pin voltage down until control saturation occurs
demanding 0% duty cycle and the PWM input to the
Control FET driver is kept OFF. When the first such
skipped pulse occurs, the IR3847 enters Body Braking
mode, wherein the Sync FET also turned OFF. The
inductor current then decays by freewheeling through
the body diode of the Sync FET. Thus, with Body
Braking, the forward voltage drop of the body diode
provides and additional voltage to discharge the
inductor current faster to the light load value as shown
in equation (3) and equation (4) below:
Vout
Fs PVin × Fs
D
ton =
=
(5)
In any application that uses IR3847, the following
condition must be satisfied:
ton(min) ≤ ton
(6)
(7)
Vout
ton(min)
≤
PVin × Fs
diL
dt
Vo +VD
= −
= −
, with body braking
(3)
(4)
Vout
L
∴PVin × Fs ≤
(8)
ton(min)
diL
dt
Vo
The minimum output voltage is limited by the
, without body braking
reference voltage and hence Vout(min)
Therefore, for Vout(min) = 0.6V,
=
0.6V.
L
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IR3847
ratio at which IR3847 can operate. Figure 28 shows a
plot of the maximum duty ratio vs. the switching
frequency with built in input voltage feed forward
mechanism.
Vout
ton(min)
0.6V
∴PVin × Fs ≤
∴PVin × Fs ≤
(9)
=12V / µS
50nS
Therefore, at the maximum recommended input
voltage 21V and minimum output voltage, the
converter should be designed at
a
switching
frequency that does not exceed 571 kHz. Conversely,
for operation at the maximum recommended
operating frequency (1.5 MHz) and minimum output
voltage (0.6V). The input voltage (PVin) should not
exceed 8V, otherwise pulse skipping may happen.
MAXIMUM DUTY RATIO
A certain off-time is specified for IR3847. This
provides an upper limit on the operating duty ratio at
any given switching frequency. The off-time remains
at a relatively fixed ratio to switching period in low and
mid frequency range, while in high frequency range
this ratio increases, thus the lower the maximum duty
Figure 28: Maximum duty cycle vs. switching
frequency
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IR3847
TYPICAL OPERATING WAVEFORM
DESIGN EXAMPLE
Output Voltage Programming
Output voltage is programmed by reference voltage
and external voltage divider. The FB pin is the
inverting input of the error amplifier, which is internally
referenced to VREF. The divider ratio is set to equal
VREF at the FB pin when the output is at its desired
value. When an external resistor divider is connected
to the output as shown in Figure 30, the output
voltage is defined by using the following equation:
The following example is a typical application for
IR3847. The application circuit is shown in Figure 35.
Vin = PVin = 12V
Fs = 600kHz
Vo = 1.2V
Io = 25A
Ripple Voltage = ± 1% * Vo
ΔVo = ± 4% * Vo (for 30% load transient)
R
5
Vo =Vref × 1+
(12)
(13)
R6
Enabling the IR3847
As explained earlier, the precise threshold of the
Enable lends itself well to implementation of a UVLO
for the Bus Voltage as shown in Figure 29.
Vref
Vo −Vref
R6 = R5 ×
PVin
For the calculated values of R5 and R6, see feedback
compensation section.
IR3847
R1
Enable
R2
Vout
IR3847
R5
FB
R6
Figure 29: Using Enable pin for UVLO implementation
For a typical Enable threshold of VEN = 1.2 V
Figure 30: Typical application of the IR3847 for
programming the output voltage
R2
PVin(min)
×
=VEN =1.2
(10)
(11)
R1 + R2
Bootstrap Capacitor Selection
VEN
To drive the Control FET, it is necessary to supply a
gate voltage at least 4V greater than the voltage at the
SW pin, which is connected to the source of the
Control FET. This is achieved by using a bootstrap
configuration, which comprises the internal bootstrap
diode and an external bootstrap capacitor (C1). The
operation of the circuit is as follows: When the sync
FET is turned on, the capacitor node connected to SW
is pulled down to ground. The capacitor charges
towards Vcc through the internal bootstrap diode
(Figure 31), which has a forward voltage drop VD. The
voltage Vc across the bootstrap capacitor C1 is
approximately given as:
R2 = R1
PVin(min) −VEN
For PVin (min)=9.2V, R1=49.9K and R2=7.5K ohm is a
good choice.
Programming the frequency
For Fs = 600 kHz, select Rt = 39.2 KΩ, using Table 1.
Vc ≅ Vcc −VD
(14)
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IR3847
When the control FET turns on in the next cycle, the
capacitor node connected to SW rises to the bus
voltage Vin. However, if the value of C1 is
appropriately chosen, the voltage Vc across C1
remains approximately unchanged and the voltage at
the Boot pin becomes:
7x22uF,
25V
ceramic
capacitors,
GRM31CR61E226KE15L from Murata. In addition to
these, although not mandatory, a 1x330uF, 25V SMD
capacitor EEV-FK1E331P from Panasonic may also
be used as a bulk capacitor and is recommended if
the input power supply is not located close to the
converter.
VBoot ≅ PVin + Vcc −VD
(15)
Inductor Selection
Inductors are selected based on output power,
operating frequency and efficiency requirements. A
low inductor value causes large ripple current,
resulting in the smaller size, faster response to a load
transient but may also result in reduced efficiency and
high output noise. Generally, the selection of the
inductor value can be reduced to the desired
maximum ripple current in the inductor (Δi). The
optimum point is usually found between 20% and 50%
ripple of the output current. For the buck converter,
the inductor value for the desired operating ripple
current can be determined using the following relation:
Cvin
PVin
+ VD
-
Boot
V
cc
+
Vc
-
C1
SW
L
IR3847
PGnd
∆i
∆t
1
Vin −Vo = L × ;∆t = D ×
Figure 31: Bootstrap circuit to generate Vc voltage
Fs
A bootstrap capacitor of value 0.1uF is suitable for
most applications.
Vo
L =
(
Vin −Vo
)
×
(18)
Vin × ∆i × Fs
Input Capacitor Selection
The ripple currents generated during the on time of
the control FETs should be provided by the input
capacitor. The RMS value of this ripple for each
channel is expressed by:
Where:
Vin = Maximum input voltage
V0 = Output Voltage
Δi = Inductor Ripple Current
Fs = Switching Frequency
Δt = On time for Control FET
IRMS = Io × D×
(
1− D
)
(16)
(17)
D
= Duty Cycle
Vo
D =
If Δi ≈ 30%*Io, then the inductor is calculated to be
0.24μH. Select L=0.215μH, PCDC1008-R215EMO,
from Cyntec which provides an inductor suitable for
this application.
Vin
Where:
D
= Duty Cycle
IRMS = RMS value of the input capacitor current
Io = output current.
Vin = Power Stage input voltage
Output Capacitor Selection
The voltage ripple and transient requirements
determine the output capacitors type and values. The
criterion is normally based on the value of the
Effective Series Resistance (ESR). However the
actual capacitance value and the Equivalent Series
Inductance (ESL) are other contributing components.
These components can be described as:
Io=25A and D = 0.1, the IRMS = 7.5A.
Ceramic capacitors are recommended due to their
peak current capabilities. They also feature low ESR
and ESL at higher frequency which enables better
efficiency. For this application, it is advisable to have
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IR3847
1
∆Vo = ∆Vo ) + ∆Vo ) + ∆Vo(C)
(
ESR
(
ESL
FLC =
2×π × Lo ×Co
∆V0(ESR) = ∆IL × ESR
(20)
V −V
L
∆IL
o
in
∆V0(ESL)
∆V0(C)
=
× ESL
Figure 32 shows gain and phase of the LC filter. Since
we already have 180o phase shift from the output filter
alone, the system runs the risk of being unstable.
=
(19)
8×Co × Fs
Phase
Gain
00
Where:
0dB
ΔV0 = Output Voltage Ripple
ΔIL = Inductor Ripple Current
-40dB/Decade
Frequency
-900
Since the output capacitor has a major role in the
overall performance of the converter and determines
the result of transient response, selection of the
capacitor is critical. The IR3847 can perform well with
all types of capacitors.
-1800
Frequency
FLC
FLC
Figure 32: Gain and Phase of LC filter
The IR3847 uses a voltage-type error amplifier with
high-gain and high-bandwidth. The output of the
amplifier is available for DC gain control and AC
phase compensation.
As a rule, the capacitor must have low enough ESR to
meet output ripple and load transient requirements.
The goal for this design is to meet the voltage ripple
requirement in the smallest possible capacitor size.
Therefore it is advisable to select ceramic capacitors
due to their low ESR and ESL and small size. Ten of
The error amplifier can be compensated either in type
II or type III compensation. Local feedback with Type
II compensation is shown in Figure 33.
TDK
C2012X5R0J476M
(47uF/0805/X5R/6.3V)
capacitors is a good choice.
This method requires that the output capacitor have
enough ESR to satisfy stability requirements. If the
output capacitor’s ESR generates a zero at 5kHz to
50kHz, the zero generates acceptable phase margin
and the Type II compensator can be used.
It is also recommended to use a 0.1µF ceramic
capacitor at the output for high frequency filtering.
Feedback Compensation
The IR3847 is a voltage mode controller. The control
loop is a single voltage feedback path including error
amplifier and error comparator. To achieve fast
transient response and accurate output regulation, a
compensation circuit is necessary. The goal of the
compensation network is to provide a closed-loop
transfer function with the highest 0 dB crossing
frequency and adequate phase margin (greater than
45o).
The ESR zero of the output capacitor is expressed as
follows:
1
FESR
=
(21)
2×π × ESR×Co
The output LC filter introduces a double pole, -
40dB/decade gain slope above its corner resonant
frequency, and a total phase lag of 180o. The resonant
frequency of the LC filter is expressed as follows:
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IR3847
V
OUT
Use the following equation to calculate R3:
ZIN
CPOLE
C3
Vramp × Fo × FESR × R5
Vin × β × FL2C
R3
R3 =
(26)
R5
Z
f
Where:
Vin = Maximum Input Voltage
ramp = Amplitude of the oscillator Ramp Voltage
Fo = Crossover Frequency
Fb
E/A
Ve
R6
Comp
V
VREF
Gain(dB)
F
β
ESR = Zero Frequency of the Output Capacitor
= (RS+ - RS-) / Vo
H(s) dB
FLC = Resonant Frequency of the Output Filter
R5 = Feedback Resistor
Frequency
FPOLE
FZ
To cancel one of the LC filter poles, place the zero
before the LC filter resonant frequency pole:
Figure 33: Type II compensation network and its
asymptotic gain plot
FZ = 75%× FLC
1
The transfer function (Ve/Vout) is given by:
FZ = 0.75×
(27)
2×π Lo ×Co
Z f
Ve
1+ sR3C3
= H(s) = −
= −
(22)
Use equation (24), (25) and (26) to calculate C3.
Vout
ZIN
sR5C3
One more capacitor is sometimes added in parallel
with C3 and R3. This introduces one more pole which
is mainly used to suppress the switching noise.
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a
gain and zero, expressed by:
The additional pole is given by:
R3
H(s) =
(23)
(24)
R5
1
Fp =
(28)
C3 ×CPOLE
C3 + CPOLE
2×π ×
1
Fz =
2×π × R3 ×C3
The pole sets to one half of the switching frequency
First select the desired zero-crossover frequency (Fo):
(25)
which results in the capacitor CPOLE
:
Fo > FESR and Fo ≤ (1/5 ~1/10)× Fs
1
1
CPOLE
=
≅
(29)
1
π × R3 × FS
π × R3 × FS −
C3
For a general unconditional stable solution for any
type of output capacitors with a wide range of ESR
values, we use a local feedback with a type III
compensation
network.
The
typically
used
compensation network for voltage-mode controller is
shown in Figure 34.
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VOUT
R5
1
ZIN
FZ1 =
(34)
(35)
C2
C3
2π × R3 ×C3
C4
R4
R3
1
1
FZ 2
=
≅
2π ×C4 ×
(
R4 × R5
)
2π ×C4 × R5
Zf
Cross over frequency is expressed as:
Fb
Ve
E A
/
R6
Comp
Vin
1
Fo = R3 ×C4 × β ×
×
Vramp 2π × Lo ×Co
V
REF
(36)
Gain (dB)
Based on the frequency of the zero generated by the
output capacitor and its ESR, relative to the crossover
frequency, the compensation type can be different.
Table 3 shows the compensation types for relative
locations of the crossover frequency.
|H(s)| dB
Frequency
F
F
F
F
P3
P2
Z1
Z2
Table 3: Different types of compensators
Figure 34: Type III Compensation network and its
asymptotic gain plot
Compensator
Type
Typical Output
Capacitor
FESR vs FO
Again, the transfer function is given by:
FLC < FESR < FO <
FS/2
Type II
Type III
Electrolytic
Z f
Ve
= H(s) = −
SP Cap,
Ceramic
FLC < FO < FESR
Vout
ZIN
By replacing Zin and Zf, according to Figure 34, the
transfer function can be expressed as:
The higher the crossover frequency is, the potentially
faster the load transient response will be. However,
the crossover frequency should be low enough to
allow attenuation of switching noise. Typically, the
control loop bandwidth or crossover frequency (Fo) is
selected such that:
(
1+ sR3C3
)
[
1+ sC4
(
R4 + R5
)
]
H(s) = −
C2 ×C3
sR5
(
C2 + C3
)
1+ sR
(
1+ sR C
)
3
4
4
C2 + C3
Fo ≤
(
1/5 ~1/10 *Fs
)
(30)
The DC gain should be large enough to provide high
DC-regulation accuracy. The phase margin should be
greater than 45o for overall stability.
The compensation network has three poles and two
zeros and they are expressed as follows:
The specifications for designing channel 1:
FP1 = 0
FP2 =
(31)
Vin = 12V
Vo = 1.2V
1
(32)
(33)
2π × R4 ×C4
Vramp= 1.8V (This is a function of Vin, pls. see
Feed-Forward section)
1
1
FP3 =
≅
Vref = 0.6V
= (RS+ - RS-) / Vo (This assumes the resistor
2π × R3 ×C2
C2 ×C3
C2 + C3
β
2π × R3
divider placed between Vout and the RSA
scales down the output voltage to Vref. If the
RSA is not used or Vout is connected directly
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to the RSA, β = 1. Please refer to the Remote
Sensing Amplifier section)
Lo = 0.215 µH
2×π × Fo × Lo ×Co ×Vramp
C4 ×Vin × β
R3 =
; R3 = 2.37 kΩ,
Co = 10 x 47µF, ESR≈3mΩ each
Select: R3 = 1.91 kΩ
It must be noted here that the value of the
capacitance used in the compensator design must be
the small signal value. For instance, the small signal
capacitance of the 47µF capacitor used in this design
is 25.7µF at 1.2 V DC bias and 600 kHz frequency. It
is this value that must be used for all computations
related to the compensation. The small signal value
may be obtained from the manufacturer’s datasheets,
design tools or SPICE models. Alternatively, they may
also be inferred from measuring the power stage
transfer function of the converter and measuring the
double pole frequency FLC and using equation (20) to
compute the small signal Co.
1
C3 =
; C3 = 7.5 nF,
2×π × FZ1 × R3
1
Select: C3 = 8.2 nF C2 =
;
2×π × FP3 × R3
C2 = 221 pF,
Select: C2 = 160 pF
Calculate R4, R5 and R6:
These result to:
1
R4 =
; R4 = 127.6 Ω,
FLC = 21.4 kHz
FESR = 2.06 MHz
2×π ×C4 × FP2
Fs/2 = 300 kHz
Select crossover frequency F0=100 kHz
Select R4 = 127 Ω
Since FLC<F0<Fs/2<FESR, Type III is selected to place
the pole and zeros.
1
R5 =
; R5 = 4.11 kΩ,
2×π ×C4 × FZ 2
Select R5 = 4.22 kΩ
Vref
Detailed calculation of compensation Type III:
Desired Phase Margin Θ = 70°
R6 =
× R5 ; R6 = 4.11 kΩ,
1− sinΘ
1+ sinΘ
Vo −Vref
FZ 2 = Fo
=
17.6 kHz
Select R6 = 4.22 kΩ
1+ sin Θ
1− sin Θ
If (β x Vo) equals Vref, R6 is not used.
FP2 = F
=567.1 kHz
o
Setting the Power Good Threshold
Select:
In this design IR3847, the PGood outer limits are set
at 95% and 120% of VREF. PGood signal is asserted
1.3ms after Vsns voltage reaches 0.95*0.6V=0.57V
(Figure 35). As long as the Vsns voltage is between
the threshold ranges, Enable is high, and no fault
happens, the PGood remains high.
FZ1 = 0.5× FZ 2 = 8.8 kHz and
FP3 = 0.5× Fs = 300 kHz
Select C4 = 2.2nF.
The following formula can be used to set the PGood
threshold. Vout (PGood_TH can be taken as 95% of Vout.
Choose Rsns1=4.22 KΩ.
)
Calculate R3, C3 and C2:
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IR3847
Vout_OVP = 1.44 V
V
out(PGood _ TH )
Rsns2 =
−1 × Rsns1
(37)
0.95×VREF
Selecting Power Good Pull-Up Resistor
The PGood is an open drain output and require pull
up resistors to VCC. The value of the pull-up resistors
should limit the current flowing into the PGood pin to
less than 5mA. A typical value used is 10kΩ.
Rsns2 = 4.22 kΩ, Select 4.22 kΩ.
OVP comparator also uses Vsns signal for Over-
Voltage detection. With above values for Rsns2 and
Rsns1, OVP trip point (Vout_OVP) is
(
Rsns1+ Rsns2
Rsns1
)
Vout_ OVP =VREF ×1.2 ×
(38)
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IR3847
TYPICAL APPLICATION
INTERNALLY BIASED SINGLE SUPPLY
Vin
Ren2
49.9 K
Cpvin1
330uF
Cpvin2
7 x 22uF
Cpvin3
0.1uF
Ren1
7.5 K
Cboot
0.1uF
En
PVin
Boot
Vo
SW
Vin
Lo
0.215uH
Rsns2
4.22 K
Rsns1
4.22 K
Cvin
1uF
Cout
10 x 47uF
Co1
VSNS
Vp
0.1 uF
Vcc
RS+
RS-
Cvcc
10uF
Rpg
10 K
IR3847
OCselect
PGood
Vref
PGood
RSo
Rbode
20
Comp
FB
Cc3
Cc2
8.2nF
Rc2
Cc1
160pF
2200pF
Rc1
Rt/Sync
Rfb2
Cref
100pF
4.22 K
AGND
PGND
1.91 K
127
Rt
39.2 K
Rfb1
4.22 K
Figure 35: Application circuit for a 12V to 1.2V, 21A Point of Load Converter Using the Internal LDO
Suggested Bill of Material for application circuit 12V to 1.2V
Part Reference
Qty
Value
Description
Manufacturer
Part Number
Cpvin1
1
330uF
SMD, electrolytic, 25V, 20%
Panasonic
EEV-FK1E331P
Cpvin2
Cref
Cvin
Cvcc
7
1
1
1
3
1
1
1
10
22uF
100pF
1.0uF
10uF
0.1uF
2200pF
8.2nF
160pF
47uF
1206, 25V, X5R, 10%
0603, 50V, C0G, 5%
Murata
Murata
Murata
TDK
Murata
Murata
Murata
Murata
TDK
GRM31CR61E226KE15L
GRM1885C1H101JA01D
GRM188R61E105KA12D
C1608X5R1A106M
GRM188R71E104KA01D
GRM188R71H222KA01D
GRM188R71H822KA01D
GRM1885C1H161JA01D
C2012X5R0J476M
0603, 25V, X5R, 20%
0603, 10V, X5R, 20%
0603, 25V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, NPO, 5%
Cpvin3 Cboot Co1
Cc1
Cc2
Cc3
Cout1
0805, 6.3V, X5R, 20%
10.1x7.8x7.3mm,
DCR=0.29mΩ
L0
1
0.215uH
Cyntec
PCDC1008-R215EMO
Rbd
Rc1
Rc2
Ren1
Ren2
1
1
1
1
1
20
127
1.91K
7.5K
49.9K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-3EKF20R0V
ERJ-3EKF1270V
ERJ-3EKF1911V
ERJ-3EKF7501V
ERJ-3EKF4992V
Rfb1 Rfb2
Rsns1Rsns1
4
4.22K
Thick Film, 0603, 1/10W, 1%
Panasonic
ERJ-3EKF4221V
Rt
Rpg
1
1
39.2K
10K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
International
Rectifier
ERJ-3EKF3922V
ERJ-3EKF1002V
U1
1
IR3847
PQFN 5x6mm
IR3847MPBF
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IR3847
EXTERNALLY BIASED DUAL SUPPLIES
PVin
Ren2
49.9 K
Cpvin1
330uF
Cpvin2
7 x 22uF
Cpvin3
0.1uF
Ren1
7.5 K
Cboot
0.1uF
En
PVin
Boot
Vin
SW
VSNS
RS+
Vo
Vin
Lo
0.215uH
Rsns2
4.22 K
Rsns1
4.22 K
Cvin
1uF
Cout
10 x 47 uF
Co1
0.1 uF
Vp
Vcc
Cvcc
10uF
Rpg
10 K
IR3847
RS-
OCselect
PGood
Vref
PGood
RSo
Rbode
20
Comp
FB
Cc3
Cc2
Cc1
160pF
8.2nF
Rc2
1.91 K
2200pF
Rc1
127
Rt/Sync
Rfb2
4.22 K
Cref
100pF
AGND
PGND
Rt
Rfb1
4.22 K
39.2 K
Figure 36: Application circuit for a 12V to 1.2V, 21A Point of Load Converter using external 5V VCC
Suggested Bill of Material for application circuit 12V to 1.2V using external 5V VCC
Part Reference
Qty
Value
Description
Manufacturer
Part Number
Cpvin1
1
330uF
SMD, electrolytic, 25V, 20%
Panasonic
EEV-FK1E331P
Cpvin2
Cref
Cvin
Cvcc
7
1
1
1
3
1
1
1
10
22uF
100pF
1.0uF
10uF
0.1uF
2200pF
8.2nF
160pF
47uF
1206, 25V, X5R, 10%
0603, 50V, C0G, 5%
Murata
Murata
Murata
TDK
Murata
Murata
Murata
Murata
TDK
GRM31CR61E226KE15L
GRM1885C1H101JA01D
GRM188R61E105KA12D
C1608X5R1A106M
GRM188R71E104KA01D
GRM188R71H222KA01D
GRM188R71H822KA01D
GRM1885C1H161JA01D
C2012X5R0J476M
0603, 25V, X5R, 20%
0603, 10V, X5R, 20%
0603, 25V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, NPO, 5%
Cpvin3 Cboot Co1
Cc1
Cc2
Cc3
Cout1
0805, 6.3V, X5R, 20%
10.1x7.8x7.3mm,
L0
1
0.215uH
Cyntec
PCDC1008-R215EMO
DCR=0.29mΩ
Rbd
Rc1
Rc2
Ren1
Ren2
1
1
1
1
1
20
52.3
1.91K
7.5K
49.9K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-3EKF20R0V
ERJ-3EKF52R3V
ERJ-3EKF1911V
ERJ-3EKF7501V
ERJ-3EKF4992V
Rfb1 Rfb2
Rsns1Rsns1
Rt
4
4.22K
Thick Film, 0603, 1/10W, 1%
Panasonic
ERJ-3EKF4221V
1
1
39.2K
10K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
ERJ-3EKF3922V
ERJ-3EKF1002V
Rpg
International
Rectifier
U1
1
IR3847
PQFN 5x6mm
IR3847MPBF
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IR3847
EXTERNALLY BIASED SINGLE SUPPLY
Vin
Ren2
41.2 K
Cpvin1
330uF
Cpvin2
7 x 22uF
Cpvin3
0.1uF
Ren1
21 K
Cboot
0.1uF
En
PVin
Boot
Vo
SW
VSNS
RS+
Vin
Lo
0.215uH
Rsns2
4.22 K
Rsns1
4.22 K
Cvin
1uF
Cout
Co1
Vp
10 x 47 uF 0.1 uF
Vcc
Cvcc
10uF
Rpg
10 K
IR3847
RS-
OCselect
PGood
Vref
PGood
RSo
Rbode
20
Comp
FB
Cc3
Cc2
Cc1
120pF
5.6nF
Rc2
2.8 K
2200pF
Rc1
127
Rt/Sync
Rfb2
4.22 K
Cref
100pF
AGND
PGND
Rt
Rfb1
4.22 K
39.2 K
Figure 37: Application circuit for a 5V to 1.2V, 25A Point of Load Converter
Suggested bill of material for application circuit 5V to 1.2V
Part Reference
Qty
Value
Description
Manufacturer
Part Number
Cpvin1
1
330uF
SMD, electrolytic, 25V, 20%
Panasonic
EEV-FK1E331P
Cpvin2
Cref
Cvin
Cvcc
7
1
1
1
3
1
1
1
10
22uF
100pF
1.0uF
10uF
0.1uF
2200pF
5.6nF
120pF
47uF
1206, 25V, X5R, 10%
0603, 50V, C0G, 5%
Murata
Murata
Murata
TDK
Murata
Murata
Murata
Murata
TDK
GRM31CR61E226KE15L
GRM1885C1H101JA01D
GRM188R61E105KA12D
C1608X5R1A106M
GRM188R71E104KA01D
GRM188R71H222KA01D
GRM188R71H562KA01D
GRM1885C1H121JA01D
C2012X5R0J476M
0603, 25V, X5R, 20%
0603, 10V, X5R, 20%
0603, 25V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, NPO, 5%
Cpvin3 Cboot Co1
Cc1
Cc2
Cc3
Cout1
0805, 6.3V, X5R, 20%
10.1x7.8x7.3mm,
L0
1
0.215uH
Cyntec
PCDC1008-R215EMO
DCR=0.29mΩ
Rbd
Rc1
Rc2
Ren1
Ren2
1
1
1
1
1
20
127
2.8K
21K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-3EKF20R0V
ERJ-3EKF1270V
ERJ-3EKF2801V
ERJ-3EKF2102V
ERJ-3EKF4122V
41.2K
Rfb1 Rfb2
Rsns1Rsns1
Rt
4
4.22K
Thick Film, 0603, 1/10W, 1%
Panasonic
ERJ-3EKF4221V
1
1
39.2K
10K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
ERJ-3EKF3922V
ERJ-3EKF1002V
Rpg
International
Rectifier
U1
1
IR3847
PQFN 5x6mm
IR3847MPBF
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IR3847
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=0-25A, Fs=600kHz, Room Temperature, No Air Flow
Figure 38: Startup with full load, Enable Signal
Figure 39: Startup with full load, VCC signal
CH1:Vin, CH2:Vout, CH3:PGood, CH4:Enable
CH1:Vin, CH2:Vout, CH3:PGood, CH4:VCC
Figure 40: Vout Startup with Pre-Bias, 1.08V
Figure 41: Recovery from Hiccup
CH1:Enable, Ch2:Vout, CH3:PGood
CH2:Vout, CH3:PGood, CH4:Iout
Figure 42: Inductor Switch Node at full load
Figure 43: Output Voltage Ripple at full load
CH2:SW
CH1:Vout
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IR3847
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=2.5-10A, Fs=600kHz, Room Temperature, No air flow
Figure 44: Vout Transient Response, 2.5A to 10.0A step at 2.5A/uSec
CH2:Vout, CH4:Iout (10A/V)
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IR3847
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=17.5-25A, Fs=600kHz, Room Temperature, No air flow
Figure 45: Vout Transient Response, 17.5A to 25A step at 2.5A/uSec
CH2:Vout, CH4:Iout (10A/V)
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TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=25A, Fs=600kHz, Room Temperature, No air flow
Figure 46: Bode Plot with 25A load: Fo = 108 kHz, Phase Margin = 50.2 Degrees
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IR3847
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=0-25A, Fs=600kHz, Room Temperature, No air flow
Figure 47: Efficiency versus load current
Figure 48: Power Loss versus load current
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IR3847
LAYOUT RECOMMENDATIONS
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to perform
with less than expected results.
pins. It is important to place the feedback components
including feedback resistors and compensation
components close to Fb and Comp pins.
In a multilayer PCB use at least one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are referenced.
The goal is to localize the high current path to a
separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout at
a single point. It is recommended to place all the
compensation parts over the analog ground plane in
top layer.
Make the connections for the power components in
the top layer with wide, copper filled areas or
polygons. In general, it is desirable to make proper
use of power planes and polygons for power
distribution and heat dissipation.
The inductor, input capacitors, output capacitors and
the IR3847 should be as close to each other as
possible. This helps to reduce the EMI radiated by the
power traces due to the high switching currents
through them. Place the input capacitor directly at the
PVin pin of IR3847.
The Power QFN is a thermally enhanced package.
Based on thermal performance it is recommended to
use at least a 6-layers PCB. To effectively remove
heat from the device the exposed pad should be
connected to the ground plane using vias. Figure
49a-f illustrates the implementation of the layout
guidelines outlined above, on the IRDC3847 6-layer
demo board.
The feedback part of the system should be kept away
from the inductor and other noise sources.
The critical bypass components such as capacitors for
PVin, Vin and VCC should be close to their respective
- Ground path between
VIN- and VOUT- should
be minimized with
maximum copper
-
Vout
- Bypass caps should be
placed as close as
PVin
possible to their
connecting pins
- Filled vias placed
under PGND and
PVin pads to help
thermal performance.
- Compensation parts
should be placed
as close as possible
to the Comp pins
- SW node copper is
kept only at the top
layer to minimize the
switching noise
- Single point connection
AGND
PGND
between AGND &
PGND, should be placed
near the part and kept
away from noise sources
Figure 49a: IRDC3847 Demo board Layout Considerations – Top Layer
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Vout
PGND
Figure 49b: IRDC3847 Demo board Layout Considerations – Bottom Layer
PGND
Figure 49c: IRDC3847 Demo board Layout Considerations – Mid Layer 1
Vout
PGND
Figure 49d: IRDC3847 Demo board Layout Considerations – Mid Layer 2
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-Feedback and Vsns traces
routing should be kept away from
noise sources
Vout
PGND
Remote Sense Traces
- tap output where voltage value is
critical.
- Avoid noisy areas and noise coupling.
- RS+ and RS- lines near each other.
- Minimize trace resistance.
Figure 49e: IRDC3847 Demo board Layout Considerations – Mid Layer 3
PGND
Figure 49f: IRDC3847 Demo board Layout Considerations – Mid Layer 4
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IR3847
PCB METAL AND COMPONENT PLACEMENT
Evaluations have shown that the best overall
performance is achieved using the substrate/PCB
layout as shown in following figures. PQFN devices
should be placed to an accuracy of 0.050mm on both
X and Y axes. Self-centering behavior is highly
dependent on solders and processes, and
experiments should be run to confirm the limits of self-
centering on specific processes. For further
information, please refer to “SupIRBuck™ Multi-Chip
Module (MCM) Power Quad Flat No-Lead (PQFN)
Board Mounting Application Note.” (AN1132)
PCB PAD SIZES (DETAIL 1)
PCB PAD SIZES (DETAIL 2)
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PCB PAD SPACING (DETAIL 1)
PCB PAD SPACING (DETAIL 2)
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SOLDER RESIST
•
IR recommends that the larger Power or Land
•
•
However, for the smaller Signal type leads
around the edge of the device, IR
recommends that these are Non Solder Mask
Defined or Copper Defined.
Area pads are Solder Mask Defined (SMD).
This allows the underlying Copper traces to be
as large as possible, which helps in terms of
current carrying capability and device cooling
capability.
When using NSMD pads, the Solder Resist
Window should be larger than the Copper Pad
by at least 0.025mm on each edge, (i.e.
0.05mm in X & Y), in order to accommodate
any layer to layer misalignment.
•
When using SMD pads, the underlying copper
traces should be at least 0.05mm larger (on
each edge) than the Solder Mask window, in
order to accommodate any layer to layer
misalignment. (i.e. 0.1mm in X & Y).
•
Ensure that the solder resist in-between the
smaller signal lead areas are at least 0.15mm
wide, due to the high x/y aspect ratio of the
solder mask strip.
SOLDER MASK DESIGN
PAD SIZES (DETAIL 1)
SOLDER MASK DESIGN
PAD SIZES (DETAIL 2)
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SOLDER MASK DESIGN
PAD SPACING (DETAIL 1)
SOLDER MASK DESIGN
PAD SPACING (DETAIL 2)
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STENCIL DESIGN
•
Stencils for PQFN can be used with
•
Evaluations have shown that the best overall
performance is achieved using the stencil
design shown in following figure. This design
for a stencil thickness of 0.127mm (0.005”).
The reduction should be adjusted for stencils
of other thicknesses.
thicknesses of 0.100-0.250mm (0.004-0.010”).
Stencils thinner than 0.100mm are unsuitable
because they deposit insufficient solder paste
to make good solder joints with the ground
pad; high reductions sometimes create similar
problems. Stencils in the range of 0.125mm-
0.200mm
(0.005-0.008”),
with
suitable
reductions, give best results.
SOLDER PASTE STENCIL
PAD SIZES (DETAIL 1)
SOLDER PASTE STENCIL
PAD SIZES (DETAIL 2)
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SOLDER PASTE STENCIL
PAD SPACING (DETAIL 1)
SOLDER PASTE STENCIL
PAD SPACING (DETAIL 2)
MARKING INFORMATION
Figure 50: Marking Information
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PACKAGING INFORMATION
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ENVIRONMENTAL QUALIFICATIONS
Industrial
Qualification Level
Moisture Sensitivity Level
5mm x 6mm PQFN
MSL3
Class A
<200V
Machine Model
(JESD22-A115A)
Class 1C
Human Body Model
(JESD22-A114F)
ESD
≥1000V to <2000V
Class III
Charged Device Model
(JESD22-C101D)
≥500V to ≤1000V
Yes
RoHS Compliant
Data and specifications subject to change without notice.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com
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