IR3870MBF [INFINEON]
10A HIGHLY INTEGRATED WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR; 10A高集成度的宽电压输入，同步降压稳压器
| 型号： | IR3870MBF |
| 厂家： | 
Infineon |
| 描述： | 10A HIGHLY INTEGRATED WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR |
| 文件： | 总20页 (文件大小：1595K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD-97392
IR3870MBF
TM
SupIRBuck
10A HIGHLY INTEGRATED
WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR
Features
Description
The IR3870M SupIRBuckTM is an easy-to-use,
fully integrated and highly efficient DC/DC
voltage regulator. The onboard constant on time
hysteretic controller and MOSFETs make IR3870
a space-efficient solution that delivers up to 10A
of precisely controlled output voltage in 60°C
ambient temperature applications without airflow.
• Input Voltage Range: 3V to 26V
• Output Voltage Range: 0.5V to 12V
• Continuous 10A Load Capability
• Constant On-Time control
• Excellent Efficiency at very low output current levels
• Gate drive charge pump option to maximize
efficiency at higher output current levels
• Compensation Loop not Required
• Programmable switching frequency, soft start, and
over current protection
Programmable switching frequency, soft start,
and over current protection allows for a very
flexible solution suitable for many different
applications. The combination of the gate drive
charge pump option and constant on time control
allow efficiency optimization in the whole output
current range, making this device an ideal choice
for battery powered applications.
• Power Good Output
• Precision Voltage Reference (0.5V, +/-1%)
• Enable Input with Voltage Monitoring Capability
• Pre-bias Start Up
• Under/Over Voltage Fault Protection
• Ultra small, low profile 5 x 6mm QFN Package
• Lead-free, halogen-free and RoHS compliant
Additional features include pre-bias startup, very
precise 0.5V reference, over/under voltage shut
down, power good output, and enable input with
voltage monitoring capability.
Applications
• Notebook and desktop computers
• Game consoles
• Consumer electronics - STB, LCD TV, Printers
• General purpose POL DC-DC Converters
Typical Notebook Application Circuit Diagram
1
1/27/2010
IR3870MBF
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND unless otherwise specified)
•
•
•
•
•
•
•
•
•
•
•
•
•
VIN ……………………………………………………. 30V
VCC ……………….….………………………………. 3.9V
PVCC ……………….….…………….……..………… 7.5V
Boot
……………………………………..……….….. 40V
PHASE …………………………………………..…….. -0.3V to 30V(DC), -5V(100ns)
Boot to PHASE…..…………………………….…..…… 7.5V
FF
………………………………………….………… 30V
PGND to GND ……………...…………………………. -0.3V to +0.3V
All other pins ……………...…………………………… 3.9V
Storage Temperature Range ..................................... -65°C To 150°C
Junction Temperature Range .................................... -10°C To 150°C
ESD Classification …………………………….……… JEDEC Class 1C
Moisture sensitivity level………………...…………….. JEDEC Level 3@260 °C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications are not implied.
PACKAGE INFORMATION
5mm x 6mm POWER QFN
θJA = 35oC / W
θJ-PCB = 2oC / W
ORDERING INFORMATI
PKG DESIG
PACKAGE
PIN COUNT
PARTS PER
REEL
DESCRIPTION
M
M
IR3870MTRPbF
IR3870MTR1PbF
23
23
4000
750
2
IR3870MBF
Block Diagram
3
IR3870MBF
Pin Description
NAME
NC
NUMBER
I/O LEVEL
DESCRIPTION
1
2
No connection
ISET
PGOOD
GND
FB
Connecting resistor to PHASE pin sets over current trip point
Power good – pull up to 5V
3
5V
4,17
5
Reference
3.3V
Bias return and signal reference
Inverting pin of PWM comparator and OVP/PGood sense
Set soft start slew-rate with a capacitor to GND
No connection
SS
6
3.3V
NC
7
VCC
CPO
PVCC
PGND
PHASE
VIN
8
3.3V
Internal bias supply
9
0.75V
5V
Charge pump output
10
11
12
13
14
Gate drive supply
Reference
VIN
Power return
Phase node (or switching node) of MOSFET half bridge
Input voltage for the system.
VIN
BOOT
VIN
+PVCC
Bootstrapped gate drive supply – connect a capacitor to
PHASE
FF
15
16
VIN
Input voltage feed forward – sets on-time with a resistor to
VIN
EN
5V
Enable – turns device on or off
4
IR3870MBF
Recommended Operating Conditions
Symbol
VIN
VCC
Boot to
PHASE
VOUT
Definition
Input Voltage
Supply Voltage
Supply Voltage
Min
Max
Units
3
3
26*
3.6
7.0
V
Output Voltage
Output Current
0.5
0
12
10
IOUT
A
Fs
Switching Frequency
1000
kHz
* Note: PHASE pin must not exceed 30V.
Electrical Specifications
Unless otherwise specified, these specification apply over VIN = 12V, PVCC = 7VDC, 0oC ≤ TJ ≤ 125oC.
PARAMETER
BIAS SUPPLIES
NOTE
TEST CONDITION
MIN
TYP
MAX
UNIT
VCC Turn-on Threshold
3
V
V
2.65
VCC Turn-off Threshold
VCC Threshold Hysteresis
PVCC Turn-on Threshold
PVCC Turn-off Threshold
PVCC Threshold Hysteresis
60
mV
V
3.05
60
2.65
V
60
30
mV
μA
EN=LOW
VCC Shutdown Current
VCC Operating Current
PVCC Operating Current
RFF = 180kΩ, EN = HIGH
1.2
8
mA
mA
RFF = 180kΩ,
EN = HIGH, Fs = 500kHz
PVCC Shutdown Current
FF Shutdown Current
VIN Shutdown Current
PHASE Shutdown Current
CONTROL LOOP
EN=LOW
EN=LOW
EN=LOW
EN=LOW
20
0.1
0
60
2
μA
μA
μA
μA
1
0.25
2
Reference Accuracy, VREF
0.495
280
0.5
0.505
320
V
On-Time Accuracy
300
ns
R
FF = 180 kΩ, TJ = 650C
Min Off Time
300
10
ns
Soft-Start Current
8
12
μA
EN = HIGH
FAULT PROTECTION
ISET pin output current
18
20
22
μA
V
Under Voltage Threshold
Under Voltage Hysteresis
Over Voltage Threshold
Over Voltage Hysteresis
PGOOD Delay Threshold (VSS)
Falling VFB & monitor PGOOD
Rising VFB
0.37
0.4
7.5
0.6
7.5
0.6
0.43
mV
V
Rising VFB & monitor PGOOD
Rising VFB
0.56
0.64
1
mV
V
5
IR3870MBF
Electrical Specifications (continued)
Unless otherwise specified, these specification apply over VIN = 12V, PVCC = 7VDC, 0oC ≤ TJ ≤ 125oC.
PARAMETER
GATE DRIVE
NOTE
TEST CONDITION
MIN
TYP
MAX
UNIT
Dead time
1
Monitor body diode conduction on
PHASE pin
5
30
ns
UPPER MOSFET
Static Drain-to-Source On-
Resistance
PVCC =5V, ID =10A, TJ =25oC
PVCC =5V, ID =10A, TJ =125oC
PVCC =7V, ID =10A, TJ =25oC
PVCC =7V, ID =10A, TJ =125oC
VGS =0V, IS =10A, TJ =25oC
14.7
11.9
mꢀ
mꢀ
mꢀ
mꢀ
V
Static Drain-to-Source On-
Resistance
26
Static Drain-to-Source On-
Resistance
Static Drain-to-Source On-
Resistance
22
Diode Forward Voltage
1.0
LOWER MOSFET
Static Drain-to-Source On-
Resistance
PVCC =5V, ID =10A, TJ =25oC
PVCC =5V, ID =10A, TJ =125oC
PVCC =7V, ID =10A, TJ =25oC
PVCC =7V, ID =10A, TJ =125oC
VGS =0V, IS =10A, TJ =25oC
6.2
5.1
mꢀ
mꢀ
mꢀ
mꢀ
V
Static Drain-to-Source On-
Resistance
11
Static Drain-to-Source On-
Resistance
Static Drain-to-Source On-
Resistance
9
Diode Forward Voltage
1.0
CHARGE PUMP OUTPUT
Source Resistance
Sink Resistance
ICPO =15mA
ICPO =15mA
3.3
1
5
ꢀ
ꢀ
V
2.1
Charge Pump Disable
Threshold, VCP TH
6.7
7.2
LOGIC INPUT AND OUTPUT
EN Rising Threshold
EN Hysteresis
1.13
40
1.21
100
1.29
160
1
V
mV
EN Input Current
μA
PGOOD pull down resistance
IPGOOD =2mA
50
100
ꢀ
Notoe1: Guaranteed by design, not tested in production
6
IR3870MBF
TYPICAL OPERATING DATA (25oC)
(Circuit of Figure 15, VCC = 3.3V, V5 = 5V, VIN = 12.6V, F = 500kHz Unless otherwise noted)
336
1000
334
332
330
V
OUT = 5V
328
326
324
322
VOUT = 0.5V
0
0
25
50
75
100
125
1000
200
Temperature (C)
Switching Frequency (KHz)
Figure 3. On-Time Variation in DCM:
VIN = 12V, VOUT =1.1V, RFF = 180kOhm
Figure 1. Feedforward Resistance Vs Switching
Frequency: 0.5V VOUT step
500
450
400
350
300
250
200
150
100
50
315
314.5
314
313.5
313
312.5
312
311.5
311
0
0
2
4
6
8
10
12
0
25
50
75
100
125
Output Current (A)
Temperature (C)
Figure 4. On-Time Variation in CCM:
VIN = 12V, VOUT =1.1V, RFF = 180kOhm
Figure 2. Switching Frequency Vs Output Current
7
IR3870MBF
TYPICAL OPERATING DATA (25oC)
(Circuit of Figure 15, VCC = 3.3V, V5 = 5V, VIN = 12.6V, F = 500kHz Unless otherwise noted)
Eff: 12.6Vin
Ef f : 19V in
Ploss: 12.6Vin
Ploss: 19V in
0.5
88
87
86
85
84
83
82
81
80
1.11400
1.10900
1.10400
1.09900
1.09400
1.08900
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
19Vin
12.6Vin
0.0
1.8
0
2
4
6
8
10
12
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Output Current (A)
Output Current(A)
Figure 5. Output Voltage Regulation Vs
Output Current
Figure 7. Light load Efficiency: VOUT = 1.1V
Eff: 12.6Vin
Eff: 19Vin
Ploss: 12.6Vin
Plos s : 19V in
3.5
16
0.080
0.070
0.060
0.050
0.040
0.030
90
89
88
87
86
85
84
83
82
81
14
12
10
8
3.0
2.5
2.0
1.5
1.0
0.5
6
4
0.020
Vin Ploss
5V PVcc Ploss
2
0.010
3.3V Vcc Ploss
0.000
80
0
0.0
12
0
2
4
6
8
10
0
2
4
6
8
10
12
Output Current(A)
Output Current(A)
Figure 6. System Efficiency: VOUT = 1.1V
Figure 8. Input Power Vs Output Current
8
IR3870MBF
TYPICAL OPERATING WAVEFORM (25oC)
(Circuit of Figure 15, VCC = 3.3V, V5 = 5V, VIN = 12.6V, F = 500kHz, Unless otherwise noted)
CH1: Vout (50mV/div); 20uS/div
CH2: PHASE (10V/div)
CH1: Vout (500mV/div); 500uS/div
CH2: PHASE (10V/div)
Figure 11: FCCM/CCM transition from 0.5A
to 5A at 12.6VIN: 30mV overshoot, 15mV
undershoot
CH3: EN (2V/div) CH4: PGOOD (5V/div)
Figure 9: Shutdown/EN at IOUT = 500mA
CH1: Vout (50mV/div); CH2: Phase (10V/div) CH4:
CPO (2V/div); Time: 2uS/div)
CH1: Vout (50mV/div); 20uS/div
CH2: Phase (10V/div)
Figure 12: Charge Pump Off at IOUT = 1A
Figure 10: Load Step (2A to 10A) Transient
(5A/us) at 12.6VIN: 50mV overshoot, 25mV
undershoot
9
IR3870MBF
TYPICAL OPERATING WAVEFORM con’t (25oC)
(Circuit of Figure 15, VCC = 3.3V, V5 = 5V, VIN = 12.6V, F = 500kHz, Unless otherwise noted)
CH1: Vout (50mV/div); CH2: Phase (10V/div)
CH4: CPO (2V/div); Time: 2uS/div)
Figure 13: Charge Pump On at IOUT = 3A
IC: 750C, Inductor: 530C, PCB: 540C
Figure 14: Thermal Image: VIN = 19V,
IOUT = 10A, Ta= 250C, no air flow
10
IR3870MBF
TYPICAL APPLICATION CIRCUIT WITH CHARGE PUMP OPTION
Figure 15. Application Circuit with Charge Pump used to boost Sync FET gate
drive voltage from 5V to ~7V, resulting in improved efficiency at higher output
current levels
F = 500kHz, VOUT = 1.1V
11
IR3870MBF
Circuit Description
PWM COMPARATOR
The PWM comparator initiates a SET signal
(PWM pulse) when the FB pin falls below the
reference (VREF) or the soft start (SS) voltage.
RDSON ⋅ IOC
RSET =
(3)
20 μA
GATE DRIVE LOGIC
ON-TIME GENERATOR
The gate drive logic features adaptive dead time,
diode emulation, and a minimum lower gate
interval.
An adaptive dead time prevents the simultaneous
conduction of the upper and lower MOSFETs.
The lower gate voltage must be below
The PWM comparator initiates a SET signal
(PWM pulse) when the FB pin falls below the
reference (VREF) or the soft start (SS) voltage.
The PWM on-time duration is programmed with
an external resistor (RFF) from the input supply
(VIN) to the FF pin. The simplified equation for
RFF is shown in equation 1. The FF pin is held
to an internal reference after EN goes HIGH. A
copy of the current in RFF charges a timing
capacitor, which sets the on-time duration, as
shown in equation 2.
approximately 1V after PWM goes HIGH before
the upper MOSFET can be gated on. Also, the
upper gate voltage, the difference voltage
between UGATE and PHASE, must be below
approximately 1V after PWM goes LOW and
before the lower MOSFET can be gated on.
The control MOSFET is gated on after the
adaptive delay for PWM = HIGH and the
synchronous MOSFET is gated on after the
adaptive delay for PWM = LOW. The lower
MOSFET is driven ‘off’ when the signal ZCROSS
indicates that the inductor current has reversed
as detected by the PHASE voltage crossing the
zero current threshold. The synchronous
MOSFET stays ‘off’ until the next PWM falling
edge. When the lower peak of inductor current is
above zero, a forced continuous current condition
is selected set. The control MOSFET is gated on
after the adaptive delay for PWM = HIGH, and
the synchronous MOSFET is gated on after the
adaptive delay for PWM = LOW.
VOUT
RFF =
(1)
1V ⋅20pF ⋅FSW
RFF⋅1V ⋅20pF
TON =
(2)
VIN
SOFT START
An internal 10uA current source charges the
external capacitor on the SS pin to set the output
voltage slew rate during the soft start interval.
The output voltage reaches regulation when the
FB pin is above the under voltage threshold and
the UV# = HIGH. Once the voltage on the SS pin
is above the PGOOD delay threshold, the
combination of the SSDelay and UV# signals
release the PGOOD pin. With EN = LOW, the
capacitor voltage and SS pin is held to the FB pin
voltage.
The synchronous MOSFET gate is driven on for
a minimum duration. This minimum duration
allows time to recharge the bootstrap capacitor
and allows the current monitor to sample the
phase voltage.
OVER CURRENT MONITOR
The over current circuitry monitors the output
current during each switching cycle. The voltage
across the synchronous MOSFET, VPHASE, is
monitored for over current and zero crossing.
The minimum LGATE interval allows time to
sample VPHASE.
The over current trip point is programmed with a
resistor from the ISET pin to PHASE pin, as
shown in equation 3. When over current is
detected, the output gates are tri-state and SS
voltage is pulled to 0V. This initiates a new soft
start cycle. If there are three consecutive OC
events the IR3870 will disable switching.
Toggling VCC or EN will allow the next start up.
CONTROL LOGIC
The control logic monitors input power sources,
sequences the converter through the soft-start
and protective modes and indicates output
voltage status on the PGOOD pin. PVCC and
VCC pins are continuously monitored and will
disable the IR3870 if the voltage of either pin
drops below the falling thresholds.
The IR3870 will initiate a soft start when the
PVCC is in the normal range and the EN pin =
HIGH. In the event of a sustained overload a
counter keeps track of 4 consecutive soft-start
cycles and then disables the IR3870.
If the overload is momentary and the output
12
IR3870MBF
Circuit Description
One can use equation 4 to find the required
inductance. The main advantage of small
inductance is increased inductor current slew
rate during a load transient, which leads to a
smaller output capacitance requirement as
discussed in the Output Capacitor Selection
section. The draw back of using smaller
inductances is increased switching power loss in
upper MOSFET, which reduces the system
efficiency and increases the thermal dissipation
as discussed in the Power Loss section.
voltage is within regulation before four
consecutive soft-start cycles, PGOOD transitions
HIGH to reset the counter.
OVER VOLTAGE PROTECTION
The IR3870 monitors the voltage at the FB node.
If the FB voltage is above the over voltage
threshold, the gates are turned off and the
PGOOD signal is pulled low. Toggling VCC will
allow the next start up.
CHARGE PUMP
The purpose of the charge pump is to improve
the system efficiency. A combination of VCC, V5
and three external components are used to boost
PVCC up to VCPTH. PVCC drives the
Input Capacitor Selection
The main function of the input capacitor bank is
to provide the input ripple current and fast slew
rate current during the load current step up. The
input capacitor bank must have adequate ripple
current carrying capability to handle the total
RMS current. Figure 16 shows a typical input
current. Equation 5 shows the RMS input current.
The RMS input current contains the DC load
current and the inductor ripple current. As shown
in equation 4, the inductor ripple current is
unrelated to the load current. The maximum
RMS input current occurs at the maximum output
current. The maximum power dissipation in the
input capacitor equals the square of the
synchronous MOSFET and reduces the RDSON
when compared to a regular 5V rail driver. The
lower FET RDSON reduces the conduction
power loss as discussed in the Power Loss
section. The charge pump is continuously
enabled for FCCM = HIGH. The charge pump
circuit is disabled when FCCM = LOW and the
output loading is less than half of inductor current
ripple. In this case, PVCC is two diode voltages
away from the V5 rail. Therefore, the power loss
for driver is reduced. The charge pump circuit
stops switching the CPO pin for PVCC above
VCPTH.
maximum RMS input current times the input
capacitor’s total ESR.
COMPONENT SELECTION
Selection of components for the converter is an
iterative process which involves meeting the
specifications and trade-offs between performance
and cost. The following sections will guide one
through the process.
Inductor Selection
Inductor selection involves meeting the steady
state output ripple requirement, minimizing the
switching loss of upper MOSFETs, meeting
transient response specifications and minimizing
the output capacitance. The output voltage
includes a DC voltage and a small AC ripple
component due to the low pass filter which has
incomplete attenuation of the switching harmonics.
Neglecting the inductance in series with the output
capacitor, the magnitude of the AC voltage ripple is
determined by the total inductor ripple current flow
through the total equivalent series resistance
(ESR) of the output capacitor bank.
Figure 16. Typical Iput Current Waveform.
Ts
1
IIN_RMS =
⋅
f2
(
t ⋅dt
)
∫
Ts
0
2
1
ΔI
⎛
⎞
⎟
= IOUT ⋅ D ⋅ 1+
⋅
(5)
⎜
⎝
3
IOUT
⎠
The voltage rating of the input capacitor needs to be
greater than the maximum input voltage because of
high frequency ringing at the phase node. The typical
percentage is 25%.
VOUT
L
VOUT ⋅
(
VIN − VOUT
)
(4)
ΔI =
⋅
(1−D
)
⋅Ts =
VIN⋅L⋅Fs
13
IR3870MBF
Output Capacitor Selection
Selection of the output capacitor requires
meeting voltage overshoot requirements during
load removal, and meeting steady state output
ripple voltage requirements. The output
capacitor is the most expensive converter
component and increases the overall system
cost. The output capacitor decoupling in the
converter typically includes the low frequency
capacitor, such as Specialty Polymer Aluminum,
and mid frequency ceramic capacitors.
VESR is usually much greater than VESL. The
IR3870 requires a total ESR such that the ripple
voltage at the FB pin is greater than 7mV.
The second purpose of the output capacitor is to
minimize the overshoot of the output voltage
when the load decreases as shown in Figure 18.
By using the law of energy before and after the
load removal, equation 7 shows the output
capacitance requirement for a load step.
The first purpose of output capacitors is to
provide current when the load demand exceeds
the inductor current, as shown in Figure 17.
Equation 6 shows the charge requirement for a
certain load. The advantage provided by the
IR3870 at a load step is to reduce the delay
compared to a fixed frequency control method (in
microseconds or (1-D)*Ts). If the load increases
right after the PWM signal goes low, the longest
delay will be equal to the minimum lower gate on
as shown in the Electrical Specification table.
The IR3870 also reduces the inductor current
slew time, the time it takes for the inductor
current to reach equality with the output current,
by increasing the switching frequency up to
2.5MHz. The result reduces the recovery time.
2
L ⋅ISTEP
COUT =
(7)
2
2
VOS − VOUT
Figure 18. Typical Output Voltage Response
Waveform.
Figure 17. Charge equirement during Load Step
Q = C⋅ V = 0.5⋅Istep⋅Δt (6a)
2
⎡
⎢
⎤
⎥
1
1 L⋅ΔIstep
COUT =
⋅
(6b)
VDROP 2
(
VIN − VOUT
)
⎢
⎥
⎣
⎦
The output voltage drops, VDROP, initially
depending on the characteristic of the output
capacitor. VDROP is the sum of the equivalent
series inductance (ESL) of the output capacitor
times the rate of change of the output current and
the ESR times the change of the output current.
14
IR3870MBF
Boot Capacitor Selection
Choose the soft start capacitor:
The boot capacitor starts the cycle fully charged
to a voltage of VB(0). Cg equals 1.16nF in
IR3870. Choose a sufficiently small ΔV such
that VB(0)-ΔV exceeds the maximum gate
threshold voltage to turn on the high side
MOSFET.
Once the soft start time has chosen, such as
1000us to reach to the reference voltage, a
22nF for CSS is used to meet 1000us.
Choose an inductor to meet the design
specification:
V (0)
⎛
⎜
⎞
B
CBOOT = C ⋅
−1 (8)
⎟
g
VOUT ⋅
VIN − VOUT
)
1.1V ⋅
21V ⋅4A⋅500KHz
(
21V -1.1V
)
= 0.52u H
ΔV
⎝
⎠
L =
=
VIN⋅ ΔI⋅Fs
Choose a boot capacitor value larger than the
calculated CBOOT in equation 8. A typically
value of 0.1uF uses. The voltage rating of this
part needs to be larger than VB(0) plus the
desired derating voltage. Its ESR and ESL
needs to be low in order to allow it to deliver the
large current and di/dt’s which drive MOSFETs
most efficiently. In support of these
1.1V ⋅
21V -1.1V
)
ΔI =
= 3.7A
21V ⋅0.56uH ⋅500K Hz
Choose an inductor with the lowest DCR and
AC power loss as possible to increase the
overall system efficiency. For instance,
choose an FDU0650-R56M manufactured by
TOKO. The inductance of this part is 820nH
and has 3.2mꢀ DCR. Ripple current needs
to be recalculated using the chosen inductor.
requirements a ceramic capacitor should be
chosen.
DESIGN EXAMPLE
Choose an input capacitor:
Design Criteria:
Input Voltage, VIN, = 6V to 21V
Output Voltage, VOUT = 1.1V
Switching Frequency, FS = 500KHz
Inductor Ripple Current, ΔI = 4A
Maximum Output Current, IOUT = 10A
Over Current Trip, IOC = 14A
2
1.1V
21V
1
3
3.7A
10A
⎛
⎜
⎞
⎟
IIN_RMS = 10A⋅
⋅ 1+
⋅
= 2.4A
⎝
⎠
A Panasonic 10uF (ECJ3YB1E106M)
accommodates 6 Arms of ripple current at
300KHz. Due to the chemistry of multilayer
ceramic capacitors, the capacitance varies
over temperature and operating voltage,
both AC and DC. One 10uF capacitor is
recommended. In a practical solution, one
1uF capacitor is required along with 10uF.
The purpose of the 1uF capacitor is to
suppress the switching noise and deliver
high frequency current.
Overshoot Allowance, VOS = VOUT + 100mV
Undershoot Allowance, VDROP = 100mV
Find RFF
:
1.1V
1V ⋅20pF ⋅500KHz
RFF =
= 110 KΩ
Pick a standard value 110 kΩ, 1% resistor.
Find RSET
:
Choose an output capacitor:
1.4⋅6.8mΩ ⋅ 14A
20μA
RISET =
= 6.7KΩ
To meet the undershoot specification, select a set
of output capacitors which has an equivalent ESR
of 10mꢀ (100mV/10A). To meet the overshoot
specification, equation 7 will be used to calculate
the minimum output capacitance. As a result,
243uF will be needed for 10A load remover.
Combine those two requirements, one can
choose a set of output capacitors from
manufactures such as SP-Cap (Specialty
Polymer Capacitor) from Panasonic or POSCAP
from Sanyo. A 270uF (EEFSX0D271) from
Panasonic is recommended.
The RDSON of the lower MOSFET could be
expected to increase by a factor of 1.4 over
temperature. Therefore, pick a 6.81 kΩ, 1%
standard resistor.
Find a resistive voltage divider for VOUT = 1.1V:
R2
VFB =
⋅ VOUT = 0.5V
R2 +R1
R2 = 1.65kΩ, R1 = 1.96 kΩ, both 1% standard
resistors.
15
IR3870MBF
This capacitor has 9mꢀ ESR which leaves
margin for the voltage drop of the ESL during
load step up. The typical ESL for this capacitor is
around 2nH. Refer to Output Capacitor Selection
section for all ceramic capacitor solution.
The purpose of the tight loop from the input
ceramic capacitor is to suppress the high
frequency (10MHz range) switching noise and
reduce Electromagnetic Interference (EMI). If
this path has high inductance, the circuit will
cause voltage spikes and ringing, and increase
the switching loss. The off time path has low
AC and high average DC current. Therefore, it
should be laid out with a tight loop and wide
trace at both ends of the inductor. Lowering the
loop resistance reduces the power loss. The
typical resistance value of 1-ounce copper
thickness is 0.5mꢀ per square inch.
LAYOUT RECOMMENDATION
Bypass Capacitor:
One 1uF high quality ceramic capacitor should
be placed as near VCC pin as possible. The
other end of capacitor can be connected to a
via or connected directly to GND plane. Use a
GND plane instead of thin trace to the GND pin
because this thin traces have too much higher
impedance. A 1uF is recommended for both
V5 and PVCC and repeat the layout procedure
above for those signals.
Charge Pump:
We recommend that D1, D2 and CCPO be
placed as close to the CPO and PVCC pins as
possible. If those components can not be
placed on the same layer as IR3870, a
minimum of two vias are needed for the
connection of CCPO and CPO pin and the
connection of D2 and PVCC.
Boot Circuit:
Figure 19. Current Path of Power Stage
C
BOOT should be placed near the BOOT and
PHASE pins to reduce the impedance when the
upper MOSFET turns on. DBOOT does not need
to be close to CBOOT because the average
current to charge CBOOT is small during the on
time of lower MOSFET.
Power Stage:
Figure 19 shows the flowing current path for
the on and off periods. The on time path has
low average DC current with high AC current.
Therefore, it is recommended to place the input
ceramic capacitor, upper, and lower MOSFET
in a tight loop as shown in Figure 19.
16
IR3870MBF
PCB Metal and Components Placement
Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to
lead spacing should be ≥ 0.2mm to minimize shorting.
Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The
outboard extension ensures a large toe fillet that can be easily inspected.
Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width.
However, the minimum metal to metal spacing should be no less than; 0.17mm for 2 oz. Copper or
no less than 0.1mm for 1 oz. Copper or no less than 0.23mm for 3 oz. Copper.
17
IR3870MBF
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist
should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist
onto the copper of 0.05mm to accommodate solder resist misalignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the
high aspect ratio of the solder resist strip separating the lead lands from the pad land.
18
IR3870MBF
Stencil Design
The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads.
Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much
solder is deposited on the center pad the part will float and the lead lands will open.
The maximum length and width of the land pad stencil aperture should be equal to the solder resist
opening minus an annular 0.2mm pull back in order to decrease the risk of shorting the center land
to the lead lands when the part is pushed into the solder paste.
19
IR3870MBF
MILIMITERS
MIN MAX
INCHES
MILIMITERS
INCHES
DIM
A
A1
b
b1
c
D
E
e
e1
e2
MIN
0.0315
0
MAX
0.0394
0.002
DIM
L
M
N
O
P
Q
R
MIN
MAX
0.45
MIN
MAX
0.0177
0.1001
0.0314
0.0858
0.1316
0.05374
0.1081
0.063
0.8
0
0.375
0.25
1
0.35
2.441
0.703
2.079
3.242
1.265
2.644
1.5
0.0138
0.0962
0.0277
0.0819
0.1276
0.0498
0.1042
0.0591
0.05
0.475
0.35
2.541
0.803
2.179
3.342
1.365
2.744
1.6
0.1477
0.0098
0.1871
0.1379
0.203 REF.
0.008 REF.
5.000 BASIC
6.000 BASIC
1.033 BASIC
0.650 BASIC
0.852 BASIC
1.970 BASIC
2.364 BASIC
0.0407 BASIC
0.0256 BASIC
0.0259 BASIC
S
t1, t2, t3
t4
0.401 BASIC
1.153 BASIC
0.727 BASIC
0.016 BACIS
0.045 BASIC
0.0286 BASIC
t5
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 05/09
20
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